Multi-gate device and method of manufacturing the same

Abstract

A multi-gate device and a method for manufacturing the same are disclosed herein. An exemplary method includes forming a gate dielectric layer around a first channel layer in a p-type gate region and around a second channel layer in an n-type gate region. Forming a sacrificial component between the second channel layers in the n-type gate region. Forming a p-type work function layer over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, removing the sacrificial component from between the second channel layers in the n-type gate region. Forming an n-type work function layer over the gate dielectric layer in the n-type gate region. Forming a metal fill layer over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Description

Technical Field

[0001] Embodiments of the present invention relate to multi-gate devices and methods of manufacturing the same. Background Art

[0002] The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that can simultaneously support a greater number of increasingly complex and sophisticated functions. In order to meet these demands, there is a continuing trend in the integrated circuit (IC) industry to manufacture low-cost, high-performance, and low-power ICs. To date, these goals have been achieved to a large extent by reducing IC size (e.g., minimum IC component size), thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of IC manufacturing processes. Therefore, to achieve continued progress in IC devices and their performance, similar advances in IC manufacturing processes and technologies are needed.

[0003] Recently, multi-gate devices have been introduced to improve gate control. It has been observed that multi-gate devices can increase gate-channel coupling, reduce off-state current and / or reduce short channel effect (SCE). One such multi-gate device is a gate-all-around (GAA) device, which includes a gate structure that can extend partially or completely around a channel region to provide access to the channel region on at least two sides. GAA devices can enable large-scale scaling of IC technology, maintain gate control and alleviate SCE, while seamlessly integrating with conventional IC manufacturing processes. As GAA devices continue to scale, challenges have arisen in manufacturing gate structures for GAA devices (including n-metal gates that share boundaries with p-metal gates), which have been observed to reduce GAA device performance and increase GAA processing complexity. Therefore, while existing GAA devices and their manufacturing methods are generally adequate for their intended purposes, they are not completely satisfactory in all aspects. Summary of the invention

[0004] An embodiment of the present invention provides a method for manufacturing a multi-gate device, comprising: forming a gate dielectric layer in a gate trench in a gate structure, wherein the gate dielectric layer is formed around a first channel layer in a p-type gate region and around a second channel layer in an n-type gate region; forming a sacrificial component between the second channel layers in the n-type gate region; forming a p-type work function layer in the gate trench above the gate dielectric layer in the p-type gate region and the n-type gate region; removing the p-type work function layer from the gate trench in the n-type gate region; after removing the p-type work function layer, removing the sacrificial component between the second channel layers in the n-type gate region; forming an n-type work function layer in the gate trench above the gate dielectric layer in the n-type gate region, wherein the n-type work function layer surrounds the gate dielectric layer and the second channel layer in the n-type gate region; and forming a metal filling layer in the gate trench above the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

[0005] Another embodiment of the present invention provides a method for manufacturing a multi-gate device, comprising: depositing a gate dielectric layer over a first semiconductor layer in a p-type gate region and over a second semiconductor layer in an n-type gate region, wherein the gate dielectric layer wraps the first semiconductor layer and the second semiconductor layer, wherein after depositing the gate dielectric layer, a first gap is provided between the first semiconductor layers and a second gap is provided between the second semiconductor layers; depositing a sacrificial layer over the gate dielectric layer in the p-type gate region and the n-type gate region; etching the sacrificial layer in the p-type gate region and the n-type gate region to form a first sacrificial component in the p-type gate region between the first semiconductor layers and a second sacrificial component in the n-type gate region between the second semiconductor layers; depositing a p-type work function layer over the gate dielectric layer in the p-type gate region and the n-type gate region after removing the first sacrificial component from the p-type gate region; removing the p-type work function layer from over the gate dielectric layer in the n-type gate region; and depositing an n-type work function layer over the gate dielectric layer in the n-type gate region after removing the second sacrificial component from the n-type gate region.

[0006] Yet another embodiment of the present invention provides a multi-gate device, comprising: a first channel layer disposed in a p-type gate region above a substrate; a second channel layer disposed in an n-type gate region above the substrate; and a gate stack spanning the p-type gate region and the n-type gate region, wherein the gate stack is disposed between a first epitaxial source / drain component and a second epitaxial source / drain component, the first epitaxial source / drain component being disposed in the p-type gate region, the second epitaxial source / drain component being disposed in the n-type gate region, and wherein the gate stack comprises: a p metal gate located in the p-type gate region, wherein , the p-metal gate surrounds the first channel layer, and the p-metal gate includes a gate dielectric layer, a p-type work function layer arranged above the gate dielectric layer, and a metal filling layer arranged above the p-type work function layer, and an n-metal gate is located in the n-type gate region, wherein the n-metal gate surrounds the second channel layer, and the n-metal gate includes the gate dielectric layer, an n-type work function layer arranged above the gate dielectric layer, and the metal filling layer arranged above the n-type work function layer, and wherein the thickness (T) of the p-type work function layer is greater than or equal to half of the gate length (Lg) of the gate stack (T≥0.5Lg). BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A and Figure 1B is a flow chart of a method for fabricating a multi-gate device according to various aspects of the present invention.

[0009] FIG. 2A to FIG. 23A , Figures 2B to 23B , Figures 2C to 23C and Figures 2D to 23D is according to various aspects of the present invention at various stages of manufacture (such as with Figure 1A and Figure 1B A partial schematic diagram of a portion or the whole of a multi-gate device (associated with the methods in FIG. 1 ). DETAILED DESCRIPTION

[0010] The present invention relates generally to integrated circuit devices and, more particularly, to multi-gate devices, such as gate-all-around (GAA) devices.

[0011] The following disclosure provides many different embodiments or examples for realizing different components. Reference numbers and / or letters may be repeated in the various examples described herein. This repetition is for the purpose of simplicity and clarity, and does not indicate the relationship between the various embodiments and / or configurations discussed in itself. In addition, the specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted to form, and may also include an embodiment in which an additional component may be formed between the first component and the second component, so that the first component and the second component may not be directly contacted. In addition, in the present invention, the formation of a component on another component, connected to another component and / or coupled to another component may include an embodiment in which the component is formed as a direct contact, and may also include an embodiment in which an additional component is formed between components so that the components may not be directly contacted.

[0012] Additionally, for ease of description, spatially relative terms such as "lower," "upper," "lateral," "vertical," "above," "above," "below," "under," "upward," "downward," "top," "bottom," and the like, and derivatives thereof (e.g., "laterally," "downwardly," "upwardly," and the like) may be used herein to describe the relationship of one element or component to another element or component. In addition to descriptions of devices including elements or components, the spatially relative terms are intended to encompass different orientations of the device in use or in the process of operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0013] Figure 1A and Figure 1B1 is a flow chart of a method 100 for manufacturing a multi-gate device according to various aspects of the present invention. In some embodiments, the method 100 manufactures a multi-gate device including a p-type GAA transistor and an n-type GAA transistor. At frame 102, a first semiconductor layer stack and a second semiconductor layer stack are formed over a substrate. The first semiconductor layer stack and the second semiconductor layer stack include a first semiconductor layer and a second semiconductor layer stacked vertically in an alternating configuration. At frame 104, a gate structure is formed over a first region of the first semiconductor layer stack and a first region of the second semiconductor layer stack. The gate structure includes a dummy gate stack and a gate spacer. At frame 106, a portion of the first semiconductor layer stack in the second region and a portion of the second semiconductor layer stack in the second region are removed to form a source / drain groove. At frame 108, an internal spacer is formed along the sidewall of the first semiconductor layer in the first semiconductor layer stack and the second semiconductor layer stack. At frame 110, an epitaxial source / drain component is formed in the source / drain groove. At frame 112, an interlayer dielectric (ILD) layer is formed over the epitaxial source / drain component. At block 114, the dummy gate stack is removed to form a gate trench that exposes the first semiconductor layer stack in the p-type gate region and the second semiconductor layer stack in the n-type gate region. At block 116, the first semiconductor layer is removed from the first semiconductor layer stack and the second semiconductor layer stack exposed by the gate trench to form a gap between the second semiconductor layers. At block 118, a gate dielectric layer is formed in the gate trench around the second semiconductor layer in the p-type gate region and the n-type gate region. The gate dielectric layer partially fills the gap between the second semiconductor layers.

[0014] At box 120, a sacrificial layer is formed over the gate dielectric layer in the gate trenches in the p-type gate region and the n-type gate region. The sacrificial layer fills any remaining portion of the gap between the second semiconductor layers. At box 122, the sacrificial layer is patterned to form a sacrificial feature between the p-type gate region and the second semiconductor layer in the n-type gate region. At box 124, the sacrificial feature is removed from between the second semiconductor layers in the p-type gate region. At box 126, a p-type work function layer is formed in the gate trenches over the gate dielectric in the p-type gate region and the n-type gate region. At box 128, the p-type work function layer is removed from the gate trenches in the n-type gate region. At box 130, it is determined whether the gate dielectric layer and the p-type work function layer fill the gate trenches in the p-type gate region along the gate length direction. If not, repeat box 128 and box 130. If yes, the method 100 proceeds to box 132, in which the sacrificial feature is removed from between the second semiconductor layers in the n-type gate region. At block 134, an n-type work function layer is formed in a gate trench over the gate dielectric layer in the n-type gate region and over the p-type work function layer in the p-type gate region. At block 136, the n-type work function layer is removed from the gate trench in the p-type gate region. At block 138, a metal body layer is formed in a gate trench over the n-type work function layer in the n-type gate region and over the p-type work function layer in the p-type gate region. At block 140, a planarization process is performed on the metal body layer, the n-type work function layer, the p-type work function layer, and the gate dielectric layer, thereby forming a p-metal gate in the p-type gate region and an n-metal gate in the n-type gate region. The method 100 then proceeds to block 142, where contacts are formed. The present invention contemplates additional processing. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be moved, replaced, or eliminated for other embodiments of the method 100. The following discussion describes various embodiments of nanowire-based integrated circuit devices that may be fabricated according to the method 100.

[0015] FIG. 2A to FIG. 22A , FIG. 2B to FIG. 22B , Figure 2C to Figure 22C and FIG. 2D to FIG. 22D is according to various aspects of the present invention at various stages of manufacture (such as with Figure 1A and Figure 1B Partial schematic diagram of a portion or the whole of a multi-gate device 200 (associated with the method 100 in FIG. 1 ). In particular, FIG. 2A to FIG. 22A is a top view of the multi-gate device 200 in the XY plane; FIG. 2B to FIG. 22B are respectively along FIG. 2A to FIG. 22A A cross-sectional view of the multi-gate device 200 in the XZ plane along line BB′, Figure 2C to Figure 22C are respectively along FIG. 2A to FIG. 22A A schematic cross-sectional view of the multi-gate device 200 in the YZ plane along line CC′; and FIG. 2D to FIG. 22D are respectively along FIG. 2A to FIG. 22A Schematic cross-sectional view of the multi-gate device 200 in the YZ plane along the line D-D' of FIG. The multi-gate device 200 may be included in a microprocessor, a memory, and / or other IC devices. In some embodiments, the multi-gate device 200 is part of an IC chip, a system on a chip (SoC), or a portion thereof, and includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. In some embodiments, the multi-gate device 200 is included in a non-volatile memory, such as a non-volatile random access memory (NVRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), an electrically programmable read-only memory (EPROM), other suitable memory types, or combinations thereof. For clarity, the multi-gate device 200 has been simplified. FIG. 2A to FIG. 22A , FIG. 2B to FIG. 22B , Figure 2C to Figure 22C and FIG. 2D to FIG. 22D , to better understand the inventive concept of the present invention. Additional components may be added to the multi-gate device 200, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the multi-gate device 200.

[0016] Steering FIG. 2A to FIG. 2D, the multi-gate device 200 includes a substrate (wafer) 202. In the illustrated embodiment, the substrate 202 includes silicon. Alternatively or additionally, the substrate 202 includes another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Optionally, the substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured using isolation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Depending on the design requirements of the multi-gate device 200, the substrate 202 may include various doped regions. In the illustrated embodiment, the substrate 202 includes a p-type doped region 204A (hereinafter referred to as a p-well) that can be configured for an n-type GAA transistor and an n-type doped region 204B (hereinafter referred to as an n-well) that can be configured for a p-type GAA transistor. The n-type doped region (such as the n-well 204B) is doped with an n-type dopant, such as phosphorus, arsenic, other n-type dopants, or a combination thereof. The p-type doped region such as the p-well 204A is doped with a p-type dopant, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, the substrate 202 includes a doped region formed by a combination of a p-type dopant and an n-type dopant. Various doped regions can be formed directly on and / or in the substrate 202, for example, providing a p-well structure, an n-well structure, a double-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form the various doped regions.

[0017] A semiconductor layer stack 205 is formed over the substrate 202, wherein the semiconductor layer stack 205 includes semiconductor layers 210 and semiconductor layers 215 stacked vertically (e.g., along the z-direction) from the surface of the substrate 202 in a staggered or alternating configuration. In some embodiments, the semiconductor layers 210 and semiconductor layers 215 are epitaxially grown in the staggered and alternating configurations shown. For example, a first of the semiconductor layers 210 is epitaxially grown on the substrate, a first of the semiconductor layers 215 is epitaxially grown on the first of the semiconductor layers 210, and a second of the semiconductor layers 210 is epitaxially grown on the first of the semiconductor layers 215 until the semiconductor layer stack 205 has a desired number of semiconductor layers 210 and semiconductor layers 215. In such embodiments, the semiconductor layers 210 and semiconductor layers 215 may be referred to as epitaxial layers. In some embodiments, the epitaxial growth of the semiconductor layers 210 and semiconductor layers 215 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or a combination thereof.

[0018] The composition of semiconductor layer 210 is different from the composition of semiconductor layer 215 to achieve etching selectivity and / or different oxidation rates during subsequent processing. In some embodiments, semiconductor layer 210 has a first etching rate to an etchant and semiconductor layer 215 has a second etching rate to an etchant, wherein the second etching rate is less than the first etching rate. In some embodiments, semiconductor layer 210 has a first oxidation rate and semiconductor layer 215 has a second oxidation rate, wherein the second oxidation rate is less than the first oxidation rate. In the illustrated embodiment, semiconductor layer 210 and semiconductor layer 215 include different materials, composition atomic percentages, composition weight percentages, thicknesses, and / or properties to achieve a desired etching selectivity during an etching process (such as an etching process implemented to form a suspended channel layer in a channel region of multi-gate device 200). For example, where semiconductor layer 210 includes silicon germanium and semiconductor layer 215 includes silicon, the silicon etching rate of semiconductor layer 215 is less than the silicon germanium etching rate of semiconductor layer 210. In some embodiments, semiconductor layer 210 and semiconductor layer 215 may include the same material, but have different composition atomic percentages to achieve etching selectivity and / or different oxidation rates. For example, semiconductor layer 210 and semiconductor layer 215 may include silicon germanium, wherein semiconductor layer 210 has a first silicon atomic percentage and / or a first germanium atomic percentage, and semiconductor layer 215 has a different second silicon atomic percentage and / or a different second germanium atomic percentage. The present invention contemplates that semiconductor layer 210 and semiconductor layer 215 include any combination of semiconductor materials (e.g., materials that maximize current) that can provide desired etching selectivity, desired oxidation rate differences, and / or desired performance characteristics, including any semiconductor material disclosed herein.

[0019] As further described below, the semiconductor layer 215 or a portion thereof forms a channel region of the multi-gate device 200. In the illustrated embodiment, the semiconductor layer stack 205 includes four semiconductor layers 210 and four semiconductor layers 215 configured to form four semiconductor layer pairs above the substrate 202, each semiconductor layer pair having a corresponding first semiconductor layer 210 and a corresponding second semiconductor layer 215. After subsequent processing, this configuration will produce a multi-gate device 200 having four channels. However, the present invention contemplates embodiments in which the semiconductor layer stack 205, for example, includes more or fewer semiconductor layers, depending on the number of channels desired for the multi-gate device 200 (e.g., a GAA transistor) and / or the design requirements of the multi-gate device 200. For example, the semiconductor layer stack 205 may include two to ten semiconductor layers 210 and two to ten semiconductor layers 215. In the further illustrated embodiment, the semiconductor layer 210 has a thickness t1, and the semiconductor layer 215 has a thickness t2, wherein the thicknesses t1 and t2 are selected based on the manufacturing and / or device performance of the multi-gate device 200. For example, thickness t1 may be configured to define a desired distance (or gap) between adjacent channels of multi-gate device 200 (e.g., between semiconductor layers 215), thickness t2 may be configured to achieve a desired thickness of the channels of multi-gate device 200, and thickness t1 and thickness t2 may be configured to achieve desired performance of multi-gate device 200. In some embodiments, thickness t1 and thickness t2 are about 1 nm to about 10 nm.

[0020] Steering FIG. 3A to FIG. 3D, patterning the semiconductor layer stack 205 to form fins 218A and fins 218B (also referred to as fin structures, fin elements, etc.). The fins 218, 218B include a substrate portion (i.e., a portion of the substrate 202) and a semiconductor layer stack portion (i.e., the remaining portion of the semiconductor layer stack 205 including the semiconductor layer 210 and the semiconductor layer 215). The fins 218A, 218B extend substantially parallel to each other along the y-direction, having a length defined in the y-direction, a width defined in the x-direction, and a height defined in the z-direction. In some embodiments, a photolithography and / or etching process is performed to pattern the semiconductor layer stack 205 to form the fins 218A, 218B. The photolithography process may include forming a photoresist layer (e.g., by spin coating) over the semiconductor layer stack 205; performing a pre-exposure bake process; performing an exposure process using a mask; performing a post-exposure bake process; and performing a development process. During the exposure process, the photoresist layer is exposed to radiation energy (such as ultraviolet (UV), deep ultraviolet (DUV) or extreme ultraviolet (EUV) light), wherein depending on the mask pattern and / or mask type of the mask (e.g., a binary mask, a phase-shift mask or an EUV mask), the mask blocks, transmits and / or reflects radiation to the photoresist layer, so that an image is projected onto the photoresist layer corresponding to the mask pattern. Since the photoresist layer is sensitive to radiation energy, depending on the characteristics of the photoresist layer and the characteristics of the developing solution used in the developing process, the exposed portion of the photoresist layer undergoes a chemical change, and the exposed (or unexposed) portion of the photoresist layer dissolves. After development, the patterned photoresist layer includes a photoresist pattern corresponding to the mask. The etching process uses the patterned photoresist layer as an etching mask to remove portions of the semiconductor layer stack 205. In some embodiments, a patterned photoresist layer is formed over a hard mask layer disposed over the semiconductor layer stack 205, a first etching process removes a portion of the hard mask layer to form a patterned hard mask layer, and a second etching process removes a portion of the semiconductor layer stack 205 using the patterned hard mask layer as an etching mask. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a reactive ion etching (RIE) process. After the etching process, the patterned photoresist layer (and in some embodiments, the hard mask layer) is removed, for example, by a photoresist stripping process or other suitable process.Optionally, the fins 218A, 218B are formed by a re-patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer is a dielectric (SID) SADP process, other double patterning processes, or a combination thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof. In some embodiments, a directed self-assembly (DSA) technique is implemented while patterning the semiconductor layer stack 205. In addition, in some embodiments, the exposure process may employ maskless lithography, electron beam (e-beam) writing, and / or ion beam writing for patterning the photoresist layer.

[0021] Isolation features 230 are formed over and / or in substrate 202 to isolate various regions of the multi-gate device 200, such as various device regions. For example, isolation features 230 surround the bottom of fins 218A, 218B, such that isolation features 230 separate and isolate fins 218A, 218B from each other. In the illustrated embodiment, isolation features 230 surround substrate portions of fins 218A, 218B (e.g., doped regions 204A, 204B of substrate 202) and partially surround semiconductor layer stack portions of fins 218A, 218B (e.g., portions of bottom-most semiconductor layer 210). However, the present invention contemplates different configurations of isolation features 230 relative to fins 218A, 218B. Isolation features 230 include silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, or other suitable isolation compositions), or combinations thereof. The isolation component 230 may include different structures, such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or a local oxidation of silicon (LOCOS) structure. For example, the isolation component 230 may include an STI component that defines the fins 218A, 218B and electrically isolates the fins 218A, 218B from other active device regions (such as fins) and / or passive device regions. The STI component may be formed by etching a trench in the substrate 202 (e.g., by using a dry etching process and / or a wet etching process) and filling the trench with an insulator material (e.g., by using a CVD process or a spin glass process). A chemical mechanical polishing (CMP) process may be performed to remove excess insulator material and / or planarize the top surface of the isolation component 230. In another example, the STI component can be formed by depositing an insulator material over the substrate 202 after forming the fins 218A, 218B (in some embodiments, such that the insulator material layer fills the gap (trench) between the fins 218A, 218B) and etching back the insulator material layer to form the isolation component 230. In some embodiments, the STI component includes a multilayer structure that fills the trench, such as a layer including silicon nitride disposed over a thermal oxide including a liner layer. In another example, the STI component includes a dielectric layer disposed over a doped liner layer (including, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG)). In yet another example, the STI component includes a body dielectric layer disposed over the liner dielectric layer, wherein the body dielectric layer and the liner dielectric layer include materials depending on the design requirements.

[0022] Steering 4A to 4D, a gate structure 240 is formed over a portion of the fins 218A, 218B and over the isolation feature 230. The gate structure 240 extends longitudinally in a direction different from the longitudinal direction (e.g., orthogonal) of the fins 218A, 218B. For example, the gate structures 240 extend substantially parallel to each other along the x-direction, have a length defined in the y-direction, a width defined in the x-direction, and a height defined in the z-direction. The gate structure 240 is disposed on a portion of the fins 218A, 218B, and defines a source / drain region 242 and a channel region 244 of the fins 218A, 218B. In the XZ plane, the gate structure 240 wraps around the top surface and sidewall surfaces of the fins 218A, 218B. In the YZ plane, the gate structure 240 is disposed over the top surface of the corresponding channel region 244 of the fins 218A, 218B, so that the gate structure 240 is between the corresponding source / drain regions 242. Each gate structure 240 includes a gate region 240-1 corresponding to a portion of the corresponding gate structure 240 to be configured for an n-type GAA transistor (thus corresponding to a portion spanning an n-type GAA transistor region) and a gate region 240-2 corresponding to a portion of the corresponding gate structure 240 to be configured for a p-type GAA transistor (thus corresponding to a portion spanning an p-type GAA transistor region). The gate structure 240 is configured differently in the gate region 240-1 and the gate region 240-2. For example, as further described below, each metal gate stack of the gate structure 240 spans the gate region 240-1 and the gate region 240-2, and is configured differently in the gate region 240-1 and the gate region 240-2 to optimize the performance of an n-type GAA transistor (having an n-gate electrode in the gate region 240-1) and a p-type GAA transistor (having a p-gate electrode in the gate region 240-2). Therefore, the gate region 240 - 1 is referred to as an n-type gate region 240 - 1 , and the gate region 240 - 2 is referred to as a p-type gate region 240 - 2 hereinafter.

[0023] exist 4A to 4DIn the embodiment shown, each gate structure 240 includes a dummy gate stack 245. In the embodiment shown, the width of the dummy gate stack 245 defines the gate length (Lg) of the gate structure 240 (here, in the y direction), wherein the gate length defines the distance (or length) that the current (e.g., carriers such as electrons or holes) propagates between the source / drain regions 242 when the n-type GAA transistor and / or the p-type GAA transistor is switched (turned on). In some embodiments, the gate length is from about 5nm to about 250nm. The gate length can be adjusted to obtain the desired operating speed of the GAA transistor and / or the desired packing density of the GAA transistor. For example, when the GAA transistor is turned on, the current flows between the source / drain regions of the GAA transistor. Increasing the gate length increases the distance required for the current to propagate between the source / drain regions, increasing the time required for the GAA transistor to be fully turned on. Conversely, reducing the gate length reduces the distance required for the current to propagate between the source / drain regions, shortening the time required for the GAA transistor to be fully turned on. Smaller gate lengths provide GAA transistors that are turned on / off faster, manufactured faster, and operate at high speeds. Smaller gate lengths also facilitate tighter packaging density (i.e., more GAA transistors can be manufactured in a given area of ​​an IC chip), increasing the number of functions and applications that can be manufactured on an IC chip. In the illustrated embodiment, the gate length of one or more gate structures 240 is configured to provide a GAA transistor with a short length (SC) channel. For example, the gate length of the SCGAA transistor is about 5nm to about 20nm. In some embodiments, the multi-gate device 200 may include GAA transistors with different gate lengths. For example, the gate length of one or more of the gate structures 240 may be configured to provide a GAA transistor with a medium length or long length channel (M / LC). In some embodiments, the gate length of the M / LC GAA transistor is about 20nm to about 250nm.

[0024] The dummy gate stack 245 includes a dummy gate electrode and, in some embodiments, a dummy gate dielectric. The dummy gate electrode includes a suitable dummy gate material, such as a polysilicon layer. In embodiments where the dummy gate stack 245 includes a dummy gate dielectric disposed between the dummy gate electrode and the fins 218A, 218B, the dummy gate dielectric includes a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or a combination thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, or a combination thereof. In some embodiments, the dummy gate dielectric includes an interface layer (including, for example, silicon oxide) disposed above the fins 218A, 218B and a high-k dielectric layer disposed above the interface layer. The dummy gate stack 245 may include many other layers, such as a capping layer, an interface layer, a diffusion layer, a barrier layer, a hard mask layer, or a combination thereof. For example, the dummy gate stack 245 may also include a hard mask layer disposed above the dummy gate electrode.

[0025] The pseudo gate stack 245 is formed by a deposition process, a photolithography process, an etching process, other suitable processes or combinations thereof. For example, a deposition process is performed to form a pseudo gate electrode layer above the fins 218A, 218B and the isolation component 230. In some embodiments, before forming the pseudo gate electrode layer, a deposition process is performed to form a pseudo gate dielectric layer above the fins 218A, 218B and the isolation component 230. In such an embodiment, the pseudo gate electrode layer is deposited above the pseudo gate dielectric layer. In some embodiments, a hard mask layer is deposited above the pseudo gate electrode layer. The deposition process includes CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods or combinations thereof. A photolithography patterning and etching process is then performed to pattern the dummy gate electrode layer (and in some embodiments, the dummy gate dielectric layer and the hard mask layer) to form a dummy gate stack 245 such that 4A to 4D The configuration shown is a dummy gate stack 245 (including a dummy gate electrode layer, a dummy gate dielectric layer, a hard mask layer and / or other suitable layers). The photolithography patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing photoresist, rinsing, drying (e.g., hard baking), other suitable photolithography processes, or combinations thereof. The etching process includes a dry etching process, a wet etching process, other etching methods, or combinations thereof.

[0026] Each gate structure 240 also includes a gate spacer 247 disposed adjacent to the corresponding dummy gate stack 245 (i.e., along the sidewall of the dummy gate stack 245). The gate spacer 247 is formed by any suitable process and includes a dielectric material. The dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). For example, a dielectric layer including silicon and nitrogen (such as a silicon nitride layer) may be deposited over the dummy gate stack 245, and then etched (e.g., anisotropically etched) the dielectric layer to form the gate spacer 247. In some embodiments, the gate spacer 247 includes a multilayer structure, such as a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some embodiments, more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the dummy gate stack 245. In such an embodiment, each set of spacers may include materials having different etch rates. For example, a first dielectric layer including silicon and oxygen (e.g., silicon oxide) may be deposited and etched to form a first set of spacers adjacent to the dummy gate stack 245, and a second dielectric layer including silicon and nitrogen (e.g., silicon nitride) may be deposited and etched to form a second set of spacers adjacent to the first set of spacers.

[0027] Steering FIG. 5A to FIG. 5D, at least partially removing the exposed portions of the fins 218A, 218B (i.e., the source / drain regions 242 of the fins 218A, 218B that are not covered by the gate structure 240) to form source / drain trenches (recesses) 250. In the illustrated embodiment, the etching process completely removes the semiconductor layer stack 205 in the source / drain regions 242 of the fins 218A, 218B, thereby exposing the substrate portions (e.g., the p-well 204A and the n-well 204B) of the fins 218A, 218B in the source / drain regions 242. Therefore, the source / drain trenches 250 have sidewalls defined by the remaining portions of the semiconductor layer stack 205, which are disposed in the channel region 244 below the gate structure 240, and a bottom defined by the substrate 202, such as the top surfaces of the p-well 204A and the n-well 204B in the source / drain regions 242. In some embodiments, the etching process removes some but not all of the semiconductor layer stack 205 so that the source / drain trench 250 has a bottom defined by the semiconductor layer 210 or the semiconductor layer 215 in the source / drain region 242. In some embodiments, the etching process also removes some but not all of the substrate portion of the fins 218A, 218B so that the source / drain recess 250 extends below the topmost surface of the substrate 202. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may alternately use an etchant to remove the semiconductor layer 210 and the semiconductor layer 215 separately and alternately. In some embodiments, the parameters of the etching process are configured to selectively etch the semiconductor layer stack by minimal (to no) etching of the gate structure 240 (i.e., the dummy gate stack 245 and the gate spacer 247) and / or the isolation feature 230. In some embodiments, a photolithography process such as those described herein is performed to form a patterned mask layer covering the gate structure 240 and / or the isolation features 230 , and an etching process uses the patterned mask layer as an etching mask.

[0028] Steering FIG. 6A to FIG. 6D, forming an internal spacer 255 in the channel region 244 along the sidewalls of the semiconductor layer 210 by any suitable process. For example, a first etching process is performed that selectively etches the semiconductor layer 210 exposed by the source / drain trench 250, while etching the semiconductor layer 215 minimally (to none), so that gaps are formed between the semiconductor layers 215 and between the semiconductor layer 215 and the substrate 202 under the gate spacer 247. Portions (edges) of the semiconductor layer 215 are thus suspended in the channel region 244 under the gate spacer 247. In some embodiments, the gap extends partially under the dummy gate stack 245. The first etching process is configured to etch the semiconductor layer 210 laterally (e.g., along the y-direction), thereby reducing the length of the semiconductor layer 210 along the y-direction. The first etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. Then, a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof, forms a spacer layer over the gate structure 240 and over the components defining the source / drain trenches 250 (e.g., the semiconductor layer 215, the semiconductor layer 210, and the substrate 202). The spacer layer partially (and in some embodiments, completely) fills the source / drain trenches 250. The deposition process is configured to ensure that the spacer layer fills the gaps between the semiconductor layers 215 and between the semiconductor layers 215 and the substrate 202 below the gate spacers 247. Then, a second etching process is performed that selectively etches the spacer layer to form inner spacers 255, such as FIG. 6A to FIG. 6D As shown, the second etching process minimally (to none) etches the semiconductor layer 215, the dummy gate stack 245, and the gate spacer 247. In some embodiments, the spacer layer is removed from the sidewalls of the gate spacer 247, the sidewalls of the semiconductor layer 215, the dummy gate stack 245, and the substrate 202. The spacer layer (and therefore the internal spacer 255) includes a material different from the material of the semiconductor layer 215 and the material of the gate spacer 247 to achieve a desired etching selectivity during the second etching process. In some embodiments, the spacer layer includes a dielectric material that includes silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or carbon oxynitride silicon). In some embodiments, the spacer layer includes a low-k dielectric material, such as those described herein. In some embodiments, a dopant (e.g., a p-type dopant, an n-type dopant, or a combination thereof) is introduced into the dielectric material so that the spacer layer includes a doped dielectric material.

[0029] Steering 7A to 7D, forming an epitaxial source / drain component in the source / drain recess 250. For example, epitaxially growing semiconductor material from the portion of the substrate 202 and the semiconductor layer 215 exposed by the source / drain recess 250, forming an epitaxial source / drain component 260A in the source / drain region 242 corresponding to the n-type GAA transistor region, and forming an epitaxial source / drain component 260B in the source / drain region 242 corresponding to the p-type GAA transistor region. The epitaxial process can use CVD deposition technology (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial process can use gaseous and / or liquid precursors that interact with components of the substrate 202 and / or the semiconductor layer stack 205 (particularly the semiconductor layer 215). The epitaxial source / drain components 260A, 260B are doped with n-type dopants and / or p-type dopants. In some embodiments, for an n-type GAA transistor, the epitaxial source / drain feature 260A includes silicon. The epitaxial source / drain feature 260A may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., to form a Si:C epitaxial source / drain feature, a Si:P epitaxial source / drain feature, or a Si:C:P epitaxial source / drain feature). In some embodiments, for a p-type GAA transistor, the epitaxial source / drain feature 260B includes silicon germanium or germanium. The epitaxial source / drain feature 260B may be doped with boron, other p-type dopants, or combinations thereof (e.g., to form a Si:Ge:B epitaxial source / drain feature). In some embodiments, the epitaxial source / drain feature 260A and / or the epitaxial source / drain feature 260B include more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may include the same or different materials and / or dopant concentrations. In some embodiments, the epitaxial source / drain features 260A, 260B include materials and / or dopants that achieve a desired tensile stress and / or compressive stress in the corresponding channel region 244. In some embodiments, the epitaxial source / drain features 260A, 260B are doped during deposition by adding impurities to the source material of the epitaxial process (i.e., in situ). In some embodiments, the epitaxial source / drain features 260A, 260B are doped by an ion implantation process after the deposition process. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate dopants in the epitaxial source / drain features 260A, 260B and / or other source / drain regions (e.g., heavily doped source / drain regions and / or lightly doped source / drain (LDD) regions).In some embodiments, the epitaxial source / drain features 260A, 260B are formed in a separate processing sequence, including, for example, masking the p-type GAA transistor region when forming the epitaxial source / drain features 260A in the n-type GAA transistor region, and masking the GAA transistor region when forming the epitaxial source / drain features 260B in the p-type GAA transistor region.

[0030] Steering FIG. 8A to FIG. 8D An interlayer dielectric (ILD) layer 270 is formed over the isolation feature 230, the epitaxial source / drain features 260A, 260B, and the gate spacer 247, for example, by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. The ILD layer 270 is disposed between adjacent gate structures 240. In some embodiments, the ILD layer 270 is formed by a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (e.g., a liquid compound) over the multi-gate device 200, and converting the flowable material into a solid material by a suitable technique such as thermal annealing and / or ultraviolet radiation treatment. The ILD layer 270 includes a dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed by TEOS, PSG, BPSG, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, (Applied Materials, Inc., Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (The Dow Chemical Company, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In the illustrated embodiment, the ILD layer 270 is a dielectric layer including a low-k dielectric material (commonly referred to as a low-k dielectric layer). The ILD layer 270 may include a multilayer structure having a variety of dielectric materials. In some embodiments, a contact etch stop layer (CESL) is disposed between the ILD layer 270 and the isolation features 230, the epitaxial source / drain features 260A, 260B, and the gate spacer 247. The CESL includes a material different from the ILD layer 270, such as a dielectric material different from the dielectric material of the ILD layer 270. For example, in the case where the ILD layer 270 includes a low-k dielectric material, the CESL includes silicon and nitrogen, such as silicon nitride or silicon oxynitride. After depositing the ILD layer 270 and / or the CESL, a CMP process and / or other planarization process may be performed until reaching (exposing) the top (or top surface) of the dummy gate stack 245. In some embodiments, the planarization process removes the hard mask layer of the dummy gate stack 245 to expose the dummy gate electrode, such as a polysilicon gate electrode layer, of the dummy gate stack 245 below.

[0031] The ILD layer 170 may be part of a multi-layer interconnect (MLI) component disposed above the substrate 202. The MLI component electrically couples various devices (e.g., p-type GAA transistors and / or n-type GAA transistors, transistors, resistors, capacitors, and / or inductors of the multi-gate device 200) and / or components (e.g., gate structures and / or epitaxial source / drain components of p-type GAA transistors and / or n-type GAA transistors) so that the various devices and / or components may operate as specified by the design requirements of the multi-gate device 200. The MLI component includes a combination of dielectric layers and conductive layers (e.g., metal layers) that are configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect components (such as device-level contacts and / or vias) and / or horizontal interconnect components (such as wires). The vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the MLI component. During operation, the interconnect features are configured to route signals between and / or distribute signals (eg, clock signals, voltage signals, and / or ground signals) to components of the device and / or multi-gate device 200 .

[0032] Steering 9A to 9D , remove the dummy gate stack 245 from the gate structure 240, thereby exposing the semiconductor layer stack 205 of the fins 218A, 218B in the n-type gate region 240-1 and the p-type gate region 240-2. In the illustrated embodiment, the etching process completely removes the dummy gate stack 245 to expose the semiconductor layer 215 and the semiconductor layer 210 in the channel region 244. The etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process can alternately use etchants to remove various layers of the dummy gate stack 245, such as a dummy gate electrode layer, a dummy gate dielectric layer, and / or a hard mask layer. In some embodiments, the etching process is configured to selectively etch the dummy gate stack 245, with minimal (to no) etching of other components of the multi-gate device 200 (such as the ILD layer 270, the gate spacer 247, the isolation component 230, the semiconductor layer 215, and the semiconductor layer 210). In some embodiments, a photolithography process, such as those described herein, is performed to form a patterned mask layer covering the ILD layer 270 and / or the gate spacers 247 , and an etching process uses the patterned mask layer as an etching mask.

[0033] Steering FIG. 10A to FIG. 10D, the semiconductor layer 210 (exposed by the gate trench 275) of the semiconductor layer stack 205 is selectively removed from the channel region 244, thereby forming a suspended semiconductor layer 215' in the channel region 244. In the embodiment shown, the etching process selectively etches the semiconductor layer 210, minimally (to no) etches the semiconductor layer 215, and in some embodiments, minimally (to no) etches the gate spacer 247 and / or the inner spacer 255. Various etching parameters can be adjusted to achieve selective etching of the semiconductor layer 210, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. For example, an etchant is selected for the etching process that etches the material of the semiconductor layer 210 (silicon germanium in the illustrated embodiment) at a higher rate than the material of the semiconductor layer 215 (silicon in the illustrated embodiment) (i.e., the etchant has a high etching selectivity with respect to the material of the semiconductor layer 210). The etching process is a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the dry etching process (such as an RIE process) utilizes a fluorine-containing gas (e.g., SF6) to selectively etch the semiconductor layer 210. In some embodiments, the ratio of the fluorine-containing gas to the oxygen-containing gas (e.g., O2), the etching temperature, and / or the RF power can be adjusted to selectively etch silicon germanium or silicon. In some embodiments, the wet etching process utilizes an etching solution including ammonium hydroxide (NH4OH) and water (H2O) to selectively etch the semiconductor layer 210. In some embodiments, a chemical vapor etching process using hydrofluoric acid (HCl) selectively etches the semiconductor layer 210.

[0034] Thus, at least one suspended semiconductor layer 215' is exposed to the n-type gate region 240-1 and the p-type gate region 240-2 through the gate trench 275. In the illustrated embodiment, each n-type gate region 240-1 and each p-type gate region 240-2 include four suspended semiconductor layers 215' stacked vertically, which will provide four channels through which current will flow between corresponding epitaxial source / drain features (epitaxial source / drain features 260A or epitaxial source / drain features 260B) during operation of the GAA transistor. Therefore, the suspended semiconductor layer 215' is referred to as the channel layer 215' hereinafter. The channel layer 215' in the n-type gate region 240-1 is separated by a gap 277A, and the channel layer 215' in the p-type gate region 240-2 is separated by a gap 277B. The channel layer 215' in the n-type gate region 240-1 is also separated from the substrate 202 by a gap 277A, and the channel layer 215' in the p-type gate region 240-2 is also separated from the substrate 202 by a gap 277B. A spacing s1 is defined between the channel layers 215' along the z-direction in the n-type gate region 240-1, and a spacing s2 is defined between the channel layers 215' along the z-direction in the p-type gate region 240-2. The spacing s1 and the spacing s2 correspond to the widths of the gap 277A and the gap 277B, respectively. In the illustrated embodiment, the spacing s1 is approximately equal to s2, but the present invention contemplates embodiments in which the spacing s1 is different from the spacing s2. In some embodiments, the spacing s1 and the spacing s2 are both approximately equal to the thickness t1 of the semiconductor layer 210. In addition, the channel layer 215' in the n-type gate region 240-1 has a length l1 along the x-direction and a width w1 along the y-direction, and the channel layer 215' in the p-type gate region 240-2 has a length l2 along the y-direction and a width w2 along the x-direction. In the illustrated embodiment, the length l1 is approximately equal to the length l2, and the width w1 is approximately equal to the width w2, but the present invention contemplates embodiments in which the length l1 is different from the length l2 and / or the width w1 is different from the width w2. In some embodiments, the length l1 and / or the length l2 is from about 10 nm to about 50 nm. In some embodiments, the width w1 and / or the width w2 is from about 4 nm to about 10 nm. In some embodiments, each channel layer 215' has nanometer dimensions and may be referred to as a "nanowire," which generally refers to a channel layer suspended in a manner that allows a metal gate to physically contact at least two sides of the channel layer, and in a GAA transistor, will allow the metal gate to physically contact at least four sides of the channel layer (i.e., surrounding the channel layer). In such an embodiment, the vertical stack of suspended channel layers may be referred to as a nanostructure, and FIG. 10A to FIG. 10DThe process shown in is called a channel nanowire release process. In some embodiments, after removing the semiconductor layer 210, an etching process is performed to modify the profile of the channel layer 215' to obtain a desired size and / or a desired shape (e.g., cylindrical (e.g., nanowire), rectangular (e.g., nanobar), sheet (e.g., nanosheet), etc.). The present invention also contemplates an embodiment in which the channel layer 215' (nanowire) has a sub-nanometer size depending on the design requirements of the multi-gate device 200.

[0035] Steering FIG. 11A to FIG. 11D , a gate dielectric layer is formed over the multi-gate device 200, wherein the gate dielectric layer partially fills the gate trench 275 and wraps (surrounds) the channel layer 215' in the n-type gate region 240-1 and the p-type gate region 240-2 of the gate structure 240. In the illustrated embodiment, the gate dielectric layer includes an interface layer 280 and a high-k dielectric layer 282, wherein the interface layer 280 is disposed between the high-k dielectric layer 282 and the channel layer 215'. In the illustrated further embodiment, the interface layer 280 and the high-k dielectric layer 282 partially fill the gap 277A between the channel layer 215' in the n-type gate region 240-1 and between the channel layer 215' and the substrate 202, and partially fill the gap 277B between the channel layer 215' in the p-type gate region 240-2 and between the channel layer 215' and the substrate 202. In some embodiments, an interface layer 280 and / or a high-k dielectric layer 282 are also disposed on the substrate 202, the isolation features 230, and / or the gate spacers 247. The interface layer 280 includes a dielectric material such as SiO2, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. The high-k dielectric layer 282 includes a high-k dielectric material such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x, ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), Si3N4, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof. High-k dielectric materials generally refer to dielectric materials with high dielectric constants, for example, dielectric constants greater than the dielectric constant of silicon oxide (k≈3.9). The interface layer 280 is formed by any process described herein, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof. In some embodiments, the interface layer 280 has a thickness of about 0.5 nm to about 3 nm. High-k dielectric layer 282 is formed by any process described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. In some embodiments, high-k dielectric layer 282 has a thickness of about 1 nm to about 2 nm.

[0036] Steering FIG. 12A to FIG. 12D, a sacrificial (dummy) layer 284 is deposited over the multi-gate device 200, wherein the sacrificial layer 284 partially fills the gate trench 275 and wraps (surrounds) the channel layer 215' in the n-type gate region 240-1 and the p-type gate region 240-2. For example, the sacrificial layer 284 is deposited on the gate dielectric layer by any process described herein (e.g., ALD, CVD, PVD, other suitable processes, or combinations thereof). In the illustrated embodiment, the sacrificial layer 284 is disposed on the high-k dielectric layer 282 and surrounds the high-k dielectric layer 282, the interface layer 280, and the channel layer 215'. For example, the sacrificial layer 284 is arranged along the sidewalls, top, and bottom of the channel layer 215'. The thickness of the sacrificial layer 284 is configured to fill any remaining portion of the gap 277A between the channel layers 215' in the n-type gate region 240-1 and any remaining portion of the gap 277B between the channel layers 215' in the p-type gate region 240-2, without filling the gate trench 275 (i.e., any portion of the gaps 277A, 277B is not filled by the gate dielectric layer). In some embodiments, the thickness of the sacrificial layer 284 is about 0.5 nm to about 5 nm. The sacrificial layer 284 includes a material different from the high-k dielectric material to achieve an etch selectivity between the sacrificial layer 284 and the high-k dielectric layer 282 during the etching process, so that the sacrificial layer 284 can be selectively etched with minimal (to no) etching of the high-k dielectric layer 282. The material of the sacrificial layer 284 is also different from the p-type work function material of the p-type work function layer (e.g., later formed as part of the gate electrode of the gate structure 240) to achieve an etch selectivity between the sacrificial layer 284 and the p-type work function layer during the etching process, so that the sacrificial layer 284 can be selectively etched with minimal (to no) etching of the p-type work function layer, and vice versa. The material of the sacrificial layer 284 can also be different from the low-k dielectric material to achieve an etch selectivity between the sacrificial layer 284 and the low-k dielectric material (such as the material of the ILD layer 270) during the etching process, so that the sacrificial layer 284 can be selectively etched with minimal (to no) etching of the ILD layer 270. In some embodiments, the sacrificial layer 284 includes a metal and oxygen (and thus can be referred to as a metal oxide layer), such as aluminum and oxygen (e.g., AlO x ). In some embodiments, sacrificial layer 284 comprises polysilicon. In some embodiments, sacrificial layer 284 comprises silicon. In some embodiments, sacrificial layer 284 comprises a dielectric material comprising silicon, such as SiO2, SiN, SiON, other suitable dielectric materials comprising silicon, or combinations thereof. The present invention contemplates that sacrificial layer 284 comprises other semiconductor materials and / or other dielectric materials that can provide the desired etch selectivity as described herein.

[0037] Steering FIG. 13A to FIG. 13D, an etching process is performed to partially remove the sacrificial layer 284, so that the sacrificial layer 284 is patterned as a sacrificial (dummy) feature 284' between the channel layer 215' in the n-type gate region 240-1 and the p-type gate region 240-2 and between the channel layer 215' and the substrate 202. In some embodiments, the etching process is a wet etching process, and the wet etching process uses an etching solution with a high etching selectivity for the sacrificial layer 284 relative to the high-k dielectric layer 282. In some embodiments, the etching solution exhibits an etching selectivity of about 10 to about 100 (i.e., the ratio of the etching rate of the sacrificial layer 284 to the etching solution to the etching rate of the high-k dielectric layer 282 to the etching solution). In some embodiments, the etching selectivity is greater than or equal to 100 to 100. In some embodiments, the wet etching process uses an NH4OH-based wet etching solution. The parameters of the etching process (such as etching temperature, etching solution concentration, etching time, other suitable wet etching parameters, or combinations thereof) are controlled (adjusted) to remove the sacrificial layer 284 from the sidewalls of the channel layer 215' and from above the isolation features 230, while minimally (to no) etching the high-k dielectric layer 282. For example, the etching time (i.e., the time the sacrificial layer 284 is exposed to the ammonia-based wet etching solution) is adjusted to remove the sacrificial layer 284 along the sidewalls of the channel layer 215' and along the topmost portion of the high-k dielectric layer 282 (i.e., the portion of the high-k dielectric layer 282 disposed above the top surface of the topmost channel layer 215'). In a further example, the etching time is further adjusted to achieve lateral etching of the sacrificial layer 284 (e.g., along the x-direction and / or the y-direction) until the width of the sacrificial member 284' (here, along the x-direction) is less than the sum of the width of the channel layer 215' and the thickness of the gate dielectric (here, the sum of the thickness of the interface layer 280 and the thickness of the high-k dielectric layer 282). In some embodiments, the width of the sacrificial member 284' is substantially equal to the width of the channel layer 215'. The sidewalls of the sacrificial member 284' are thus recessed along the x-direction relative to the sidewalls of the high-k dielectric layer 282 by a distance d. In some embodiments, the distance d is greater than 0, for example, from about 0.5 nm to about 5 nm. In some embodiments, the sidewalls are not recessed along the x-direction relative to the sidewalls of the high-k dielectric layer 282, such that the distance d is equal to 0.

[0038] Steering FIG. 14A to FIG. 14D, the sacrificial component 284' is removed from the p-type gate region 240-2 by implementing a photolithography process and an etching process. For example, a patterned mask layer 290 having one or more openings 292 is formed above the multi-gate device 200 by a photolithography process. The patterned mask layer 290 covers the n-type GAA transistor region including the n-type gate region 240-1. The patterned mask layer 290 includes a material different from the material of the sacrificial component 284' and the material of the high-k dielectric layer 282 to achieve etching selectivity during the removal of the sacrificial component 284'. For example, the patterned mask layer 290 includes a photoresist material (and therefore can be referred to as a patterned photoresist layer and / or a patterned photoresist layer). In some embodiments, the patterned mask layer 290 has a multi-layer structure, such as a photoresist layer disposed above an anti-reflective coating (ARC). The present invention contemplates other materials for the patterned mask layer 290, as long as etching selectivity is achieved during the removal of the sacrificial component 284'. In some embodiments, the photolithography process includes forming a photoresist layer (e.g., by spin coating) above the multi-gate device 200, performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process. During the exposure process, the photoresist layer is exposed to radiation energy (e.g., UV light, DUV light, or EUV light), wherein depending on the mask pattern and / or mask type of the mask (e.g., a binary mask, a phase-shift mask, or an EUV mask), the mask blocks, transmits, and / or reflects radiation to the photoresist layer, so that an image is projected onto the photoresist layer corresponding to the mask pattern. Since the photoresist layer is sensitive to radiation energy, the exposed portion of the photoresist layer undergoes a chemical change, and depending on the characteristics of the photoresist layer and the characteristics of the developing solution used in the development process, the exposed (or unexposed) portion of the photoresist layer dissolves. After development, the patterned photoresist layer (e.g., patterned mask layer 290) includes a photoresist pattern corresponding to the mask, wherein the patterned photoresist layer covers the n-type GAA transistor region including the n-type gate region 240-1 and exposes the p-type GAA transistor region including the p-type gate region 240-2. Alternatively, the exposure process may be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing, or a combination thereof.

[0039] Then, when removing the sacrificial members 284' between the channel layers 215' and between the channel layers 215' and the substrate 202, the etching process uses the patterned mask layer 290 as an etching mask to expose the high-k dielectric layer 282 in the p-type gate region 240-2. The etching process substantially re-forms a portion of the gap 277B in the p-type gate region 240-2. In some embodiments, the etching process is a wet etching process that uses an etching solution having a high etching selectivity for the sacrificial members 284' relative to the high-k dielectric layer 282. In some embodiments, the etching solution exhibits an etching selectivity of about 10 to about 100. In some embodiments, the etching selectivity is greater than or equal to 100. In some embodiments, the wet etching process uses an NH4OH-based wet etching solution. The parameters of the etching process (such as etching temperature, etching solution concentration, etching time, other suitable wet etching parameters, or combinations thereof) are controlled to ensure complete removal of the sacrificial members 284' in the p-type gate region 240-2. For example, the etching time (i.e., the time the sacrificial member 284' is exposed to the ammonia-based wet etching solution) is adjusted to completely remove the sacrificial member 284' while minimally (to no) etching the high-k dielectric layer 282. In some embodiments, the etching time for completely removing the sacrificial member 284' is greater than the etching time for patterning the sacrificial layer 284 into the sacrificial member 284'. In some embodiments, the etching solution has an etching selectivity for the sacrificial member 284' relative to the patterned mask layer 290. In some embodiments, the etching process partially etches the patterned mask layer 290. After the etching process, the patterned mask layer 290 can be removed from the multi-gate device 200, for example, by a photoresist stripping process or other suitable process.

[0040] Steering FIG. 15A to FIG. 15D, a p-type work function layer 300 is formed over the multi-gate device 200 (particularly over the high-k dielectric layer 282). For example, the ALD process conformally deposits the p-type work function layer 300 on the high-k dielectric layer 282 so that the p-type work function layer 300 has a substantially uniform thickness and partially fills the gate trench 275. In the p-type gate region 240-2, the p-type work function layer 300 is disposed on the high-k dielectric layer 282 and surrounds the high-k dielectric layer 282, the interface layer 280, and the channel layer 215'. For example, the p-type work function layer 300 is disposed along the sidewalls, top, and bottom of the channel layer 215'. The thickness of the p-type work function layer 300 is configured to at least partially fill the gap 277B between the channel layer 215' and between the channel layer 215' and the substrate 202 (and in some embodiments, the gate trench 275 is not filled along the gate length direction (here, along the y direction)). In some embodiments, the p-type work function layer 300 has a thickness of about 1 nm to about 10 nm. In contrast, in the n-type gate region 240-1, the p-type work function layer 300 is disposed along the sidewalls of the channel layer 215' and the top surface of the topmost channel layer 215'. The sacrificial member 284' thus acts as a deposition stop layer, preventing the p-type work function layer 300 from being significantly deposited in the gap 277A between the channel layer 215' and the substrate 202 in the n-type gate region 240-1. In the illustrated embodiment, the p-type work function layer 300 is also disposed along the sidewalls of the sacrificial member 284'. The p-type work function layer 300 includes any suitable p-type work function material, such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function materials, or combinations thereof. In the illustrated embodiment, the p-type work function layer 300 includes titanium and nitrogen, such as TiN. The P-type work function layer 300 may be formed using another suitable deposition process, such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, plating, other deposition processes, or a combination thereof.

[0041] Steering FIG. 16A to FIG. 16D, for example, by performing a photolithography process and an etching process, the p-type work function layer 300 is removed from the n-type gate region 240-1 of the gate structure 240. For example, a patterned mask layer 310 having one or more openings 312 is formed over the multi-gate device 200 by a photolithography process, such as the photolithography process described above for forming the patterned mask layer 290. The patterned mask layer 310 covers the p-type gate region 240-2 of the gate structure 240. The patterned mask layer 310 includes a material different from the material of the p-type work function layer 300, the material of the sacrificial member 284', and the material of the high-k dielectric layer 282 to achieve etching selectivity during the removal of the p-type work function layer 300. For example, the patterned mask layer 310 includes a photoresist material. In some embodiments, the patterned mask layer 310 has a multi-layer structure, such as a photoresist layer disposed over the ARC layer. The present invention contemplates other materials for the patterned mask layer 310 as long as etch selectivity is achieved during the removal of the p-type work function layer 300 from the n-type gate region 240 - 1 .

[0042] Then, the p-type work function layer 300 is completely removed from the n-type gate region 240-1 using any suitable process, thereby exposing the high-k dielectric layer 282 in the n-type gate region 240-1. In some embodiments, the etching process is a wet etching process that uses an etching solution having a high etching selectivity for the p-type work function layer 300 relative to the high-k dielectric layer 282 and the sacrificial member 284'. In some embodiments, the etching solution exhibits an etching selectivity of about 10 to about 100 (i.e., the ratio of the etching rate of the etching solution on the p-type work function layer 300 to the etching rate of the etching solution on the high-k dielectric layer 282 (and / or the sacrificial member 284)). In some embodiments, the etching selectivity is greater than or equal to 100. In some embodiments, the wet etching process uses a wet etching solution including NH4OH, HCl, and dioxadiazine (N2H2) (in other words, a NH4OH:HCl:N2H2 solution). The parameters of the etching process (such as etching temperature, etching solution concentration, etching time, other suitable wet etching parameters, or combinations thereof) are controlled (adjusted) to remove the p-type work function layer 300 while minimally (to no) etching the high-k dielectric layer 282 and / or the sacrificial member 284'. In some embodiments, the wet etching solution includes NH4OH, hydrogen peroxide (H2O2), sulfuric acid (H2SO4), tetramethylammonium hydroxide (TMAH), HCl, other suitable wet etching solutions, or combinations thereof. For example, the wet etching solution may utilize NH4OH:H2O2 solution, HCl:H2O2:H2O solution (referred to as a hydrochloric acid-hydrogen peroxide mixture (HPM)), NH4OH:H2O2:H2O solution (referred to as an ammonia-hydrogen peroxide mixture (APM)), or H2SO4:H2O2 solution (referred to as a sulfuric acid-hydrogen peroxide mixture (SPM)). In some embodiments, a dry etching process or a combination of a dry etching process and a wet etching process is performed to remove the p-type work function layer 300. After the etching process, the patterned mask layer 310 may be removed from the multi-gate device 200 , for example, by a photoresist stripping process or other suitable process.

[0043] In some embodiments, the etching process is not an over-etching process, which generally refers to an etching process that is performed for a longer time than the expected etching time required to remove a given material. In conventional GAA gate replacement processes, an over-etching process is often required to completely remove the p-type work function layer 300 from the n-type gate region 240-1 (particularly from between the channel layer 215' and between the channel layer 215' and the substrate 202). However, it has been observed that the over-etching process may undesirably laterally etch a portion of the p-type work function layer 300 in the p-type gate region 240-2 below the patterned mask layer 310 at the boundary 315 between the n-type gate region 240-1 and the p-type gate region 240-2 (commonly referred to as the n / p boundary or mixed threshold voltage boundary). One solution to mitigate the lateral loss of the metal gate at the boundary 315 is to limit the thickness of the p-type work function layer 300, which limits the threshold voltage adjustment of the p-type GAA transistor. The proposed GAA gate replacement process overcomes such problems by forming a sacrificial member 284' between the channel layer 215' in the n-type gate region 240-1 and between the channel layer 215' and the substrate 202 before forming the p-type work function layer of the gate electrode. This eliminates the need for an over-etching process to remove the p-type work function layer (such as the p-type work function layer 300) from between the channel layer 215' in the n-type gate region 240-2 and between the channel layer 215' and the substrate 202, and allows for a thicker p-type work function layer in the p-type gate region 240-2, increases the threshold voltage adjustment flexibility for the p-type GAA transistor, and avoids an unexpected increase in the threshold voltage of the p-type GAA transistor. For example, in some embodiments, the etching time of the etching process for removing the p-type work function layer 300 is not configured to ensure the removal of the p-type work function material between the channel layer 215' in the n-type gate region 240-1 and between the channel layer 215' and the substrate 202. Different embodiments may have different advantages, and no particular advantage is required of any embodiment.

[0044] refer to FIG. 15A to FIG. 15D and FIG. 16A to FIG. 16D The process described may be referred to as a p-type work function layer deposition / etching cycle, and the present invention proposes to repeat the process until the gate dielectric and the p-type work function layer completely fill the gate trench 275 along the gate length direction in the p-type gate region 240-2 of the gate structure 240. For example, in Fig.15D and Fig.16DIn the embodiment, the interfacial layer 280, the high-k dielectric layer 282, and the p-type work function layer 300 do not completely fill the gate trench 275 in the p-type gate region 240-2 along the gate length direction. Therefore, additional p-type work function layer deposition / etching cycles are performed until the gate trench 275 in the p-type gate region 240-2 is completely filled along the gate length direction by the interfacial layer 280, the high-k dielectric layer 282, and the p-type work function layer (including the p-type work function layer 300). In some embodiments, the p-type work function layer deposition / etching cycles are performed until the thickness T of the combined p-type work function layer is greater than or equal to about half of the gate length (i.e., T≥Lg), wherein the thickness T is defined between the sidewalls of the high-k dielectric layer 282 and the sidewalls of the p-type work function layer (both disposed along the sidewalls of the channel layer 215'). The gate trench 275 completely filled in the p-type gate region 240-1 along the gate length direction ensures that the subsequently formed n-type work function layer is formed over the gate structure 240 (particularly over the gate spacer 247) along the gate length direction, so that the p-type gate region 240-2 does not include residues of the n-type work function layer along the gate length direction, which would adversely change the desired threshold voltage of the p-type GAA transistor of the p-type gate region 240-2. Different embodiments may have different advantages, and no particular advantage is required by any embodiment.

[0045] Steering 17A to 17D, a p-type work function layer 320 is formed over the multi-gate device 200 (particularly over the high-k dielectric layer 282 in the n-type gate region 240-1 of the gate structure 240 and over the p-type work function layer 300 in the p-type gate region 240-2 of the gate structure 240). For example, the ALD process conformally deposits the p-type work function layer 320 over the high-k dielectric layer 282 and the p-type work function layer 300, so that the p-type work function layer 320 has a substantially uniform thickness and partially fills the gate trench 275 along the gate length direction in the n-type gate region 240-1, and completely fills any remaining portion of the gate trench along the gate length direction in the p-type gate region 240-2. In the p-type gate region 240-2, the p-type work function layer 320 is disposed on the p-type work function layer 300 and surrounds the p-type work function layer 300, the high-k dielectric layer 282, the interface layer 280, and the channel layer 215'. For example, the p-type work function layer 320 is disposed along the sidewalls, top, and bottom of the channel layer 215'. The thickness of the p-type work function layer 320 is configured to fill any remaining portion of the gap 277B between the channel layers 215' and between the channel layer 215' and the substrate 202. In some embodiments, the thickness of the p-type work function layer 320 is about 1 nm to about 10 nm. In the embodiment shown, the thickness T (i.e., the sum of the thickness of the p-type work function layer 300 and the thickness of the p-type work function layer 320) is greater than or equal to about half of the gate length (i.e., T≥Lg). In some embodiments, the thickness T is about 2 nm to about 20 nm. In contrast, in the n-type gate region 240-1 of the gate structure 240, the p-type work function layer 320 is disposed along the sidewalls of the channel layer 215' and the top surface of the topmost channel layer 215'. The sacrificial member 284' thus again serves as a deposition stop layer, preventing significant deposition of the p-type work function layer 320 between the channel layer 215' in the n-type gate region 240-1 and between the channel layer 215' and the substrate 202. In the illustrated embodiment, the p-type work function layer 320 is disposed along the sidewalls of the sacrificial member 284'. The p-type work function layer 320 includes any suitable p-type work function material, such as TiN, TaN, TaSN, Ru, Mo, Al, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, other p-type work function materials, or combinations thereof. In the illustrated embodiment, the p-type work function layer 320 includes titanium and nitrogen, such as TiN. The p-type work function layer 320 can be formed using another suitable deposition process, such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, plating, other deposition processes, or combinations thereof.

[0046] Steering 18A to 18D, for example, by performing a photolithography process and an etching process, the p-type work function layer 320 is removed from the n-type gate region 240-1 of the gate structure 240. For example, a patterned mask layer 330 having one or more openings 332 is formed over the multi-gate device 200 by a photolithography process (such as the photolithography process for forming the patterned mask layer 290 described above). The patterned mask layer 330 covers the p-type gate region 240-2 of the gate structure 240. The patterned mask layer 330 includes a material different from the material of the p-type work function layer 320, the material of the sacrificial member 284', and the material of the high-k dielectric layer 282 to achieve etching selectivity during the removal of the p-type work function layer 320. For example, the patterned mask layer 330 includes a photoresist material. In some embodiments, the patterned mask layer 330 has a multi-layer structure, such as a photoresist layer disposed above the ARC layer. The present invention contemplates other materials for the patterned mask layer 330, so long as etch selectivity is achieved during the removal of the p-type work function layer 320 from the n-type gate region 240-1. Any suitable process (such as the etching process described above for removing the p-type work function layer 300) is then used to completely remove the p-type work function layer 320 from the n-type gate region 240-1, thereby exposing the high-k dielectric layer 282 in the n-type gate region 240-1. In some embodiments, the patterned mask layer 330 may intentionally or unintentionally (e.g., due to overlay shift associated with the photolithography process) cover portions of the n-type gate region 240-1 at the boundary 315, such as Fig.18B As shown. This results in the p-type work function layer having different thicknesses (e.g., along the z direction) at the boundary 315, such as thickness t3 and thickness t4. In some embodiments, the difference between thickness t4 (e.g., the sum of the thickness of the p-type work function layer 300 and the thickness of the p-type work function layer 320) and thickness t3 (substantially equal to the thickness of the p-type work function layer 300) is greater than or equal to about 1 nm. After the etching process, the patterned mask layer 330 can be removed from the multi-gate device 200, for example, by a photoresist stripping process or other suitable process.

[0047] Steering 19A to 19D, the sacrificial member 284' is removed from the n-type gate region 240-1 of the gate structure 240 by performing an etching process. In the embodiment shown, the sacrificial member 284' is removed from between the channel layer 215' and between the channel layer 215' and the substrate 202, thereby exposing the high-k dielectric layer 282 in the n-type gate region 240-1. The etching process substantially re-forms a portion of the gap 277A in the n-type gate region 240-1. In some embodiments, the etching process is a wet etching process, and the wet etching process uses an etching solution with high etching selectivity for the sacrificial member 284' relative to the high-k dielectric layer 282 and the p-type work function layer 330. In some embodiments, the etching solution exhibits an etching selectivity of about 10 to about 100. In some embodiments, the etching selectivity is greater than or equal to 100. In some embodiments, the wet etching process uses an NH4OH-based wet etching solution. Control the parameters of the etching process (such as etching temperature, etching solution concentration, etching time, other suitable wet etching parameters, or combinations thereof) to ensure complete removal of the sacrificial member 284' in the n-type gate region 240-1. For example, the etching time (i.e., the time the sacrificial features 284' are exposed to the ammonia-based wet etching solution) is adjusted to completely remove the sacrificial features 284' while minimally (to no) etching the high-k dielectric layer 282 and the p-type work function layer 330. In some embodiments, the etching time for completely removing the sacrificial features 284' is greater than the etching time for patterning the sacrificial layer 284 into the sacrificial features 284'. In some embodiments, the etching time for completely removing the sacrificial features 284' from between the channel layers 215' and from between the channel layers 215' and the substrate 202 is greater than the etching time required to remove the material of the sacrificial features 284' from above the portions of the gate dielectric layer disposed above the ILD layer 270, the gate spacers 247, and / or the isolation features 230. The etching process can therefore be configured as an over-etching process to ensure complete removal of the sacrificial features 284'. The etching solution used in the over-etching process is configured to have a high etching selectivity for the sacrificial member 284' relative to the p-type work function layer 300, 320 to reduce (or eliminate) the problem of lateral loss of the p-type work function layer 300, 320 in the p-type gate region 240-2 at the boundary 315. In some embodiments, the etching solution also has an etching selectivity for the sacrificial member 284' relative to the patterned mask layer. In some embodiments, the etching process partially removes (etches) the patterned mask layer. In some embodiments, during the removal of the sacrificial member 284' from the n-type gate region 240-1, the patterned mask layer 330 remains above the p-type gate region 240-2, and the etching process then uses the patterned mask layer 330 as an etching mask. In such an embodiment, after the etching process, the patterned mask layer 330 can be removed, for example, by a photoresist stripping process or other suitable process.

[0048] Steering FIG. 20A to FIG. 20D , an n-type work function layer 340 is formed over the multi-gate device 200 (particularly over the high-k dielectric layer 282 in the n-type gate region 240-1 of the gate structure 240 and over the p-type work function layer 320 in the p-type gate region 240-2 of the gate structure 240). For example, the ALD process conformally deposits the n-type work function layer 340 on the high-k dielectric layer 282 and the p-type work function layer 320, so that the n-type work function layer 340 has a substantially uniform thickness and partially fills the gate trench 275 along the gate length direction in the n-type gate region 240-1. In the n-type gate region 240-1, the n-type work function layer 340 is disposed on the high-k dielectric layer 282 and surrounds the high-k dielectric layer 282, the interface layer 280, and the channel layer 215'. For example, the n-type work function layer 340 is disposed along the sidewalls, top, and bottom of the channel layer 215'. In contrast, in the p-type gate region 240-2, because the disclosed gate replacement process ensures that the gate trench 275 (e.g., the gate dielectric (i.e., the high-k dielectric layer 282 and the interface layer 280) and the p-type work function layer (i.e., the p-type work function layer 300 and the p-type work function layer 320)) are filled along the gate length direction in the p-type gate region 240-2, an n-type work function layer 340 is formed over the gate structure 240 (particularly over the gate spacer 247) in the p-type gate region 240-2. This prevents the n-type work function layer 340 or any remnant (residue) thereof from affecting the threshold voltage of the p-type GAA transistor, particularly for a short-channel p-type GAA transistor. In the illustrated embodiment, the thickness of the n-type work function layer 340 completely fills the remaining portion of the gap 277B between the channel layer 215' and between the channel layer 215' and the substrate 202 in the n-type gate region 240-1. In some embodiments, the n-type work function layer 340 has a thickness of about 1 nm to about 5 nm. In some embodiments, the thickness of the n-type work function layer 340 is less than the thickness of the p-type work function layer (i.e., the combined thickness of the p-type work function layer 300 and the p-type work function layer 320). The n-type work function layer 340 includes any suitable n-type work function material, such as Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TaAl, TaAlC, TaSiAlC, TiAlN, other n-type work function materials, or combinations thereof. In the illustrated embodiment, the n-type work function layer 340 includes aluminum. For example, the n-type work function layer 340 includes titanium and aluminum, such as TiAl, TiAlC, TaSiAl, or TiSiAlC. Alternatively, the n-type work function layer 340 is formed using another suitable deposition process, such as CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, plating, other deposition processes, or combinations thereof.

[0049] Steering FIG. 21A to FIG. 21D , the n-type work function layer 340 is removed from the p-type gate region 240-2 of the gate structure 240, for example, by performing a photolithography process and an etching process. For example, a patterned mask layer 345 having one or more openings 347 is formed above the multi-gate device 200 by a photolithography process, such as the photolithography process described above for forming the patterned mask layer 290. The patterned mask layer 345 covers the n-type gate region 240-1 of the gate structure 240. The patterned mask layer 345 includes a material different from the material of the n-type work function layer 340 to achieve etching selectivity during the removal of the n-type work function layer 340. For example, the patterned mask layer 345 includes a photoresist material. In some embodiments, the patterned mask layer 345 has a multi-layer structure, such as a photoresist layer disposed above the ARC layer. The present invention contemplates other materials for the patterned mask layer 345, as long as etching selectivity is achieved during the removal of the n-type work function layer 340 from the n-type gate region 240-1. Then, any suitable process (such as the etching process described herein) is used to completely remove the n-type work function layer 340 from the p-type gate region 240-2, thereby exposing the p-type work function layer 320 in the p-type gate region 240-2. After the etching process, the patterned mask layer 345 can be removed from the multi-gate device 200, for example, by a photoresist stripping process or other suitable process.

[0050] Steering FIG. 22A to FIG. 22D, a metal fill (or body) layer 350 is formed over the multi-gate device 200 (particularly over the n-type work function layer 340 in the n-type gate region 240-1 and over the p-type work function layer 320 in the p-type gate region 240-2). For example, a CVD process or a PVD process deposits the metal fill layer 350 on the n-type work function layer 340 and the p-type work function layer 320, so that the metal fill layer 350 fills any remaining portion of the gate trench 275, including any remaining portion of the gap 277A in the n-type gate region 240-1. The metal fill layer 350 includes a suitable conductive material, such as Al, W and / or Cu. The metal fill layer 350 may additionally or collectively include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof. In some embodiments, before forming the metal fill layer 350, a barrier layer is optionally formed over the n-type work function layer 340 and the p-type work function layer 320, so that the metal fill layer 350 is disposed on the barrier layer. For example, the ALD process conformally deposits a barrier layer on the n-type work function layer 340 and the p-type work function layer 320, so that the barrier layer has a substantially uniform thickness and partially fills the gate trench 275. The barrier layer includes a material that blocks and / or reduces diffusion between gate layers such as the metal fill layer 350 and the n-type work function layer 340 and / or the p-type work function layer 300, 320. Alternatively, the metal fill layer 350 and / or the barrier layer are formed using another suitable deposition process, such as ALD, CVD, PVD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, spin coating, plating, other deposition processes, or combinations thereof.

[0051] Steering FIG. 23A to FIG. 23D, a planarization process is performed to remove excess gate material from the multi-gate device 200. For example, a CMP process is performed until the top surface of the ILD layer 270 is reached (exposed), so that after the CMP process, the top surface of the gate structure 240 is substantially flush with the top surface of the ILD layer 270. In the illustrated embodiment, the gate structure 240 is thus configured to have two different metal gate portions-n-metal gate 360A in the n-type gate region 240-1 and p-metal gate 360B in the p-type gate region 240-2. The metal gate 360A includes a gate dielectric (e.g., an interface layer 280 and a high-k dielectric layer 282) and a gate electrode (e.g., an n-type work function layer 340 and a metal fill layer 350). The metal gate 360B includes a gate dielectric (e.g., the interface layer 280 and the high-k dielectric layer 282) and a gate electrode (e.g., a p-type work function layer 362 (e.g., the p-type work function layer 300 and the p-type work function layer 320) and a metal fill layer 350). Therefore, the multi-gate device 200 includes an n-type GAA transistor having a metal gate 360A wrapping a corresponding channel layer 215' so that the metal gate 360A is disposed between corresponding epitaxial source / drain features 260A, and a p-type GAA transistor having a metal gate 360B wrapping a corresponding channel layer 215' so that the metal gate 360B is disposed between corresponding epitaxial source / drain features 260B.

[0052] Manufacturing can continue to continue manufacturing multi-gate device 200. For example, various contacts can be formed to facilitate the operation of n-type GAA transistors and p-type GAA transistors. For example, one or more ILD layers and / or CESL layers similar to ILD layer 270 can be formed above substrate 202 (particularly above ILD layer 270 and gate structure 240). Contacts can then be formed in ILD layer 270 and / or an ILD layer disposed above ILD layer 270. For example, the contacts are electrically and / or physically coupled to gate structure 240, respectively, and the contacts are electrically and / or physically coupled to source / drain regions (particularly epitaxial source / drain components 260A, 260B) of n-type GAA transistors and p-type GAA transistors, respectively. The contacts include conductive materials, such as metals. Metals include aluminum, aluminum alloys (such as aluminum / silicon / copper alloys), copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or a combination thereof. In some embodiments, the ILD layer disposed above the ILD layer 270 and the contacts (e.g., extending through the ILD layer 270 and / or other ILD layers) are part of the MLI component described above.

[0053] The present invention provides many different embodiments. An exemplary method includes forming a gate dielectric layer in a gate trench in a gate structure. A gate dielectric layer is formed around a first channel layer in a p-type gate region and around a second channel layer in an n-type gate region. The method also includes forming a p-type work function layer in the gate trench above the gate dielectric layer in the p-type gate region and the n-type gate region. In some embodiments, the p-type work function layer completely fills the gate trench along the gate length direction. Before forming the p-type work function layer, a sacrificial component is formed between the second channel layers in the n-type gate region, and after removing the p-type work function layer from the gate trench in the n-type gate region, the sacrificial component between the second channel layers in the n-type gate region is removed. In some embodiments, removing the sacrificial component between the second channel layers in the n-type gate region includes performing an etching process that selectively etches the sacrificial component without substantially etching the p-type work function layer. In some embodiments, the p-type work function layer is removed from the gate trench in the n-type gate region by performing an etching process that selectively etches the p-type work function layer without substantially etching the gate dielectric layer and the sacrificial component. The method also includes forming an n-type work function layer in the gate trench above the gate dielectric layer in the n-type gate region. The n-type work function layer surrounds the gate dielectric layer and the second channel layer in the n-type gate region. The method also includes forming a metal fill layer in the gate trench above the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region. In some embodiments, the n-type work function layer is also formed in the gate trench above the p-type work function layer in the p-type gate region. In such an embodiment, the n-type work function layer is disposed above the gate spacer of the gate structure, and the gate trench is free of the n-type work function layer along the gate length of the gate trench in the p-type gate region. In such an embodiment, the n-type work function layer is removed from the gate trench in the p-type gate region before forming the metal fill layer.

[0054] In some embodiments, forming a sacrificial component in a gate trench between the second channel layers in the n-type gate region includes forming a sacrificial layer over a gate dielectric layer in the gate trench. The sacrificial layer and the gate dielectric layer fill the gap between the first channel layers in the p-type gate region, and the gate dielectric layer and the sacrificial layer fill the gap between the second channel layers in the n-type gate region. Then, the sacrificial layer is patterned to form a sacrificial component between the first channel layers in the p-type gate region and between the second channel layers in the n-type gate region. The sacrificial component is removed from between the first channel layers in the p-type gate region. In some embodiments, removing the sacrificial component from between the first channel layers in the p-type gate region includes performing a photolithography process to form a patterned mask layer covering the n-type gate region and exposing the p-type gate region, and performing an etching process to remove the sacrificial component in the p-type gate region. The etching process may use the patterned mask layer as an etching mask.

[0055] In some embodiments, forming the p-type work function layer includes forming a first p-type work function layer in a gate trench over the gate dielectric layer in the p-type gate region and the n-type gate region, and forming a second p-type work function layer in a gate trench over the first p-type work function layer in the p-type gate region and over the gate dielectric layer in the n-type gate region. In such embodiments, removing the p-type work function layer from the gate trench in the n-type gate region includes removing the first p-type work function layer from the gate trench in the n-type gate region before forming the second p-type work function layer, and removing the second p-type work function layer from the gate trench in the n-type gate region. In some embodiments, the first p-type work function layer is removed from the gate trench in the n-type gate region by performing a first photolithography process and a first etching process, wherein the first photolithography process forms a mask layer covering the p-type gate region. In some embodiments, the second p-type work function layer is removed from the gate trench in the n-type gate region by performing a second photolithography process and a second etching process, wherein the second photolithography process forms a mask layer covering the p-type gate region and a portion of the n-type gate region at a boundary of the p-type gate region and the n-type gate region.

[0056] Another exemplary method includes depositing a gate dielectric layer over a first semiconductor layer in a p-type gate region and over a second semiconductor layer in an n-type gate region, wherein the gate dielectric layer wraps around the first semiconductor layer and the second semiconductor layer. After depositing the gate dielectric layer, there is a first gap between the first semiconductor layers and a second gap between the second semiconductor layers. The method also includes depositing a sacrificial layer over the gate dielectric layer in the p-type gate region and the n-type gate region, and etching the sacrificial layer in the p-type gate region and the n-type gate region to form a first sacrificial component in the p-type gate region between the first semiconductor layers and a second sacrificial component in the n-type gate region between the second semiconductor layers. The method also includes, after removing the first sacrificial component from the p-type gate region, depositing a p-type work function layer over the gate dielectric layer in the p-type gate region and the n-type gate region. In some embodiments, the material of the sacrificial layer is different from the material of the p-type work function layer. In some embodiments, the thickness (T) of the p-type work function layer is greater than or equal to half of the gate length (Lg) (T≥0.5Lg). The method further includes removing the p-type work function layer from over the gate dielectric layer in the n-type gate region, and depositing an n-type work function layer over the gate dielectric layer in the n-type gate region after removing the second sacrificial member from the n-type gate region.

[0057] In some embodiments, etching the sacrificial layer, removing the first sacrificial component from the p-type gate region, and removing the second sacrificial component from the n-type gate region each include performing a wet etching process that selectively etches the sacrificial layer without substantially etching the gate dielectric layer. The wet etching process may utilize an ammonium hydroxide-based etching solution. The etching time of the wet etching process for etching the sacrificial layer is less than the etching time of the wet etching process for removing the first sacrificial component from the p-type gate region and removing the second sacrificial component from the n-type gate region. In some embodiments, etching the p-type work function layer includes performing a wet etching process that selectively etches the p-type work function layer without substantially etching the gate dielectric layer. The wet etching process may utilize an ammonium hydroxide / hydrogen chloride / oxadiazine-based etching solution.

[0058] An exemplary multi-gate device includes: a first channel layer disposed in a p-type gate region above a substrate; and a second channel layer disposed in an n-type gate region above the substrate. A gate stack spans the p-type gate region and the n-type gate region. The gate stack is disposed between a first epitaxial source / drain component and a second epitaxial source / drain component, the first epitaxial source / drain component being disposed in the p-type gate region, and the second epitaxial source / drain component being disposed in the n-type gate region. The gate stack includes a p-metal gate in a p-type gate region surrounding the first channel layer. The p-metal gate includes a gate dielectric layer, a p-type work function layer disposed above the gate dielectric layer, and a metal fill layer disposed above the p-type work function layer. The gate stack also includes an n-metal gate in an n-type gate region surrounding the second channel layer. The n-metal gate includes a gate dielectric layer, an n-type work function layer disposed above the gate dielectric layer, and a metal fill layer disposed above the n-type work function layer. The thickness (T) of the p-type work function layer is greater than or equal to half of the gate length (Lg) of the gate stack (T≥0.5Lg). In some embodiments, the p-type work function layer has a first thickness and a second thickness in a boundary region between the p-metal gate and the n-metal gate, wherein the difference between the first thickness and the second thickness is greater than or equal to about 1 nm. In some embodiments, the thickness of the p-type work function layer is greater than the thickness of the n-type work function layer.

[0059] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent configuration does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a multi-gate device, comprising: forming a gate dielectric layer in a gate trench in the gate structure, wherein the gate dielectric layer is formed around the first channel layer in the p-type gate region and around the second channel layer in the n-type gate region; forming a sacrificial member between the second channel layers in the n-type gate region; forming a p-type work function layer in the gate trench above the gate dielectric layer in the p-type gate region and the n-type gate region, wherein in the p-type gate region, the p-type work function layer completely fills the gate trench along a gate length direction; removing the p-type work function layer from the gate trench in the n-type gate region; After removing the p-type work function layer, removing the sacrificial component between the second channel layers in the n-type gate region; forming an n-type work function layer in the gate trench above the gate dielectric layer in the n-type gate region, wherein the n-type work function layer surrounds the gate dielectric layer and the second channel layer in the n-type gate region; and A metal filling layer is formed in the gate trench over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

2. The method according to claim 1, wherein: Forming the sacrificial member in the gate trench between the second channel layers in the n-type gate region comprises: forming a sacrificial layer over the gate dielectric layer in the gate trench, wherein the sacrificial layer and the gate dielectric layer fill the gap between the first channel layers in the p-type gate region, and the gate dielectric layer and the sacrificial layer fill the gap between the second channel layers in the n-type gate region; patterning the sacrificial layer to form the sacrificial member between the first channel layers in the p-type gate region and between the second channel layers in the n-type gate region; and The sacrificial member is removed from between the first channel layers in the p-type gate region.

3. The method according to claim 2, wherein: Removing the sacrificial member from between the first channel layers in the p-type gate region includes: performing a photolithography process to form a patterned mask layer covering the n-type gate region and exposing the p-type gate region; and An etching process is performed to remove the sacrificial member in the p-type gate region, wherein the etching process uses the patterned mask layer as an etching mask.

4. The method according to claim 1, wherein: Removing the sacrificial member between the second channel layers in the n-type gate region includes performing an etching process that selectively etches the sacrificial member without etching the p-type work function layer.

5. The method according to claim 1, wherein: Forming the p-type work function layer in the gate trench above the gate dielectric layer in the p-type gate region and the n-type gate region comprises: forming a first p-type work function layer in the gate trench over the gate dielectric layer in the p-type gate region and the n-type gate region, and forming a second p-type work function layer in the gate trench over the first p-type work function layer in the p-type gate region and over the gate dielectric layer in the n-type gate region; and Removing the p-type work function layer from the gate trench in the n-type gate region comprises: before forming the second p-type work function layer, removing the first p-type work function layer from the gate trench in the n-type gate region, and The second p-type work function layer is removed from the gate trench in the n-type gate region.

6. The method according to claim 5, wherein: Before forming the second p-type work function layer, removing the first p-type work function layer from the gate trench in the n-type gate region comprises performing a first photolithography process and a first etching process, wherein the first photolithography process forms a mask layer covering the p-type gate region; and Removing the second p-type work function layer from the gate trench in the n-type gate region includes performing a second photolithography process and a second etching process, wherein the second photolithography process forms a mask layer covering the p-type gate region and a portion of the n-type gate region at a boundary between the p-type gate region and the n-type gate region.

7. The method according to claim 1, wherein: Removing the p-type work function layer from the gate trench in the n-type gate region includes performing an etching process that selectively etches the p-type work function layer without etching the gate dielectric layer and the sacrificial feature.

8. The method according to claim 1, further comprising: forming the n-type work function layer in the gate trench above the p-type work function layer in the p-type gate region, wherein the n-type work function layer is disposed above a gate spacer of the gate structure and the gate trench is free of the n-type work function layer along a gate length of the gate trench in the p-type gate region; and Before forming the metal filling layer, the n-type work function layer is removed from the gate trench in the p-type gate region.

9. The method according to claim 1, wherein: forming the gate dielectric layer in the gate trench includes partially filling a first spacing between the first channel layers in the p-type gate region and a second spacing between the second channel layers in the n-type gate region, Forming the p-type work function layer in the gate trench over the gate dielectric layer in the p-type gate region includes filling a remaining portion between the first channel layers in the p-type gate region.

10. A method for manufacturing a multi-gate device, comprising: Depositing a gate dielectric layer over the first semiconductor layer in the p-type gate region and over the second semiconductor layer in the n-type gate region, wherein the gate dielectric layer wraps the first semiconductor layer and the second semiconductor layer, wherein after depositing the gate dielectric layer, there is a first gap between the first semiconductor layers and there is a second gap between the second semiconductor layers; depositing a sacrificial layer over the gate dielectric layer in the p-type gate region and the n-type gate region; etching the sacrificial layer in the p-type gate region and the n-type gate region to form a first sacrificial member in the p-type gate region between the first semiconductor layers and a second sacrificial member in the n-type gate region between the second semiconductor layers; depositing a p-type work function layer over the gate dielectric layer in the p-type gate region and the n-type gate region after removing the first sacrificial member from the p-type gate region; removing the p-type work function layer from over the gate dielectric layer in the n-type gate region; and After removing the second sacrificial member from the n-type gate region, an n-type work function layer is deposited over the gate dielectric layer in the n-type gate region.

11. The method according to claim 10, wherein: The material of the sacrificial layer is different from the material of the p-type work function layer.

12. The method according to claim 10, wherein: Etching the sacrificial layer, removing the first sacrificial feature from the p-type gate region, and removing the second sacrificial feature from the n-type gate region includes performing a wet etching process that selectively etches the sacrificial layer without etching the gate dielectric layer.

13. The method according to claim 12, wherein: The wet etching process utilizes an ammonium hydroxide based etching solution.

14. The method according to claim 12, wherein: An etching time of the wet etching process for etching the sacrificial layer is less than an etching time of the wet etching process for removing the first sacrificial member from the p-type gate region and removing the second sacrificial member from the n-type gate region.

15. The method according to claim 10, wherein: Etching the p-type work function layer includes performing a wet etching process that selectively etches the p-type work function layer without etching the gate dielectric layer.

16. The method according to claim 15, wherein: The wet etching process may utilize an ammonium hydroxide / hydrogen chloride / diazine based etching solution.

17. The method according to claim 10, wherein: The thickness (T) of the p-type work function layer is greater than or equal to half of the gate length (Lg) (T≥0.5Lg).

18. A multi-gate device comprising: A first channel layer is disposed in a p-type gate region above the substrate; A second channel layer is disposed in an n-type gate region above the substrate; as well as a gate stack spanning the p-type gate region and the n-type gate region, wherein the gate stack is disposed between a first epitaxial source / drain component and a second epitaxial source / drain component, the first epitaxial source / drain component being disposed in the p-type gate region, the second epitaxial source / drain component being disposed in the n-type gate region, and wherein the gate stack comprises: a p-metal gate located in the p-type gate region, wherein the p-metal gate surrounds the first channel layer and comprises a gate dielectric layer, a p-type work function layer disposed above the gate dielectric layer, and a metal filling layer disposed above the p-type work function layer, an n-metal gate located in the n-type gate region, wherein the n-metal gate surrounds the second channel layer, and the n-metal gate includes the gate dielectric layer, an n-type work function layer disposed above the gate dielectric layer, and the metal filling layer disposed above the n-type work function layer, and Wherein, the thickness (T) of the p-type work function layer is greater than or equal to half of the gate length (Lg) of the gate stack (T≥0.5Lg).

19. The multi-gate device according to claim 18, wherein: The p-type work function layer has a first thickness and a second thickness in a boundary region between the p-metal gate and the n-metal gate, wherein a difference between the first thickness and the second thickness is greater than or equal to 1 nm.

20. The multi-gate device of claim 18, wherein: The thickness of the p-type work function layer is greater than the thickness of the n-type work function layer.

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