Integrated circuit device and method for forming the same

Abstract

A transistor includes a gate structure having a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed above a substrate. The first gate dielectric layer includes a first type of dielectric material having a first dielectric constant. The second gate dielectric layer is disposed above the first gate dielectric layer. The second gate dielectric layer includes a second type of dielectric material having a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than the dielectric constant of silicon oxide. Embodiments of the present invention also relate to semiconductor devices and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuit devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each of which is smaller and more complex than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as the gate size of transistors continues to scale down at each technology node, gate leakage can become a problem. Gate leakage is undesirable because it can degrade device performance such as speed and / or power consumption. Conventional semiconductor manufacturing methods have not yet devised a satisfactory solution to this problem. Therefore, while conventional methods of manufacturing semiconductor devices are generally adequate, they are not satisfactory in all respects. Summary of the invention

[0004] According to one aspect of an embodiment of the present invention, an integrated circuit device is provided, comprising: a substrate; a first gate dielectric layer disposed above the substrate, wherein the first gate dielectric layer has a first material component; and a second gate dielectric layer disposed above the first gate dielectric layer, wherein the second gate dielectric layer has a second material component; wherein: the first material component is different from the second material component; and the first material component and the second material component each have a dielectric constant greater than the dielectric constant of silicon oxide.

[0005] According to another aspect of an embodiment of the present invention, an integrated circuit device is provided, comprising: a source region and a drain region, arranged in a substrate; a channel region, arranged between the source region and the drain region; and a gate structure, arranged above the channel region, wherein the gate structure comprises a gate dielectric component and a metal-containing gate electrode component; wherein: the gate dielectric component comprises a plurality of different dielectric layers, each of the dielectric layers having a dielectric constant greater than the dielectric constant of silicon oxide; and different dielectric layers have dielectric constants different from each other.

[0006] According to another aspect of an embodiment of the present invention, a method for forming an integrated circuit is provided, comprising: forming an interface layer above a channel region of a substrate; using a first atomic layer deposition process, depositing a first type of dielectric material as a first portion of a gate dielectric above the interface layer, wherein the first type of dielectric material has a first dielectric constant greater than the dielectric constant of silicon oxide; using a second atomic layer deposition process, depositing a second type of dielectric material as a second portion of a gate dielectric above the first type of dielectric material, wherein the second type of dielectric material has a second dielectric constant greater than the first dielectric constant; and forming a metal-containing gate electrode above the second type of dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A is a perspective view of an IC device according to various aspects of the present invention.

[0009] Figure 1B is a top plan view of an IC device according to various aspects of the present invention.

[0010] Figures 2 to 13 are cross-sectional views of IC devices at various stages of fabrication in accordance with various aspects of the present invention.

[0011] Fig.14 is a cross-sectional view of a portion of an IC device according to various aspects of the present invention and a graph indicating material concentration levels next to the IC device.

[0012] Figure 15 to Figure 16 is a cross-sectional view of an IC device at a stage of fabrication in accordance with various aspects of the present invention.

[0013] Fig.17 is a cross-sectional view of a portion of an IC device according to various aspects of the present invention and a graph indicating material concentration levels next to the IC device.

[0014] Fig.18 is a schematic diagram of an SRAM circuit cell according to various aspects of the present invention.

[0015] Fig.19 is a block diagram of a semiconductor manufacturing system according to various aspects of the present invention.

[0016] Fig. 20 is a flow chart of a method of manufacturing a semiconductor device according to various aspects of the present invention.

[0017] Fig.21 is a flow chart of a method of manufacturing a multi-gate device or portion thereof provided in accordance with one or more aspects disclosed in US Pat. No. 9,887,269 and including an isolation region under a gate. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to include different orientations of the device in use or operation. Further, when "about," "approximately," and the like are used to describe a number or a range of numbers, the term is intended to encompass numbers within a reasonable range including the described number (such as within + / - 10% of the described number or other value), as understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0020] The present invention relates generally to semiconductor devices, and more specifically to field effect transistors (FETs) such as planar FETs or three-dimensional fin line FETs (FinFETs). One aspect of the present invention relates to forming a multilayer high-k gate dielectric. In this regard, a conventional metal oxide semiconductor field effect transistor (MOSFET) includes a source element, a drain component, a channel element between the source element and the drain element, and a gate element above the channel element. The gate element may include a gate dielectric and a gate electrode. The gate dielectric serves as an electrically insulating pad. Transistor performance may be improved by reducing the thickness of the gate dielectric.

[0021] However, because the thickness of the gate dielectric becomes thinner as the scaling process continues, the transistor will encounter current leakage and excessive heat that can be referred to as gate leakage. Gate leakage can cause problems such as excessive power consumption, poorer reliability and / or device performance degradation. The recent use of high-k materials to implement gate dielectrics has enabled the gate dielectric to be significantly thicker, while achieving an equivalent capacitance equivalent thickness (CET) of the entire gate structure that is the same as a much thinner conventional silicon oxide gate dielectric. In this regard, the use of high-k gate dielectrics can be beneficial relative to the equivalent oxide thickness (EOT). In this regard, the equivalent oxide thickness is a distance generally given in nanometers (nm) that indicates how thick the silicon oxide film will need to be in order to produce the same effect as the high-k material being used. Materials with larger dielectric constants enable the use of thicker films (still with low equivalent oxide thickness) while maintaining fast transistor switching. In this way, high-k dielectric materials have become good candidates for implementing the gate dielectric of transistors. Unfortunately, high-k dielectric materials also have lower band gaps, which are associated with higher gate leakage. As semiconductor technology nodes advance to 7 nanometer generations or smaller, the problems discussed above become more serious.

[0022] In order to overcome the problems discussed above, the present invention forms a gate structure that includes not only one gate dielectric layer, but also a plurality of different gate dielectric layers having different material compositions. In a double-layer gate dielectric embodiment, the gate dielectric includes a bottom gate dielectric layer implemented as a channel closer to the transistor and a top gate dielectric layer located on top of the bottom gate dielectric layer. The bottom gate dielectric layer and the top gate dielectric layer have different properties and / or physical properties from each other. For example, the top gate dielectric layer can have a larger dielectric constant than the bottom gate dielectric layer (although both of them have high-k material components) to ensure that the overall dielectric constant of the gate structure is still high enough so that a low equivalent oxide thickness can be maintained. The top gate dielectric layer also has fewer traps than the bottom gate dielectric layer, which can lead to lower noise levels and faster speeds. At the same time, the bottom gate dielectric layer has a material component that is configured to achieve a better interface (or better integration) with a layer disposed below the gate structure such as an interface oxide layer. The thickness and material composition of the top gate dielectric layer and the bottom gate dielectric layer are configured so that a desired high-k dielectric value can be obtained for the gate structure to increase speed without inducing too much gate leakage.

[0023] In a three-layer gate dielectric embodiment, the gate dielectric includes a bottom gate dielectric layer that can form a good interface with the underlying interface layer (e.g., similar to the bottom layer of a double-layer gate dielectric solution), an intermediate layer that can achieve a high dielectric constant and / or fewer traps (e.g., similar to the top layer of a double-layer gate dielectric solution), and a top layer that can form a good interface with the upper metal gate electrode and / or can help tune the threshold voltage. Fig. 20 The details of the gate structure are discussed.

[0024] Figure 1A and Figure 1B A three-dimensional stereogram and a top view of a portion of an integrated circuit (IC) device 90 are illustrated, respectively. The IC device 90 may be an intermediate device or a portion thereof in the IC processing process, and may include static random access memory (SRAM) and / or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and / or other memory cells. Unless otherwise required, the present invention is not limited to any particular number of devices or device regions or any particular device configuration. For example, although the illustrated IC device 90 is a three-dimensional FinFET device, the concepts of the present invention may also be applied to planar FET devices.

[0025] Reference Figure 1A, the IC device 90 includes a substrate 110. The substrate 110 may include a basic (single element) semiconductor such as silicon, germanium and / or other suitable materials; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide and / or other suitable materials; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP and / or other suitable materials. The substrate 110 may be a single layer of material having a uniform composition. Alternatively, the substrate 110 may include multiple material layers having similar or different compositions suitable for IC device manufacturing. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions such as source / drain regions may be formed in or on the substrate 110. Depending on the design requirements, the doped regions may be doped with n-type dopants such as phosphorus or arsenic and / or p-type dopants such as boron. The doped regions may be formed directly on the substrate 110 in a p-well structure, an n-well structure, a double-well structure, or a structure using a protrusion. The doped regions may be formed by implanting dopant atoms, epitaxial growth of in-situ doping, and / or other suitable techniques.

[0026] A three-dimensional active region 120 is formed on the substrate 110. The active region 120 is an elongated fin-shaped structure that protrudes upward beyond the substrate 110. As such, the active region 120 is interchangeably referred to as the fin structure 120 hereinafter. The fin structure 120 may be manufactured using a suitable process (including photolithography and etching processes). The photolithography process may include forming a photoresist layer covering the substrate 110, thereby exposing the photoresist to be patterned, performing a post-exposure baking process, and developing the photoresist to form a shielding element (not shown) including the photoresist. Then, a recess is etched in the substrate 110 using the shielding element, thereby leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed by a double patterning or multi-patterning process. Typically, the double patterning or multi-patterning process combines a photolithography process with a self-alignment process to enable the formation of a pattern having, for example, a pitch smaller than that originally obtainable using a single direct photolithography process. As an example, a layer may be formed over a substrate and patterned using a photolithography process. Spacers may be formed next to the patterned layer using a self-aligned process. The layer may then be removed and the remaining spacers or mandrels may then be used to pattern the fin structure 120.

[0027] The IC device 90 also includes a source / drain feature 122 formed over the fin structure 120 . The source / drain feature 122 may include an epitaxial layer epitaxially grown on the fin structure 120 .

[0028] The IC device 90 also includes an isolation structure 130 formed above the substrate 110. The isolation structure 130 electrically separates the various components of the IC device 90. The isolation structure 130 may include silicon oxide, silicon nitride, silicon oxynitride, doped fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable materials. In some embodiments, the isolation structure 130 may include a shallow trench isolation (STI) component. In one embodiment, the isolation structure 130 is formed by etching a trench in the substrate 110 during the formation of the fin structure 120. The trench may then be filled with the above-mentioned isolation material, followed by a chemical mechanical planarization (CMP) process. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures may also be implemented as the isolation structure 130. Optionally, the isolation structure 130 may include, for example, a multilayer structure having one or more thermal oxide liner layers.

[0029] The IC device 90 also includes a gate structure 140 formed over and bonded to three sides in the channel region of each fin structure 120. In some embodiments, the gate structure 140 may be an HKMG structure including a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing a dummy gate structure. Although not depicted herein, the gate structure 140 may include additional material layers such as an interface layer, a protective layer, other suitable layers, or combinations thereof over the fin structure 120.

[0030] Reference Figure 1B , the plurality of fin structures 120 are oriented longitudinally along the X direction, and the plurality of gate structures 140 are oriented longitudinally along the Y direction (i.e., substantially perpendicular to the fin structures 120). In many embodiments, the IC device 90 includes additional features such as gate spacers disposed along the sidewalls of the gate structures 40, a hard mask layer disposed above the gate structures 40, and numerous other components. For simplicity, in one embodiment, reference is made to Figures 2 to 15 The corresponding cross-sectional view describes the processing steps of the present invention, wherein the cross section of the IC device 90 is taken along Figure 1A to Figure 1B The cross-sectional view taken along the dashed line AA' and BB' shown in the figure corresponds to the XZ cross section (for example, Figure 1A The plane defined by the X-direction and the Z-direction), and the cross-sectional view taken along the dashed line BB' corresponds to the cut YZ cross section (for example, Figure 1A The plane defined by the Y and Z directions).

[0031] Now refer to Figures 2 to 3 , the IC device 90 in this manufacturing stage includes the substrate 110 discussed above. The dummy gate structure 40 is formed above the substrate 110 in the Z direction orthogonal to the horizontal plane defined by the X direction and the Y direction. The dummy gate structures 40 are each inserted into a source region and a drain region (e.g., a source / drain region including a source / drain feature 122), wherein a channel region is defined between the source region and the drain region in the substrate 110. The dummy gate structure 40 engages the channel region so that current can flow between the source / drain region during operation. In some implementations, the dummy gate structure 40 is formed on a fin structure (e.g., Figure 1A to Figure 1B The dummy gate structures 40 are disposed above the fin structure 120 such that each of the dummy gate structures 40 wraps a portion of the fin structure 120. For example, the dummy gate structure 40 wraps a channel region of the fin structure 120, thereby inserting a source region and a drain region of the fin structure 120.

[0032] The dummy gate structures 40 may each include a dummy gate dielectric and a dummy gate electrode formed over the dummy gate dielectric. In some embodiments, the dummy gate dielectric may include silicon oxide (SiO2), and the dummy gate electrode may include polysilicon. Figure 3 As shown in the YZ cross-sectional view of , each dummy gate structure 40 may at least partially wrap around the plurality of fin structures 120 .

[0033] Still refer to Figure 2 , the source / drain component 122 is formed in the source / drain region of the substrate 110. In some embodiments, the source / drain component 122 can be formed using an epitaxial process. For example, a semiconductor material is epitaxially grown on the substrate 110, thereby forming the source / drain component 122 as an epitaxially grown structure. In the depicted embodiment, the dummy gate structure 40 is inserted into the corresponding source / drain component 122, and a corresponding channel region is defined in the substrate 110 between the corresponding epitaxial source / drain components 122 under the corresponding dummy gate structure 40. Therefore, the IC device 90 can be configured to include transistors that include a gate structure that will be formed later to replace the dummy gate structure 40 and its corresponding source / drain component 122 and channel region. In some implementations, the dummy gate structures 40 are each wrapped around a fin structure (for example, Figure 1A to Figure 1B The transistor is configured as a FinFET on a source / drain region of a fin structure 120 extending from the substrate 10.

[0034] The epitaxial process may implement a CVD deposition technique (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with components of the substrate 110. The source / drain component 122 is doped with an n-type dopant and / or a p-type dopant. In some implementations, where the transistor is configured as an n-type device, the source / drain component 122 may be a silicon-containing epitaxial layer or a silicon-carbon-containing epitaxial layer doped with phosphorus, other n-type dopants, or a combination thereof (e.g., forming a Si:P epitaxial layer or a Si:C:P epitaxial layer). In some implementations, where the transistor is configured as a p-type device, the source / drain component 122 may be a silicon- and germanium-containing epitaxial layer doped with boron, other p-type dopants, or a combination thereof (e.g., forming a Si:Ge:B epitaxial layer). In some implementations, the source / drain features 122 include materials and / or dopants that achieve the desired tensile stress and / or compressive stress in the channel region. In some implementations, the source / drain features 122 are doped during deposition by adding impurities to the source material of the epitaxial process. In some implementations, the source / drain features 122 are doped by an ion implantation process after the deposition process. In some implementations, an annealing process is performed to activate dopants in the source / drain features 122 and / or other source / drain regions of the IC device 90.

[0035] like Figure 3 As shown in , the isolation structure 130 can also be formed above and / or inside the substrate 110 to isolate various regions of the IC device 90. For example, the isolation structure 130 can define active device regions and / or passive device regions and electrically isolate them from each other. In some implementations, the isolation structure 130 can be configured to isolate the transistor (corresponding to the transistor to be formed to replace the dummy gate structure 40 and / or the source / drain component 122) from other transistors, devices, and / or regions of the IC device 90. The isolation structure 130 includes isolation materials such as silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (for example, including silicon, oxygen, nitrogen, carbon and / or other suitable isolation formations) or combinations thereof. The isolation structure 130 may include different structures such as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure and / or a local oxidation of silicon (LOCOS) structure.

[0036] In some implementations, the STI structure (as an example of the isolation structure 130) can be formed by etching a trench in the substrate 110 (e.g., by using a dry etching process and / or a wet etching process) and filling the trench with an insulator material (e.g., by using a chemical vapor deposition process or a spin-on-glass process). Chemical mechanical polishing (CMP) can be performed to remove excess insulator material and / or flatten the top surface of the STI structure. In some implementations, the STI structure can be formed by depositing an insulator material over the substrate 110 after forming the fins so that the insulator material layer fills the gap between the fin structures (construction) and then etching back the insulator material layer. In some implementations, the isolation structure 130 can include a multi-layer structure that fills the trench, such as a body dielectric layer disposed over a liner dielectric layer, wherein the body dielectric layer and the liner dielectric layer contain materials that depend on design requirements (e.g., a body dielectric layer containing silicon nitride disposed over a liner dielectric layer containing thermal oxide). In some implementations, the isolation structure 130 can include a dielectric layer disposed over a doped liner layer including, for example, borosilicate glass or phosphosilicate glass.

[0037] like Figure 2 As shown in , a gate spacer 230 may be formed adjacent to the gate structure 40, for example, on the sidewalls of the gate structure 40 in the X direction. The gate spacer 230 may be formed by depositing a dielectric material and patterning the dielectric material. The deposited dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the depicted embodiment, a dielectric layer such as a silicon nitride layer containing silicon and nitrogen may be deposited over the substrate 110 and then anisotropically etched to form the gate spacer 230.

[0038] Although not specifically illustrated herein for simplicity reasons, in some embodiments, the gate spacer 230 may include a multilayer structure. For example, the gate spacers 230 may each include a first dielectric layer including silicon nitride and a second dielectric layer including silicon oxide. In some implementations, the gate spacer 230 may include more than one group of spacers such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers formed adjacent to the gate structure 40. In such an implementation, the spacers of each group may include materials with different etching rates. For example, a first dielectric layer including silicon and oxygen may be deposited above the substrate 110, followed by anisotropic etching to form a first spacer group adjacent to the gate stack, and a second dielectric layer including silicon and nitrogen may be deposited above the substrate 110, followed by anisotropic etching to form a second spacer group adjacent to the first spacer group. Implantation, diffusion and / or annealing processes may be performed to form lightly doped source and drain (LDD) features and / or heavily doped source and drain (HDD) features in the source / drain (S / D) regions 122 before and / or after forming the gate spacers 230 .

[0039] An interlayer dielectric (ILD) layer 250 is disposed over the substrate 110 and the gate structure 40 in the Z direction and surrounds the dummy gate structure 40 laterally, for example, in the X direction. In some embodiments, the ILD layer 250 may include a dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from TEOS, PSG, BPSG, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, (Applied Materials, Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In some implementations, the ILD layer 250 may include a multilayer structure having a variety of dielectric materials. The ILD layer 250 may be formed over the substrate 110 by a deposition process such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In some implementations, the ILD layer 250 is formed by a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (such as a liquid compound) over the substrate 110 and converting the flowable material into a solid material by a suitable technique such as thermal annealing and / or ultraviolet radiation treatment. After depositing the ILD layer 250 , one or more CMP processes and / or other planarization processes may be performed so that the ILD layer 250 has a substantially planar upper surface.

[0040] Now refer to Figure 4 and Figure 5 , one or more etching processes 270 are performed on the IC device 90 to remove the dummy gate structure 40. The one or more etching processes 270 may include a wet etching process or a dry etching process, and they may be performed with sufficient etching selectivity between the material of the dummy gate structure 40 and the rest of the material of the IC device 90 (such as the ILD layer 250, the gate spacer 230, and the fin structure 120). In other words, the one or more etching processes 270 may be able to etch away the dummy gate electrode (e.g., comprising polysilicon) and the dummy gate dielectric (e.g., comprising silicon oxide), while the ILD layer 250, the gate spacer 230, and the fin structure 120 remain substantially intact. As a result of the execution of the one or more etching processes 270, a trench 280 (or recess) is formed to replace the removed dummy gate structure 40. For example, the trench 280 may expose the upper surface of the fin structure 120 and the side surface of the gate spacer 230.

[0041] Now refer to Figure 6 and Figure 7, a deposition process 290 is performed on the IC device 90 to form an interface layer 300 in the trench 280. The deposition process 290 may include various types of CVD, PVD or ALD processes or combinations thereof. The interface layer 300 is formed on the exposed surface of the fin structure 120. Some portions of the interface layer 300 are also formed on the side surfaces of the gate isolation member 230 and the upper surface of the ILD layer 250. As such, the portion of the interface layer 300 formed inside the trench 280 may have a U-shape. In some embodiments, the interface layer 300 includes silicon oxide.

[0042] Now refer to Figure 8 and Fig. 9 , a deposition process 310 is performed on the IC device 90 to form a gate dielectric layer 350 above the interface layer 300. The deposition process 290 may include an ALD process. The gate dielectric layer 350 includes a high-k dielectric material. A high-k dielectric material generally refers to a dielectric material having a dielectric constant greater than that of silicon oxide (a dielectric constant of approximately 3.9 or k≈3.9). In the illustrated embodiment, the high-k dielectric material of the gate dielectric layer 350 is hafnium oxide (HfO2) having a dielectric constant of approximately 22. Hafnium oxide is selected as a material component of the gate dielectric layer 350 at least in part due to its ability to form a good interface with the underlying interface layer 300. In other words, the hafnium oxide material component of the gate dielectric layer 350 enables it to have good integration with the interface layer 300, such that the interface is substantially defect-free. In addition, the hafnium oxide material component of the gate dielectric layer 350 has a higher band gap than most other types of high-k dielectric materials. The bandgap represents the minimum energy required to excite an electron to a state in the conduction band where it can participate in electrical conduction. Thus, the hafnium oxide material composition enables the overall gate dielectric structure herein to achieve a reasonably high dielectric constant (and thus helps reduce the equivalent oxide thickness) without causing excessive gate leakage, which often increases as the bandgap becomes lower.

[0043] The gate dielectric layer 350 is formed to have a thickness 360. The value of the thickness 360 can be flexibly configured by tuning the process parameters of the deposition process 310 (e.g., by adjusting the process duration of the deposition process 310). In some embodiments, the thickness 360 is configured to be in a range between about 9 angstroms and about 14 angstroms. As will be discussed in more detail below, such a range of thickness 360 is not randomly selected, but it is specifically configured to optimize the performance of the IC device 90. For example, such a range of values ​​of the thickness 360 helps to optimize the trade-off between gate leakage and effective gate thickness. If the thickness 360 is too high, the overall dielectric constant of the gate may not be high enough, thereby reducing device performance such as speed. If the thickness 360 is too small, the overall gate leakage may be too high because the gate dielectric layer to be formed above the gate dielectric layer 350 will have a higher dielectric constant (and therefore a higher gate leakage), as discussed in more detail below.

[0044] Now refer to Fig.10 and Fig.11 , a deposition process 380 is performed on the IC device 90 to form a gate dielectric layer 390 above the gate dielectric layer 350. The deposition process 380 may include another ALD process. In some embodiments, the ALD process of the deposition process 380 and the ALD process of the deposition process 290 may be performed in the same deposition chamber. The gate dielectric layer 390 contains another type of high-k dielectric material that is different from the high-k dielectric material of the gate dielectric layer 350. In other words, although both the gate dielectric layer 350 and the gate dielectric layer 390 can be high-k dielectric materials, they have different high-k material components. For example, the gate dielectric layer 390 has a larger dielectric constant than the gate dielectric layer 350. This enables the gate dielectric layer 390 to help raise the overall dielectric constant of the gate dielectric as a whole, which will achieve a lower equivalent oxide thickness without excessively increasing the overall thickness of the gate dielectric. With a larger dielectric constant, the IC device 90 can achieve a faster speed.

[0045] As another example, the gate dielectric layer 390 has fewer traps than the gate dielectric layer 350. Traps can be considered defects. Traps within the film can be caused by imperfections in the atom-to-atom bonding of the film. If the traps capture ion chargers (e.g., electrons or holes), this can have adverse film effects on mobility / speed, noise, and / or threshold voltage. Trap energy levels within a given material can be measured using a variety of techniques (e.g., using 1 / f noise measurement methods). Such techniques can be used to confirm the material composition of such a layer by measuring the trap energy levels of such a layer. Having a lower trap energy level enables the gate dielectric layer 390 to help reduce noise introduced by the gate structure, which in turn helps to expand the circuit design window or reduce the chip area.

[0046] However, the higher dielectric constant of the gate dielectric layer 390 may have a lower band gap, which, as discussed above, may cause increased gate leakage. Therefore, the gate dielectric layer 390 should not be the only gate dielectric layer of the gate structure. Alternatively, the gate dielectric layer 390 is used in combination with the underlying gate dielectric layer 350 to optimize the performance of the overall gate dielectric structure. In other words, the gate dielectric layer 350 and the gate dielectric layer 390 are selected or configured for different purposes or functions. As the bottom layer in direct physical contact with the interface layer 300 (and also closer to the channel region of the transistor), it is more important that the gate dielectric layer 350 can form a good interface with the interface layer 300 and the channel region below it or have good integration with it. In contrast, as the top layer farther from the interface layer 300 and the channel region of the transistor, whether the gate dielectric layer 390 can form a good interface with the interface layer is a smaller issue. Alternatively, it is more important that the gate dielectric layer 350 has a larger dielectric constant (so as to increase the overall dielectric constant of the gate dielectric structure). Fewer traps in the gate dielectric layer 390 also help reduce noise and can increase speed and expand the circuit design window. The greater gate leakage associated with the higher dielectric constant of the gate dielectric layer 390 is offset by the lower gate leakage associated with the lower dielectric constant of the underlying gate dielectric layer 350 (but still greater than the dielectric constant of silicon oxide).

[0047] In some embodiments, the gate dielectric layer 390 does not include hafnium oxide, but may include zirconium oxide (ZrO x ), titanium oxide (TiO2), lanthanum oxide (La2O3), or a combination thereof. Zirconium oxide has a dielectric constant of about 29, titanium oxide has a dielectric constant of about 80, and lanthanum oxide has a dielectric constant of about 30. In other words, the dielectric constants of all of these candidate materials for the gate dielectric layer 390 have a dielectric constant that is not only greater than the dielectric constant of silicon oxide but also greater than the dielectric constant of hafnium oxide (about 22). Likewise, such a high dielectric constant enables the gate dielectric layer 390 to increase the overall dielectric constant of the gate dielectric structure, thereby enabling thinner equivalent oxide thickness and faster speed.

[0048] The gate dielectric layer 390 is formed to have a thickness 400. The value of the thickness 400 can be configured by tuning the process parameters of the deposition process 380 (e.g., by tuning the process duration of the deposition process 380). According to an embodiment of the present invention, the thickness 360 of the gate dielectric layer 350 is significantly greater than the thickness 400 of the gate dielectric layer 390. For example, in some embodiments, the thickness 360 is in a range between about 9 angstroms and about 14 angstroms, while the thickness 400 is in a range between about 2.5 angstroms and about 7 angstroms. In some embodiments, the ratio of the thickness 360 to the thickness 400 is in a range between about 1.3:1 and about 5.6:1. In some embodiments, the ratio of the thickness 360 to the thickness 400 is in a range between about 2:1 and about 3.6:1. Again, these ranges of the thickness 360 and the thickness 400 and their ratios are not randomly selected, but are specifically configured to optimize the performance of the IC device 90 so as to optimize the speed and / or gate leakage of the IC device 90. Without sacrificing the effective gate thickness. For example, if the gate dielectric layer 350 is too thick relative to the gate dielectric layer 390, the overall dielectric constant of the gate dielectric structure may not be large enough to achieve a low equivalent oxide thickness, which means that the gate structure may not be able to be scaled down as much as desired. On the other hand, if the gate dielectric layer 350 is too thin relative to the gate dielectric layer 390, the gate leakage may be greater than desired, and / or the integration between the overall dielectric structure and the interface layer 300 may be poor. The ranges discussed above ensure that the gate dielectric structure can still integrate well with the underlying layers while also achieving sufficient equivalent oxide thickness without necessarily making the gate dielectric thicker and without excessively increasing the gate leakage.

[0049] Now refer to Fig.12 and Fig.13, one or more deposition processes 420 are performed on the IC device 90 to form a gate electrode 430 over the gate dielectric layer 390. The gate electrode 430 includes a metal and may include multiple layers such as one or more protective layers, work function layers, glue / barrier layers, and / or metal fill (or body) layers. The protective layer may include a material that prevents and / or eliminates diffusion and / or reaction between the gate dielectric layers 350 and 390 and other layers of the gate electrode 430. In some implementations, the protective layer includes a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or a combination thereof. The work function layer includes a conductive material such as an n-type work function material and / or a p-type work function material that is tuned to have a desired work function (such as, n-type work function or p-type work function). The p-type work function material includes TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials or combinations thereof. The n-type work function material includes Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials or combinations thereof. The glue / barrier layer may include materials that promote adhesion between adjacent layers such as work function layers and metal filling layers and / or materials that block and / or reduce diffusion between gate layers such as work function layers and metal filling layers. For example, the glue / barrier layer includes a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals or combinations thereof), a metal oxide, a metal nitride (e.g., TiN) or a combination thereof. The metal filling layer serves as the main conductive portion of the gate electrode 430 and may include a suitable conductive material such as Al, W and / or Cu. For the sake of simplicity, the various layers of the gate electrode 430 are not illustrated in detail herein.

[0050] After all layers of the gate electrode 430 have been deposited, a planarization process such as a chemical mechanical polishing (CMP) process may be performed on the IC device 90. The planarization process may remove excess portions of the interface layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the gate electrode 430 outside the trench 280 until the remaining portions of the interface layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the gate electrode 430 have upper surfaces that are substantially coplanar (e.g., horizontally flat) with the ILD layer 250. In this manufacturing stage, the HKMG structure including the interface layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the remaining portions of the gate electrode 430 filling the trench 280 is formed.

[0051] It should be understood that additional steps may be performed to complete the manufacture of the IC device 90. For example, a multi-layer interconnect (MLI) structure may be formed. The MLI structure electrically couples various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or source / drain components) of the IC device 90 together so that the various devices and / or components operate as specified by the design requirements of the IC device 90. The MLI structure may include a combination of dielectric layers and conductive layers (e.g., metal lines, vias, and contacts) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect components such as contacts and / or vias (providing, for example, vertical connections and / or vertical electrical wiring between components) and / or horizontal interconnect components such as conductive lines (providing, for example, horizontal electrical wiring). Vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the MLI structure. During operation, the MLI structure routes signals between and / or distributes signals (eg, clock signals, voltage signals, and / or ground signals) to devices and / or elements of IC device 90 .

[0052] Fig.14 A portion of IC device 90 is illustrated with graph 500 displayed adjacent to the portion of IC device 90. In this regard, the portion of IC device 90 shown includes fin structure 120, interface layer 300, gate dielectric layer 350, gate dielectric layer 390, and a portion of gate electrode 430. Fig.14 The portion of the IC device 90 shown in FIG. 1 may also correspond to a cross-sectional view of the IC device 90 , for example, an XZ cross-sectional view or a YZ cross-sectional view.

[0053] At the same time, the graph 500 includes an H-axis as its horizontal axis and a Z-axis as its vertical axis. The Z-axis corresponds to the same Z-axis (or Z-direction) of the IC device 90. In other words, the up and down movement on the Z-axis in the graph 500 corresponds to the up and down vertical movement of the IC device 90 (e.g., into and out of different layers). The H-axis represents the concentration level of the material. Movement to the "left" along the H-axis means that the concentration level of the material increases, and movement to the "right" along the H-axis means that the concentration level of the material decreases.

[0054] Graph 500 includes curve 510 and curve 520. Curve 510 represents the concentration level of the material of gate dielectric layer 350 as the position of gate dielectric layer 350 along the Z-axis varies, and curve 520 represents the concentration level of the material of gate dielectric layer 390 as the position of gate dielectric layer 390 along the Z-axis varies. For example, in an embodiment where gate dielectric layer 350 has a hafnium oxide material composition and gate dielectric layer 390 has a zirconium oxide material composition (e.g., as non-limiting example materials for layer 390 only), curve 510 represents how the concentration level of hafnium oxide varies as the vertical position within IC device 90 varies (i.e., up and down along the Z-axis), and curve 520 represents how the concentration level of zirconium oxide varies as the vertical position within IC device 90 varies (i.e., up and down along the Z-axis). It should be understood that the vertical position along the Z-axis of graph 500 is related to the Z-axis of the gate dielectric layer 350. Fig.14 Also note that the hafnium oxide composition and zirconium oxide composition used for layers 350 and 390 are only non-limiting examples, and in alternative embodiments, other suitable materials may be used to implement layers 350 and 390.

[0055] Based on the graph 500, it can be seen that the concentration level of the material (e.g., hafnium oxide) of the gate dielectric layer 350 starts from a negligible low level in the fin structure 120 (since the fin structure 120 does not contain hafnium oxide or is at least assumed not to contain hafnium oxide) and gradually moves upward into the interface layer 300, piercing sharply upward into the gate dielectric layer 350 until reaching a peak level 530 near the midpoint of the gate dielectric layer 350, and then gradually slopes back down. In some embodiments, the peak level 530 may vary as the thickness of the layer 350 varies. In other words, as the layer 350 becomes thicker, the peak level 530 may increase, and vice versa.

[0056] In addition, the concentration level of the material (e.g., zirconium oxide) of the gate dielectric layer 390 also starts at a negligible low level in the fin structure 120 (again, the fin structure 120 is free of zirconium oxide or at least assumed to contain no zirconium oxide), remains relatively low in the interface layer 300 and the gate dielectric layer 350, penetrates upward into the gate dielectric layer 390 until reaching a peak level 540 near the midpoint of the gate dielectric layer 390, and then gradually slopes down backward. In some embodiments, the peak level 540 can vary as the thickness of the layer 390 varies. In other words, as the layer 390 becomes thicker, the peak level 540 can increase, and vice versa. In some embodiments, the ratio of the peak level 530 to the peak level 540 is in a range between about 6:1 and about 22:1. It should be understood that the ranges and ratios involving the peak level 530 and the peak level 540 are not randomly selected, but are specifically configured to optimize the performance of the IC device 90. For example, these ranges and ratios enable the gate dielectric layer 350 to effectively form a good interface with the underlying interfacial layer 300 and, at the same time, enable the gate dielectric layer 390 to raise the overall dielectric constant of the gate dielectric structure without contributing much to gate leakage.

[0057] The graph 500 may also reflect the conditions or characteristics of the IC device 90 in the example real-world environment. For example, although the figures discussed above illustrate a clear boundary between the gate dielectric layer 350 and the gate dielectric layer 390, the IC device 90 in the real world may lack such a clear boundary. Alternatively, the materials of the gate dielectric layers 350 and 390 may be slightly fused or diffused into each other, thereby making any boundary between the two layers difficult to identify. However, using a machine such as a transmission electron microscope (TEM) tool and / or an energy dispersive X-ray spectroscopy (EDS or EDX) tool, the concentration levels of different materials of the gate dielectric layer 350 and the gate dielectric layer 390 can be identified as varying with changes in vertical position within the IC device 90. In this way, by reverse engineering the IC device using a TEM tool or an EDS tool, it can be determined that the IC device has implemented a multi-layer gate dielectric scheme similar to an embodiment of the present invention.

[0058] The above discussion relates to a double-layer gate dielectric solution. However, the concept of the present invention can also be applied to a triple-layer gate dielectric. Figure 15 to Figure 16 An embodiment of a three-layer gate dielectric scheme is illustrated in FIG. Figure 15 to Figure 16 The following are cross-sectional views of the IC device in the XZ plane and YZ plane, respectively. For consistency and clarity, Figures 2 to 14 and Figure 15 to Figure 16 Similar elements appearing in the drawings will be labeled identically.

[0059] Figure 15 to Figure 16 The manufacturing stages shown are Figure 12 to Figure 13. In addition to the gate dielectric layers 350 and 390, the gate dielectric structure in this embodiment also includes a gate dielectric layer 450 formed by a deposition process 440 (e.g., an ALD process). The gate dielectric layer 450 is formed directly on the gate dielectric layer 390 and directly below the gate electrode 430. The gate dielectric layer 450 has a different material composition from the gate dielectric layers 350 and 390. In more detail, although the gate dielectric layer 350 is configured to form a good interface with the interface layer 300 or have good integration with the channel below, and the gate dielectric layer 390 is configured to increase the overall dielectric constant of the gate structure and reduce noise, the gate dielectric layer 450 is configured to facilitate the gate electrode 430 to tune the threshold voltage. For example, the material composition of the gate dielectric layer 450 is selected to assist the work function metal layer of the gate electrode 430 in tuning the threshold voltage. In some embodiments, the gate dielectric layer 350 has a hafnium oxide material composition, the gate dielectric layer 390 has a zirconium oxide material composition, and the gate dielectric layer 450 has an aluminum oxide (Al 2 O 3 ) material composition or a lanthanum oxide (La 2 O 3 ) material composition.

[0060] The gate dielectric layer 450 is formed to have a thickness 460. The thickness 460 is less than the thickness 400 of the gate dielectric layer 390 and less than the thickness 360 of the gate dielectric layer 350. Again, the thickness 460 can be configured by adjusting the process parameters (e.g., deposition duration) of the deposition process 440. In some embodiments, the thickness 460 is configured to be within a range between about 1.5 angstroms and about 2.5 angstroms, the ratio between the thickness 360 and the thickness 460 is within a range between about 5:1 and about 10:1, and the ratio between the thickness 400 and the thickness 460 is within a range between about 1:1 and about 4:1. These ranges and ratios are not randomly selected, but are specifically configured to ensure that the gate dielectric layer 450 can adequately assist in threshold voltage tuning without degrading the gate dielectric constant or noise level. Therefore, each of the gate dielectric layers 350 , 390 and 450 can fully and effectively play its corresponding role, such as forming a good interface with the interface layer 300 , improving the overall dielectric constant of the gate structure and reducing noise and facilitating threshold voltage tuning.

[0061] Fig.17 A portion of IC device 90 is shown and graph 600 is displayed next to the portion of IC device 90. Fig.14 The graph 500 corresponds to the graph described above with reference to FIGS. 1 to Figure 3 The dual-layer gate dielectric embodiment discussed above, however, plot 600 corresponds to the above reference Figure 15 to Figure 16 For simplicity, Fig.14 Similar components appearing in Fig.17 are marked identically in .

[0062] Like graph 500 , graph 600 also includes curves 510 and 520 that represent the variation of the concentration level of gate dielectric layer 350 and gate dielectric layer 390 along vertical axis Z. Graph 600 also includes curve 610 that represents the variation of the concentration level of gate dielectric layer 450 along vertical axis Z.

[0063] Curve 610 indicates that the concentration level of the material (e.g., aluminum oxide or lanthanum oxide) of gate dielectric layer 450 also starts from a negligible low level in fin structure 120 (again, fin structure 120 does not contain aluminum oxide or lanthanum oxide or is at least assumed not to contain aluminum oxide or lanthanum oxide), remains relatively low in interface layer 300 and gate dielectric layers 350 and 390, penetrates upward into gate dielectric layer 450 until reaching a peak level 620 near the midpoint of gate dielectric layer 450, and then gradually slopes back down. Again, peak level 620 may vary as the thickness of the gate dielectric layer varies. Peak level 620 is less than peak levels 540 and 530. In some embodiments, the ratio of peak level 620 to peak level 530 is in a range between about 1:19 and about 1:40. It should be understood that the ranges and ratios involving peak level 620 and peak level 530 are not randomly selected, but are specifically configured to optimize the performance of IC device 90. For example, these ranges and ratios allow the gate dielectric layer 450 to be thick enough to adequately assist the work function metal in tuning the threshold voltage, but not so thick as to reduce the dielectric constant of the overall gate dielectric structure or introduce too much noise.

[0064] The multilayer gate dielectric structure of the present invention can be applied to various types of IC applications. For example, the multilayer gate dielectric structure can be implemented in a static random access memory (SRAM) device. An SRAM device is a semiconductor memory that uses a bistable latch circuit (e.g., a flip-flop) to store binary bits of information. A typical SRAM cell may include a pull-up (PU) transistor, a pull-down (PD) transistor, and a transfer gate (PG) transistor. As semiconductor technology nodes continue to evolve to smaller generations (e.g., less than 10 nanometer nodes), the write and read margins of SRAMs become more important. The alpha ratio of the SRAM—defined as the Id of the PU—can be tuned. sat (saturation current) divided by PG's Id sat —to achieve the desired write and / or read margin of the SRAM. sat It is an inverse function of the threshold voltage (Vt), so the threshold voltage can be tuned to the desired Id sat .

[0065] Fig.18An example circuit schematic of a single-port SRAM cell (e.g., a 1-bit SRAM cell) 800 is illustrated. The single-port SRAM cell 800 includes pull-up transistors PU1, PU2; pull-down transistors PD1, PD2; and pass-gate transistors PG1, PG2. As shown in the circuit diagram, transistors PU1 and PU2 are p-type transistors, and transistors PG1, PG2, PD1, and PD2 are n-type transistors. Since the SRAM cell 800 includes six transistors in the illustrated embodiment, it may also be referred to as a 6T SRAM cell.

[0066] The drains of the pull-up transistor PU1 and the pull-down transistor PD1 are coupled together, and the drains of the pull-up transistor PU2 and the pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and coupled with the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and coupled with the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of the pull-up transistors PU1 and PU2 are coupled to a power supply voltage Vcc (also referred to as Vdd), and the sources of the pull-down transistors PD1 and PD2 are coupled to a voltage Vss, which in some embodiments may be electrically grounded.

[0067] The first storage node SN1 of the first data latch is coupled to the bit line BL through the pass gate transistor PG1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB through the pass gate transistor PG2. The first storage node N1 and the complementary first storage node SNB1 are complementary nodes that are usually at opposite logic levels (logic high or logic low). The gates of the pass gate transistors PG1 and PG2 are coupled to the word line WL.

[0068] Similarly, according to various aspects of the present invention, each of transistors PU1, PU2, PD1, PD2, PG1 and PG2 can be implemented using the double or triple gate dielectric structure discussed above. Doing so will improve gate leakage issues and the performance of SRAM devices, such as with respect to speed and power dissipation. It should also be understood that although SRAM devices are used as non-limiting examples of IC applications that can implement various aspects of the present invention, other types of IC applications can also implement various aspects of the present invention. For example, the multi-layer gate dielectric scheme herein can be applied to peripheral logic circuit devices (such as row decoders, column decoders, read / write circuits) in SRAM devices or other circuit devices such as ring oscillators, radio frequency (RF) devices, amplifiers, mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc.

[0069] Fig.19 An integrated circuit manufacturing system 900 according to an embodiment of the present invention is illustrated. The manufacturing system 900 includes multiple entities 902, 904, 906, 908, 910, 912, 914, 916 ..., N connected by a communication network 918. The network 918 can be a single network, or can be a variety of different networks such as an intranet and the Internet, and can include both wired and wireless communication channels.

[0070] In an embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user such as a product engineer who monitors a product of interest; entity 906 represents an engineer such as a process engineer who controls a process and related recipes or monitors or tunes conditions and settings of a process tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor process tool such as an EUV tool for performing a lithography process; entity 912 represents a virtual metrology module associated with process tool 910; entity 914 represents an advanced process control module associated with process tool 910 and further other process tools; and entity 916 represents a sampling module associated with process tool 910.

[0071] Each entity can interact with other entities and can provide integrated circuit manufacturing, process control and / or computing capabilities to receive such capabilities from other entities. Each entity can also include one or more computer systems for performing calculations and performing automation. For example, the advanced processing control module of entity 914 can include a plurality of computer hardware in which software instructions are encoded. The computer hardware can include a hard drive, a flash drive, a CD-ROM, a RAM memory, a display device (e.g., a monitor), an input / output device (e.g., a mouse and a keyboard). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0072] The integrated circuit manufacturing system 900 enables interaction between entities for the purpose of integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In an embodiment, the advanced process control includes adjusting the processing conditions, settings and / or recipes of a processing tool applicable to the associated wafer based on the metrology results.

[0073] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0074] One of the capabilities that IC manufacturing system 900 provides can enable collaboration and information access in fields such as design, processing and handling, metrology and advanced process control. Another capability that IC manufacturing system 900 provides can be system integration between facilities (such as, between metrology tools and processing tools). Such integration enables facilities to coordinate their activities. For example, integrated metrology tools and processing tools can enable manufacturing information to be more effectively incorporated into manufacturing process or APC modules, and can utilize the metrology tools integrated in the associated processing tools to enable wafer data from online or on-site measurements.

[0075] Fig. 20 1 is a flow chart showing a method 1000 for manufacturing a semiconductor device according to another embodiment of the present invention. The method 1000 includes a step 1010 of forming an interface layer above a channel region of a substrate.

[0076] The method 1000 includes depositing a first type of dielectric material as a first portion of a gate dielectric over the interface layer using a first atomic layer deposition (ALD) process 1020. The first type of dielectric material has a first dielectric constant greater than that of silicon oxide.

[0077] The method 1000 includes depositing a second type of dielectric material as a second portion of the gate dielectric over the first type of dielectric material using a second ALD process 1030. The second type of dielectric material has a second dielectric constant greater than the first dielectric constant.

[0078] The method 1000 includes a step 1040 of forming a metal-containing gate electrode over the second type of dielectric material.

[0079] In some embodiments, the first ALD process and the second ALD process are performed in the same ALD chamber, and the first ALD process is performed with a longer process duration than the second ALD process. In some embodiments, the process durations of the first ALD process and the second ALD process are configured such that the first type of dielectric material is thicker than the second type of dielectric material by a factor between about 1.3 and about 5.6.

[0080] In some embodiments, forming the metal-containing gate electrode includes depositing a work function metal component of the gate electrode directly on the second type of dielectric material, and depositing a fill metal component of the gate electrode over the work function metal component.

[0081] It should be understood that additional steps may be performed before, during, or after steps 1010-1040. For example, after performing the second ALD process but before forming the metal-containing gate electrode, the method may include the following steps: depositing a third type of dielectric material as a third portion of the gate dielectric over the second type of dielectric material via a third ALD process. The third type of dielectric material is different from the first type of dielectric material and the second type of dielectric material. In some embodiments, depositing the first type of dielectric material includes depositing hafnium oxide directly on the upper surface of the interface layer. In some embodiments, depositing the second type of dielectric material includes depositing zirconium oxide directly on the upper surface of the first type of dielectric material. In some embodiments, depositing the third type of dielectric material includes depositing lanthanum oxide or aluminum oxide directly on the upper surface of the second type of dielectric material. Additional steps may include forming additional interconnect components, packaging, or testing processes.

[0082] In summary, the present invention relates to forming a multilayer gate dielectric structure rather than a single layer gate dielectric structure. The multilayer gate dielectric structure implements different types of materials for each gate dielectric layer, wherein each type of material (and its corresponding thickness) is selected to achieve a specific goal. For example, in a double-layer gate dielectric scheme, the bottom gate dielectric layer has a material and thickness configured to form a good interface and / or integration with the underlying interface layer and / or channel, and the top gate dielectric layer has a material and thickness configured to increase the overall dielectric constant and reduce the noise level. In a three-layer gate dielectric scheme, the bottom gate dielectric layer has a material and thickness configured to form a good interface and / or integration with the underlying interface layer and / or channel, the middle gate dielectric layer has a material and thickness configured to increase the overall dielectric constant and reduce the noise level, and the top gate dielectric layer has a material and thickness configured to facilitate tuning of the threshold voltage.

[0083] Based on the above discussion, it can be seen that the present invention provides advantages over conventional source / drain vias. However, it should be understood that not all advantages are discussed herein, different embodiments may provide different advantages, and specific advantages are not required for any embodiment. One advantage is that the present invention enables the scaling process to continue. When device scaling reaches the 7 nanometer technology node or higher, conventional single-layer gate dielectric structures may become unfeasible or may suffer performance degradation. For example, when a silicon oxide material is used to implement the gate dielectric, the gate dielectric must be very thin. On the other hand, when a high-k material such as hafnium oxide is used to implement the gate dielectric, it cannot achieve the high dielectric constant required to meet performance requirements such as speed. When a high-k material with a dielectric constant even greater than that of hafnium oxide is used to implement the gate dielectric, the lower band gap associated with such a high-k dielectric material can cause excessive gate leakage, thereby increasing the power consumption of the IC device and reducing its reliability.

[0084] In contrast, the multilayer gate dielectric solution utilizes multiple gate dielectric layers to achieve different purposes at the same time. In some embodiments, the bottom layer of the gate dielectric structure is configured to form a good interface with the layer below (e.g., an interface layer or a channel) and / or have good integration to prevent defects from forming at the bottom of the substrate. The bottom layer has a relatively high band gap among high-k dielectric materials, which helps to reduce gate leakage. At the same time, the top layer (in a double-layer gate dielectric solution) or the middle layer (in a three-layer gate dielectric solution) has a material composition different from the bottom layer, for example, it can have a material composition associated with a larger dielectric constant and / or fewer traps than the bottom layer. In this way, the top layer / middle layer can increase the overall dielectric constant of the gate dielectric structure, which enables the gate dielectric structure to achieve the thin thickness required for advanced technology nodes. The high-k dielectric constant helps to increase the speed of IC devices. Fewer traps in the middle layer also help to reduce the noise level, which expands the circuit design window and enables the chip area to shrink. In addition, in a three-layer solution that implements the top layer, such a top layer has a material composition that is specifically configured to enable it to promote the gate electrode when tuning the threshold voltage. Based on the above, the multi-layer gate dielectric structure can achieve a low equivalent oxide thickness while still remaining thin, and it can also reduce gate leakage (or at least not increase gate leakage) and improve device performance such as speed, power consumption, noise and reliability. Other advantages include compatibility with existing manufacturing processes and simplicity and low cost of implementation.

[0085] The advanced lithography processes, methods and materials described above can be used in many applications, including fin field effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacing between components, and the above disclosure is well suited for this. In addition, spacers for forming fins of FinFETs, also known as mandrels, can be processed according to the above disclosure.

[0086] It should also be understood that the multi-layer gate dielectric structure of the present invention discussed above can also be applied to multi-channel devices such as all-around gate (GAA) devices. In this regard, GAA devices have fin structures like the fin structures discussed above, and they have multi-channel structures such as nanosheets, nanowires, or nanotubes formed above the fin structure and wrapped by the gate. The gate dielectric structure (e.g., a double or triple layer structure) can surround each channel 360 degrees circumferentially (e.g., in the form of a nanostructure such as a nanosheet or nanowire). Additional details related to GAA device fabrication are disclosed in U.S. Patent No. 10,164,012, entitled “Semiconductor Device and Manufacturing Method Thereof,” published on December 25, 2018, and U.S. Patent No. 10,361,278, entitled “Method of Manufacturing a Semiconductor Device and a Semiconductor Device,” published on July 23, 2019, and U.S. Patent No. 9,887,269, entitled “Multi-Gate Device and Method of Fabrication Thereof,” published on February 6, 2018, the disclosures of each of which are hereby incorporated by reference in their respective entireties. To the extent the present invention relates to fin structures or FinFET devices, such discussion may be equally applicable to GAA devices.

[0087] In one embodiment, the manufacture of a GAA device is described below (see U.S. Patent No. 10,164,012). A first semiconductor layer is formed on a substrate along a first direction and sandwiched between second semiconductor layers. The first semiconductor layer and the second semiconductor layer are patterned to form a fin structure, so that the fin structure includes a sacrificial layer formed by the second semiconductor layer and a channel layer formed by the first semiconductor layer. A sacrificial gate structure is formed on the fin structure, so that the sacrificial gate structure covers a portion of the fin structure and the remaining portion of the fin structure is exposed. The remaining portion of the fin structure not covered by the sacrificial gate structure is removed. The sacrificial layer is horizontally recessed so that the edge of the sacrificial layer is located below the side of the sacrificial gate structure. A pad epitaxial layer is formed, at least on the recessed surface of the sacrificial layer. A source / drain region is formed. The sacrificial gate structure is removed. After removing the sacrificial gate structure, the sacrificial layer in the fin structure is removed to expose the channel layer. A gate dielectric layer and a gate electrode layer are formed around the exposed channel layer.

[0088] In one embodiment, the manufacture of a GAA device is described below (see U.S. Pat. No. 10,361,278). A fin structure is formed, wherein the fin structure includes a first semiconductor layer and a second semiconductor layer that are alternately stacked. A sacrificial gate structure is formed above the fin structure. A source / drain region of the fin structure that is not covered by the sacrificial gate structure is etched, thereby forming a source / drain spacing. The first semiconductor layer is laterally etched through the source / drain spacing. In the source / drain spacing, a first insulating layer is formed at least on the etched first semiconductor layer. A source / drain epitaxial layer is formed in the source / drain spacing, thereby forming an air gap between the source / drain epitaxial layer and the first insulating layer. In another embodiment, a fin structure of a first semiconductor layer and a second semiconductor layer that are alternately stacked is formed. A sacrificial gate structure is formed above the fin structure. The first semiconductor layer is removed from the source / drain region of the fin structure that is not covered by the sacrificial gate structure. The first insulating layer is formed around the second semiconductor layer in the source / drain region and on the lateral ends of the first semiconductor layer. The first insulating layer is partially removed from the second semiconductor layer in the source / drain region. A source / drain epitaxial layer is formed on the source / drain region, thereby forming an air gap between the source / drain epitaxial layer and lateral ends of the first semiconductor layer.

[0089] In one embodiment, the following will refer to Fig.21The fabrication of GAA devices is described (see U.S. Pat. No. 9,887,269). The fabrication method 2200 begins at step 2202 by applying an anti-punch through (APT) implant to a substrate. The fabrication method 2200 then proceeds to step 2204, where an epitaxial stack is formed on the APT implanted substrate. The epitaxial stack includes a first epitaxial layer of a first composition inserted by a second epitaxial layer of a second composition. The fabrication method 2200 proceeds to step 2206, where a plurality of fins extending from the substrate are formed. The fabrication method 2200 proceeds to step 2208, where an oxidation process is performed to form isolation regions within the fin features. The fabrication method 2200 proceeds to step 2210, where shallow trench isolation (STI) features are formed between the fins. The fabrication method 2200 proceeds to step 2212, where the STI features are recessed to form STI features, and fins are inserted to provide fins extending over the recessed STI features. The manufacturing method 2200 proceeds to step 2214, where a dummy dielectric layer is formed on the fin. The manufacturing method 2200 proceeds to step 2216, where a dummy gate stack is formed. The dummy gate stack may also define a source / drain (S / D) region of the fin. The manufacturing method 2200 proceeds to step 2218, where a spacer layer is formed on the substrate. The manufacturing method 2200 proceeds to step 2220, where the spacer layer is etched back. The manufacturing method 2200 proceeds to step 2222, where the first epitaxial layer is removed from the S / D region. The manufacturing method 2200 proceeds to step 2224, where an inner spacer layer is formed on the substrate, including on each of the second epitaxial layer surrounding the S / D region. The manufacturing method 2200 proceeds to step 2226, where the inner spacer layer is etched back. The manufacturing method 2200 proceeds to step 2228, where S / D features are formed in the S / D region. The manufacturing method 2200 proceeds to step 2230, where a contact etch stop layer (CESL) is formed on the substrate. The manufacturing method 2200 proceeds to step 2232, where an inter-layer dielectric (ILD) layer is formed on the substrate. The manufacturing method 100 proceeds to step 2234, where the remaining dummy gate stack previously formed is removed to form a gate trench in the channel region. The manufacturing method 2200 proceeds to step 2236, which is to remove the dummy dielectric layer and the first epitaxial layer from the fin in the gate trench. The manufacturing method 2200 proceeds to step 2238, where a final gate stack is formed in the gate trench, including wrapping around the nanowire. The manufacturing method 2200 proceeds to step 2240, where a patterned hard mask is formed on the substrate. The manufacturing method 2200 proceeds to step 2242, where the ILD layer is removed through the opening and the portion of the S / D features to form a source / drain (S / D) contact trench.The manufacturing method 2200 proceeds to step 2244, where a conductive layer is deposited in the common S / D contact trench to form a source / drain (S / D) conductive metal.

[0090] One aspect of the present invention relates to a semiconductor device. The semiconductor device includes a substrate. A first gate dielectric layer is disposed above the substrate. The first gate dielectric layer has a first material component. A second gate dielectric layer is disposed above the first gate dielectric layer. The second gate dielectric layer has a second material component. The first material component is different from the second material component. The first material component and the second material component each have a dielectric constant greater than the dielectric constant of silicon oxide.

[0091] In the above semiconductor device, the second material composition has a larger dielectric constant than the first material composition.

[0092] In the above semiconductor device, the second material composition has fewer traps than the first material composition.

[0093] In the above semiconductor device, the first material component includes hafnium oxide; and the second material component includes zirconium oxide, titanium oxide, or lanthanum oxide.

[0094] In the above semiconductor device, the first gate dielectric layer has a first thickness; the second gate dielectric layer has a second thickness; and the first thickness is greater than the second thickness.

[0095] In the above semiconductor device, a ratio of the first thickness to the second thickness is in a range between about 1.3:1 and about 5.6:1.

[0096] In the above semiconductor device, a ratio of the first thickness to the second thickness is in a range between about 2:1 and about 3.6:1.

[0097] In the above semiconductor device, it further includes a third gate dielectric layer disposed above the second gate dielectric layer, wherein the third gate dielectric layer has a third material composition different from the first material composition and the second material composition.

[0098] In the above semiconductor device, the first material component includes hafnium oxide; the second material component includes zirconium oxide; and the third material component includes lanthanum oxide or aluminum oxide.

[0099] In the above semiconductor device, it also includes an interface layer arranged between the substrate and the first gate dielectric layer.

[0100] One aspect of the present invention relates to a semiconductor device. The semiconductor device includes a source region and a drain region arranged in a substrate, a channel region arranged between the source region and the drain region, and a gate structure arranged above the channel region. The gate structure includes a gate dielectric component and a metal-containing gate electrode component. The gate dielectric component includes a plurality of different dielectric layers, and the dielectric constant of each dielectric layer is greater than the dielectric constant of silicon oxide. Different dielectric layers have different dielectric constants from each other.

[0101] In the above semiconductor device, the plurality of different dielectric layers include a first dielectric layer disposed over the channel region and a second dielectric layer disposed over the first dielectric layer; the first dielectric layer is thicker than the second dielectric layer; and the second dielectric layer has a larger dielectric constant than the first dielectric layer.

[0102] In the above semiconductor device, the plurality of different dielectric layers further includes a third dielectric layer disposed above the second dielectric layer; the first dielectric layer includes hafnium oxide; the second dielectric layer includes zirconium oxide; and the third dielectric layer includes lanthanum oxide or aluminum oxide.

[0103] In the above semiconductor device, different dielectric layers have different levels of traps.

[0104] Another aspect of the present invention relates to a method for manufacturing a semiconductor device. An interfacial layer is formed over a channel region of a substrate. A first type of dielectric material is deposited over the interfacial layer as a first portion of a gate dielectric using a first atomic layer deposition (ALD) process. The first type of dielectric material has a first dielectric constant greater than the dielectric constant of silicon oxide. A second type of dielectric material is deposited over the first type of dielectric material as a second portion of a gate dielectric using a second ALD process. The second type of dielectric material has a second dielectric constant greater than the first dielectric constant. A metal-containing gate electrode is formed over the second type of dielectric material.

[0105] In the above method, the first atomic layer deposition process and the second atomic layer deposition process are performed in the same atomic layer deposition chamber; and the first atomic layer deposition process is performed with a longer process duration than the second atomic layer deposition process.

[0106] In the above method, process durations of the first atomic layer deposition process and the second atomic layer deposition process are configured such that the first type of dielectric material is thicker than the second type of dielectric material by a factor between about 1.3 and about 5.6 times.

[0107] In the above method, it also includes: depositing a third type of dielectric material as a third part of the gate dielectric over the second type of dielectric material via a third atomic layer deposition process, wherein the third type of dielectric material is different from the first type of dielectric material and the second type of dielectric material.

[0108] In the above method, depositing the first type of dielectric material includes depositing hafnium oxide directly on the upper surface of the interface layer; depositing the second type of dielectric material includes depositing zirconium oxide directly on the upper surface of the first type of dielectric material; and depositing the third type of dielectric material includes depositing lanthanum oxide or aluminum oxide directly on the upper surface of the second type of dielectric material.

[0109] In the above method, forming the metal-containing gate electrode includes: depositing a work function metal component of the gate electrode directly on the second type of dielectric material; and depositing a fill metal component of the gate electrode over the work function metal component.

[0110] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: substrate; a first gate dielectric layer disposed above the substrate, wherein the first gate dielectric layer has a first material composition; and a second gate dielectric layer disposed above the first gate dielectric layer, wherein the second gate dielectric layer has a second material composition; in: the first material composition is different from the second material composition; and The first material component and the second material component each have a dielectric constant greater than a dielectric constant of silicon oxide; The concentration level of the first material component varies with depth in the thickness direction within the first gate dielectric layer and reaches a first peak at a midpoint of the thickness of the first gate dielectric layer; The concentration level of the second material component varies with depth in the thickness direction within the second gate dielectric layer and reaches a second peak at a midpoint of the thickness of the second gate dielectric layer; and The first peak value is greater than the second peak value.

2. The semiconductor device according to claim 1, wherein The second material composition has a greater dielectric constant than the first material composition.

3. The semiconductor device according to claim 1, wherein The second material component has fewer traps than the first material component.

4. The semiconductor device according to claim 1, wherein: The first material component includes hafnium oxide; and The second material component includes zirconium oxide, titanium oxide or lanthanum oxide.

5. The semiconductor device according to claim 1, wherein: The first gate dielectric layer has a first thickness; The second gate dielectric layer has a second thickness; and The first thickness is greater than the second thickness.

6. The semiconductor device according to claim 5, wherein: A ratio of the first thickness to the second thickness is in a range between 1.3:1 and 5.6:

1.

7. The semiconductor device according to claim 6, wherein: A ratio of the first thickness to the second thickness is in a range between 2:1 and 3.6:

1.

8. The semiconductor device according to claim 1, further comprising a third gate dielectric layer disposed above the second gate dielectric layer, wherein: The third gate dielectric layer has a third material composition different from the first material composition and the second material composition.

9. The device according to claim 8, wherein: The first material component includes hafnium oxide; The second material component includes zirconium oxide; and The third material component includes lanthanum oxide or aluminum oxide. 10 . The device of claim 1 , further comprising an interfacial layer disposed between the substrate and the first gate dielectric layer.

11. A semiconductor device comprising: A source region and a drain region are disposed in the substrate; a channel region, disposed between the source region and the drain region; as well as a gate structure disposed above the channel region, wherein the gate structure includes a gate dielectric component and a gate electrode component containing a metal; in: The gate dielectric component includes a plurality of different dielectric layers, each of the dielectric layers having a dielectric constant greater than a dielectric constant of silicon oxide; and The different dielectric layers have different dielectric constants from each other; A bottommost dielectric layer of the plurality of different dielectric layers is a first dielectric layer, the plurality of different dielectric layers further comprising a second dielectric layer located above the first dielectric layer, a first material composition of the first dielectric layer being different from a second material composition of the second dielectric layer; The concentration level of the first material component varies with depth in the thickness direction within the first dielectric layer and reaches a first peak at a midpoint of the thickness of the first dielectric layer; The concentration level of the second material component varies with depth in the thickness direction within the second dielectric layer and reaches a second peak at a midpoint of the thickness of the second dielectric layer; and The first peak value is greater than the second peak value.

12. The semiconductor device according to claim 11, wherein: The plurality of different dielectric layers include a first dielectric layer disposed over the channel region and a second dielectric layer disposed over the first dielectric layer; The first dielectric layer is thicker than the second dielectric layer; and The second dielectric layer has a larger dielectric constant than the first dielectric layer.

13. The semiconductor device according to claim 12, wherein: The plurality of different dielectric layers further includes a third dielectric layer disposed over the second dielectric layer; The first dielectric layer includes hafnium oxide; The second dielectric layer comprises zirconium oxide; and The third dielectric layer includes lanthanum oxide or aluminum oxide.

14. The semiconductor device according to claim 11, wherein The different dielectric layers have different levels of traps therein.

15. A method of forming a semiconductor device, comprising: forming an interface layer over the channel region of the substrate; Depositing a first type of dielectric material as a first portion of a gate dielectric over the interface layer using a first atomic layer deposition process, wherein the first type of dielectric material has a first dielectric constant greater than a dielectric constant of silicon oxide, and a first material component of the first type of dielectric material has a first peak concentration level; depositing a second type of dielectric material as a second portion of the gate dielectric over the first type of dielectric material using a second atomic layer deposition process, wherein the second type of dielectric material has a second dielectric constant greater than the first dielectric constant, a second material component of the second type of dielectric material has a second peak concentration level, and wherein a ratio of the first peak concentration level to the second peak concentration level is in a range between 6:1 and 22:1; and A metal-containing gate electrode is formed over the second type of dielectric material.

16. The method according to claim 15, wherein: The first atomic layer deposition process and the second atomic layer deposition process are performed in the same atomic layer deposition chamber; and The first atomic layer deposition process is performed with a longer process duration than the second atomic layer deposition process.

17. The method according to claim 16, wherein: The process durations of the first atomic layer deposition process and the second atomic layer deposition process are configured such that the first type of dielectric material is thicker than the second type of dielectric material by a factor between 1.3 and 5.

6.

18. The method according to claim 15, further comprising: A third type of dielectric material is deposited as a third portion of the gate dielectric over the second type of dielectric material via a third atomic layer deposition process, wherein the third type of dielectric material is different from the first type of dielectric material and the second type of dielectric material.

19. The method of claim 18, wherein: Depositing the first type of dielectric material includes depositing hafnium oxide directly on an upper surface of the interface layer; Depositing the second type of dielectric material includes depositing zirconium oxide directly on an upper surface of the first type of dielectric material; and Depositing the third type of dielectric material includes depositing lanthanum oxide or aluminum oxide directly on an upper surface of the second type of dielectric material.

20. The method according to claim 15, wherein: Forming the metal-containing gate electrode includes: depositing a work function metal component of a gate electrode directly on the second type of dielectric material; and A fill metal component of the gate electrode is deposited over the work function metal element.

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