Apparatus of integrated circuit and manufacturing method thereof

Abstract

An integrated circuit device and method of manufacturing the same includes a silicon-based layer, an oxide-based layer, a first top silicon layer, a second top silicon layer, a first semiconductor element, and a second semiconductor element. The oxide-based layer is formed over the silicon-based layer. The first top silicon layer is formed over a first region of the oxide-based layer and has a first thickness. The second top silicon layer is formed over a second region of the oxide-based layer and has a second thickness that is less than the first thickness. The first semiconductor element is formed over the first top silicon layer and the second semiconductor element is formed over the second top silicon layer. By the ability to manufacture different thickness top silicon layers, a monolithic substrate with different characteristic elements can be provided, such as a monolithic substrate with both fully depleted elements and partially depleted elements.

Description

Technical Field

[0001] This disclosure relates to an apparatus for manufacturing integrated circuits and a method thereof. Background Technology

[0002] This disclosure generally relates to semiconductor devices and methods for manufacturing semiconductor structures. In some previous methods, semiconductor devices on the same wafer were limited to having the same top layer thickness, and thus limited to having similar properties. Semiconductor devices are used in a wide variety of electronic devices, and there is often a desire to improve their manufacturing and performance. Summary of the Invention

[0003] One embodiment disclosed herein is an integrated circuit apparatus. An apparatus for a semiconductor integrated circuit includes a silicon substrate, an oxide substrate, a first top silicon layer, a second top silicon layer, a first semiconductor element, and a second semiconductor element. The oxide substrate is formed over the silicon substrate. The first top silicon layer is formed over a first region of the oxide substrate and has a first thickness. The second top silicon layer is formed over a second region of the oxide substrate and has a second thickness less than the first thickness. The first semiconductor element is formed over the first top silicon layer, and the second semiconductor element is formed over the second top silicon layer.

[0004] Another embodiment disclosed herein is a method for manufacturing an integrated circuit device. The method includes: forming a carrier wafer by forming an oxide substrate over a silicon substrate. The method further includes the steps of: forming a first element wafer by forming a first top silicon layer having a first thickness over a first doped silicon layer and forming a first oxide layer over the first top silicon layer, and bonding the first element wafer to a first region of the carrier wafer such that the first oxide layer is in contact with the oxide substrate. The method further includes the steps of: forming a second element wafer by forming a second top silicon layer having a second thickness less than the first thickness over a second doped silicon layer and forming a second oxide layer over the second top silicon layer, and bonding the second element wafer to a second region of the carrier wafer such that the second oxide layer is in contact with the oxide substrate. The method further includes the steps of: removing the first doped silicon layer and removing the second doped silicon layer to expose the first and second top silicon layers, forming a first semiconductor element over the first top silicon layer, and forming a second semiconductor element over the second top silicon layer.

[0005] Another embodiment disclosed herein is a method for manufacturing an integrated circuit device. The method includes forming a carrier wafer by forming an oxide substrate over a silicon substrate. The method further includes the steps of forming a device wafer by forming a silicon-germanium layer over a doped silicon layer, forming a top silicon layer over the silicon-germanium layer, and forming an oxide layer over the top silicon layer. A first region of the top silicon layer has a first thickness, and a second region of the top silicon layer has a second thickness different from the first thickness. The method further includes the steps of bonding the device wafer to the carrier wafer such that the oxide layer contacts the oxide substrate, and removing the doped silicon layer and the silicon-germanium layer to expose the top silicon layer. The method further includes the steps of forming a first semiconductor device over the first region of the top silicon layer and forming a second semiconductor device over the second region of the top silicon layer. Attached Figure Description

[0006] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 The diagram shows an example circuit according to some embodiments, including multiple semiconductor elements with different top layer thicknesses;

[0008] Figure 2A The flowcharts, based on some embodiments, illustrate a process for manufacturing semiconductor wafers with elements having different top-layer thicknesses;

[0009] Figures 2B to 2I A series of figures illustrating some embodiments. Figure 2A Each step of the manufacturing process;

[0010] Figure 3A The flowcharts, based on some embodiments, illustrate another process for manufacturing semiconductor wafers with elements having different top layer thicknesses;

[0011] Figures 3B to 3J A series of figures illustrating some embodiments. Figure 3A The steps in the manufacturing process;

[0012] Figure 4 The flowcharts, based on some embodiments, illustrate yet another process for manufacturing semiconductor wafers with elements having different top layer thicknesses.

[0013] [Symbol Explanation]

[0014] 100: Circuit

[0015] 106: Silicon layer

[0016] 107: Oxide layer

[0017] 110: Components

[0018] 111: Gate oxide layer

[0019] 112: Gate

[0020] 113: Spacer

[0021] 114: Source

[0022] 115: Drain

[0023] 116: Top silicon layer

[0024] 117: Additional oxide layer

[0025] 120: Components

[0026] 121: Gate oxide layer

[0027] 122: Gate

[0028] 123: Spacers

[0029] 124: Source

[0030] 125: Drain

[0031] 126: Top silicon layer

[0032] 127: Additional oxide layer

[0033] 130: Components

[0034] 131: Gate oxide layer

[0035] 132: Gate

[0036] 133: Spacer

[0037] 134: Source

[0038] 135: Drain

[0039] 136: Top silicon layer

[0040] 137: Additional oxide layer

[0041] 140: BOX layer

[0042] 150: Silicon substrate

[0043] 152: Doped substrate layer

[0044] 161: Isolation Structure

[0045] 162: Isolation Structure

[0046] 163: Isolation Structure

[0047] 164: Isolation Structure

[0048] 170: Silicon-germanium layer

[0049] 200: Process

[0050] 206: Silicon layer

[0051] 207: Oxide layer

[0052] 212: Steps

[0053] 222: Steps

[0054] 224: Steps

[0055] 226: Steps

[0056] 228: Steps

[0057] 232: Steps

[0058] 234: Steps

[0059] 236: Steps

[0060] 240: Insulation layer

[0061] 250: Substrate layer

[0062] 252: Doped substrate layer

[0063] 270: Silicon-germanium layer

[0064] 280: Rich Trap Layer

[0065] 300: Process

[0066] 312: Steps

[0067] 314: Steps

[0068] 322: Steps

[0069] 324: Steps

[0070] 326: Steps

[0071] 328: Steps

[0072] 332: Steps

[0073] 334: Steps

[0074] 336: Steps

[0075] 400: Process

[0076] 401: Steps

[0077] 402: Steps

[0078] 403: Steps

[0079] 404: Steps

[0080] 405: Steps

[0081] T O1 :variable

[0082] T O2 :variable

[0083] T O3 :variable

[0084] T S1 :variable

[0085] T S2 :variable

[0086] T S3 :variable Detailed Implementation

[0087] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0088] Furthermore, for ease of explanation, spatially relative terms such as “below,” “under,” “below,” “above,” “above,” and the like may be used herein to describe the relationship between one component or feature as illustrated in the figures and other components or features(s). These spatially relative terms are intended to cover different orientations of elements in use or operation, in addition to those described in the figures. The device may be otherwise positioned (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0089] Now refer to Figure 1According to some embodiments, example circuit 100 includes a plurality of semiconductor elements with different top layer thicknesses. Circuit 100 is generally a monolithic substrate (sometimes also referred to as a wafer or chip) comprising a plurality of semiconductor elements. In some embodiments, these semiconductor elements are metal-oxide-semiconductor field-effect transistors (MOSFETs) disposed on a silicon-on-insulator (SOI) substrate structure. For example, these semiconductor elements can be used as multiple-time programmable (MTP) memory elements in non-volatile memory structures. Nevertheless, other similar types of materials and elements are also contemplated.

[0090] The circuit 100 shown includes three separate semiconductor elements: semiconductor element 110, semiconductor element 120, and semiconductor element 130. Semiconductor elements 110, 120, and 130 are formed on a common substrate. The circuit 100 includes a silicon substrate 150 and a buried oxide (BOX) layer 140 formed on the top surface of the silicon substrate 150. For example, the silicon substrate 150 and the BOX layer 140 may be the bottom layer of an SOI structure. In some embodiments, the silicon substrate 150 is a bulk silicon layer. The BOX layer 140 may be formed of a silicon dioxide material, and, for example, an insulating layer disposed between the silicon layers can be provided to reduce parasitic capacitance.

[0091] The semiconductor device 110 shown includes a gate oxide layer 111, a gate 112, a spacer 113, a source 114, and a drain 115. The gate oxide layer 111 is generally a dielectric layer that spaces the gate 112 from the source 114 and the drain 115. For example, the gate oxide layer 111 may be formed of, for example, silicon nitride, aluminum oxide, silicon dioxide, and other suitable materials. In some embodiments, the gate 112 is formed of polysilicon. However, the gate 112 may also be a metal gate. The voltage applied to the gate 112 can generally control the operation and conduction of the semiconductor device 110. The spacer 113 is formed around the gate 112 to provide electrical isolation of the gate 112 and prevent charge leakage. The spacer 113 may be formed of a material having a high dielectric constant, for example, silicon nitride, silicon oxide, or other suitable materials and combinations thereof. The source 114 and the drain 115 are (e.g., n-type, p-type) doped regions.

[0092] The semiconductor device 110 shown also includes a top silicon layer 116 and an additional oxide layer 117. The top silicon layer 116 is an activation layer in contact with the source 114, drain 115, and gate oxide layer 111. The additional oxide layer 117 is an additional oxide material substantially below device 110 but not below device 120 or device 130 that thickens the BOX layer 140. For example, the additional oxide layer 117 may be additional silicon dioxide material disposed on top of the BOX layer 140 to form a larger depletion region.

[0093] Similarly, the illustrated semiconductor device 120 includes a gate oxide layer 121, a gate 122, a spacer 123, a source 124, a drain 125, a top silicon layer 126, and an additional oxide layer 127. These structures are similar to those described above, including a gate oxide layer 111, a gate 112, a spacer 113, a source 114, a drain 115, a top silicon layer 116, and an additional oxide layer 117. Further, the illustrated semiconductor device 130 includes a gate oxide layer 131, a gate 132, a spacer 133, a source 134, a drain 135, a top silicon layer 136, and an additional oxide layer 137. These structures are also similar to those described above, including a gate oxide layer 111, a gate 112, a spacer 113, a source 114, a drain 115, a top silicon layer 116, and an additional oxide layer 117.

[0094] The circuit 100 shown also includes multiple isolation structures 161, 162, 163, and 164. These isolation structures can be formed between components to prevent crosstalk and other undesirable phenomena. Isolation structures 161, 162, 163, and 164 can be formed of a dielectric material, for example, silicon oxide, silicon nitride, and other suitable materials and combinations thereof. The height of isolation structures 161, 162, 163, and 164 can vary depending on the thickness of the surrounding top silicon layer. For example, the height of isolation structure 162 can depend on T... S1 and T S2 This makes the height of the isolation structure 162 need to be greater than T. S1 and T S2 Both are significantly larger than a threshold. Similarly, the height of the isolation structure 163 can depend on T. S2 and T S3 This makes the height of the isolation structure 163 need to be greater than T. S2 and T S3 All must be at least one threshold value larger. However, the height and / or other dimensions of any of the isolation structures 161, 162, 163, and 164 can also be independent of the surrounding top silicon layer. These variables T will be discussed in more detail below. S1 T S2 and T S3 .

[0095] In some previous SOI structures, the thickness of the top silicon layer (similar to top silicon layers 116, 126, and 136) and the thickness of the BOX layer (similar to the sum of BOX layer 140 and associated additional oxide layers, such as additional oxide layer 117) were substantially the same for all elements on a common substrate. However, it is desirable to provide the ability to fabricate elements with different characteristics on a monolithic substrate. For example, it is desirable to simultaneously fabricate fully depleted semiconductor elements and partially depleted semiconductor elements on a monolithic substrate. Therefore, it is desirable to vary the thickness of the top silicon layer and the BOX layer for different elements on the same substrate. Circuit 100 provides an example of such a structure, in which top silicon layers 116, 126, and 136 all have different thicknesses, which will be discussed in more detail below.

[0096] Figure 1 The diagram provides illustrations of various dimensional characteristics of circuit 100, which can be altered to provide different properties to the semiconductor element. For semiconductor element 110, the variable T... S1 The thickness of the top silicon layer 116, measured vertically (along a direction perpendicular to the bottom surface of the gate 112), is represented by the variable T. O1 This represents the thickness of the additional oxide layer 117 as measured vertically (along a direction perpendicular to the bottom surface of the gate 112). For semiconductor device 120, the variable T... S2 The thickness of the top silicon layer 126, measured vertically (along a direction perpendicular to the bottom surface of the gate 122), is represented by the variable T. O2 This represents the thickness of the additional oxide layer 127 measured vertically (along a direction perpendicular to the bottom surface of the gate 122). Similarly, for the semiconductor element 130, the variable T... S3 The thickness of the top silicon layer 136, measured vertically (along the direction perpendicular to the bottom surface of the gate 132), is represented by the variable T. O3 This represents the thickness of the additional oxide layer 137 as measured vertically (along the direction perpendicular to the bottom surface of the gate 132).

[0097] Compared to partially depleted devices, fully depleted devices generally have a thinner top silicon layer. For example, in the structure of circuit 100, the top silicon layer thickness of a fully depleted device is typically between approximately 50 angstroms and 500 angstroms, while the top silicon layer thickness of a partially depleted device is typically between approximately 500 angstroms and 3000 angstroms. However, thicknesses outside these ranges are also possible depending on the intended application, and these ranges can vary. Figure 1As shown, semiconductor elements 110 and 120 are both partially depleted elements, while semiconductor element 130 is a fully depleted element. Furthermore, the combined thickness of the BOX layer 140 and the additional oxide layer 117 (or additional oxide layer 127 or additional oxide layer 137) typically ranges from approximately 500 angstroms to 5000 angstroms. However, this range can vary depending on the intended application, and thicknesses outside this range can also be considered. Further, in some embodiments, T... S1 +T O1 and, T S2 +T O2 The sum of T S3 +T O3 The sums are equal or approximately equal (e.g., within 10%).

[0098] Now refer to Figure 2A The flowchart illustrates a process 200 for manufacturing semiconductor wafers with different top layer thicknesses, according to some embodiments. Figures 2B to 2I A series of figures are provided according to some embodiments, illustrating the steps of process 200. Process 200 can be used to produce circuit structures such as circuit 100, wherein semiconductor elements on the same substrate (e.g., SOI structure) have different top layer thicknesses. For example, some elements on a wafer produced using process 200 may be partially depleted elements, and other elements on the wafer may be fully depleted elements.

[0099] Process 200 can be broadly divided into three sub-processes. In the first sub-process, a carrier wafer is formed. In the second sub-process, a component wafer is formed. In the third sub-process, the carrier wafer and the component wafer are bonded together. In step 212, an insulating layer is formed on top of the substrate layer to form the carrier wafer. Figure 2B For example, step 212 may include forming a BOX layer 140 on top of the silicon substrate 150. However, the insulating layer and the substrate layer can be formed of various suitable materials. The carrier wafer is typically large enough to form numerous semiconductor elements on it. The insulating layer can be formed on the substrate layer in various ways, such as depositing or growing the insulating layer on the substrate layer.

[0100] In step 222, a device wafer is formed by forming a silicon layer and a silicon-germanium layer on the doped substrate layer. Figure 2C For example, the doped substrate layer can be a bulk silicon substrate layer doped with a p-type dopant, such as boron, thereby forming a P+ / P- doping interface within the bulk silicon substrate layer. In some embodiments, a silicon-germanium layer is formed above the doped substrate layer, and a silicon layer is formed above the silicon-germanium layer. In some embodiments, both the silicon-germanium layer and the silicon layer are formed on the doped substrate layer using an epitaxial growth process. Figure 2CAs shown, a silicon-germanium layer 170 is formed above a doped substrate layer 152, and a silicon layer 106 is formed above a silicon-germanium layer 170.

[0101] In step 224, the silicon layer is etched based on the expected top layer thickness for one or more components. Figure 2D For example, if a fully depleted device is desired, step 224 may include etching at least a portion of the silicon layer to a thickness between approximately 50 and 500 angstroms. However, if a partially depleted device is desired, step 224 may include etching at least a portion of the silicon layer to a thickness between approximately 500 and 3000 angstroms. Depending on the intended application, thicknesses outside these ranges may also be applicable, and these ranges can vary. The ability to control the silicon layer thickness in step 224 provides the capability to fabricate devices with different top-layer thicknesses on the same wafer. Figure 2D As shown, silicon layer 106 is etched to different thicknesses in different regions, ultimately forming individual devices on top of each region. These different regions can ultimately become top silicon layers 116 and 126. For example, for ease of fabrication or use in memory applications, partially depleted devices with thicker top silicon layers are desirable. For example, for reduced power consumption, fully depleted devices with thinner top silicon layers are desirable.

[0102] In step 226, an oxide layer is formed over the etched silicon layer. Figure 2E For example, step 226 may include the step of forming an additional oxide layer 117. In some embodiments, in step 226, the oxide layer is deposited over the etched silicon layer. However, the oxide layer can be formed over the etched silicon layer in various ways, including growing the oxide layer over the etched silicon layer. Figure 2E As shown, oxide layer 107 is formed above silicon layer 106.

[0103] In step 228, the oxide layer is polished. Figure 2F The oxide layer can be polished in various ways, including chemical-mechanical polishing (CMP), wet cleaning, dry cleaning, etching, and other suitable methods and combinations thereof. Step 228 generally involves thinning the oxide layer to create a flat and smooth surface, rather than the rough surface that can exist after depositing the oxide layer in step 226. Figure 2F As shown, after polishing in step 228, the oxide layer 107 has different thicknesses in different regions depending on the thickness of the underlying silicon layer 106. This structure is consistent with the structure described above for circuit 100, wherein, for example, T S1 +T O1The sum of T S2 +T O2 The sums are equal or approximately equal. Furthermore, such as... Figure 2F As shown, the oxide layer 107 has an exposed flat surface for bonding to a carrier wafer.

[0104] After step 228 is completed, the component wafer is formed, and process 200 then proceeds to the wafer bonding stage. In step 232, the carrier wafer and the component wafer are bonded together such that the oxide layer of the component wafer contacts the insulating layer of the carrier wafer. Figure 2G For example, a component wafer can be bonded to a carrier wafer such that the additional oxide layer 117 contacts the BOX layer 140. As discussed, the additional oxide layer 117 and the BOX layer 140 can be formed of the same or similar materials, such as silicon dioxide. Multiple different component wafers can be bonded to the carrier wafer in this manner to ultimately provide the wafer with numerous components with different top layer thicknesses. Figure 2G As shown, after the bonding in step 228, the oxide layer 107 comes into contact with the BOX layer 140.

[0105] In step 234, the doped substrate layer of the component wafer is removed. Figure 2H Step 234 can be performed in various ways, such as polishing the doped substrate layer, etching the doped substrate layer using a mixture of hydrofluoric acid, nitric acid, and acetic acid (HNA), and other suitable processes. Polishing and / or HNA processes can be used to thin the doped substrate layer down to the doped region, for example, to the P+ / P- interface. That is, polishing and / or HNA processes can be used to partially remove the doped substrate layer of the device wafer. Step 234 may then include polishing the remaining material on the doped substrate layer. For example, this can be done by using a chemical mechanical polishing process and / or a wet etching process to expose the underlying silicon-germanium layer. Because the doped substrate layer has been treated using an ion implantation process, it can be removed more easily and / or more cleanly compared to a previously undoped similar substrate layer. Figure 2H As shown, the doped substrate layer 152 has been removed.

[0106] In step 236, the silicon-germanium layer is removed and the top surface of the silicon layer is polished. Figure 2IIn some embodiments, a wet etching process is used to remove the silicon-germanium layer. Further, a wet washing process and / or a thermal washing process can be used to polish the top surface of the silicon layer. After performing step 236, semiconductor device structures (such as those described above) can be formed on the remaining structure. For example, a shallow trench isolation (STI) process can be performed to fabricate structures such as isolation structures 161, 162, 163, and 164. Further, a gate oxide layer 111, a gate 112, a spacer 113, a source 114, and a drain 115 can be formed over the polished silicon layer. Additionally, the silicon layer can be doped, and silicide can be deposited to form conductive electrode terminals over the gate 112, source 114, and drain 115. Figure 2I As shown, the silicon-germanium layer 170 was removed.

[0107] Now refer to Figure 3A The flowchart, according to some embodiments, illustrates a process 300 for manufacturing semiconductor wafers with elements having different top layer thicknesses. Figures 3B to 3J A series of figures are provided according to some embodiments, illustrating the steps of process 300. Process 300 can be used to produce circuit structures such as circuit 100, wherein semiconductor elements on the same substrate (e.g., SOI structure) have different top layer thicknesses. For example, some elements on a wafer produced using process 300 may be partially depleted elements, and other elements on the wafer may be fully depleted elements. Process 300 also includes the step of forming a trap-rich layer within a carrier wafer.

[0108] Process 300 can be broadly divided into three sub-processes. In the first sub-process, a carrier wafer is formed. In the second sub-process, a device wafer is formed. In the third sub-process, the carrier wafer and the device wafer are bonded together. In step 312, a trap-rich layer is formed on top of the substrate layer. Figure 3B The substrate layer 250 and the trap-rich layer 280 are included. In step 314, an insulating layer is formed on top of the trap-rich layer. Figure 3C The carrier wafer is formed by the insulating layer 240. For example, a trap-rich layer may be formed between the BOX layer 140 and the silicon substrate 150. The trap-rich layer can reduce the effective resistivity of the carrier wafer structure by trapping charges such as positive surface charges. For example, the trap-rich layer may be formed from crystalline silicon and other suitable materials.

[0109] The steps involved in forming the device wafer and bonding it to the carrier wafer in process 300 are similar to those in process 200 described above. In step 322, a silicon layer and a silicon-germanium layer are formed on the doped substrate layer. Figure 3DThe device wafer is formed by using a doped substrate layer 252, a silicon-germanium layer 270, and a silicon layer 206. In step 324, the silicon layer is etched based on the expected top layer thickness for one or more devices. Figure 3E In step 326, an oxide layer is formed over the etched silicon layer. Figure 3F The oxide layer 207 in the middle). In step 328, the oxide layer is polished ( Figure 3G In step 332, the carrier wafer and the component wafer are bonded such that the oxide layer of the component wafer contacts the insulating layer of the carrier wafer. Figure 3H In step 334, the doped substrate layer of the component wafer is removed. Figure 3I In step 336, the silicon-germanium layer is removed and the top surface of the silicon layer is polished. Figure 3J ).

[0110] Now refer to Figure 4 The flowchart illustrates a process 400 for manufacturing semiconductor wafers with elements having different top-layer thicknesses, according to some embodiments. Process 400 can be used to produce circuit structures such as circuit 100, wherein semiconductor elements on the same substrate (e.g., an SOI substrate) have different top-layer thicknesses. For example, some elements on a wafer produced using process 400 may be partially depleted elements, while other elements on this wafer may be fully depleted elements.

[0111] The illustrated process 400 includes forming a carrier wafer by forming an oxide substrate over a silicon substrate (step 401). For example, step 401 may include forming a BOX layer 140 over a silicon substrate 150. In some embodiments, a trap-rich layer is formed between the oxide substrate and the silicon substrate to trap charges and reduce the effective resistivity of the carrier wafer structure.

[0112] The illustrated process 400 also includes forming a device wafer by forming a silicon-germanium layer over a doped silicon layer, a top silicon layer over the silicon-germanium layer, and an oxide layer over the top silicon layer (step 402). In some embodiments, both the silicon-germanium layer and the top silicon layer are formed over the doped silicon layer using an epitaxial growth process. Furthermore, in some embodiments, the top silicon layer is etched so that it has different thicknesses in different regions. For example, the top silicon layer may be etched so that it has two or more different regions with different thicknesses. In this sense, different semiconductor devices can be formed over these different regions of the top silicon layer, such that these devices have different characteristics but are disposed on this wafer.

[0113] The illustrated process 400 includes bonding a component wafer to a carrier wafer such that an oxide layer contacts an oxide substrate (step 403). Prior to bonding in step 403, the oxide layer may be polished using, for example, a chemical mechanical polishing process. Multiple component wafers may be bonded to the carrier wafer, or a single component wafer may be bonded to different regions of the carrier wafer with different thicknesses.

[0114] The illustrated process 400 also includes removing the doped silicon layer and the silicon-germanium layer to expose the top silicon layer (step 404). The step of removing the doped silicon layer may include using a polishing process and / or using an HNA mixture to remove at least a portion of the doped silicon layer. The step of removing the silicon-germanium layer may include using a wet etching process to remove the silicon-germanium layer. After exposing the top silicon layer, for example, a wet cleaning process or a thermal cleaning process may be used to polish the top silicon layer.

[0115] The illustrated process 400 also includes forming a first semiconductor element over a first region of the top silicon layer and forming a second semiconductor element over a second region of the top silicon layer (step 405). For example, these regions can be different regions of the top silicon layer with different thicknesses as described above. In this sense, different semiconductor elements can be formed over these different regions of the top silicon layer, such that these elements have different characteristics but are disposed on the same wafer. For example, the first region of the top silicon layer can have a thickness between 500 angstroms and 3000 angstroms, and the second region of the top silicon layer can have a thickness between 50 angstroms and 500 angstroms. Depending on the intended application, thicknesses outside these ranges may also be applicable, and these ranges can vary. In this example, the first semiconductor element is a partially depleted element, and the second semiconductor element is a fully depleted element.

[0116] The methods discussed in this paper enable the fabrication of single semiconductor wafers with varying top-layer thicknesses. An advantage of this structure is that all semiconductor elements need not possess identical or nearly identical characteristics. For example, fully depleted and partially depleted elements can be formed on a single wafer. Depending on the intended application, this structure and the fabrication processes discussed in this paper can be utilized in various ways.

[0117] One embodiment of this disclosure is an integrated circuit device. The circuit includes a silicon substrate, an oxide substrate, a first top silicon layer, a second top silicon layer, a first semiconductor element, and a second semiconductor element. The oxide substrate is formed over the silicon substrate. The first top silicon layer is formed over a first region of the oxide substrate and has a first thickness. The second top silicon layer is formed over a second region of the oxide substrate and has a second thickness less than the first thickness. The first semiconductor element is formed over the first top silicon layer, and the second semiconductor element is formed over the second top silicon layer. In some embodiments, the first semiconductor element includes a partially depleted element, and the first thickness is between 500 angstroms and 3000 angstroms. The second semiconductor element includes a fully depleted element, and the second thickness is between 50 angstroms and 500 angstroms. In some embodiments, the first region of the oxide substrate has a third thickness. The second region of the oxide substrate has a fourth thickness, and the fourth thickness is greater than the third thickness. In some embodiments, the sum of the first thickness and the third thickness is equal to the sum of the second thickness and the fourth thickness. In some embodiments, the oxide substrate includes a buried oxide layer formed of silicon dioxide. In some embodiments, the aforementioned circuit further includes an isolation structure formed between the first semiconductor element and the second semiconductor element. The height of the isolation structure is greater than the first thickness or the second thickness.

[0118] Another embodiment of this disclosure is a method for manufacturing an integrated circuit device. The method includes forming a carrier wafer by forming an oxide substrate over a silicon substrate. The method further includes the steps of forming a first element wafer by forming a first top silicon layer having a first thickness over a first doped silicon layer and forming a first oxide layer over the first top silicon layer, and bonding the first element wafer to a first region of the carrier wafer such that the first oxide layer is in contact with the oxide substrate. The method further includes the steps of forming a second element wafer by forming a second top silicon layer having a second thickness less than the first thickness over a second doped silicon layer and forming a second oxide layer over the second top silicon layer, and bonding the second element wafer to a second region of the carrier wafer such that the second oxide layer is in contact with the oxide substrate. The method further includes the steps of removing the first doped silicon layer and removing the second doped silicon layer to expose the first and second top silicon layers, forming a first semiconductor element over the first top silicon layer, and forming a second semiconductor element over the second top silicon layer. In some embodiments, the step of forming the first top silicon layer over the first doped silicon layer includes the step of forming the first top silicon layer over the first doped silicon layer using an epitaxial growth process. In some embodiments, the aforementioned method further includes the following steps: forming a silicon-germanium layer over the first doped silicon layer before forming a first top silicon layer over the first doped silicon layer, and the step of forming the first top silicon layer over the first doped silicon layer includes the step of forming the first top silicon layer over the silicon-germanium layer. In some embodiments, the aforementioned method further includes the step of etching the first top silicon layer according to a first thickness before forming a first oxide layer over the first top silicon layer. In some embodiments, the aforementioned method further includes the step of polishing the top surface of the first top silicon layer using a wet cleaning process or a thermal cleaning process before forming a first semiconductor device over the first top silicon layer. In some embodiments, the aforementioned method further includes the step of polishing the first oxide layer using a chemical mechanical polishing process before bonding the first device wafer to a first region of the carrier wafer. In some embodiments, the aforementioned method further includes the step of forming a trap-rich silicon layer over the oxide substrate before forming an oxide substrate on the silicon substrate. The step of forming an oxide substrate on the silicon substrate includes the step of forming an oxide substrate on the trap-rich silicon layer.

[0119] Another embodiment disclosed herein is a method for manufacturing an integrated circuit device. The method includes forming a carrier wafer by forming an oxide substrate over a silicon substrate. The method further includes the steps of forming a device wafer by forming a silicon-germanium layer over a doped silicon layer, forming a top silicon layer over the silicon-germanium layer, and forming an oxide layer over the top silicon layer. A first region of the top silicon layer has a first thickness, and a second region of the top silicon layer has a second thickness different from the first thickness. The method further includes the steps of bonding a device wafer to a carrier wafer such that the oxide layer contacts the oxide substrate, and removing the doped silicon layer and the silicon-germanium layer to expose the top silicon layer. The method further includes the steps of forming a first semiconductor device over the first region of the top silicon layer and forming a second semiconductor device over the second region of the top silicon layer. In some embodiments, the step of removing the doped silicon layer includes the step of removing at least a portion of the doped silicon layer using a mixture of hydrofluoric acid, nitric acid, and acetic acid. In some embodiments, the step of removing the silicon-germanium layer includes the step of removing the silicon-germanium layer using a wet etching process. In some embodiments, the aforementioned method further includes the step of forming a trap-rich silicon layer over the oxide substrate before forming the oxide substrate on the silicon substrate. The step of forming an oxide substrate on a silicon substrate includes the step of forming an oxide substrate on a trap-rich silicon layer. In some embodiments, the step of removing a doped silicon layer includes the step of removing at least a portion of the doped silicon layer using a polishing process. In some embodiments, the aforementioned method further includes the step of polishing the top surface of the top silicon layer using a wet cleaning process or a thermal cleaning process before forming a semiconductor device over the top silicon layer. In some embodiments, the aforementioned method further includes the step of etching a first region of the top silicon layer according to a first thickness and etching a second region of the top silicon layer according to a second thickness before forming an oxide layer over the top silicon layer.

[0120] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A method of fabricating an integrated circuit device, characterized by, Includes the following steps: A carrier wafer is formed by forming an oxide substrate over a silicon substrate, wherein a trap-rich silicon layer is formed below the oxide substrate before the step of forming the oxide substrate on the silicon substrate, and the step of forming the oxide substrate on the silicon substrate includes forming the oxide substrate on the trap-rich silicon layer. A first device wafer is formed by forming a first top silicon layer over a first doped silicon layer and a first oxide layer over the first top silicon layer, the first top silicon layer having a first thickness; The first component wafer is bonded to a first region of the carrier wafer such that the first oxide layer is in contact with the oxide base layer; A second device wafer is formed by forming a second top silicon layer over a second doped silicon layer and a second oxide layer over the second top silicon layer, wherein the second top silicon layer has a second thickness less than the first thickness; The second element wafer is bonded to a second region of the carrier wafer such that the second oxide layer is in contact with the oxide base layer; Remove the first doped silicon layer and the second doped silicon layer to expose the first top silicon layer and the second top silicon layer; A first semiconductor element is formed above the first top silicon layer, and a second semiconductor element is formed above the second top silicon layer; as well as An isolation structure is formed between the first semiconductor element and the second semiconductor element, wherein the isolation structure separates the first oxide layer and the second oxide layer.

2. The method of claim 1, wherein, The step of forming the first top silicon layer over the first doped silicon layer includes the following steps: forming the first top silicon layer over the first doped silicon layer using an epitaxial growth process.

3. The method of claim 2, wherein, The method further includes the following steps: before forming the first top silicon layer over the first doped silicon layer, forming a silicon-germanium layer over the first doped silicon layer, wherein the step of forming the first top silicon layer over the first doped silicon layer includes the following steps: forming the first top silicon layer over the silicon-germanium layer.

4. The method of claim 1, wherein, It further includes the following step: etching the first top silicon layer according to the first thickness before the step of forming the first oxide layer over the first top silicon layer.

5. The method of claim 1, wherein, The method further includes the following step: prior to the step of forming the first semiconductor element over the first top silicon layer, polishing a top surface of the first top silicon layer using a wet cleaning process or a hot cleaning process.

6. The method of claim 1, wherein, The method further includes the following step: polishing the first oxide layer using a chemical mechanical polishing process prior to bonding the first element wafer to a first region of the carrier wafer.

7. The method of claim 1, wherein, One bottom surface of the isolation structure is lower than one bottom surface of the first top silicon layer and one bottom surface of the second top silicon layer.

8. A method of fabricating an integrated circuit device, characterized by: Includes the following steps: A carrier wafer is formed by forming an oxide substrate over a silicon substrate; A device wafer is formed by forming a silicon-germanium layer above a doped silicon layer, a top silicon layer is formed above the silicon-germanium layer, and an oxide layer is formed above the top silicon layer, wherein a first region of the top silicon layer has a first thickness and a second region of the top silicon layer has a second thickness different from the first thickness; The component wafer is bonded to the carrier wafer such that the oxide layer is in contact with the oxide base layer; Remove the doped silicon layer and the silicon-germanium layer to expose the top silicon layer; A first semiconductor element is formed above the first region of the top silicon layer, and a second semiconductor element is formed above the second region of the top silicon layer; as well as An isolation structure is formed between the first semiconductor element and the second semiconductor element, wherein a top surface of the isolation structure is higher than a top surface of the top silicon layer.

9. The method according to claim 8, characterized in that, The step of removing the doped silicon layer includes the following steps: removing at least a portion of the doped silicon layer using a mixture of hydrofluoric acid, nitric acid and acetic acid.

10. The method of claim 8, wherein, The process of removing the silicon-germanium layer includes the following steps: removing the silicon-germanium layer using a wet etching process.

11. The method of claim 8, wherein, The method further includes the following steps: forming a trap-rich silicon layer on top of the oxide layer before forming the oxide layer on the silicon substrate, wherein the step of forming the oxide layer on the silicon substrate includes the following steps: forming the oxide layer on the trap-rich silicon layer.

12. The method of claim 8, wherein, The step of removing the doped silicon layer includes the following steps: removing at least a portion of the doped silicon layer using a polishing process.

13. The method of claim 8, wherein, The method further includes the following step: prior to the step of forming the semiconductor device over the top silicon layer, polishing a top surface of the top silicon layer using a wet cleaning process or a hot cleaning process.

14. The method of claim 8, wherein, The method further includes the following steps: before forming the oxide layer over the top silicon layer, etching the first region of the top silicon layer according to the first thickness and etching the second region of the top silicon layer according to the second thickness.

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