Semiconductor structure, image sensor, and method for forming semiconductor structure

Abstract

A semiconductor structure, an image sensor, and a method for forming a semiconductor structure, wherein the semiconductor structure includes a photodiode, wherein the photodiode includes a substrate semiconductor layer having a first conductivity type doping, a second conductivity type photodiode layer forming a p-n junction with the substrate semiconductor layer, a floating diffusion region laterally separated from the second conductivity type photodiode layer, and a transfer gate electrode. The transfer gate electrode includes a transfer gate electrode lower portion formed in the substrate semiconductor layer, and the transfer gate electrode lower portion is located between the second conductivity type photodiode layer and the floating diffusion region. The transfer gate electrode can laterally surround the p-n junction and provide enhanced electron transfer efficiency from the p-n junction to the floating diffusion region. The photodiode array can be used in an image sensor.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures including photodetectors and methods of manufacturing the same. Background Art

[0002] Semiconductor image sensors are used to sense electromagnetic radiation, such as visible range light, infrared radiation, and / or ultraviolet light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications, such as digital cameras or cameras installed in mobile devices. These devices use pixel arrays (which may include photodiodes and transistors) and use photoelectric generation of electron-hole pairs to detect radiation. Summary of the invention

[0003] According to some embodiments of the present disclosure, a semiconductor structure including a photodiode is provided, wherein the photodiode includes a substrate semiconductor layer having a first conductivity type doping, a second conductivity type photodiode layer forming a pn junction with the substrate semiconductor layer, a floating diffusion region laterally separated from the second conductivity type photodiode layer, and a transfer gate electrode. The transfer gate electrode includes a transfer gate electrode lower portion formed in the substrate semiconductor layer, and the transfer gate electrode lower portion is located between the second conductivity type photodiode layer and the floating diffusion region.

[0004] According to some embodiments of the present disclosure, an image sensor is provided, comprising a plurality of pixels located in a substrate semiconductor layer having a first conductivity type doping. Each pixel comprises a photodiode circuit, the photodiode circuit comprising a photodiode and a sensing circuit. The photodiode comprises a second conductivity type photodiode layer forming a pn junction with the substrate semiconductor layer, a floating diffusion region laterally separated from the second conductivity type photodiode layer, and a transfer gate electrode, wherein the floating diffusion region is located on the front horizontal surface of the substrate semiconductor layer. The transfer gate electrode comprises a lower portion of the transfer gate electrode formed in the substrate semiconductor layer, and the lower portion of the transfer gate electrode is located between the second conductivity type photodiode layer and the floating diffusion region. Each pixel comprises an individual optical component located on the substrate semiconductor layer and configured to guide incident light to an individual pn junction of the photodiode.

[0005] According to some embodiments of the present disclosure, a method for forming a semiconductor structure is provided, including providing a semiconductor substrate including a substrate semiconductor layer, forming a second conductive type photodiode layer in the substrate semiconductor layer, forming a transfer gate electrode including a lower portion of a transfer gate electrode, and forming a floating diffusion region in a portion of the substrate semiconductor layer adjacent to the transfer gate electrode. The substrate semiconductor layer includes a first conductive type doping. The second conductive type photodiode layer and the substrate semiconductor layer form a pn junction. The lower portion of the transfer gate electrode is formed in the substrate semiconductor layer adjacent to the pn junction. The transfer gate electrode is located between the second conductive type photodiode layer and the floating diffusion region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard methods in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a top view of a first configuration of an image sensor pixel array according to an embodiment of the present disclosure;

[0008] Figure 1B is a top view of a second configuration of an image sensor pixel array according to another embodiment of the present disclosure;

[0009] Figure 2A is a vertical cross-sectional view of a first exemplary structure of forming a sub-pixel in a process step after forming a trench in a semiconductor layer of a substrate according to a first embodiment of the present disclosure;

[0010] Figure 2B yes Figure 2A The vertical plane AA′-A″ is Figure 2A Vertical cross-sectional view of the plane, connecting Figure 2A The vertical axes A, A′ and A″;

[0011] Figure 3A is a vertical cross-sectional view of a first exemplary structure in a process step after forming a gate dielectric and a gate electrode according to a first embodiment of the present disclosure;

[0012] Figure 3B yes Figure 3A The vertical plane AA′-A″ is Figure 3A Vertical cross-sectional view of the plane, connecting Figure 3A The vertical axes A, A′ and A″;

[0013] Figure 4Ais a vertical cross-sectional view of a first exemplary structure in a process step after forming a field effect transistor according to the first embodiment of the present disclosure;

[0014] Figure 4B yes Figure 4A The vertical plane AA′-A″ is Figure 4A Vertical cross-sectional view of the plane, connecting Figure 4A The vertical axes A, A′ and A″;

[0015] Figure 4C yes Figure 4A and Figure 4B The first exemplary structure, along the Figure 4B vertical cross-section of the vertical plane CC′;

[0016] Figure 5 According to the second embodiment of the present disclosure, FIG. 4A to FIG. 4C A vertical cross-sectional view of the second exemplary structure during the process step of ;

[0017] Fig. 6A is a top view of a first configuration of a third exemplary structure after forming a field effect transistor according to a third embodiment of the present disclosure;

[0018] Figure 6B is a second configuration top view of the third exemplary structure after forming a field effect transistor according to the third embodiment of the present disclosure;

[0019] Fig. 7A is a first configuration top view of a fourth exemplary structure after forming a field effect transistor according to a fourth embodiment of the present disclosure;

[0020] Figure 7B is a second configuration top view of the fourth exemplary structure after forming a field effect transistor according to a fourth embodiment of the present disclosure;

[0021] Fig. 8A is a first configuration vertical cross-sectional view of a fifth exemplary structure after forming a field effect transistor according to a fifth embodiment of the present disclosure;

[0022] Figure 8B is a second configuration vertical cross-sectional view of the fifth exemplary structure after forming a field effect transistor according to a fifth embodiment of the present disclosure;

[0023] Fig. 9 is a vertical cross-sectional view of a sixth exemplary structure after forming a field effect transistor according to a sixth embodiment of the present disclosure;

[0024] Fig.10 is a vertical cross-sectional view of a seventh exemplary structure after forming a field effect transistor according to a seventh embodiment of the present disclosure;

[0025] Fig.11 is a vertical cross-sectional view of an exemplary structure after a metal interconnect structure is formed in an interconnect dielectric layer and connected to a carrier substrate according to an embodiment of the present disclosure;

[0026] Fig.12 is a vertical cross-sectional view of an exemplary structure after thinning the semiconductor substrate according to an embodiment of the present disclosure;

[0027] Fig.13 is a vertical cross-sectional view of an exemplary structure after forming a deep trench isolation structure according to an embodiment of the present disclosure;

[0028] Fig.14 is a vertical cross-sectional view of an exemplary structure after forming an antireflective coating (ARC), a light refractive layer, a dielectric grid material layer, a metal reflective material layer and a patterned photoresist layer according to an embodiment of the present disclosure;

[0029] Fig.15A is a vertical cross-sectional view of an exemplary structure after forming a composite grid structure according to an embodiment of the present disclosure;

[0030] Fig. 15B yes Fig.15A The vertical plane AA′ corresponds to Fig.15A The plane of the vertical cross-section;

[0031] Fig.16 is a vertical cross-sectional view of an exemplary structure after forming an optically transparent layer, a filter, and a lens according to an embodiment of the present disclosure;

[0032] Fig.17 is a vertical cross-sectional view of an exemplary structure after removing a carrier substrate according to an embodiment of the present disclosure;

[0033] Fig.18 is a circuit diagram of a light detector circuit according to an embodiment of the present disclosure;

[0034] Fig.19 is a process flow diagram illustrating an exemplary process sequence for forming a semiconductor structure including a photodetector according to an embodiment of the present disclosure.

[0035]

Explanation of symbols

[0036] 495: First Demonstration Structure

[0037] 500:Semiconductor substrate

[0038] 510: Thinning the semiconductor substrate

[0039] 595: Second Demonstration Structure

[0040] 600:Front sensor assembly

[0041] 601: substrate semiconductor layer

[0042] 602: second conductivity type photodiode layer

[0043] 605: Transmission gate electrode

[0044] 605a, 605b, 605c, 605d: transmission gate electrodes

[0045] 605L: Transmission gate electrode bottom

[0046] 605U: Transfer gate electrode upper part

[0047] 606: buried second conductivity type photodiode layer

[0048] 606A: Upper sublayer of the second conductive type photodiode

[0049] 606B: Lower sublayer of the second conductive type photodiode

[0050] 607: Doping well structure

[0051] 608: floating diffusion area

[0052] 608a, 608b, 608c, 608d: floating diffusion area

[0053] 608D: Deep floating diffusion area

[0054] 608E: Floating diffusion extension area

[0055] 609: front surface

[0056] 610: Back surface

[0057] 611: Transfer transistor body region

[0058] 612: Active area

[0059] 614: Gate dielectric

[0060] 614T: Transfer Gate Dielectric

[0061] 615: Gate electrode

[0062] 620: Shallow Trench Isolation Structure

[0063] 630: Transmission transistor

[0064] 639: Groove

[0065] 640: Reset transistor

[0066] 650: Power Follower Transistor

[0067] 660: Select transistor

[0068] 670:Internal connection dielectric layer

[0069] 680:Metal internal connection structure

[0070] 682:Metal Through Hole Structure

[0071] 684: Metal wire structure

[0072] 689: Bonding buffer layer

[0073] 690: Carrier substrate

[0074] 695: First Configuration

[0075] 696: Second Configuration

[0076] 709: Back surface

[0077] 720: Deep trench isolation structure

[0078] 732: Optional anti-reflective coating

[0079] 734: Optical buffer layer

[0080] 740: Grid structure

[0081] 742: Dielectric Grid Structure

[0082] 742L: Dielectric grid material layer

[0083] 744:Metal Grid Structure

[0084] 744L: Metal reflective material layer

[0085] 747: Photoresist layer

[0086] 770: Optically transparent layer

[0087] 780:Filter

[0088] 781: Type 1 filter

[0089] 782: Second type filter

[0090] 783: The third type of filter

[0091] 790: Optical lens

[0092] 795: First Configuration

[0093] 796: Second Configuration

[0094] 800: Sub-pixel

[0095] 801: first sub-pixel

[0096] 801D: First sensor area

[0097] 801S: First sensing circuit area

[0098] 802: second sub-pixel

[0099] 802D: Second sensor area

[0100] 802S: Second sensing circuit area

[0101] 803: third sub-pixel

[0102] 803D: Third sensor area

[0103] 803S: Third sensing circuit area

[0104] 895: First Configuration

[0105] 896: Second Configuration

[0106] 900: Pixels

[0107] 995: Sixth Demonstration Structure

[0108] 1000: Array

[0109] 1095: Seventh Demonstration Structure

[0110] 1910, 1920, 1930, 1940: Steps

[0111] A,A′,A″,C,C′: axis

[0112] C: Column

[0113] d1: first depth

[0114] d2: second depth

[0115] FD: Floating Diffusion Region

[0116] hd1: first horizontal direction

[0117] hd2: second horizontal direction

[0118] i,j,M,N: integer

[0119] P: Pixel

[0120] PD: Photodetector

[0121] R: OK

[0122] RST: Reset transistor

[0123] SEL: Select transistor

[0124] SF: Power Follower Transistor

[0125] TG: Transfer Gate Electrode

[0126] UC:Unit Cell

[0127] V_out: output voltage DETAILED DESCRIPTION

[0128] In order to realize the different features of the mentioned subject matter, the following disclosure provides many different embodiments or examples. Specific examples of components and configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not restrictive. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0129] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0130] The present disclosure focuses on semiconductor devices, and more particularly, photodetectors including buried gate electrodes of transfer transistors and methods of fabricating the same.

[0131] Generally speaking, the structures and methods of the present disclosure may be used to provide a photodetector including a transfer transistor including a transfer gate electrode formed in a substrate semiconductor layer. Thus, the transfer gate electrode extends from a top surface of the substrate semiconductor layer into the substrate semiconductor layer and functions as a buried transfer gate electrode. The transfer gate electrode may be formed in a trench formed in the substrate semiconductor layer. The transfer gate electrode may laterally surround a pn junction of the photodetector. Thus, the transfer gate electrode may laterally surround and electrically isolate a photovoltaic region of the photodetector. Additionally, the buried transfer gate electrode may improve the electron transfer efficiency of the photodetector. The buried transfer gate electrode of the disclosed embodiments may overcome the difficulty of electronic isolation of the photodetector, which relies on the implantation of electronic dopants. Various features and aspects of the disclosed embodiments are described in detail below with reference to illustrations of application demonstrations.

[0132] refer to Figure 1A and Figure 1B , a first configuration of an array 1000 of pixels 900 in an image sensor and a second configuration of an array 1000 of pixels 900 in an image sensor are depicted in top view, respectively. The image sensor may be a backside illuminated (BSI) image sensor device. However, it should be understood that embodiments of the present disclosure may be used in a frontside illuminated (FSI) image sensor.

[0133] Each pixel 900 represents the smallest unit area sufficient to generate an image from the image sensor. The area of ​​the array 1000 including the pixels 900 is referred to herein as the pixel array area. The pixels 900 in the pixel array area may be arranged in rows and columns. For example, the pixel array area may include M rows and N columns, where M and N are in the range from 1 to 2. 16 Integer, for example, from 2 8 To 2 14 The rows of pixels 900 may be numbered consecutively using integers ranging from 1 to M, and the columns of pixels 900 may be numbered consecutively using integers ranging from 1 to N. ij Represents pixel 900 at the i-th row and j-th column.

[0134] Each pixel 900 includes at least one photodetector configured to detect radiation in a specified wavelength range. Each pixel 900 may include a plurality of photodetectors configured to detect radiation in respective wavelength ranges, each of the plurality of photodetectors may have a different wavelength range. In one embodiment, each pixel 900 may include a plurality of sub-pixels, each of the sub-pixels including a respective combination of a photodetector and electronic circuitry, the respective combination of which is configured to detect radiation incident on the photodetector. For example, a pixel 900 may include a sub-pixel configured to detect radiation in a red wavelength range (e.g., in a range from 635 nanometers to 700 nanometers), a sub-pixel configured to detect radiation in a green wavelength range (e.g., in a range from 520 nanometers to 560 nanometers), and a sub-pixel configured to detect radiation in a blue wavelength range (e.g., in a range from 450 nanometers to 490 nanometers). Such sub-pixels are referred to as red sub-pixels, green sub-pixels, and blue sub-pixels, respectively.

[0135] Generally, the pixel 900 generates information about incident radiation in a unit detection area. A sub-pixel can generate information about the intensity of incident radiation measured in a specific wavelength range within the unit detection area. A monochrome pixel 900 may include only one sub-pixel. A pixel 900 configured to detect a spectral distribution of incident radiation includes a plurality of pixels having at least two different detection wavelength ranges. The light detectors in the pixel array area include photodiodes, complementary metal oxide semiconductor image sensors, charge coupled device sensors, active sensors, passive sensors, other suitable sensors, or combinations thereof.

[0136] refer to Figure 2A and Figure 2B , depicts a region where a sub-pixel is formed in the first exemplary structure 495 . Figure 2A and Figure 2B The area shown in FIG. 1 corresponds to pixels in the pixel array area (eg Figure 1A and Figure 1B The first exemplary structure includes a semiconductor substrate 500 including a substrate semiconductor layer 601 and various front-side device components formed in the substrate semiconductor layer 601.

[0137] Each sub-pixel may be formed on or in a substrate semiconductor layer 601 having a front surface 609 and a back surface 610. The substrate semiconductor layer 601 includes a semiconductor material such as silicon, germanium, a silicon-germanium alloy, a compound semiconductor material, or any other semiconductor material having a band gap, wherein the band gap does not exceed the energy of the photons to be detected. The selection of the material in the substrate semiconductor layer 601 may be based on the energy range of the photons to be detected by the sub-pixels. In one embodiment, the substrate semiconductor layer 601 may include single crystal silicon. Commercially available single crystal semiconductor substrates may be used for the semiconductor substrate 500. The semiconductor substrate 500 provided by this process step may have a thickness that is thick enough to withstand standard complementary metal oxide semiconductor process steps. For example, the thickness of the semiconductor substrate 500 may range from 200 microns to 1 millimeter, although lesser or greater thicknesses may also be used.

[0138] The top of the substrate semiconductor layer 601 may be suitably doped to have a first conductivity type, which may be a p-type or an n-type. The top of the substrate semiconductor layer 601 is a portion of the substrate semiconductor layer 601 that is used to form various front-side device components thereon, and the top remains in the final device structure after the bottom of the substrate semiconductor layer 601 is removed in a subsequent substrate thinning process. For example, an epitaxial semiconductor deposition process is performed to form a single crystal epitaxial semiconductor material layer on top of the substrate semiconductor layer 601, so that the atomic concentration of the first conductivity type dopant ranges from 1.0×10 13 / cm 3 to 1.0×10 16 / cm 3 , however, lesser or greater atomic concentrations may also be used. The thickness of the single crystal epitaxial semiconductor material layer may range from 1 micron to 10 microns, however, lesser or greater thicknesses may also be used.

[0139] Around the region of the photodetector pn junction to be formed later, ion implantation of the first conductivity type dopant may form a doped well structure 607. The doped well structure 607 may laterally surround the photodetector pn junction region and may be used to form a floating diffusion region (e.g. Figure 4B The atomic concentration of the first conductive type dopant in the doping well structure 607 ranges from 1.0×10 15 / cm 3 to 1.0×10 18 / cm 3 , however smaller or larger atomic concentrations may also be used.

[0140] Shallow trench isolation structures 620 may be formed to provide device isolation between various semiconductor devices formed subsequently or to isolate the devices themselves. One of the shallow trench isolation structures 620 may be formed in the top of the doped well structure 607. Shallow trench isolation structures 620 may be formed to provide electrical isolation between various components in a sub-pixel or to isolate the components themselves.

[0141] At least one mask ion implantation process may be used to implant a second conductivity type dopant through the front surface 609 of the semiconductor substrate 500. The second conductivity type is relative to the first conductivity type, and may be p-type or n-type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. At least one mask ion implantation process may be used to form various doped regions with the second conductivity type doping. Figure 2A The second conductive type photodiode layer 602 may be formed below the front surface 609 of the semiconductor substrate 500, so that the edge of the second conductive type photodiode layer 602 may overlap with the edge of the subsequently formed transfer gate electrode 605 in a top view. The lateral extension of the second conductive type photodiode layer 602 may be limited to one side of the subsequently formed transfer gate electrode 605. Therefore, at least one edge of the second conductive type photodiode layer 602 may be laterally separated from the shallow trench isolation structure 620 by the subsequently formed transfer gate electrode and the floating diffusion region.

[0142] By implanting the second conductivity type dopant with an implantation energy higher than the implantation process for forming the second conductivity type photodiode layer 602, a buried second conductivity type photodiode layer 606 can be formed below the second conductivity type photodiode layer 602 at a depth at the bottom of the doping well structure 607. The buried second conductivity type photodiode layer 606 can be offset laterally inward from the doping well structure 607.

[0143] In each sub-pixel, the top of the buried second conductivity type photodiode layer 606 may be adjacent to the bottom of the second conductivity type photodiode layer 602. In each sub-pixel, the area of ​​the second conductivity type photodiode layer 602 may be entirely located in the area of ​​the buried second conductivity type photodiode layer 606 below. In one embodiment, the buried second conductivity type photodiode layer 606 may include multiple sub-layers, such as a second conductivity type photodiode upper sub-layer 606A and a second conductivity type photodiode lower sub-layer 606B. The multiple sub-layers of the buried second conductivity type photodiode layer 606 may be formed by multiple ion implantation processes, wherein the implantation process implants the second conductivity type dopant at different depths in the semiconductor substrate 500.

[0144] In one embodiment, the depth of the top surface of the buried second conductivity type photodiode layer 606 can be in the range of 400 nanometers to 1500 nanometers, although lesser or greater depths can also be used. In one embodiment, the depth of the bottom surface of the buried second conductivity type photodiode layer 606 can be in the range of 800 nanometers to 2500 nanometers, although lesser or greater depths can also be used.

[0145] The undoped portion of the substrate semiconductor layer 601 covering the buried second conductivity type photodiode layer 606 (i.e., the transfer transistor body region 611) may have the first conductivity type of doping and may subsequently serve as the body region of the transfer transistor. Therefore, the undoped portion of the substrate semiconductor layer 601 covering the buried second conductivity type photodiode layer 606 is referred to herein as the transfer transistor body region 611. In one embodiment, the buried second conductivity type photodiode layer 606 may have the same lateral extension as the subsequently formed transfer transistor 630, and the transfer transistor 630 may overlap with a portion of the shallow trench isolation structure 620 that surrounds the combination of the second conductivity type photodiode layer 602 and the transfer transistor body region 611. The transfer transistor body region 611 is a portion of the substrate semiconductor layer 601.

[0146] Generally, a semiconductor substrate 500 including a substrate semiconductor layer 601 doped with a first conductivity type is provided, and a second conductivity type photodiode layer 602 is formed in the substrate semiconductor layer 601 by implanting a second conductivity type dopant. The second conductivity type photodiode layer 602 forms a pn junction with the substrate semiconductor layer 601 in a pn junction region, wherein the pn junction region is a photon detection region of the photodetector.

[0147] Figure 2B The portion shown in the first exemplary structure in FIG. 1 may constitute a unit cell (UC). A plurality of unit cells UC may be exemplarily repeated in a two-dimensional periodic array to form Figure 1A and Figure 1B Pixel array 1000 is shown in FIG.

[0148] refer to Figure 2A and Figure 2B, and according to aspects of the present disclosure, a photoresist layer (not shown) may be applied on the top surface of the semiconductor substrate 500 and may be lithographically patterned to form dispersed openings through the photoresist layer. The pattern of openings in the photoresist layer includes at least one opening configured around a respective pn junction region, wherein the pn junction region is the location of the interface between the transfer transistor body region 611 and a combination including the second conductivity type photodiode layer 602 and the buried second conductivity type photodiode layer 606. The photoresist layer may have a single opening defining the pn junction region, or may have multiple openings defining multiple pn junction regions.

[0149] An anisotropic etching process is performed to transfer the pattern of the opening in the photoresist layer to the upper portion of the substrate semiconductor layer 601. At least one trench 639 may be formed in each unit cell UC of the first exemplary structure. Each trench 639 extends vertically from the front horizontal surface (i.e., the front surface 609) of the substrate semiconductor layer 601 to the back horizontal back surface 610 of the substrate semiconductor layer 601. Each trench 639 may be formed adjacent to a respective second conductivity type photodiode layer 602.

[0150] In one embodiment, each trench 639 has a depth greater than that of a subsequently formed floating diffusion region (eg, Figure 4B The depth of the bottom surface of each trench 639 is greater than the vertical thickness of the floating diffusion region 608 in the second conductivity type photodiode layer 606. The depth of the bottom surface of each trench 639 is greater than the depth of the pn junction between the top surface of the second conductivity type photodiode layer 602 and the transfer transistor body region 611. The depth of the bottom surface of each trench 639 can be equal to, greater than, or less than the depth of the buried second conductivity type photodiode layer 606. For example, the depth of the bottom surface of each trench 639 can be in the range of 600 nanometers to 3000 nanometers (e.g., 800 nanometers to 2500 nanometers), although smaller or larger depths can also be used. Generally speaking, the depth of the bottom surface of each trench 639 can be selected so that the transfer gate electrode 605 subsequently formed therein can provide effective channel control between the pn junction and the subsequently formed floating diffusion region. In one embodiment, the depth of the bottom surface of each trench 639 can be greater than the depth of the buried second conductivity type photodiode layer 606. The depth of the bottom surface of each trench 639 can be selected so that the photoresist layer is not completely consumed during the anisotropic etching process. In other words, the anisotropic etching capability of etching the unmasked portion of the substrate semiconductor layer 601 can limit the maximum depth of the bottom surface of each trench 639 without indirectly damaging the masked portion of the substrate semiconductor layer 601 due to the consumption of the photoresist material.

[0151] In one embodiment, each trench 639 may be formed as a protection trench (moat trench) that laterally surrounds the respective second conductivity type photodiode layer 602. Figure 2A and Figure 2BAs shown, a protection groove refers to a groove having an inner edge that surrounds an area in the groove. Therefore, the inner edge of the protection groove can be separated laterally by the lateral width of the protection groove and the outer edge of the protection groove. The width of each groove 639 (that is, the lateral distance between the inner sidewall and the outer sidewall of the individual groove 639) can range from 100 nanometers to 600 nanometers, but smaller or larger widths can also be used. In one embodiment, each groove 639 may include a sidewall that extends vertically straight from the front surface 609 of the semiconductor substrate 500 to the bottom surface of the individual groove 639. In one embodiment, the groove 639 may not have any stepped surface. The photoresist layer can be removed subsequently, for example, by ashing. In an embodiment having a doped well structure 607 in each unit cell UC, the doped well structure 607 can laterally surround the groove 639 but does not laterally close the groove 639. The spacing in the doped well structure 607 can be located in an area close to a floating diffusion region formed subsequently.

[0152] refer to Figure 3A and Figure 3B , a gate dielectric layer may be formed on the bottom surface and sidewalls of each trench 639, and on the front horizontal surface of the substrate semiconductor layer 601 (i.e., the front surface 609 of the semiconductor substrate 500). The gate dielectric layer may include any gate dielectric material known in the art. For example, the gate dielectric layer may include silicon oxide, silicon oxynitride, and / or a dielectric metal oxide (e.g., aluminum oxide and / or hafnium oxide). Other suitable dielectric materials are also within the intended scope of the present disclosure. The gate dielectric layer may be formed as a conformal layer by thermal oxidation of a portion of the semiconductor material surface that physically exposes the semiconductor substrate 500, and / or conformal deposition of a dielectric material layer (e.g., chemical vapor deposition or atomic layer deposition). The thickness of the gate dielectric layer may range from 3 nanometers to 12 nanometers, although lesser or greater thicknesses may also be used.

[0153] A gate electrode material layer may be subsequently formed on the gate dielectric layer, wherein the gate dielectric layer is in and above each trench 639. The gate electrode material layer includes at least one gate electrode material, which may include heavily doped semiconductor materials (e.g., doped polysilicon) and / or metal gate materials, such as metal nitrides (e.g., titanium nitride), metal elements, or intermetallic alloys. The thickness of the gate electrode material layer may be selected so that the combination of the gate dielectric layer and the gate electrode material layer fills the entire volume of the trench 639 in each unit cell UC.

[0154] A photoresist layer (not shown) may be applied on the gate electrode material layer, and may be lithographically patterned to cover the area of ​​the gate electrode to be formed subsequently. The area covered by the patterned portion of the photoresist layer includes the entire area of ​​each trench 639. In one embodiment, each trench 639 in the unit cell UC may be a protection trench having an inner sidewall and an outer sidewall, and the area covered by the photoresist layer may include the entire area of ​​the protection trench. In addition, the area covered by the patterned portion of the photoresist layer may include the gate electrode area of ​​the field effect transistor in the sensing circuit to be formed subsequently.

[0155] An anisotropic etch may be performed to transfer the pattern in the photoresist layer, penetrating the gate electrode material layer and the gate dielectric layer. The patterned portion of the gate electrode layer includes a gate electrode. The gate electrode includes a transfer gate electrode 605 formed in or on individual trenches 639, and a planar gate electrode 615 may be formed in the sensing circuit area. The gate dielectric layer may be subsequently patterned using an anisotropic or isotropic etch process to form a gate dielectric 614, wherein the gate dielectric 614 includes a transfer gate dielectric 614T formed below the individual transfer gate electrodes 605, and includes a planar gate dielectric 614 that serves as a gate dielectric for a field effect transistor in the sensing circuit. Generally speaking, the transfer gate dielectric 614T may be patterned out of the gate dielectric layer after the gate electrode material layer is patterned into various gate electrodes.

[0156] In one embodiment, each transfer gate electrode 605 may include a transfer gate electrode lower portion 605L formed in the substrate semiconductor layer 601 and adjacent to the pn junction of the photodetector. The transfer gate electrode lower portion 605L may laterally surround the pn junction. The transfer gate electrode lower portion 605L is located in the trench. In one embodiment, each transfer gate electrode lower portion 605L may be located in a respective protection trench, and the protection trench laterally surrounds the respective second conductivity type photodiode layer 602. In addition, each transfer gate electrode 605 includes a transfer gate electrode upper portion 605U formed on the substrate semiconductor layer 601, and the transfer gate electrode upper portion 605U has a lateral extension greater than the transfer gate electrode lower portion 605L. Specifically, an edge portion of the transfer gate electrode upper portion 605U may be located in an area outside the lower trench and cover the front surface 609 of the semiconductor substrate 500. In one embodiment, each transfer gate electrode 605 may be topologically homeomorphic to the torus, that is, may be continuously extended into a torus shape without forming new holes or destroying existing holes.

[0157] refer to FIG. 4A to FIG. 4C , a masked ion implantation process can be performed to form various active regions, including a floating diffusion region 608 and an active region 612 of a field effect transistor in a sensing circuit. Various gate electrodes can be used as self-aligned mask structures outside of a patterned implanted mask layer (e.g., a lithography patterned photoresist layer) during the masked ion implantation process.

[0158] Each floating diffusion region 608 may be formed in a portion of the substrate semiconductor layer 601 adjacent to the respective transfer gate electrode 605. Each transfer gate electrode 605 is located between the second conductivity type photodiode layer 602 and the floating diffusion region 608 in the respective unit cell UC. In one embodiment, the floating diffusion region 608 in each unit cell UC may be formed by implanting a second conductivity type dopant in a portion of the substrate semiconductor layer 601 located below an edge region of the transfer gate electrode upper portion 605U, the transfer gate electrode upper portion 605U being located above the trench 639. In one embodiment, each floating diffusion region 608 may include a floating diffusion extension region 608E located below an edge region of the transfer gate electrode upper portion 605U, and a deep floating diffusion region 608D laterally spaced from the trench 639 and adjacent to a sidewall of the floating diffusion extension region 608E. Generally speaking, in a top view, the edge region of the transfer gate electrode upper portion 605U may have a portion that partially overlaps with the edge of the floating diffusion region 608, where the top view is along a direction perpendicular to the front horizontal surface of the substrate semiconductor layer 601 (i.e., the front surface 609 of the semiconductor substrate 500).

[0159] In one embodiment, the trench 639 in each unit cell UC may have a depth greater than the vertical thickness of the floating diffusion region 608 in the unit cell UC. For example, the floating diffusion region 608 may have a maximum depth in the range of 100 nanometers to 400 nanometers, although a smaller or larger maximum thickness may also be used. The transfer gate electrode 605 in each unit cell UC includes a transfer gate electrode lower portion 605L formed in the substrate semiconductor layer 601, and the transfer gate electrode lower portion 605L is located between the second conductivity type photodiode layer 602 and the floating diffusion region 608. In one embodiment, the transfer gate electrode lower portion 605L includes a flat bottom surface having an inner edge and an outer edge. The inner edge and the outer edge of the flat bottom surface laterally surround the second conductivity type photodiode layer 602 at the same depth from the horizontal surface of the front side of the substrate semiconductor layer 601. The current between the second conductivity type photodiode layer 602 and the floating diffusion region 608 in each unit cell UC can be controlled by the transfer gate electrode 605 in the unit cell UC.

[0160] A sensing circuit may be formed in each unit cell UC and configured to measure the amount of charge transferred from a pn junction between the transfer transistor body region 611 and the second conductivity type photodiode layer 602 through a semiconductor channel surrounding the transfer gate electrode 605 to the floating diffusion region 608 .

[0161] Photodetector circuits may be formed in each sub-pixel region on semiconductor substrate 500. Each photodetector circuit includes a respective set of front-side sensor components 600. Front-side sensor components 600 refer to all components of an image sensor, where the components may be formed on front surface 609 of semiconductor substrate 500 or may be formed in substrate semiconductor layer 601. Each photodetector circuit may include a photodetector (including transfer transistor 630) and a sensing circuit (including reset transistor 640, source follower transistor 650, and select transistor 660).

[0162] An interconnect-level dielectric layer 670 may be formed on the front surface 609 of the semiconductor substrate 500, and a metal interconnect structure 680 connecting various nodes of transistors (including the transfer transistor 630, the reset transistor 640, the power follower transistor 650, and the select transistor 660) may be formed in each sub-pixel. The interconnect dielectric layer 670 may include individual dielectric materials, such as undoped silicon glass, doped silicon glass, organic silicon glass, porous dielectric materials, or combinations thereof. Dielectric liners including various dielectric materials (such as silicon nitride, silicon oxynitride, silicon oxycarbide, and / or dielectric metal oxides) may be selectively used for the interconnect dielectric layer 670. The metal interconnect structures 680 may include various metal via structures 682 and various metal line structures 684. For example, each floating diffusion region 608 may be connected to the gate electrode 615 of the individual power follower transistor 650 through a subset of the metal interconnect structures 680. The light detector may include a transfer transistor 630 and may be connected to a sensing circuit including additional transistors including a reset transistor 640 , a power follower transistor 650 , and a select transistor 660 .

[0163] Each sub-pixel may include an individual photodetector circuit including a subset of the front-side sensor components 600 located in the sub-pixel region, where the sub-pixel region may be a unit cell UC region. A collection of sub-pixels may be used for a pixel, and the array 1000 of pixels may be configured as follows: Figure 1A or Figure 1B , or any other suitable array configuration to provide an image sensor. Each sub-pixel may include a unit cell UC, and the unit cell UC may be repeated along at least one horizontal direction to provide a single pixel of the front sensor component 600, wherein the single pixel may include one sub-pixel, two sub-pixels, or more than three sub-pixels. In one embodiment, a plurality of unit cells UC may be repeated along at least one horizontal direction. For example, the unit cell UC may be repeated as a two-dimensional array of unit cells UC, and the two-dimensional array has a first periodicity along the first horizontal direction hd1 and a second periodicity along the second horizontal direction hd2. As described above with respect to Figure 1A and Figure 1B , the two-dimensional array may be a rectangular array or a hexagonal array. Therefore, the second horizontal direction hd2 may or may not be perpendicular to the first horizontal direction hd1.

[0164] refer to Figure 5 The second exemplary structure 595 according to the second embodiment of the present disclosure may be derived from FIG. 4A to FIG. 4C The first exemplary structure 495 of the illustrated process steps is formed by introducing vertical steps into the bottom surface of each trench 639 in the first exemplary structure 495. Generally speaking, the process steps for forming the second exemplary structure 595 can be the same as the process steps for forming the first exemplary structure 495, except that the process steps for forming the trenches 639 can be modified to form a first section having a first depth d1 in each trench 639 and a second section having a second depth d2 in each trench 639. Two lithographic patterning processes and two anisotropic etching processes can be used to form Figure 5 639 of a second exemplary structure in the embodiment of the present invention. The first depth d1 can be in the range of 600 nanometers to 3000 nanometers, such as from 800 nanometers to 2500 nanometers, although lesser or greater depths can also be used. The second depth d2 is in the range of 15% to 85% of the first depth d1, such as 30% to 70%, although lesser or greater depths can also be used. In one embodiment, the first segment having the first depth d1 and the second segment having the second depth d2 can vary according to the horizontal length of each groove 639. A castellated bottom surface (i.e., having a concave pattern resembling a castle including battlements) can be provided in each groove 639. Each bottom surface segment at the first depth d1 can be connected to an adjacent bottom surface segment at the second depth d2 through a substantially vertical or vertical connecting sidewall in the groove 639. In such an embodiment, the transfer gate electrode lower portion 605L may include a castellated bottom region having a plurality of bottom surface segments that are adjacent to each other through the vertical sidewalls of the transfer gate electrode lower portion 605L. In the charge transfer step from the photodiode region to the floating diffusion region 608, each segment of the trench 639 having the second depth d2 may provide a shorter current path than the segment of the trench 639 having the first depth d1.

[0165] refer to Fig. 6A and Figure 6B, respectively, a first configuration 695 and a second configuration 696 of a third exemplary structure according to a third embodiment of the present disclosure. The third exemplary structure may be derived from the first exemplary structure 495 by forming a plurality of trenches 639 along the edge of the second conductivity type photodiode layer 602 in each unit cell UC. In addition, a plurality of transfer gate electrodes 605 may be formed in the third exemplary structure, at positions equivalent to the single transfer gate electrode 605 in the first exemplary structure 495. Each transfer gate electrode 605 may include a respective transfer gate electrode lower portion 605L in a respective trench 639. A metal through hole structure 682 may be formed on each transfer gate electrode 605 to electrically bias the transfer gate electrode 605. The transfer gate electrodes 605 in the same unit cell UC may be electrically connected to each other.

[0166] In general, the third exemplary structures may be derived from the first exemplary structure 495 by modifying the transfer gate electrode 605 of the first exemplary structure 495 to be non-topologically homeomorphic to the torus and to form a plurality of separate regions. Thus, each of the third exemplary structures may include at least one additional transfer gate electrode 605 in addition to the transfer gate electrode 605 in the substrate semiconductor layer 601. The transfer gate electrode 605 and the at least one additional transfer gate electrode 605 (i.e., a plurality of transfer gate electrodes 605) may be located around the edge of the second conductivity type photodiode layer 602 and may be laterally spaced apart from each other. A shallow trench isolation structure 620 may be present between adjacent pairs of transfer gate electrodes 605.

[0167] refer to Fig. 7A and Figure 7B , respectively, are the first configuration 795 and the second configuration 796 of the fourth exemplary structure according to the fourth embodiment of the present disclosure. The first configuration 795 of the fourth exemplary structure can be derived from the first exemplary structure 495, by forming a plurality of floating diffusion regions 608 and trenches 639 along the edge of the second conductive type photodiode layer 602 in each unit cell UC, and the trenches 639 have a topological homeomorphism with the torus (such as Fig. 7A The second configuration 796 of the fourth exemplary structure can be derived from the first exemplary structure 495 by forming a plurality of floating diffusion regions 608 and a plurality of trenches 639 (such as Figure 7B The plurality of floating diffusion regions 608 are laterally separated from each other and may be laterally separated from the second conductivity type photodiode layer 602 by a plurality of transfer gate electrodes 605 .

[0168] The plurality of transfer gate electrodes 605 are each located in the substrate semiconductor layer 601. In one embodiment, the plurality of transfer gate electrodes 605 (e.g., transfer gate electrode 605a and at least one additional transfer gate electrode 605b, 605c, 605d) may be located around the edge of the second conductivity type photodiode layer 602 in the substrate semiconductor layer 601 and laterally separated from each other. The plurality of floating diffusion regions 608 (e.g., floating diffusion region 608a and at least one additional floating diffusion region 608b, 608c, 608d) may be laterally separated from the second conductivity type photodiode layer 602 and may laterally surround the second conductivity type photodiode layer 602. Each of the plurality of transfer gate electrodes 605 (i.e., transfer gate electrode 605a and at least one additional transfer gate electrode 605b, 605c, 605d) may be located between the second conductivity type photodiode layer 602 and a respective one of the plurality of floating diffusion regions 608 (i.e., floating diffusion region 608a and at least one additional floating diffusion region 608b, 608c, 608d). In one embodiment, the plurality of floating diffusion regions 608 may be electrically connected (i.e., electrically shorted) to each other via a subset of the metal interconnect structures 680. Additionally or alternatively, the plurality of transfer gate electrodes 605 may be electrically connected to each other via a subset of the metal interconnect structures 680.

[0169] refer to Fig. 8A and Figure 8B , respectively, are a first configuration 895 and a second configuration 896 of a fifth exemplary structure according to a fifth embodiment of the present disclosure. The fifth exemplary structure may be derived from the first exemplary structure 495 by forming at least one stepped sidewall when forming the trench 639. For example, the stepped sidewall of the trench 639 may be formed by forming narrow openings in the photoresist layer for each trench 639 to be formed subsequently, performing a first anisotropic etching step, transferring the pattern of the narrow openings in the photoresist layer to the upper portion of the substrate semiconductor layer 601, trimming the photoresist layer so that each narrow opening is converted into a wide opening, and performing a second anisotropic etching process to transfer the pattern of the wide opening to the upper portion of the substrate semiconductor layer 601 while deepening the existing trenches of the substrate semiconductor layer 601. The total number of the photoresist layer trimming process may be the same as the number of horizontal steps formed in the sidewalls of the trench 639.

[0170] In the fifth exemplary structure, each transfer gate electrode lower portion 605L in the unit cell UC may have a vertical cross-sectional view, at a position vertically distanced from the front horizontal top surface of the substrate semiconductor layer 601 (i.e., the front surface 609 of the semiconductor substrate 500), wherein the width of the transfer gate electrode lower portion 605L gradually decreases at least once. Fig. 8A A configuration is shown in which the trench 639 is formed using one photoresist trimming process and two anisotropic etching steps. Figure 8BA configuration is shown using three photoresist trimming processes and four anisotropic etching steps to form the trench 639. Generally, at least one photoresist trimming process and at least two anisotropic etching processes may be used to form the trench having at least one stepped sidewall and the transfer gate electrode 605 having a sidewall and at least one horizontal step connecting the vertical sidewalls.

[0171] In another embodiment (not shown), the sidewalls of the trench 639 may be formed to have a tapered angle at the horizontal step position. In this embodiment, the etch chemistry of the anisotropic etch process for forming the trench 639 may be selected such that the polymer coating is temporarily formed during the anisotropic etch process to facilitate the formation of the tapered sidewalls of the trench 639.

[0172] refer to Fig. 9 According to the sixth exemplary structure 995 of the sixth embodiment of the present disclosure, it can be derived from Fig. 8A and Figure 8B Any of the first to fifth exemplary structures of the present disclosure illustrated in the drawings omits the formation of the doping well structure 607 .

[0173] refer to Fig.10 According to the seventh exemplary structure 1095 of the seventh embodiment of the present disclosure, it can be derived from Fig. 8A and Figure 8B In any of the first to fifth exemplary structures of the present disclosure shown in FIG. 6 , the shallow trench isolation structure 620 is not formed in the region of the doping well structure 607 .

[0174] refer to Fig.11 , additional interconnect dielectric layers 670 and additional metal interconnect structures 680 may be formed on the front side of the semiconductor substrate 500. The front surface 609 of the semiconductor substrate 500 components, the interconnect dielectric layers 670, and the structures formed therein may be joined to a carrier substrate 690. The carrier substrate 690 may be temporarily connected to the semiconductor substrate 500 components and the interconnect dielectric layers 670 to provide for subsequent thinning of the semiconductor substrate 500, and to provide for subsequent processing of the thinned semiconductor substrate 510 and the interconnect dielectric layers 670. The carrier substrate 690 may include a semiconductor material, an insulating material, or a metallized material, and may have a thickness in the range of from 300 microns to 1 millimeter, although lesser or greater thicknesses may also be used.

[0175] Any suitable bonding method can be used to bond the carrier substrate 690 to the front side of the interconnect dielectric layer 670. Exemplary bonding methods that can be used to bond the carrier substrate 690 to the interconnect dielectric layer 670 include, but are not limited to, oxide-to-oxide bonding, oxide-to-semiconductor bonding, fusion bonding, hybrid bonding, anodic bonding, direct bonding, other suitable bonding processes, and / or combinations thereof. Optionally, a bonding buffer layer 689 comprising an intermediate bonding material (e.g., silicon oxide, silicon nitride, or a semiconductor material) can be used to provide bonding between the interconnect dielectric layer 670 and the carrier substrate 690.

[0176] refer to Fig.12 , the back surface 610 of the semiconductor substrate 500 can be thinned, for example, by grinding, lapping, an isotropic etching process and / or an anisotropic etching process. The carrier substrate 690 can provide mechanical support for the semiconductor substrate 500 during the thinning process. In one embodiment, the semiconductor substrate 500 can be thinned to a thickness in a range from 1 micron to 12 microns, for example from 1.5 microns to 8 microns, although lesser or greater thicknesses can also be used. The semiconductor substrate 500 that is thinned after the thinning process is referred to herein as a thinned semiconductor substrate 510, or semiconductor substrate 510. The thickness of the thinned semiconductor substrate 510 can be determined by the maximum depth of the deep trenches subsequently formed on the back side of the thinned semiconductor substrate 510. In one embodiment, the thickness of the thinned semiconductor substrate 510 can be selected so that the deep trenches subsequently formed on the back side of the thinned semiconductor substrate 510 contact the adjacent surface of the shallow trench isolation structure 620. The back surface 709 of the thinned semiconductor substrate 510 may be ground to provide a flat horizontal surface that is parallel to the front surface 609 of the thinned semiconductor substrate 510. The exemplary structure may be subsequently flipped upside down for subsequent processing.

[0177] refer to Fig.13 , a photoresist layer (not shown) may be applied to the back surface 709 of the thinned semiconductor substrate 510 and may be lithographically patterned to form openings, wherein the openings generally replicate the pattern of the underlying shallow trench isolation structures 620. Unmasked portions of the thinned semiconductor substrate 510 may be etched by an anisotropic etching process to transfer the pattern of the openings in the photoresist layer to the thinned semiconductor substrate 510. The depth of the deep trenches may range from 1 micron to 10 microns, such as from 1.5 microns to 8 microns, although lesser or greater thicknesses may also be used. The deep trenches may be formed in the thinned semiconductor substrate 510. The photoresist layer may be subsequently removed, such as by ashing.

[0178] At least one dielectric material, such as silicon oxide, may be deposited in the deep trench. Excessive portions of the at least one dielectric material covering the back surface 709 of the thinned semiconductor substrate 510 may be removed by a planarization process. The planarization process may include a chemical mechanical planarization (CMP) process and / or a recess etching process. The remaining portion of the at least one dielectric material filling the deep trench constitutes a deep trench isolation structure 720.

[0179] The deep trench isolation structure 720 may define regions of sub-pixels 800. Each sub-pixel 800 may be located in a respective sub-pixel region, which is located in a region of a pixel (i.e., within the pixel region). For example, the region of a pixel may include a region of a first sub-pixel 801, a region of a second sub-pixel 802, and a region of a third sub-pixel 803. In the illustrated example, the first sub-pixel 801 may be formed in a region including a light detector configured to detect green light, the second sub-pixel 802 may be formed in a region including a light detector configured to detect red light, and the third sub-pixel 803 may be formed in a region including a light detector configured to detect blue light. Each sub-pixel 800 may include a volume containing a patterned columnar portion in the thinned semiconductor substrate 510, the volume being laterally enclosed by a connected set of deep trenches. The pixel region of a pixel includes a sub-pixel region in the pixel as a set of sub-pixels 800.

[0180] refer to Fig.14 An optional anti-reflective coating (ARC) 732 , an optical buffer layer 734 , a dielectric grid material layer 742L, and a metal reflective material layer 744L may be sequentially deposited on the back surface 709 of the thinned semiconductor substrate 510 .

[0181] The optional anti-reflective coating 732 includes an anti-reflective coating material that reduces reflections between the semiconductor material of the thinned semiconductor substrate 510 and the overlying material layer (i.e., the optical buffer layer 734). If the optional anti-reflective coating 732 is present, the optional anti-reflective coating 732 may have a refractive index between the refractive index of the semiconductor material of the thinned semiconductor substrate 510 and the refractive index of the optical buffer layer 734. The optional anti-reflective coating 732 may include a single material layer, or a multi-level layer stack with a gradually changing refractive index. The optional anti-reflective coating 732 includes an optically transparent material, and may include a semiconductor material, an insulating material, a conductive material, and / or a polymer material. The optional anti-reflective coating 732 may have a thickness ranging from 50 nanometers to 300 nanometers, although lesser or greater thicknesses may also be used.

[0182] The optical buffer layer 734 includes a semiconductor material (e.g., silicon, germanium, a silicon-germanium alloy, or a III-V compound semiconductor material) or a dielectric material (e.g., silicon oxide, silicon oxynitride, silicon nitride, or a dielectric metal oxide (e.g., aluminum oxide)). The optical buffer layer 734 includes a material that is conducive to the formation of grooves, wherein the grooves have a high aspect ratio in a subsequent anisotropic etching process. The optical buffer layer 734 can be formed as an unpatterned (blanket) material layer having two horizontal flat surfaces parallel to the back surface 709 of the thinned semiconductor substrate 510. The distal surface of the optical buffer layer 734 is one of the two horizontal flat surfaces of the optical buffer layer 734 that is relatively farther away from the thinned semiconductor substrate 510 (i.e., the top surface of the optical buffer layer 734).

[0183] The dielectric mesh material layer 742L may include a dielectric material, such as silicon oxide, a porous dielectric material, a polyimide, or other dielectric material. The thickness of the dielectric mesh material layer 742L may range from 50 nanometers to 500 nanometers, although lesser or greater thicknesses may also be used. The metal reflective material layer 744L may include a metallized material that provides high reflectivity. For example, the metal reflective material layer 744L may include silver, aluminum, copper, gold, or any other high reflectivity metallized material. The thickness of the metal reflective material layer 744L may range from 50 nanometers to 500 nanometers, although lesser or greater thicknesses may also be used.

[0184] A photoresist layer 747 may be applied on the metal reflective material layer 744L and may be lithographically patterned to form openings in the region of the second conductivity type photodiode layer 602, i.e., in the photodetector region including the respective pn junctions between the second conductivity type photodiode layer 602 and the doped well structure 607. The transistor region of the sensing circuit (including the reset transistor 640, the power follower transistor 650, and the select transistor 660) may be covered or uncovered by the photoresist layer 747.

[0185] refer to Fig.15A and Fig. 15B , the portions of the dielectric mesh material layer 742L and the metal reflective material layer 744L that are not masked by the patterned photoresist layer 747 can be etched to form openings that penetrate the two material layers. The remaining portion of the dielectric mesh material layer 742L forms a dielectric mesh structure 742, and the remaining portion of the metal reflective material layer 744L forms a metal mesh structure 744. The stack of the dielectric mesh structure 742 and the metal mesh structure 744 constitutes a mesh structure 740, which can also be called a composite mesh structure.

[0186] The grid structure 740 may cover the edge of the second conductivity type photodiode layer 602 and define a light collection area of ​​each light detector in an individual sub-pixel 800. The pixel 900 may include a set of sub-pixels 800 (e.g., a first sub-pixel 801, a second sub-pixel 802, and a third sub-pixel 803) configured to detect light of different wavelengths. Each pixel 900 may be located in an individual pixel region, and the pixel region includes the set of sub-pixels 800. For example, the pixel 900 may include at least one first sub-pixel 801, at least one second sub-pixel 802, and at least one third sub-pixel 803. In the illustrated example, the pixel may include one first sub-pixel 801 (e.g., a green sub-pixel) located in the first sub-pixel region, two second sub-pixels 802 (e.g., a red sub-pixel) located in two second sub-pixel regions, and one third sub-pixel 803 (e.g., a blue sub-pixel) located in the third sub-pixel region. In general, the pixel 900 may include various combinations of at least two sub-pixels 800 configured to detect light of different wavelength ranges. Alternatively, the image sensor may be a monochrome image sensor including a single type of sub-pixel 800. In such an embodiment, each pixel 900 may include only a single sub-pixel 800.

[0187] Generally, mesh structure 740 includes at least one metal mesh structure 744 having reflective sidewalls. Mesh structure 740 includes a composite mesh structure including a vertical stack of metal mesh structure 744 and dielectric mesh structure 742, wherein metal mesh structure 744 has reflective sidewalls. Mesh structure 740 may be formed on a distal surface of optical buffer layer 734. Mesh structure 740 includes openings covering individual photodetectors, including transfer transistors 630. The portion of the distal surface of optical buffer layer 734 that contacts the bottom surface of mesh structure 740 is a flat portion of the distal surface of optical buffer layer 734. During the anisotropic etching process of patterning mesh structure 740, the portion of the distal surface of optical buffer layer 734 that does not contact mesh structure 740 may be incidentally vertically recessed relative to a horizontal plane, wherein the horizontal plane includes the bottom surface of mesh structure 740.

[0188] The grid structure 740 can divide each sub-pixel 800 into a detector region and a sensing circuit region. For example, the first sub-pixel 801 may include a first sensor region 801D covering the second conductive type photodiode layer 602 in the first sub-pixel 801, and a first sensing circuit region 801S covering the sensing circuit (including the reset transistor 640, the power follower transistor 650, and the selection transistor 660) in the first sub-pixel 801. The second sub-pixel 802 may include a second sensor region 802D covering the second conductive type photodiode layer 602 in the second sub-pixel 802, and a second sensing circuit region 802S covering the sensing circuit (including the reset transistor 640, the power follower transistor 650, and the selection transistor 660) in the second sub-pixel 802. The third sub-pixel 803 may include a third sensor region 803D covering the second conductivity type photodiode layer 602 in the third sub-pixel 803, and a third sensing circuit region 803S covering the sensing circuit (including the reset transistor 640, the power follower transistor 650, and the selection transistor 660) in the third sub-pixel 803. In general, the set of all sub-pixels 800 in the pixel 900 may be configured into any pattern that facilitates the periodic repetition of the pixels 900 in the array 1000.

[0189] refer to Fig.16 , an optically transparent layer 770 having a flat top surface may be formed on the mesh structure 740. The optically transparent layer 770 may be formed by depositing a self-planarizing dielectric material, such as flowable oxide (FOX). Alternatively, a transparent dielectric material may be deposited and planarized (e.g., by chemical mechanical polishing) to provide the optically transparent layer 770.

[0190] The optically transparent layer 770 vertically extends through the opening in the mesh structure 740 and has a second refractive index different from the first refractive index. The optically transparent layer 770 may be formed on the optical buffer layer 734.

[0191] Various color filter materials may be applied on the optically transparent layer 770 and may be patterned to form various filters 780. The filters 780 may include a first type filter 781 formed in the region of the first sub-pixel 801, a second type filter 782 formed in the region of the second sub-pixel 802, and a third type filter 783 formed in the region of the third sub-pixel 803. The composition of each color filter material may be selected so that light within a target wavelength range passes through the color filter material, while light outside the target wavelength range is absorbed by the color filter material.

[0192] The optical lens 790 may be formed on the filter 780 by applying an optically transparent material to the filter 780 and patterning the optically transparent material into a material portion having an arcuate surface centered over an opening in each of the underlying grid structures 740 .

[0193] The optional anti-reflective coating 732, optical buffer layer 734, mesh structure 740 and optically transparent layer 770 in sub-pixel 800, as well as the respective combinations of overlying filter 780 and overlying optical lens 790, form an optical assembly configured to filter and focus light onto individual light detectors.

[0194] refer to Fig.17 , carrier substrate 690 and bonding buffer layer 689 (if present) may be separated from interconnect dielectric layer 670. Before or after separation of carrier substrate 690 from thinned semiconductor substrate 510, thinned semiconductor substrate 510 and the device structures thereon may be separated into separate image sensors.

[0195] Generally speaking, the array of pixels 1000 may be formed on a thinned semiconductor substrate 510. Each pixel in the array of pixels 1000 includes at least one sub-pixel, and each sub-pixel includes a respective photodetector (including a transfer transistor 630) and a respective sensing circuit (including a reset transistor 640, a power follower transistor 650, and a select transistor 660) located on the front surface 609 of the thinned semiconductor substrate 510.

[0196] refer to Fig.18 , a circuit diagram of a photodetector circuit is shown according to an embodiment of the present disclosure. The configuration of the photodetector circuit includes an internally connected combination of a transfer transistor 630 and a field effect transistor (including a reset transistor 640, a power follower transistor 650, and a select transistor 660). The transfer transistor 630 may include a pn junction between a combination and a substrate semiconductor layer 601, the combination including a second conductivity type photodiode layer 602 and a buried second conductivity type photodiode layer 606, the substrate semiconductor layer 601 having a first conductivity type doping. The combination of the substrate semiconductor layer 601, the buried second conductivity type photodiode layer 606, and the second conductivity type photodiode layer 602 functions as a photodiode (labeled as PD). The second conductivity type photodiode layer 602 functions as a source region of the transfer transistor 630.

[0197] The floating diffusion region 608 (labeled as FD) functions as a drain region of the transfer transistor 630. The transfer gate electrode 605 (labeled as TG) controls charge transfer, and transfers the charges accumulated in the second conductivity type photodiode layer 602 to the floating diffusion region 608 through the semiconductor channel located below the transfer gate electrode 605. The transfer transistor 630 can be used as a photodetector.

[0198] The sensing circuit includes an internal connection combination of field effect transistors (including a reset transistor 640, a power follower transistor 650, and a selection transistor 660). The internal connection combination of the field effect transistors (including the reset transistor 640, the power follower transistor 650, and the selection transistor 660) is connected to the floating diffusion region 608. The internal connection combination of the field effect transistors (including the reset transistor 640, the power follower transistor 650, and the selection transistor 660) includes a reset transistor (labeled as RST), a power follower transistor (labeled as SF), and a selection transistor (labeled as SEL). The reset transistor 640 (i.e., RST) can be configured to drain the charge in the floating diffusion region 608 immediately before sensing, so that the charge accumulated in the floating diffusion region 608 during sensing is linearly proportional to the charge accumulated in the second conductivity type photodiode layer 602. The gate electrode of the power follower transistor 650 (i.e., SF) is electrically connected to the floating diffusion region 608 through a set of metal internal connection structures. Therefore, the voltage on the gate electrode of the power follower transistor 650 may be proportional to the charge accumulated in the floating diffusion region 608. The select transistor 660 (i.e., SEL) may be turned on during the read period to output the common node voltage of the power follower transistor 650 and the select transistor 660 (modulated by the voltage on the gate electrode of the power follower transistor 650) to a common output voltage (labeled as V_out).

[0199] refer to Figures 1A to 18 According to an embodiment of the present disclosure, a semiconductor structure having a photodetector (including a transfer transistor 630) is provided. The photodetector includes a substrate semiconductor layer 601 having a first conductivity type doping, a second conductivity type photodiode layer 602 forming a pn junction with the substrate semiconductor layer 601, a floating diffusion region 608 laterally separated from the second conductivity type photodiode layer 602, and a transfer gate electrode 605, wherein the transfer gate electrode 605 includes a transfer gate electrode lower portion 605L formed in the substrate semiconductor layer 601 and located between the second conductivity type photodiode layer 602 and the floating diffusion region 608.

[0200] In addition, the image sensor provided by various embodiments of the present disclosure includes a plurality of pixels 900 located on a substrate semiconductor layer 601, wherein the substrate semiconductor layer 601 has a first conductive type doping. Each independent pixel 900 among the plurality of pixels 900 may include a photodetector circuit, wherein the photodetector circuit includes a photodetector (including a transfer transistor 630) and a sensing circuit (including a reset transistor 640, a power follower transistor 650, and a selection transistor 660). Each photodetector includes a second conductive type photodiode layer 602 forming a pn junction with the substrate semiconductor layer 601, a floating diffusion region 608 laterally separated from the second conductive type photodiode layer 602, and a transfer gate electrode 605, wherein the floating diffusion region 608 is located on the front horizontal surface of the substrate semiconductor layer 601, and the transfer gate electrode 605 includes a transfer gate electrode lower portion 605L formed in the substrate semiconductor layer 601 and located between the second conductive type photodiode layer 602 and the floating diffusion region 608. Each pixel 900 among the plurality of pixels 900 includes a respective optical component located on the backside horizontal surface of the substrate semiconductor layer 601 , the optical component being configured to direct incident light to a respective pn junction of the photodetector.

[0201] In one embodiment, a plurality of trenches 639 may be located in the substrate semiconductor layer 601. The plurality of trenches 639 may extend vertically from the front horizontal surface of the substrate semiconductor layer 601 (on which the light detector is located) to the back horizontal surface of the substrate semiconductor layer 601 (on which the optical component is located). Each transfer gate electrode lower portion 605L may be located in a respective trench 639.

[0202] refer to Fig.19 , a process flow chart depicts an example process sequence for forming a semiconductor structure including a photodetector according to an embodiment of the present disclosure. Referring to step 1910, a semiconductor substrate 500 including a substrate semiconductor layer 601 having a first conductivity type doping is provided. Referring to step 1920, a second conductivity type photodiode layer 602 is formed on the substrate semiconductor layer 601. The second conductivity type photodiode layer 602 forms a pn junction with the substrate semiconductor layer 601. Referring to step 1930, a transfer gate electrode 605 is formed, including a transfer gate electrode lower portion 605L formed in the substrate semiconductor layer 601 and adjacent to the pn junction. Referring to step 1940, a floating diffusion region 608 is formed in a portion of the substrate semiconductor layer 601 adjacent to the transfer gate electrode 605. The transfer gate electrode 605 is located between the second conductivity type photodiode layer 602 and the floating diffusion region 608.

[0203] Various methods and structures of the present disclosure may be used to provide a photodetector circuit in which charge transfer from a photodiode region to a floating diffusion region 608 is controlled by a buried transfer gate electrode 605, the transfer gate electrode 605 including a portion located in a trench located between the photodiode region and the floating diffusion region 608. The loss of stored charge in the photodiode region is minimized, and charge is transferred from the photodiode region to the floating diffusion region 608 only when the buried transfer gate electrode 605 is turned on. Thus, high fidelity optical images may be generated by using the buried transfer gate electrode 605 of the present disclosure.

[0204] According to some embodiments of the present disclosure, a semiconductor structure including a photodiode is provided, wherein the photodiode includes a substrate semiconductor layer doped with a first conductivity type, a second conductivity type photodiode layer forming a pn junction with the substrate semiconductor layer, a floating diffusion region laterally separated from the second conductivity type photodiode layer, and a transfer gate electrode. The transfer gate electrode includes a transfer gate electrode lower portion formed in the substrate semiconductor layer, and the transfer gate electrode lower portion is located between the second conductivity type photodiode layer and the floating diffusion region. In some embodiments, the photodiode includes a groove located in the substrate semiconductor layer and a transfer gate electrode lower portion located in the groove, the groove extending vertically from the front horizontal surface of the substrate semiconductor layer to the back horizontal surface of the substrate semiconductor layer. In some embodiments, the groove has a depth greater than the vertical thickness of the floating diffusion region. In some embodiments, the transfer gate electrode includes a transfer gate electrode upper portion located on the substrate semiconductor layer, and the transfer gate electrode upper portion has a lateral extension greater than the transfer gate electrode lower portion. In some embodiments, in a top view along a direction perpendicular to the front horizontal surface of the substrate semiconductor layer, an edge region of the transfer gate electrode upper portion and an edge region of the floating diffusion region have a partial overlap. In some embodiments, the lower portion of the transfer gate electrode is located in a protection trench, and the protection trench laterally surrounds the second conductivity type photodiode layer. In some embodiments, the lower portion of the transfer gate electrode includes a flat bottom surface having an inner edge and an outer edge, and the inner edge and the outer edge are at the same depth from the front horizontal surface of the substrate semiconductor layer, and laterally surround the second conductivity type photodiode layer. In some embodiments, the lower portion of the transfer gate electrode includes a castellated bottom surface having a plurality of bottom surface segments, and the plurality of bottom surface segments are connected to each other through the vertical sidewalls of the lower portion of the transfer gate electrode. In some embodiments, the semiconductor structure includes at least one additional floating diffusion region and the floating diffusion region is laterally separated and laterally separated from the second conductivity type photodiode layer. In some embodiments, the semiconductor structure includes at least one additional transfer gate electrode in the substrate semiconductor layer, wherein the transfer gate electrode and the at least one additional transfer gate electrode surround the edge of the second conductivity type photodiode layer and are laterally separated from each other. In some embodiments, the semiconductor structure includes at least one additional floating diffusion region and the second conductivity type photodiode layer is laterally separated, and each of the at least one additional transfer gate electrodes is located between the second conductivity type photodiode layer and the respective additional floating diffusion regions. In some embodiments, the lower portion of the transfer gate electrode has a vertical cross-sectional view, and the width of the lower portion of the transfer gate electrode gradually decreases at least once at a position vertically spaced from the front horizontal top surface of the substrate semiconductor layer. In some embodiments, the semiconductor structure includes a doping well structure containing a first conductivity type dopant, the atomic concentration of the doping in the doping well structure is greater than the atomic concentration of the doping in the substrate semiconductor layer, and the doping well structure laterally surrounds the lower portion of the transfer gate electrode that is not adjacent to the floating diffusion region.

[0205] According to some embodiments of the present disclosure, an image sensor is provided, comprising a plurality of pixels located in a substrate semiconductor layer having a first conductive type doping. Each pixel comprises a photodiode circuit, the photodiode circuit comprising a photodiode and a sensing circuit. The photodiode comprises a second conductive type photodiode layer forming a pn junction with the substrate semiconductor layer, a floating diffusion region laterally separated from the second conductive type photodiode layer, and a transfer gate electrode, wherein the floating diffusion region is located on the front horizontal surface of the substrate semiconductor layer. The transfer gate electrode comprises a transfer gate electrode lower portion formed in the substrate semiconductor layer, and the transfer gate electrode lower portion is located between the second conductive type photodiode layer and the floating diffusion region. Each pixel comprises an individual optical component located on the substrate semiconductor layer and configured to guide incident light to an individual pn junction of the photodiode. In some embodiments, the image sensor comprises a plurality of grooves located in the substrate semiconductor layer, the plurality of grooves extending vertically from the front horizontal surface of the substrate semiconductor layer to the back horizontal surface of the substrate semiconductor layer, wherein each transfer gate electrode lower portion is located in an individual groove.

[0206] According to some embodiments of the present disclosure, a method for forming a semiconductor structure is provided, including providing a semiconductor substrate including a substrate semiconductor layer, forming a second conductive type photodiode layer in the substrate semiconductor layer, forming a transfer gate electrode including a lower portion of a transfer gate electrode, and forming a floating diffusion region in a portion of the substrate semiconductor layer adjacent to the transfer gate electrode. The substrate semiconductor layer includes a first conductive type doping. The second conductive type photodiode layer and the substrate semiconductor layer form a pn junction. The lower portion of the transfer gate electrode is formed in the substrate semiconductor layer adjacent to the pn junction. The transfer gate electrode is located between the second conductive type photodiode layer and the floating diffusion region. In some embodiments, the method includes forming a groove extending from a front horizontal surface of the substrate semiconductor layer adjacent to the second conductive type photodiode layer to a back horizontal surface of the substrate semiconductor layer, wherein the transfer gate electrode is formed by depositing and patterning a gate electrode material layer, and the gate electrode material layer is located in and above the groove. In some embodiments, the method includes forming a gate dielectric layer on the sidewalls of the trench and on the front horizontal surface of the substrate semiconductor layer, forming a gate electrode material layer on the gate dielectric layer, and after the gate electrode material layer is patterned into the transfer gate electrode, patterning the gate dielectric layer into a transfer gate dielectric. In some embodiments, the method includes forming a sensing circuit on the front horizontal surface of the substrate semiconductor layer, thinning the substrate semiconductor layer, and forming an optical component configured to guide incident light to the pn junction on the substrate semiconductor layer, wherein the substrate semiconductor layer is recessed from the back horizontal surface of the substrate semiconductor layer to the front horizontal surface of the substrate semiconductor layer. In some embodiments, the trench has a depth greater than the vertical depth of the floating diffusion region, and the floating diffusion region is formed by implanting a second conductive type dopant in a portion of the substrate semiconductor layer below an edge region of an upper portion of the transfer gate electrode, the upper portion of the transfer gate electrode being located above the trench, wherein in a top view along a direction perpendicular to the front horizontal surface of the substrate semiconductor layer, an edge region of the upper portion of the transfer gate electrode and an edge region of the floating diffusion region have a partial overlap.

[0207] The features of some embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: A photodiode is included, wherein the photodiode includes: A substrate semiconductor layer having a first conductivity type doping; a combination, comprising a second conductivity type first photodiode layer and a second conductivity type second photodiode layer, wherein the combination forms a pn junction with the substrate semiconductor layer, and a top surface of the second conductivity type second photodiode layer is adjacent to a bottom surface of the second conductivity type first photodiode layer; a floating diffusion region laterally separated from the second conductivity type first photodiode layer; and A transfer gate electrode, including a transfer gate electrode lower portion formed in the substrate semiconductor layer, and the transfer gate electrode lower portion is located between the second conductive type first photodiode layer and the floating diffusion region, wherein the depth of the bottom surface of the transfer gate electrode lower portion is equal to or greater than the depth of the bottom surface of the second conductive type second photodiode layer.

2. The semiconductor structure according to claim 1, wherein: The photodiode includes a trench located in the substrate semiconductor layer, the trench vertically extending from a front horizontal surface of the substrate semiconductor layer to a back horizontal surface of the substrate semiconductor layer; and The lower portion of the transfer gate electrode is located in the trench.

3. The semiconductor structure according to claim 2, characterized in that: The trench has a depth greater than the vertical thickness of the floating diffusion region.

4. The semiconductor structure according to claim 1, characterized in that The transmission gate electrode comprises an upper portion of the transmission gate electrode located on the substrate semiconductor layer, and the upper portion of the transmission gate electrode has a lateral extension greater than the lower portion of the transmission gate electrode.

5. The semiconductor structure according to claim 4, characterized in that: In a top view along a direction perpendicular to a front horizontal surface of the substrate semiconductor layer, an edge region of an upper portion of the transfer gate electrode and an edge region of the floating diffusion region partially overlap.

6. The semiconductor structure according to claim 1, characterized in that The lower portion of the transfer gate electrode is located in a protection trench, and the protection trench laterally surrounds the second conductive type first photodiode layer.

7. The semiconductor structure according to claim 6, characterized in that: The lower portion of the transfer gate electrode includes a flat bottom surface having an inner edge and an outer edge, the inner edge and the outer edge laterally surrounding the second conductivity type first photodiode layer at the same depth from a front horizontal surface of the substrate semiconductor layer.

8. The semiconductor structure according to claim 6, characterized in that: The transfer gate electrode lower portion includes a castellated bottom surface having a plurality of bottom surface segments, and the bottom surface segments are connected to each other through vertical sidewalls of the transfer gate electrode lower portion.

9. The semiconductor structure according to claim 1, characterized in that: The invention further includes at least one additional floating diffusion region, the additional floating diffusion region being laterally separated from the floating diffusion region and laterally separated from the second conductivity type first photodiode layer.

10. The semiconductor structure according to claim 1, characterized in that Further comprising at least one additional transfer gate electrode in the substrate semiconductor layer, wherein the transfer gate electrode and the additional transfer gate electrode surround an edge of the second conductivity type first photodiode layer and are laterally spaced apart from each other.

11. The semiconductor structure according to claim 10, characterized in that: Further comprising at least one additional floating diffusion region laterally separated from the second conductivity type first photodiode layer, wherein each of the additional transfer gate electrodes is located between the second conductivity type first photodiode layer and the respective additional floating diffusion region.

12. The semiconductor structure according to claim 1, characterized in that The lower portion of the transmission gate electrode has a vertical cross-sectional view, and the width of the lower portion of the transmission gate electrode gradually decreases at least once at a position vertically spaced from a front horizontal top surface of the substrate semiconductor layer.

13. The semiconductor structure according to claim 1, characterized in that It further includes a doping well structure, which includes an atomic concentration of the first conductive type doping, the atomic concentration is greater than the atomic concentration of the substrate semiconductor layer, and the doping well structure laterally surrounds the lower portion of the transfer gate electrode that is not adjacent to the floating diffusion region.

14. An image sensor, characterized in that: The invention comprises a plurality of pixels located in a substrate semiconductor layer doped with a first conductive type, wherein each of the pixels comprises a photodiode circuit, the photodiode circuit comprises a photodiode and a sensing circuit, and the photodiode comprises: a combination, comprising a second conductivity type first photodiode layer and a second conductivity type second photodiode layer, wherein the combination forms a pn junction with the substrate semiconductor layer, and a top surface of the second conductivity type second photodiode layer is adjacent to a bottom surface of the second conductivity type first photodiode layer; a floating diffusion region, laterally separated from the second conductivity type first photodiode layer and located on a front horizontal surface of the substrate semiconductor layer; and A transfer gate electrode, including a transfer gate electrode lower portion formed in the substrate semiconductor layer, and the transfer gate electrode lower portion is located between the second conductive type first photodiode layer and the floating diffusion region, wherein the depth of the bottom surface of the transfer gate electrode lower portion is equal to or greater than the depth of the bottom surface of the second conductive type second photodiode layer, and wherein each of the pixels includes an individual optical component located on the substrate semiconductor layer and configured to guide incident light to the individual pn junction of the photodiode.

15. The image sensor according to claim 14, wherein: The invention further comprises a plurality of trenches in the substrate semiconductor layer, wherein the trenches vertically extend from the front horizontal surface of the substrate semiconductor layer to a back horizontal surface of the substrate semiconductor layer, wherein the lower portion of each transfer gate electrode is located in a respective one of the trenches.

16. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate including a substrate semiconductor layer, wherein the substrate semiconductor layer includes a first conductivity type doping; Forming a combination including a second conductivity type first photodiode layer and a second conductivity type second photodiode layer in the substrate semiconductor layer, wherein the combination and the substrate semiconductor layer form a pn junction, and the top surface of the second conductivity type second photodiode layer is adjacent to the bottom surface of the second conductivity type first photodiode layer; forming a transfer gate electrode including a transfer gate electrode lower portion, the transfer gate electrode lower portion being formed in the substrate semiconductor layer adjacent to the pn junction, wherein a depth of a bottom surface of the transfer gate electrode lower portion is equal to or greater than a depth of a bottom surface of the second conductivity type second photodiode layer; and A floating diffusion region is formed in a portion of the substrate semiconductor layer adjacent to the transfer gate electrode, wherein the transfer gate electrode is located between the second conductivity type first photodiode layer and the floating diffusion region.

17. The method according to claim 16, characterized in that Further including forming a groove extending from a front horizontal surface of the substrate semiconductor layer adjacent to the second conductive type first photodiode layer to a back horizontal surface of the substrate semiconductor layer, wherein the transfer gate electrode is formed by depositing and patterning a gate electrode material layer, and the gate electrode material layer is located in and above the groove.

18. The method according to claim 17, characterized in that Further including: forming a gate dielectric layer on the sidewalls of the trench and on the front horizontal surface of the substrate semiconductor layer, wherein the gate electrode material layer is formed on the gate dielectric layer; and After patterning the gate electrode material layer into the transfer gate electrode, the gate dielectric layer is patterned into a transfer gate dielectric.

19. The method according to claim 17, characterized in that Further including: Forming a sensing circuit on the front horizontal surface of the semiconductor layer of the substrate; Thinning the substrate semiconductor layer, the substrate semiconductor layer being recessed from the backside horizontal surface of the substrate semiconductor layer toward the frontside horizontal surface of the substrate semiconductor layer; and An optical component is formed on the substrate semiconductor layer, wherein the optical component is configured to guide incident light to the pn junction.

20. The method according to claim 17, characterized in that: The trench has a depth greater than a vertical depth of the floating diffusion region; and The floating diffusion region is formed by implanting a second conductive type dopant in a portion of the substrate semiconductor layer below an edge region of an upper portion of a transfer gate electrode, wherein the upper portion of the transfer gate electrode is located above the groove, wherein in a top view along a direction perpendicular to the front horizontal surface of the substrate semiconductor layer, the edge region of the upper portion of the transfer gate electrode and an edge region of the floating diffusion region have a partial overlap.

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