Variable resistance memory device

Abstract

A variable resistance memory device is disclosed. The variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and is formed of a second material having a density different from that of the first material. The first conductive element and the second conductive element are located on the variable resistance layer and are spaced apart from each other to form a current path in the variable resistance layer. The current path is in a direction perpendicular to the direction in which the first layer and the second layer are stacked.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0176732 filed on December 27, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to nonvolatile memory devices using variable resistance materials. Background Art

[0004] A nonvolatile memory device is a semiconductor memory device in which stored data is not damaged even when power is interrupted, and examples of nonvolatile memory devices include a programmable read-only memory (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), and a flash memory.

[0005] In accordance with the demand for technology having high integration, low power consumption, and random access (access) capability to memory cells, next generation semiconductor memory devices such as magnetic random access memory (MRAM) and phase change random access memory (PRAM) have recently been developed.

[0006] Such next-generation semiconductor memory devices use resistance switching (switch) devices having resistance values ​​that change according to applied current or voltage and remain unchanged even when the current or voltage supply is interrupted. For high integration and low power consumption, resistance switching of the resistance switching device at a low applied voltage and a wide resistance switching range are desirable. Summary of the invention

[0007] A variable resistance memory device having improved variable resistance performance is provided.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0009] According to an embodiment, a variable resistance memory device includes: a variable resistance layer including a first layer and a second layer, the first layer being formed of a first material, the second layer being on the first layer, the second layer being formed of a second material having a density different from that of the first material; and a first conductive element and a second conductive element, which are on the variable resistance layer and spaced apart from each other to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

[0010] In some embodiments, the density of the second material can be higher than the density of the first material.

[0011] In some embodiments, the density difference between the first material and the second material may be greater than 1 g / cm 3 .

[0012] In some embodiments, the variable resistance layer may further include a third layer on the second layer. The third layer may be formed of a third material having a density lower than that of the second material.

[0013] In some embodiments, the density difference between the second material and the third material may be greater than 1 g / cm 3 .

[0014] In some embodiments, the first material and the third material may be the same material.

[0015] In some embodiments, the thickness of the second layer may be less than the thickness of the first layer, and the thickness of the second layer may be less than the thickness of the third layer.

[0016] In some embodiments, each of the first material and the second material may be an oxide (metal oxide) having a band gap energy of 2 eV or more.

[0017] In some embodiments, the first material and the second material can each independently be Rb 2 O、TiO 2 、BaO、ZrO 2 , CaO, HfO 2 、SrO、Sc 2 O 3 、MgO、Li 2 O、Al 2 O 3 、SiO 2 , BeO, Nb 2 O 5 、NiO、Ta 2 O 5 , WO 3 、V 2 O 5 ,La 2 O 3 , Gd 2 O 3 ,CuO,MoO 3 Cr 2 O 3 and MnO 2 Any of.

[0018] In some embodiments, the first material and the second material may be different metal oxide materials, and the metals in the metal oxide materials have the same valence, and the density difference between the first material and the second material may be greater than 1.5 g / cm 3 .

[0019] In some embodiments, the first material may be HfO 2 , and the second material may be TiO 2 、MnO 2 、ZrO 2 、SiO 2 or Cr 2 O 3 .

[0020] In some embodiments, the first material may be Gd 2 O 3 , and the second material may be Cr 2 O 3 or La 2 O 3 .

[0021] In some embodiments, the first material may be NiO, and the second material may be SrO, CaO, or BeO.

[0022] In some embodiments, the first material may be WO 3 , and the second material may be MoO 3 .

[0023] According to an embodiment, a variable resistance memory device includes: an insulating layer; a variable resistance layer on the insulating layer, the variable resistance layer including a first layer and a second layer, the first layer is formed of a first material, the second layer is on the first layer and is formed of a second material, and the density of the second material is different from the density of the first material; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a plurality of gate electrodes spaced apart from each other on the gate insulating layer.

[0024] In some embodiments, the density of the second material can be higher than the density of the first material.

[0025] In some embodiments, the density difference between the first material and the second material may be greater than 1 g / cm 3 .

[0026] In some embodiments, the variable resistance layer may further include a third layer on the second layer and formed of a third material. The density of the third material may be lower than that of the second material.

[0027] In some embodiments, the thickness of each of the first layer, the second layer, and the third layer may be equal to or less than 10 nm.

[0028] In some embodiments, the second layer can have a thickness equal to or less than 2 nm.

[0029] In some embodiments, the third layer may contact the channel layer and may have a thickness equal to or greater than 5 nm.

[0030] In some embodiments, the density difference between the second material and the third material may be greater than 1 g / cm 3 .

[0031] In some embodiments, the first material and the third material may be the same material.

[0032] In some embodiments, each of the first material and the second material may be an oxide (metal oxide) having a band gap energy of 2 eV or more.

[0033] In some embodiments, the first material and the second material can each independently be Rb 2 O、TiO 2 、BaO、ZrO 2 , CaO, HfO 2 、SrO、Sc 2 O 3 、MgO、Li 2 O、Al 2 O 3 、SiO 2 , BeO, Nb 2 O 5 、NiO、Ta 2 O 5 , WO 3 、V 2 O 5 ,La 2 O 3 , Gd 2 O 3 ,CuO,MoO 3 Cr 2 O 3 and MnO 2 Any of.

[0034] According to an embodiment, a variable resistance memory device includes: a variable resistance layer including a first layer and a second layer, the first layer including a first material, the second layer being on the first layer, the second layer including a second material having a density different from that of the first material; and a first conductive element and a second conductive element, which are on the variable resistance layer and spaced apart from each other to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

[0035] In some embodiments, the first material may be HfO 2 , and the second material may be TiO 2 、MnO 2 、ZrO 2 、SiO 2 or Cr 2 O 3.

[0036] In some embodiments, the first material may be Gd 2 O 3 , and the second material may be Cr 2 O 3 or La 2 O 3 .

[0037] In some embodiments, the first material may be NiO, and the second material may be SrO, CaO, or BeO.

[0038] In some embodiments, the first material may be WO 3 , and the second material may be MoO 3 . BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and other aspects, features and advantages of some embodiments of the present disclosure will become more apparent from the following description considered in conjunction with the accompanying drawings, in which:

[0040] Figure 1 A cross-sectional view illustrating a structure of a variable resistance memory device according to an embodiment;

[0041] Figure 2 For use in describing the Figure 1 A conceptual diagram of a principle of resistance change occurring in a variable resistance layer in a variable resistance memory device;

[0042] Figure 3 A cross-sectional view for explaining a configuration of a variable resistance memory device according to another embodiment;

[0043] Figure 4 A cross-sectional view for explaining a configuration of a variable resistance memory device according to another embodiment;

[0044] Figure 5 To describe the Figure 4 A conceptual diagram of a principle of resistance change occurring in a variable resistance layer in a variable resistance memory device;

[0045] Figure 6 and 7 A cross-sectional view for explaining the construction of a sample manufactured for testing the variable resistance performance of a structure in which variable resistance materials having a density difference are stacked adjacent to each other;

[0046] Figure 8 A cross-sectional view for explaining a configuration of a variable resistance memory device according to another embodiment;

[0047] Fig. 9 for Figure 8An equivalent circuit diagram of a variable resistance memory device;

[0048] Fig.10 For depiction Figure 8 A conceptual diagram of the operation of a variable resistance memory device;

[0049] Fig.11 A cross-sectional view illustrating a structure of a variable resistance memory device according to another embodiment;

[0050] Fig.12 A cross-sectional view illustrating a structure of a variable resistance memory device according to another embodiment;

[0051] Fig.13 To illustrate the setting Fig.12 A perspective view of a structure of a memory string in a variable resistance memory device;

[0052] Fig.14 for Fig.12 An equivalent circuit diagram of a variable resistance memory device;

[0053] Fig.15 A cross-sectional view illustrating a structure of a variable resistance memory device according to another embodiment;

[0054] Fig.16 To illustrate the setting Fig.15 A perspective view of a structure of a memory string in a variable resistance memory device;

[0055] Fig.17 is a block diagram of a storage system according to an embodiment; and

[0056] Fig.18 A diagram illustrating a neuromorphic device and external devices connected thereto according to an embodiment. DETAILED DESCRIPTION

[0057] The embodiment will now be described in detail, and its examples are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiment is described below only by reference to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. The expression, for example, "at least one (kind) of" modifies the entire list of elements and does not modify the individual elements of the list when it is before or after a list of elements (e.g., A, B, and C). For example, "at least one (kind) of A, B, and C", "at least one (kind) of A, B, or C", "one of A, B, C, or a combination thereof", and "one of A, B, C, and a combination thereof" can be interpreted as covering any of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.

[0058] The present disclosure will now be described more fully with reference to the accompanying drawings in which embodiments are shown. Moreover, embodiments of the present disclosure are described and various modifications may be made therefrom. The same reference numerals in the accompanying drawings represent the same elements, and the sizes of the elements in the accompanying drawings may be exaggerated for clarity and ease of description.

[0059] When an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween.

[0060] Although terms such as "first", "second", etc. may be used to describe various components, the above terms are only used to distinguish one component from another. The terms do not mean that the materials or structures of the components are different.

[0061] The singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. When a part "includes" an element, it may further include additional elements, rather than excluding the presence of additional elements, unless otherwise described.

[0062] Terms such as “unit” or “module” refer to a unit that performs at least one function or operation, and the unit may be implemented as hardware or software, or as a combination of hardware and software.

[0063] The use of the terms "a," "an," and "the" and similar referents in the context of describing the present disclosure are to be construed to cover both the singular and the plural.

[0064] The steps of all methods described herein can be performed in any suitable order, unless otherwise specified herein or otherwise clearly contradictory to the context. The use of any and all examples or example language (e.g., "such as") provided herein is intended only to describe the present disclosure in detail, and does not impose limitations on the scope of the present disclosure, unless otherwise stated.

[0065] As used herein, the term "metal" includes metals (eg, Hf, Ti, Mn, Zr, etc.) and semi-metals (eg, Si), such as in the phrase "metal oxide material" and the like.

[0066] Figure 1 is a cross-sectional view illustrating a structure of a variable resistance memory device according to an embodiment. Figure 2 For use in describing the Figure 1 A conceptual diagram of the principle of resistance change occurring in a variable resistance layer in a variable resistance memory device.

[0067] Reference Figure 1 The variable resistance memory device 100 includes a variable resistance layer 120 including a first layer 11 and a second layer 12 , and a first conductive element E1 and a second conductive element E2 that apply a voltage to the variable resistance layer 120 .

[0068] The variable resistance layer 120 includes a first layer 11 formed of a first material, and a second layer 12 formed of a second material having a density different from that of the first material and located on the first layer 11. The second layer 12 may have a higher density than the first layer 11.

[0069] The first conductive element E1 and the second conductive element E2 may be located on both ends on the variable resistance layer 120 to form a current path in the horizontal direction (i.e., a direction perpendicular to the direction in which the first layer 11 and the second layer 12 are stacked) in the variable resistance layer 120 when a voltage is applied. The first conductive element E1 and the second conductive element E2 may be formed to contact both ends of the second layer 12. However, this is only an example, and the first conductive element E1 and the second conductive element E2 may be formed to contact both ends of the first layer 11.

[0070] The variable resistance layer 120 is a layer having resistance characteristics that change according to an applied voltage. The resistance characteristics of the variable resistance layer 120 depend on whether conductive filaments are formed due to the behavior of oxygen occurring in the variable resistance layer 120 according to the voltage applied to the first conductive element E1 and the second conductive element E2 formed on the variable resistance layer 120. Depending on whether the conductive filaments are formed, the variable resistance layer 120 may have a low resistance state or a high resistance state, and information "1" or "0" is written accordingly. The applied voltage for changing the variable resistance layer 120 from a high resistance state to a low resistance state is referred to as a set voltage V 设定The applied voltage for changing the variable resistance layer 120 from the low resistance state to the high resistance state is called the reset voltage V 复位 , and the variable resistance memory device 100 according to the embodiment includes the variable resistance layer 120 configured to have a low set voltage.

[0071] Reference Figure 2 When current flows between the two ends of the variable resistance layer 120 due to the applied voltage, oxygen vacancies (V o ) and interstitial oxygen ions (O 2- ). Oxygen vacancies (V o ) are aggregated to form conductive filaments, and due to the conductive filaments, the resistance of the variable resistance layer 120 is reduced.

[0072] When the conductive filaments are easily formed even at a low voltage and the resistance difference between the low resistance state and the high resistance state due to the applied voltage is large, the variable resistance performance is excellent. For this reason, oxygen vacancies (V o As in the embodiment, when the variable resistance layer 120 has a multilayer structure in which the first layer 11 having a low density and the second layer 12 having a high density are adjacent to each other, since the oxide having a low density has a wider space between atoms than the oxide having a high density, the oxygen ions (O 2- ) can diffuse more smoothly (smoothly) from the second layer 12 to the first layer 11. Once the oxygen ions (O 2- ) diffuses from the second layer 12 to the first layer 11, and the oxygen vacancies (V o ) may be gathered in the second layer 12 and may easily form conductive filaments.

[0073] When the variable resistance layer 120 is configured as described above, the desired resistance switching range can be ensured at a low thickness when compared with an existing variable resistance device based on charge trapping or a variable resistance device using a phase change material. The first layer 11 and the second layer 12 constituting the variable resistance layer 120 may each have a thickness equal to or less than 10 nm (e.g., greater than 0 nm and less than or equal to 10 nm).

[0074] The first material and the second material included in the variable resistance layer 120 may be formed of any of a variety of oxides. For example, the first material and the second material may each include an oxide of at least one element selected from the following: zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), praseodymium (Pr) and silicon (Si). For each of the first material and the second material, an oxide (metal oxide) having a band gap energy of 2eV or more may be used, and for example, Rb may be used for each of the first material and the second material. 2 O、TiO 2 、BaO、ZrO 2 , CaO, HfO 2 、SrO、Sc 2 O 3 、MgO、Li 2 O、Al 2 O 3 、SiO 2 , BeO, Sc 2 O 3 , Nb 2 O 5 、NiO、Ta 2 O 5 , WO 3 、V 2 O 5 ,La 2 O 3 , Gd 2 O 3 ,CuO,MoO 3 Cr 2 O 3 and MnO 2 Any of.

[0075] The densities of the above materials are shown in Table 1.

[0076] [Table 1]

[0077]

[0078]

[0079] Referring to Table 1, the first layer 11 may be formed of a material having a low density, and the second layer 12 may be formed by selecting a material having a relatively high density. A density difference between the first layer 11 and the second layer 12 may be set so that oxygen ions diffuse smoothly and conductive filaments are easily formed due to oxygen vacancies. For example, the materials of the first layer 11 and the second layer 12 may be set so that the density difference between the first layer 11 and the second layer 12 is greater than 1 g / cm3 Since oxygen ions can diffuse more smoothly as the density difference increases, the materials of the first layer 11 and the second layer 12 may be arranged so that the density difference is greater than 1.5 g / cm 3 or greater than 2g / cm 3 For example, the first layer 11 may include SiO 2 , and the second layer 12 may include HfO 2 In addition, any of the following combinations may be used.

[0080] [Table 2]

[0081]

[0082]

[0083] As shown in each of the above combinations, the first material (metal oxide material) and the second material (metal oxide material) having the same metal valence may be selected so that the density difference is greater than 1 g / cm 3 For example, you can choose HfO 2 / TiO 2 , HfO 2 / MnO 2 , HfO 2 / ZrO 2 , or HfO 2 / SiO 2 As a combination of materials (metal oxide materials) having a metal valence of 4. The density difference of the above combination may be greater than 4 g / cm 3 . Gd can be selected 2 O 3 / Cr 2 O 3 or Gd 2 O 3 / La 2 O 3 As a combination of materials (metal oxide materials) having a metal valence of 3. The density difference of the combination may be greater than 2 g / cm 3 NiO / SrO, NiO / CaO, or NiO / BeO may be selected as a combination of materials (metal oxide materials) having a metal valence of 2, and the density difference of the combination may be greater than 1.5 g / cm 3 . WO can be selected 3 / MoO 3 As a combination of materials (metal oxide materials) having a metal valence of 6. However, the present disclosure is not limited to the above combination, and materials having different metal valences and having a metal oxide content of 1 g / cm or more may be selected. 3 Materials with different densities (metal oxide materials).

[0084] Figure 3 is a cross-sectional view illustrating a configuration of a variable resistance memory device 101 according to another embodiment.

[0085] The variable resistance memory device 101 of the present embodiment is different from the variable resistance memory device 101 in that the first layer 11 and the second layer 12 constituting the variable resistance layer 120 are positioned in the order in which the first layer 11 and the second layer 12 are positioned. Figure 1 The first layer 11 formed of a material having a low density may be located above the second layer 12 formed of a material having a high density, and the first and second conductive elements E1 and E2 may be located to contact both ends of the first layer 11.

[0086] Figure 4 is a cross-sectional view illustrating a configuration of a variable resistance memory device according to another embodiment. Figure 5 For use in describing the Figure 4 A conceptual diagram of the principle of resistance change occurring in a variable resistance layer in a variable resistance memory device.

[0087] Reference Figure 4 , the variable resistance memory device 102 includes a variable resistance layer 122 including a first layer 11, a second layer 12, and a third layer 13. The second layer 12 is an intermediate layer of the variable resistance layer 122 and may have a higher density than the first layer 11 and the third layer 13. The first layer 11 and the third layer 13 may be formed of the same material having a lower density than the second layer 12. However, the present disclosure is not limited thereto, and the first layer 11 and the third layer 13 may be formed of different materials each having a lower density than the second layer 12. The first layer 11 and the third layer 13 may each include SiO 2 , and the second layer 12 may include HfO 2 In addition, the first layer 11 and the third layer 13 may each include a first material, the second layer 12 may include a second material, and a combination of the first material and the second material may be selected as shown in Table 2.

[0088] The first layer 11, the second layer 12, and the third layer 13 may each have a thickness equal to or less than 10 nm. The second layer 12 may have the smallest thickness. For example, the second layer 12 may have a thickness equal to or less than 2 nm.

[0089] In the present embodiment, since the second layer 12 formed of a material having a high density is located in the middle and the first layer 11 and the third layer 13 each formed of a material having a low density are located adjacent to both surfaces of the second layer 12, the oxygen ions (O 2- ) will widen the diffusion space.

[0090] like Figure 5As shown in FIG. 1 , when oxygen vacancies (V o ) and interstitial oxygen ions (O 2- ) when oxygen ions (O 2- ) can be quickly diffused from the second layer 12 to the first layer 11 and / or the third layer 13 having low density and wide spaces between atoms. o ), it is easier to form conductive filaments. Figure 1 Compared with the structure of or 3, such diffusion can occur more smoothly and conductive filaments can be formed more easily.

[0091] Figure 6 and 7 A cross-sectional view illustrating the configuration of a sample manufactured for testing the variable resistance performance of a structure in which variable resistance materials having a density difference are stacked adjacent to each other.

[0092] like Figure 6 As shown in FIG. , a SiO 2 layer, an N-type Si layer with a thickness of 400 nm, and a SiO layer with a thickness of 10 nm. 2 A layer and an N-type Si layer having a thickness of 50 nm are sequentially deposited on a Si wafer, and then patterning and etching processes are performed to form an N-Si (50 nm) / SiO 2 (10nm) / N-Si (400nm) cylindrical device. When HfO as the resistance switching material is deposited on the side surface of the cylindrical device 2 When a voltage is applied between the N-Si electrode as the upper electrode and the N-Si electrode as the lower electrode, a current flows along the HfO 2 / SiO 2 The layer flows from the upper electrode N-Si to the lower electrode N-Si. In this case, in order to improve the contact resistance between the probe station terminal and the upper electrode N-Si, Ti (10nm) / Pt (40nm) is deposited on the upper electrode N-Si.

[0093] Figure 7 Describe the following structure: where Figure 6 Compared with the structure of HfO 2 The layer has a thickness of 2 nm and is in HfO 2 A SiO layer with a thickness of 5 nm is further deposited on the 2 When voltage is applied between the upper N-Si electrode and the lower N-Si electrode, current flows along the SiO 2 / HfO 2 / SiO 2 The layers flow from the upper electrode N-Si to the lower electrode N-Si.

[0094] Figure 6 and Figure 7 The structures are used to simulate Figure 1 and 4 Examples of the performance of the variable resistance layer 120 having a two-layer structure and the variable resistance layer 122 having a three-layer structure.

[0095] In both structures, the set voltage V for changing from the high resistance state to the low resistance state is measured. 设定 , and 35 such as Figure 6 The average set voltage V of the samples shown in 设定 is 12.36V, and 58 Figure 7 The average set voltage V of the samples shown in 设定 It is 11.17V.

[0096] It is found that when the voltage V 设定 Compared with the setting voltage V of 15V or higher in the existing variable resistance device using the charge trapping layer 设定 When compared, a structure in which two layers with different densities are positioned adjacent to each other can reduce the set voltage. Moreover, it was found that when the variable resistance layer is formed to have a three-layer structure in which the layer with the highest density is located in the middle, the set voltage can be further reduced.

[0097] Figure 8 is a cross-sectional view illustrating a configuration of a variable resistance memory device according to another embodiment. Fig. 9 for Figure 8 Equivalent circuit diagram of a variable resistance memory device.

[0098] Reference Figure 8 , the variable resistance memory device 200 includes an insulating layer 210, a variable resistance layer 220 located on the insulating layer 210, a channel layer 240 located on the variable resistance layer 220, a gate insulating layer 250 located on the channel layer 240, and a plurality of gate electrodes 260 formed on the gate insulating layer 250. Spaces between the plurality of gate electrodes 260 may be filled with an insulating layer 270. However, this is merely an example, and the insulating layer 270 may be omitted.

[0099] The variable resistance layer 220 includes a first layer 11 formed of a first material and a second layer 12 formed of a second material having a density different from that of the first material. The second layer 12 may have a higher density than that of the first layer 11. The materials and characteristics of the variable resistance layer 220 are similar to those of the first layer 11. Figure 1That is, the variable resistance layer 220 is formed to have a multilayer structure in which the first layer 11 having a low density and the second layer 12 having a high density are adjacent to each other, oxygen ions can be smoothly diffused into the oxide having a wide space between atoms and a low density, and due to oxygen vacancies (V o ), conductive filaments can be easily formed.

[0100] Although the second layer 12 having a high density is located above the first layer 11 having a low density in the variable resistance layer 220, the present disclosure is not limited thereto, and the order in which the first layer 11 and the second layer 12 are stacked may be changed. That is, the first layer 11 having a low density may be formed on the second layer 12 having a high density so that the first layer 11 may contact the channel layer 240.

[0101] The channel layer 240 may be formed of a semiconductor material. The channel layer 240 may be formed of, for example, polycrystalline silicon (poly-Si). A source electrode S and a drain electrode D may be connected to both ends of the channel layer 240.

[0102] The gate insulating layer 250 may be formed of any of a variety of insulating materials. For example, silicon oxide, silicon nitride, or silicon oxynitride may be used for the gate insulating layer 250 .

[0103] A voltage for turning on / off the channel layer 240 may be selectively applied to each of the plurality of gate electrodes 260 .

[0104] The variable resistance memory device 200 has a structure in which a plurality of memory cells MC are arranged, and each of the memory cells MC includes a Fig. 9 The transistors and variable resistors are connected in parallel as shown in the equivalent circuit diagram of . The resistance value of each variable resistor is set by the voltage applied to the gate electrode and the voltage between the source electrode S and the drain electrode D, and it corresponds to information 1 or 0.

[0105] Now refer to Fig.10 The operation of the variable resistance memory device 200 is described.

[0106] When selecting a memory cell to be written, the gate voltage value of the selected cell is adjusted so that no channel is formed in the selected cell, that is, the selected cell is in a channel-off state, and the gate voltage value of the unselected cell is adjusted so that the unselected cell is in a channel-on state.

[0107] Fig.10The gate voltage is applied to the gate electrode 260 of each cell, so that the memory cell MC2 in the middle is turned off, and the two memory cells MC1 and MC3 on both sides are turned on. When a voltage is applied between the source electrode S and the drain electrode D, a conductive path is formed as marked by arrow A. When the applied voltage is V 设定 or V 复位 When , the desired information 1 or 0 can be written into the memory cell MC2 which is the selected memory cell.

[0108] Moreover, a read operation can be performed on the selected cell in a similar manner. That is, after adjusting the gate voltage applied to each gate electrode 260 so that the selected memory cell MC2 is in a channel-off state and the unselected memory cells MC1 and MC3 are in a channel-on state, the cell state (1 or 0) can be checked by measuring the voltage V applied between the source electrode S and the drain electrode D. 读取 And the current flowing through the memory cell MC2.

[0109] Fig.11 is a cross-sectional view illustrating a structure of a variable resistance memory device according to another embodiment.

[0110] The variable resistance memory device 201 of this embodiment is Figure 8 The variable resistance memory device 200 is substantially the same as that of FIG. 1 , except that the variable resistance layer 221 includes a first layer 11 , a second layer 12 , and a third layer 13 .

[0111] The variable resistance layer 221 includes a first layer 11, a second layer 12, and a third layer 13. The second layer 12 as an intermediate layer of the variable resistance layer 221 may have a density higher than that of the first layer 11 and the third layer 13. The first layer 11 and the third layer 13 may be formed of the same material having a density lower than that of the second layer 12. However, the present disclosure is not limited thereto, and the first layer 11 and the third layer 13 may be formed of different materials.

[0112] Since the variable resistance memory device 201 of the present embodiment includes the variable resistance layer 221 in which the second layer 12 formed of a material having a high density is located in the middle, and the first layer 11 and the third layer 13 each formed of a material having a low density are located adjacent to both surfaces of the second layer 12, oxygen ions can be more easily diffused into the layer having a wide space between atoms and a low density, and a conductive filament can be more smoothly formed due to oxygen vacancies. The variable resistance memory device 201 of the embodiment can have a low set voltage, and, for example, can have a higher set voltage than Figure 8 The set voltage of the variable resistance memory device 200 is lower than the set voltage.

[0113] Fig.12is a cross-sectional view illustrating a structure of a variable resistance memory device according to another embodiment.

[0114] Fig.13 To illustrate the setting Fig.12 A perspective view of a structure of a memory string in a variable resistance memory device.

[0115] Fig.14 for Fig.12 Equivalent circuit diagram of a variable resistance memory device.

[0116] The variable resistance memory device 500 of the present embodiment is a vertical NAND (VNAND) memory in which a plurality of memory cells MC including a variable resistance material are vertically arranged.

[0117] Reference Figures 12 to 14 , a specific configuration of the variable resistance memory device 500 will now be described.

[0118] First, refer to Fig.12 , a plurality of cell strings CS are formed on a substrate 530 .

[0119] The substrate 530 may include a silicon material doped with a first type impurity. For example, the substrate 530 may include a silicon material doped with a p-type impurity. For example, the substrate 530 may be a p-type well (e.g., a pocket p-well). The following will be described under the assumption that the substrate 530 is a p-type silicon substrate. However, the substrate 530 is not limited to a p-type silicon substrate.

[0120] The doping region 535 is disposed on the substrate 530. For example, the doping region 535 may be a second type different from the substrate 530. For example, the doping region 535 may be an n-type region. The following description will be made under the assumption that the doping region 535 is an n-type region. However, the doping region 535 is not limited to the n-type region. The doping region 535 may be connected to the common source line CSL.

[0121] The k×n cell strings CS can be Fig.14 The cells are arranged in a matrix as shown in the equivalent circuit diagram of , and each can be represented by CSij (1≤i≤k and 1≤j≤n) according to each row and column position. Each cell string CSij is connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL.

[0122] Each cell string CSij includes a memory cell MC and a string selection transistor SST. The memory cell MC and the string selection transistor SST of each cell string CSij may be stacked in a height direction.

[0123] The rows of the plurality of cell strings CS are respectively connected to different string selection lines SSL1 to SSLk. For example, the string selection transistors SST of the cell strings CS11 to CS1n are commonly connected to the string selection line SSL1. The string selection transistors SST of the cell strings CSk1 to CSkn are commonly connected to the string selection line SSLk.

[0124] The columns of the plurality of cell strings CS are respectively connected to different bit lines BL1 to BLn. For example, the memory cells MC and string selection transistors SST of the cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and string selection transistors SST of the cell strings CS1n to CSkn may be commonly connected to the bit line BLn.

[0125] Rows of a plurality of cell strings CS may be connected to different common source lines CSL1 to CSLk, respectively. For example, string selection transistors SST of cell strings CS11 to CS1n may be commonly connected to a common source line CSL1, and string selection transistors SST of cell strings CSk1 to CSkn may be commonly connected to a common source line CSLk.

[0126] Memory cells MC or string selection transistors SST located at the same height from the substrate 530 may be commonly connected to one word line WL, and memory cells MC or string selection transistors SST located at different heights may be respectively connected to different word lines WL1 to WLn.

[0127] Fig.14 The circuit structure shown in is only an example. For example, the number of rows of cell strings CS may increase or decrease. As the number of rows of cell strings CS changes, the number of string selection lines connected to the rows of cell strings CS and the number of cell strings CS connected to one bit line may also change. As the number of rows of cell strings CS changes, the number of common source lines connected to the rows of cell strings CS may also change.

[0128] The number of columns of cell strings CS may also increase or decrease. As the number of columns of cell strings CS changes, the number of bit lines connected to the columns of cell strings CS and the number of cell strings CS connected to one string selection line may also change.

[0129] The height of the cell string CS may also increase or decrease. For example, the number of memory cells MC stacked in each of the cell strings CS may increase or decrease. As the number of memory cells MC stacked in each cell string CS changes, the number of word lines WL may also change. For example, the number of string selection transistors respectively provided to the cell string CS may increase. As the number of string selection transistors provided to the cell string CS changes, the number of string selection lines or common source lines may also change. When the number of string selection transistors increases, the string selection transistors may be stacked in the same manner as the memory cells MC.

[0130] For example, write and read operations may be performed in row units of cell strings CS. Cell strings CS may be selected in row units through common source lines CSL, and cell strings CS may be selected in row units through string selection lines SSL. Moreover, a voltage may be applied to the common source lines CSL in units of at least two common source lines CSL. A voltage may be applied to the common source lines CSL in units of all common source lines CSL.

[0131] In the selected row of the cell string CS, write and read operations may be performed in units of pages. A page may be a row of memory cells connected to one word line WL. In the selected row of the cell string CS, memory cells may be selected in units of pages through the word lines WL.

[0132] One cell string CS includes a cylindrical pillar PL and a plurality of gate electrodes 560 and a plurality of insulators 570 surrounding the cylindrical pillar PL in a ring shape, as shown in FIG. Fig.13 As shown in . A plurality of gate electrodes 560 and a plurality of insulators 570 may be alternately stacked in a vertical direction (eg, Z direction).

[0133] The gate electrodes 560 may be formed of a metal material or a heavily doped silicon material. Each gate electrode 560 is connected to one of a word line WL and a string selection line SSL.

[0134] Insulator 570 may be formed of any of a variety of insulating materials such as silicon oxide or silicon nitride.

[0135] The pillar PL may include a plurality of layers. The outermost layer of the pillar PL may be a gate insulating layer 550. For example, the gate insulating layer 550 may be formed of any of a variety of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The gate insulating layer 550 may be conformally deposited on the pillar PL.

[0136] The channel layer 540 may be conformally deposited along the inner surface of the gate insulating layer 550. The channel layer 540 may include a semiconductor material doped with a first type dopant. The channel layer 540 may include a silicon material doped with the same type of dopant as the substrate 530, and when the substrate 530 includes a silicon material doped with a p-type dopant, the channel layer 540 may include a silicon material also doped with a p-type dopant. Alternatively, the channel layer 540 may include a material such as germanium (Ge), IGZO, or GaAs.

[0137] The variable resistance layer 520 may be positioned along an inner surface of the channel layer 540. The variable resistance layer 520 may contact the channel layer 540 and may be conformally deposited on the channel layer 540.

[0138] The variable resistance layer 520 that changes to a high resistance state or a low resistance state according to an applied voltage may include a first layer 11 and a second layer 12 formed of oxides having different densities. Figure 1 The variable resistance layers 120 are substantially the same.

[0139] The first layer 11 and the second layer 12 of the variable resistance layer 520 may each include an oxide of at least one element selected from the group consisting of zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), praseodymium (Pr), and silicon (Si). For each of the first material 11 and the second material 12, an oxide having a band gap energy of 2 eV or more may be used, and for example, Rb may be used. 2 O、TiO 2 、BaO、ZrO 2 , CaO, HfO 2 、SrO、Sc 2 O 3 、MgO、Li 2 O、Al 2 O 3 、SiO 2 and BeO. That is, the first layer 11 may be formed of a material having a low density, and the second layer 12 may be formed by selecting a material having a relatively high density. Therefore, since oxygen ions may be smoothly diffused and conductive filaments may be easily formed due to oxygen vacancies, the variable resistance memory device 500 may have characteristics of low set voltage and reset voltage.

[0140] The channel layer 540 and the variable resistance layer 520 may contact the doping region 535 , ie, a common source region.

[0141] The drain 580 may be disposed on the pillar PL. The drain 580 may include a silicon material doped with a second type dopant. For example, the drain 580 may include a silicon material doped with an n-type dopant.

[0142] The bit line 590 may be disposed on the drain 580. The drain 580 and the bit line 590 may be connected through a contact plug.

[0143] Each gate electrode 560 and a portion of the gate insulating layer 550, the channel layer 540, and the variable resistance layer 520 facing the gate electrode 560 in the horizontal direction (e.g., the X direction) constitute a memory cell MC. That is, the memory cell MC has a circuit structure in which a transistor including the gate electrode 560, the gate insulating layer 550, and the channel layer 540 is connected in parallel with a variable resistor formed by the variable resistance layer 520.

[0144] Such parallel connection structures are continuously arranged in a vertical direction (eg, Z direction) to form a cell string CS. Both ends of the cell string CS may be connected to a common source line CSL and a bit line BL, such as Fig.14 By applying voltage to the common source line CSL and the bit line BL, programming, reading and erasing operations can be performed on a plurality of memory cells MC.

[0145] For example, when a memory cell MC to be written is selected, the gate voltage value of the selected cell is adjusted so that no channel is formed in the selected cell, that is, the selected cell is in a channel-off state, and the gate voltage value of the unselected cell is adjusted so that the unselected cell is in a channel-on state. Therefore, the current path formed by the voltage applied to the common source line CSL and the bit line BL can pass through the variable resistance layer 520 of the selected memory cell MC, and when the applied voltage is V 设定 or V 复位 When , a low resistance state or a high resistance state can be obtained and desired information 1 or 0 can be written to the selected memory cell MC.

[0146] Furthermore, a read operation can be performed on the selected cell in a similar manner. That is, after adjusting the gate voltage applied to each gate electrode 560 so that the selected memory cell MC is in a channel-off state and the unselected memory cells are in a channel-on state, the cell state (1 or 0) can be checked by measuring the voltage V applied between the common source line CSL and the bit line BL. 读取 And the current flowing through the memory cell MC.

[0147] Fig.15 is a cross-sectional view illustrating a structure of a variable resistance memory device according to another embodiment.

[0148] The variable resistance memory device 501 of this embodiment is Fig.12 The variable resistance memory device 500 is substantially the same as that of FIG. 5 , except that the variable resistance layer 521 includes a first layer 11, a second layer 12, and a third layer 13 having different densities. One cell string CS includes a cylindrical pillar PL and a plurality of gate electrodes 560 and a plurality of insulators 570 surrounding the cylindrical pillar PL in a ring shape, such as Fig.16 As shown in . A plurality of gate electrodes 560 and a plurality of insulators 570 may be alternately stacked in a vertical direction (eg, Z direction).

[0149] The second layer 12 may have a higher density than the first layer 11 and the third layer 13. The first layer 11 and the third layer 13 may be formed of the same material having a density lower than that of the second layer 12. However, the present disclosure is not limited thereto, and the first layer 11 and the third layer 13 may be formed of different materials each having a density lower than that of the second layer 12. The first layer 11 and the third layer 13 may each include SiO 2 , and the second layer 12 may include HfO 2 . In addition, the first layer 11 and the third layer 13 may each include a first material, and the second layer 12 may include a second material, and a combination of the first material and the second material may be selected as shown in Table 2. The first layer 11, the second layer 12, and the third layer 13 may each have a thickness equal to or less than 10 nm. The second layer 12 may have a minimum thickness. For example, the second layer 12 may have a thickness equal to or less than 2 nm. Moreover, the third layer 13 contacting the channel layer 540 may have a thickness equal to or greater than 5 nm.

[0150] In the present embodiment, since the second layer 12 formed of a material having a high density is located in the middle and the first layer 11 and the third layer 13 each formed of a material having a low density are located adjacent to both surfaces of the second layer 12, the oxygen ions (O 2- ) The diffusion space can be widened and the conductive filaments due to the oxygen vacancies can be more easily formed. The variable resistance memory device 501 can have a Fig.12 The set voltage is lower than the set voltage.

[0151] Although the variable resistance layer includes two or three layers in the above embodiments, the present disclosure is not limited thereto, and the variable resistance layer may include three or more layers in which layers having a desired and / or alternatively predetermined density difference are positioned adjacent to each other.

[0152] As described above, since the variable resistance memory devices 500 and 501 according to the embodiments can be implemented by arranging memory cells MC including variable resistance layers 520 and 521, which have a structure in which conductive filaments are easily formed due to oxygen vacancies, the variable resistance layers 520 and 521 can be thinner and can achieve a lower operating voltage compared to those having an existing structure such as a phase change material or a charge trap-based memory device. Since the variable resistance memory devices 500 and 501 can solve the scaling problem between memory cells in the next generation VNAND, the integration density can be increased and low power consumption can be achieved.

[0153] The variable resistance memory devices 500 and 501 according to the present disclosure may include a chip-type memory block and may be used in a memory system, may be used as a neuromorphic computing platform, or may be used to form a neural network.

[0154] Fig.17 is a block diagram of a storage system according to an embodiment.

[0155] Reference Fig.17 , the memory system 1700 may include a memory controller 1701 and a memory device 1702. The memory controller 1701 performs a control operation on the memory device 1702, for example, the memory controller 1701 provides an address ADD and a command CMD to the memory device 1702 to perform a program (or write), read and / or erase operation on the memory device 1702. Moreover, data for a program operation and read data may be transmitted between the memory controller 1701 and the memory device 1702.

[0156] The memory device 1702 may include a memory cell array 1710 and a voltage generator 1720. The memory cell array 1710 may include a plurality of memory cells arranged on a region where a plurality of word lines and a plurality of bit lines intersect each other. The memory cell array 1710 includes a memory cell array 1710 based on the present application. Figure 1-5 The non-volatile memory cell of the embodiments in and 8-16.

[0157] The storage controller 1701 may include processing circuitry such as hardware including logic circuitry; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The storage controller 1701 may operate in response to a request from a host (not shown) and may be configured to access the storage device 1702 and control the operations discussed above (e.g., for Fig.10 1701), thereby converting the memory controller 1701 into a dedicated controller. The memory controller 1701 may generate an address ADD and a command CMD for performing a program / read / erase operation on the memory cell array 1710. Moreover, in response to a command from the memory controller 1701, the voltage generator 1720 (e.g., a power supply circuit) may generate a voltage control signal for controlling at least one voltage level used in the nonvolatile memory device 1702. As an example, the voltage generator 1720 may generate a voltage control signal for controlling a voltage level of a word line to read data from the memory cell array 1710 or program data on the memory cell array 1710.

[0158] In addition, the memory controller 1701 may perform a determination operation on the data read from the nonvolatile memory device 1702. For example, by determining the data read from the memory cell, the number of on cells and / or off cells from among the memory cells may be determined. The memory device 1702 may provide a pass / fail signal P / F to the memory controller 1701 according to the read result of the read data. The memory controller 1701 may refer to the pass / fail signal P / F and thus control the write and read operations of the memory cell array 1710.

[0159] Fig.18 A diagram illustrating a neuromorphic device and external devices connected thereto according to an embodiment.

[0160] Reference Fig.18 , the neuromorphic device 1800 may include a processing circuit 1810 and / or a memory 1820. The neuromorphic device 1800 may include a processing circuit 1810 and / or a memory 1820 based on the present application Figure 1-5 and the memory device of the embodiments in 8-16.

[0161] In some example embodiments, the processing circuit 1810 may be configured to control functions for driving the neuromorphic device 1800. For example, the processing circuit 1810 may be configured to control the neuromorphic device 1800 by executing a program stored in a memory (e.g., on-chip memory) 1820 of the neuromorphic device 1800. In some example embodiments, the processing circuit may include hardware such as a logic circuit; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1800, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit 1810 may be configured to read / write various data from / in the external device 1830, and / or manipulate the neuromorphic device 1800 by using the read / written data. In some embodiments, external device 1830 may include external memory and / or a sensor array having an image sensor (eg, a CMOS image sensor circuit).

[0162] In some embodiments, Fig.18The neuromorphic device in the invention can be applied to a machine learning system. The machine learning system can utilize various artificial neural network organizations and processing models such as convolutional neural networks (CNNs), deconvolutional neural networks, recurrent neural networks (RNNs) optionally including long short-term memory (LSTM) units and / or gated recurrent units (GRUs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0163] Alternatively or additionally, such a machine learning system may include other forms of machine learning models such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and / or combinations thereof, including ensembles such as random forests. Such machine learning models may also be used to provide a variety of services and / or applications such as image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance system (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc., which may be executed, implemented or processed by electronic devices.

[0164] Although the variable resistance memory device has been described with reference to embodiments, this is only an example, and a person skilled in the art will understand that a variety of variations and equivalent embodiments may be generated therefrom. Although the present disclosure has been described with reference to some embodiments, the embodiments are only examples and do not limit the scope of the present disclosure. The scope of the present disclosure is not limited by the described embodiments, but only by the claims.

[0165] The variable resistance memory device may have resistance switching at a low applied voltage.

[0166] The variable resistance memory device may have a wide variable resistance range.

[0167] The variable resistance memory device can easily have low power consumption and high integration density.

[0168] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should typically be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A variable resistance memory device, comprising: A variable resistance layer including a first layer, a second layer, and a third layer, The first layer is formed of a first material, The second layer is on the first layer, and the second layer is formed of a second material, The density of the second material is higher than the density of the first material, The third layer is on the second layer, and the third layer is formed of a third material, The density of the third material is lower than the density of the second material, wherein the thickness of each of the first layer, the second layer and the third layer is equal to or less than 10 nm; as well as and a first conductive element and a second conductive element on the variable resistance layer and spaced apart from each other to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

2. A variable resistance memory device, comprising: Insulation layer; a variable resistance layer on the insulating layer, the variable resistance layer comprising a first layer, a second layer, and a third layer, The first layer is formed of a first material, The second layer is on the first layer, and the second layer is formed of a second material, The density of the second material is higher than the density of the first material, The third layer is on the second layer, and the third layer is formed of a third material, The density of the third material is lower than the density of the second material, wherein the thickness of each of the first layer, the second layer and the third layer is equal to or less than 10 nm; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; as well as A plurality of gate electrodes are spaced apart from each other on the gate insulating layer, wherein the plurality of gate electrodes are configured to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

3. The variable resistance memory device according to claim 2, wherein The third layer contacts the channel layer and has a thickness equal to or greater than 5 nm.

4. A variable resistance memory device, comprising: A variable resistance layer including a first layer, a second layer, and a third layer, The first layer comprises a first material, the second layer is on the first layer, The second layer comprises a second material, The density of the second material is higher than the density of the first material, The third layer is on the second layer, and the third layer is formed of a third material, The density of the third material is lower than the density of the second material, wherein the thickness of each of the first layer, the second layer and the third layer is equal to or less than 10 nm; as well as and a first conductive element and a second conductive element on the variable resistance layer and spaced apart from each other to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

5. The variable resistance memory device according to any one of claims 1, 2 and 4, wherein a density difference between the first material and the second material is greater than 1 g / cm 3 .

6. The variable resistance memory device according to any one of claims 1, 2 and 4, wherein a density difference between the second material and the third material is greater than 1 g / cm 3 . 7 . The variable resistance memory device according to claim 1 , wherein the first material and the third material are the same material.

8. The variable resistance memory device according to any one of claims 1, 2 and 4, wherein The thickness of the second layer is less than the thickness of the first layer, and The thickness of the second layer is smaller than the thickness of the third layer.

9. The variable resistance memory device according to any one of claims 1, 2 and 4, wherein the first material and the second material are each an oxide having a band gap energy of 2 eV or more.

10. The variable resistance memory device of any one of claims 1, 2 and 4, wherein the first material and the second material are each independently any one of Rb2O, TiO2, BaO, ZrO2, CaO, HfO2, SrO, Sc2O3, MgO, Li2O, Al2O3, SiO2, BeO, Nb2O5, NiO, Ta2O5, WO3, V2O5, La2O3, Gd2O3, CuO, MoO3, Cr2O3 and MnO2.

11. The variable resistance memory device according to any one of claims 1, 2 and 4, wherein The first material and the second material are different metal oxide materials, and the metals in the metal oxide materials have the same valence, and The density difference between the first material and the second material is greater than 1.5 g / cm 3 .

12. The variable resistance memory device according to any one of claims 1, 2 and 4, wherein The first material is HfO2, and the second material is TiO2, MnO2, ZrO2, SiO2 or Cr2O3, or The first material is Gd2O3, and the second material is Cr2O3 or La2O3, or The first material is NiO, and the second material is SrO, CaO or BeO, or The first material is WO3, and the second material is MoO3.

13. The variable resistance memory device according to any one of claims 1, 2 and 4, wherein the second layer has a thickness equal to or less than 2 nm.

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