Variable resistance memory device

Abstract

A variable resistance memory device is disclosed. The variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer including a first metal oxide material and a second layer on the first layer, and the second layer includes a second metal oxide material. The second metal oxide material has a metal valence different from that of the first metal oxide material. The first conductive element and the second conductive element are on the variable resistance layer and separated from each other to form a current path in the variable resistance layer in a direction perpendicular to the direction in which the first layer and the second layer are stacked.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0176731 filed on December 27, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a nonvolatile memory device including a variable resistance material. Background Art

[0004] Nonvolatile memory is a semiconductor memory device that can retain stored data even when power is terminated. Examples of nonvolatile memory devices may include programmable read-only memory (PROM), erasable PROM (EPROM), electrical EPROM (EEPROM), flash memory devices, etc.

[0005] Recently, according to technical requirements for high integration and low power consumption characteristics and random access (access) to memory cells, next generation semiconductor memory devices such as magnetic random access memory (MRAM) and phase change random access memory (PRAM) have been developed.

[0006] Such next-generation semiconductor memory devices use variable resistance devices, which have a resistance value that changes according to the current or voltage applied thereto and can maintain the resistance value even when the current or voltage supply is cut off. In order to achieve high integration and low power consumption, it is expected that the resistance change characteristics of the variable resistance device appear at a low applied voltage and the resistance variable range is increased. Summary of the invention

[0007] A variable resistance memory device is provided.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0009] According to an embodiment, a variable resistance memory device includes: a variable resistance layer, which includes a first layer and a second layer on the first layer, the first layer includes a first metal oxide material and the second layer includes a second metal oxide material having a metal valence (valence state) different from that of the first metal oxide material; and a first conductive element and a second conductive element, which are on the variable resistance layer and separated from each other so that a current path is formed in the variable resistance layer in a direction perpendicular to the direction in which the first layer and the second layer are stacked.

[0010] In some embodiments, the difference between the metal valence of the first metal oxide material and the metal valence of the second metal oxide material may be 1 or more.

[0011] In some embodiments, the difference between the density of the first metal oxide material and the density of the second metal oxide material may be 1 g / cm 3 or larger.

[0012] In some embodiments, the variable resistance layer may further include a third layer on the second layer. The third layer may include a third metal oxide material having a metal valence different from that of the second metal oxide material.

[0013] In some embodiments, the first layer and the third layer may include the same metal oxide material.

[0014] In some embodiments, the variable resistance layer may further include a fourth layer on the third layer, the fourth layer including a fourth metal oxide material having a metal valence different from that of the third metal oxide material.

[0015] In some embodiments, the first metal oxide material can be the same as the third metal oxide material.

[0016] In some embodiments, the second metal oxide material can be the same as the fourth metal oxide material.

[0017] In some embodiments, the first metal oxide material and the second metal oxide material independently may each include a metal oxide material having a band gap energy of 2 eV or more.

[0018] In some embodiments, the first metal oxide material and the second metal oxide material may each independently include one of the following: Rb 2 O、TiO 2 、BaO、ZrO 2 , CaO, HfO 2 、SrO、Sc 2 O 3 、MgO、Li 2 O、Al 2 O 3 、SiO 2 , BeO, Nb 2 O 5 、NiO、Ta 2 O 5 , WO 3 、V 2 O 5 ,La 2 O 3 , Gd 2 O3 ,CuO,MoO 3 Cr 2 O 3 , and MnO 2 .

[0019] According to an embodiment, a variable resistance memory device includes: a support layer including an insulating material; a variable resistance layer on the support layer, the variable resistance layer including a first layer and a second layer on the first layer, the first layer including a first metal oxide material and the second layer including a second metal oxide material having a metal valence different from that of the first metal oxide material; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a plurality of gate electrodes on the gate insulating layer and separated from each other.

[0020] In some embodiments, the difference between the metal valence of the first metal oxide material and the metal valence of the second metal oxide material may be 1 or more.

[0021] In some embodiments, the difference between the density of the first metal oxide material and the density of the second metal oxide material may be 1 g / cm 3 or larger.

[0022] In some embodiments, the variable resistance layer may further include a third layer on the second layer. The third layer may include a third metal oxide material having a metal valence different from that of the second metal oxide material.

[0023] The first layer and the third layer may include the same metal oxide material.

[0024] In some embodiments, the variable resistance layer may further include a fourth layer on the third layer. The fourth layer may include a fourth metal oxide material having a metal valence different from that of the third metal oxide material.

[0025] In some embodiments, the first metal oxide material can be the same as the third metal oxide material.

[0026] In some embodiments, the second metal oxide material can be the same as the fourth metal oxide material.

[0027] In some embodiments, the first layer and the second layer each may have a thickness of 10 nm or less.

[0028] In some embodiments, the first metal oxide material and the second metal oxide material may each include a metal oxide material having a band gap energy of 2 eV or more.

[0029] The first metal oxide material and the second metal oxide material may each include one of the following: Rb2 O、TiO 2 、BaO、ZrO 2 , CaO, HfO 2 、SrO、Sc 2 O 3 、MgO、Li 2 O、Al 2 O 3 、SiO 2 , BeO, Nb 2 O 5 、NiO、Ta 2 O 5 , WO 3 、V 2 O 5 ,La 2 O 3 , Gd 2 O 3 ,CuO,MoO 3 Cr 2 O 3 , and MnO 2 .

[0030] According to an embodiment, a variable resistance memory device includes: a variable resistance layer including a plurality of layers sequentially stacked on each other, the plurality of layers including a first layer and a second layer, the first layer and the second layer contacting each other and having metal oxide materials having different metal valences from each other, an interface between the first layer and the second layer including a plurality of oxygen vacancies; a first conductive element connected to a first region of the variable resistance layer; and a second conductive element connected to a second region of the variable resistance layer, the second conductive element being spaced apart from the first conductive element.

[0031] In some embodiments, the first metal oxide material in the first layer and the second metal oxide material in the second layer each independently include one of the following: Rb 2 O、TiO 2 、BaO、ZrO 2 , CaO, HfO 2 、SrO、Sc 2 O 3 、MgO、Li 2 O、Al 2 O 3 、SiO 2 , BeO, Sc 2 O 3 , Nb 2 O 5 、NiO、Ta 2 O 5 , WO 3 、V 2 O5 ,La 2 O 3 , Gd 2 O 3 ,CuO,MoO 3 Cr 2 O 3 , and MnO 2 .

[0032] In some embodiments, the variable resistance memory device may further include: a support layer including an insulating material; a channel layer on the support layer; a gate insulating layer on the channel layer; a plurality of gate electrodes on the gate insulating layer, the plurality of gate electrodes being separated from each other. The variable resistance layer may be between the support layer and the channel layer.

[0033] In some embodiments, the first layer and the second layer each have a thickness of 10 nm or less.

[0034] In some embodiments, the first layer may include HfO 2 , and the second layer may include Al 2 O 3 . BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other aspects, features and advantages of some embodiments of the present disclosure will become more apparent from the following description considered in conjunction with the accompanying drawings, in which:

[0036] Figure 1 is a cross-sectional view of a variable resistance memory device according to an embodiment;

[0037] Figure 2 For illustration Figure 1 A conceptual diagram of a principle of a variable resistance in a variable resistance layer included in a variable resistance memory device;

[0038] Figure 3 is a cross-sectional view of a variable resistance memory device according to another embodiment;

[0039] Figure 4 For illustration Figure 3 A conceptual diagram of a principle of a variable resistance in a variable resistance layer included in a variable resistance memory device;

[0040] Figure 5 is a cross-sectional view of a variable resistance memory device according to another embodiment;

[0041] Figure 6 and 7 is a cross-sectional view of a sample for testing the variable resistance characteristics of a configuration in which variable resistance metal oxide materials having different metal valences are adjacently stacked;

[0042] Figure 8 is a cross-sectional view of a variable resistance memory device according to another embodiment;

[0043] Fig. 9 for Figure 8 An equivalent circuit diagram of a variable resistance memory device;

[0044] Fig.10 For illustration Figure 8 A conceptual diagram of an example operation (running) of a variable resistance memory device;

[0045] Fig.11 is a cross-sectional view of a variable resistance memory device according to another embodiment;

[0046] Fig.12 is a cross-sectional view of a variable resistance memory device according to another embodiment;

[0047] Fig.13 is a cross-sectional view of a variable resistance memory device according to another embodiment;

[0048] Fig.14 for Fig.13 A perspective view of a memory string (string) included in a variable resistance memory device;

[0049] Fig.15 for Fig.13 An equivalent circuit diagram of a variable resistance memory device;

[0050] Fig.16 is a block diagram of a storage system according to an embodiment; and

[0051] Fig.17 A diagram illustrating a neuromorphic device and external devices connected thereto according to an embodiment. DETAILED DESCRIPTION

[0052] The embodiment will now be described in detail, and its examples are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiment is described below only by reference to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. The expression, for example, "at least one (kind) of" modifies the entire list of elements and does not modify the individual elements of the list when it is before or after a list of elements (e.g., A, B, and C). For example, "at least one (kind) of A, B, and C", "at least one (kind) of A, B, or C", "one of A, B, C, or a combination thereof", and "one of A, B, C, and a combination thereof" can be interpreted as covering any of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.

[0053] The present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments of the present disclosure can be varied and can be embodied in many different forms. In the accompanying drawings, the same reference numerals represent the same components, and for ease of description, the sizes of the components in the accompanying drawings may be exaggerated.

[0054] When a layer, film, region, or panel is referred to as being “on” another element, it can be directly on the other element or intervening layers may also be present.

[0055] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another component. The terms do not limit the components to have different materials or structures from each other.

[0056] An expression used in the singular includes the expression in the plural unless it has an apparently different meaning in the context. Throughout the specification, when a part "includes" an element, it may further include additional elements rather than excluding the presence of the additional elements unless otherwise described.

[0057] In addition, terms such as “unit”, “module” and the like provided herein mean a unit that performs at least one function or operation and may be implemented by hardware, software, or a combination of hardware and software.

[0058] As used herein, in particular, terms such as "the" and similar referential terms may refer to both the singular and the plural.

[0059] Moreover, the steps of all methods described herein can be performed in any suitable order, unless otherwise specified herein or otherwise clearly contradictory to the context. The use of any and all examples or example language (e.g., "such as") provided herein is intended only to better illustrate the present disclosure, and does not impose limitations on the scope of the present disclosure, unless otherwise stated.

[0060] As used herein, the term "metal" includes metals (e.g., Zr, Hf, Al, Ni, etc.) and semi-metals (e.g., Si), such as in phrases "first metal oxide material", "second metal oxide material", "third metal oxide material", "fourth metal oxide material", etc.

[0061] Figure 1 is a cross-sectional view of a variable resistance memory device 100 according to an embodiment, and Figure 2 To illustrate the Figure 1 A conceptual diagram of a principle of resistance change occurring in a variable resistance layer included in a variable resistance memory device.

[0062] Reference Figure 1 The variable resistance memory device 100 includes a variable resistance layer 130 including a first layer 11 and a second layer 12 , and a first conductive element E1 and a second conductive element E2 for applying a voltage to the variable resistance layer 130 .

[0063] The variable resistance layer 130 includes a first layer 11 including a first metal oxide material, and a second layer 12 on the first layer 11, the second layer 12 including a second metal oxide material having a metal valence different from that of the first metal oxide material. The first layer 11 may have a metal valence greater than or less than that of the second layer 12.

[0064] The first conductive element E1 and the second conductive element E2 are at opposite ends on the variable resistance layer 130, and may be arranged to form a current path in the horizontal direction (i.e., a direction perpendicular to the direction in which the first layer 11 and the second layer 12 are stacked) in the variable resistance layer 130 when a voltage is applied thereto. The first conductive element E1 and the second conductive element E2 may be formed in contact with the opposite ends on the second layer 12. However, the present disclosure is not limited to the above example, i.e., the first and second conductive elements E1 and E2 may be formed in contact with the opposite ends on the first layer 11.

[0065] The variable resistance layer 130 exhibits resistance characteristics that change depending on the applied voltage. The resistance characteristics of the variable resistance layer 130 depend on whether conductive filaments are formed by the behavior of oxygen in the variable resistance layer 130 according to the voltage applied to the first conductive element E1 and the second conductive element E2 on the variable resistance layer 130. Depending on whether the conductive filaments are formed, the variable resistance layer 130 may exhibit a low resistance state or a high resistance state, and thus, information of "1" or "0" may be recorded. The applied voltage that changes the variable resistance layer 130 from the high resistance state to the low resistance state is referred to as a set voltage V 设定 , and the applied voltage that changes the variable resistance layer 130 from the low resistance state to the high resistance state is called the reset voltage V 复位 The variable resistance memory device 100 according to the embodiment proposes (includes) the variable resistance layer 130 capable of realizing a low set voltage.

[0066] As in the embodiment, when the variable resistance layer 130 includes a plurality of layers in which the first layer 11 and the second layer 12 including metal oxide materials having different metal valences from each other are stacked adjacent to each other, as shown in FIG. Figure 2 As shown in FIG. 1 , oxygen vacancies V are formed at the interface between the first and second layers 11 and 12. o to balance the charge.

[0067] For example, when the first metal oxide material included in the first layer 11 is HfO having a metal valence of 4 2 And the second metal oxide material included in the second layer 12 is Al having a metal valence of 3. 2 O 3 When Al enters the Hf site to form an oxygen vacancy at the interface between the first layer 11 and the second layer 12. The above atomic behavior can be represented by the following formula.

[0068] Al 2 O 3 +HfO 2 →2Al Hf ′+V o ** +3O o x

[0069] In the above formula, Al Hf ’ Indicates that in Al 2 O 3 Some Al in the structure occupies HfO 2 The structure of the Hf position in V O ·· represents a structure in which the O position is empty (also called an oxygen vacancy V o ), and O Ox represents a structure in which O is in the O position.

[0070] The oxygen vacancies V formed above o are collected to form conductive filaments, and the resistance of the variable resistance layer 130 is reduced by the conductive filaments.

[0071] When a reset voltage is applied, the Al that previously occupied the Hf position returns to the second layer, and thus the oxygen vacancy V o The disappearance of the conductive filaments causes the variable resistance layer to return to a high resistance state. This process is the opposite of the process of changing the variable resistance layer from a high resistance state to a low resistance state.

[0072] When the conductive filaments are sufficiently formed even at a low applied voltage and the difference between the resistances in the low resistance state and the high resistance state generated by the applied voltage increases, the variable resistance performance is excellent. To this end, the variable resistance layer 130 includes a structure in which metal oxide materials having different metal valences are arranged adjacent to each other, and the difference between the metal valences of the metal oxide materials of the first layer 11 and the second layer 12 may be 1 or more, so that oxygen vacancies V can be sufficiently formed. o .

[0073] When the variable resistance layer 130 is configured as in the embodiment, a desired resistance variation range can be achieved with a smaller thickness than a variable resistance device based on charge trapping or a variable resistance device using a phase change material. The first layer 11 and the second layer 12 in the variable resistance layer 130 may each have a thickness of, for example, about 10 nm or less.

[0074] The first metal oxide material and the second metal oxide material included in the variable resistance layer 130 may include various metal oxide materials. For example, the first metal oxide material and the second metal oxide material may include a metal oxide material of at least one atom (element) selected from the following: zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), praseodymium (Pr), rubidium (Rb), barium (Ba), magnesium (Mg), beryllium (Be), niobium (Nb), vanadium (V), gadolinium (Gd), scandium (Sc) and silicon (Si). The first metal oxide material and the second metal oxide material may each include a metal oxide material having a band gap energy of 2eV or more, such as one of the following: Rb 2 O、TiO 2 、BaO、ZrO 2 , CaO, HfO 2 、SrO、Sc 2 O3 、MgO、Li 2 O、Al 2 O 3 、SiO 2 , BeO, Sc 2 O 3 , Nb 2 O 5 、NiO、Ta 2 O 5 , WO 3 、V 2 O 5 ,La 2 O 3 , Gd 2 O 3 ,CuO,MoO 3 Cr 2 O 3 , and MnO 2 .

[0075] The metal valences of the above metal oxide materials are shown in Table 1 below.

[0076] [Table 1]

[0077]

[0078]

[0079] Referring to Table 1 above, two metal oxide materials having different metal valences may be selected and applied to the first layer 11 and the second layer 12. The difference between the metal valences of the metal oxide materials of the first layer 11 and the second layer 12 may be set so that substitution (replacement) between atoms easily occurs due to the difference in metal valences, and oxygen vacancies may be sufficiently formed. For example, the metal oxide materials used in the first layer 11 and the second layer 12 may be selected so that the difference between the metal valences of the metal oxide materials in the first layer 11 and the second layer 12 may be 1 or more. For example, the first layer 11 may include HfO having a metal valence of 4. 2 , and the second layer 12 may include Al having a metal valence of 3 2 O 3 . In addition, any of the following combinations may be used.

[0080] [Table 2]

[0081]

[0082] As shown in the above combination, the first metal oxide material and the second metal oxide material may be selected from metal oxide materials having a metal valence difference of 1. However, one or more embodiments are not limited thereto, and other combinations having a metal valence difference of 2 or more may be selected.

[0083] Even when the metal valence difference between the first metal oxide material and the second metal oxide material is constant, oxygen vacancies may be sufficiently formed as the density difference between the first metal oxide material and the second metal oxide material increases. Since an oxide having a low density has a larger space between atoms than an oxide having a high density, oxygen ions (O 2- ) can be diffused toward the oxide with a low density. In this regard, the first metal oxide material and the second metal oxide material can be selected so that the difference between the density of the first layer 11 and the second layer 12 is, for example, 1 g / cm 3 or greater. Among the combinations in Table 1 above, Al 2 O 3 / HfO 2 The combination of has the largest density difference between the two metal oxide materials, and thus oxygen vacancies may be sufficiently formed. However, one or more embodiments are not limited to the above combination.

[0084] Figure 3 is a cross-sectional view of a variable resistance memory device 101 according to another embodiment. Figure 4 For illustration Figure 3 A conceptual diagram of a principle of variable resistance in a variable resistance layer included in a variable resistance memory device.

[0085] The variable resistance layer 131 of the variable resistance memory device 101 includes a first layer 11 , a second layer 12 , and a third layer 13 , and the first and second conductive elements E1 and E2 may be arranged in contact with opposite ends on the third layer 13 .

[0086] The variable resistance layer 131 has a structure in which two or more metal oxide materials having different metal valences are stacked, and two adjacent layers from among the first to third layers 11, 12, and 13 may have metal oxide materials having different metal valences from each other. That is, the first metal oxide material in the first layer 11 and the second metal oxide material in the second layer 12 may have different metal valences, and the second metal oxide material in the second layer 12 and the third metal oxide material in the third layer 13 may have different metal valences. The first metal oxide material and the third metal oxide material may be the same as or different from each other.

[0087] The difference between the metal valence of the first metal oxide material in the first layer 11 and the second metal oxide material in the second layer 12 may be 1 or more. The difference between the metal valence of the second metal oxide material in the second layer 12 and the third metal oxide material in the third layer 13 may be 1 or more.

[0088] The second metal oxide material in the second layer 12 as the intermediate layer in the variable resistance layer 131 is not particularly limited, provided that its metal valence is different from the metal valence of the first and third metal oxide materials. For example, the metal valence of the first layer 11, the second layer 12, and the third layer 13 may be in the order of gradually increasing or gradually decreasing, or the metal valence of the second metal oxide material in the second layer 12 may be the largest or the smallest.

[0089] Each of the first to third metal oxide materials may be selected so that oxygen vacancies can be sufficiently generated, which are generated at the interfaces between the first to third layers 11, 12, and 13 due to the metal valence difference. The first layer 11 and the third layer 13 may include the first metal oxide material, and the second layer 12 may include the second metal oxide material. For example, a combination of the first and second metal oxide materials shown in Table 2 above may be selected. Furthermore, a 1 g / cm 3 As the first and second metal oxide materials, metal oxide materials having a density difference of 1 g / cm or more may be selected, or metal oxide materials having a density difference of 1 g / cm or more may be selected from a combination of metals having different valences. 3 or greater density difference as the first and second metal oxide materials. For example, the first layer 11 and the third layer 13 may include HfO 2 The second layer 12 may include Al 2 O 3 .

[0090] The first to third layers 11, 12, and 13 may each have a thickness of 10 nm or less. The second layer 12 may have the smallest thickness, for example, a thickness of 2 nm or less.

[0091] In the embodiment, the variable resistance layer 131 is configured to have a three-layer structure in which metal oxide materials having different metal valences are adjacent to each other, and thus, an interface in which oxygen vacancies caused by a difference in metal valence are generated can be increased. Figure 4 As shown in FIG. 1 , when oxygen vacancies V are formed in the variable resistance layer 131 due to the application of voltage, o and interstitial oxygen ions O 2- When the oxygen vacancies V are sufficiently formed, atomic substitution may occur at the interface between the two metal oxide materials having different metal valences, that is, at the interface between the first and second layers 11 and 12 and at the interface between the second and third layers 12 and 13.o and can be easily generated by oxygen vacancies V o For example, the conductive filaments Figure 1 The structure shown in more fully forms the conductive filaments.

[0092] Figure 5 is a cross-sectional view of a variable resistance memory device 102 according to another embodiment.

[0093] In the variable resistance memory device 102 according to the embodiment, the variable resistance layer 132 includes a first layer 11 , a second layer 12 , a third layer 13 , and a fourth layer 14 .

[0094] Two or more metal oxide materials from among the first metal oxide material, the second metal oxide material, the third metal oxide material and the fourth metal oxide material respectively included in the first to fourth layers 11, 12, 13 and 14 may have metal valences different from each other. Moreover, adjacent layers may have metal oxide materials having metal valences different from each other. That is, the first metal oxide material and the second metal oxide material have different metal valences, the second metal oxide material and the third metal oxide material have different metal valences, and the third metal oxide material and the fourth metal oxide material have different metal valences. The first metal oxide material may be the same as the third metal oxide material. The second metal oxide material may be the same as the fourth metal oxide material. For example, the first and third layers 11 and 13 may include the first metal oxide material, and the second and fourth layers 12 and 14 may include the second metal oxide material. A combination of the first and second metal oxide materials as shown in Table 2 above may be selected. Moreover, a layer having a relative humidity of 1 g / cm 3 As the first and second metal oxide materials, metal oxide materials having a density difference of 1 g / cm or more may be selected, or metal oxide materials having a density difference of 1 g / cm or more may be selected from a combination of metals having different valences. 3 or more metal oxide materials having a density difference as the first and second metal oxide materials. However, one or more embodiments are not limited to the above examples.

[0095] The metal oxide material included in the first to fourth layers 11, 12, 13 and 14 of the variable resistance layer 132 is not particularly limited, provided that the metal oxide materials in adjacent layers have metal valences different from each other. For example, the metal valences of the first to fourth layers 11, 12, 13 and 14 may be in a gradually increasing or gradually decreasing order, or the second layer 12 or the third layer 13 may include a metal oxide material having the largest or smallest metal valence.

[0096] The first to fourth metal oxide materials may be disposed so that the difference between the metal valences of adjacent layers is 1 or more and so that oxygen vacancies generated due to the difference between the metal valences at the interface may be sufficiently generated.

[0097] A plurality of oxides each having a band gap energy of 2 eV or more may be included in each of the first to fourth layers 11, 12, 13, and 14, and as described above, may be selected so that the difference between metal valences at the interface between adjacent layers is as large as possible.

[0098] Due to the provision of the metal oxide material, the difference between the valences of the metals at the interface between the plurality of layers can be as large as possible, and oxygen vacancies caused by substitution between atoms can be easily formed.

[0099] The variable resistance layer 132 may have a structure in which an interface between metal oxide materials having different metal valences is further added (increased). In addition, since interfaces in which conductive filaments are formed by oxygen vacancies increase, the variable resistance range may also be increased.

[0100] Figure 6 and 7 is a cross-sectional view of a sample manufactured for testing variable resistance performance for a configuration in which variable resistance metal oxide materials having different metal valences are adjacently stacked.

[0101] like Figure 6 As shown in FIG. , a SiO 2 , N-type Si layer with a thickness of 400nm, SiO with a thickness of 10nm 2 A layer and an N-type Si layer having a thickness of 50 nm are sequentially stacked on a Si wafer, and then a patterning process (process) and an etching process are performed to form a N-Si (50 nm) / SiO 2 (10nm) / N-Si (400nm) cylindrical device. 2 The HfO layer is deposited to 10 nm on the side surface of the cylindrical device, and then when a voltage is applied between an upper electrode such as N-Si and a lower electrode such as N-Si, a current flows along the HfO 2 / SiO 2 The layers flow from the upper electrode to the lower electrode. Here, Ti (10 nm) / Pt (40 nm) is deposited on the upper electrode such as N-Si to improve the contact resistance between the upper electrode such as N-Si and the probe station terminal.

[0102] Figure 7 The following structure is shown: Figure 6 The structure of HfO 2layer is formed to a thickness of 2 nm, and furthermore, in the HfO 2 Al is deposited on the layer 2 O 3 to 2nm and deposit HfO 2 When a voltage is applied between an upper electrode such as N-Si and a lower electrode such as N-Si, a current flows along the SiO 2 / HfO 2 / Al 2 O 3 / HfO 2 The layers flow from the upper electrode to the lower electrode.

[0103] Figure 6 and 7 The structure is provided for simulating the variable resistance performance of a multilayer structure in which metal oxide materials having different metal valences are adjacent to each other.

[0104] In the above two structures, the set voltage V by which the high resistance state is changed to the low resistance state is measured. 设定 , and in 35 Figure 6 The average set voltage V 设定 is 12.36V, and has 56 Figure 7 The average set voltage V 设定 is 6.85V.

[0105] When compared with the set voltage V which is generally 15 V or more in the variable resistance device using the charge trapping layer according to the prior art, 设定 When comparing, the measured set voltage V 设定 In addition, it is recognized that in the case of two layers comprising metal oxide materials having different metal valences arranged adjacent to each other, Figure 7 The structure has the effect of reducing the set voltage.

[0106] In the above embodiments, the variable resistance layers 130 , 131 , and 132 have double, triple, and quadruple structures, but one or more embodiments are not limited thereto, that is, a structure including five or more layers to which interfaces having different metal valences are added may be used.

[0107] Figure 8 is a cross-sectional view of a variable resistance memory device 200 according to another embodiment, and Fig. 9 for Figure 8 1 is an equivalent circuit diagram of a variable resistance memory device 200 . Fig.10 For illustration Figure 8 A conceptual diagram of an example operation of a variable resistance memory device 200 is shown.

[0108] Reference Figure 8 , the variable resistance memory device 200 includes an insulating layer 210, a variable resistance layer 230 on the insulating layer 210, a channel layer 240 on the variable resistance layer 230, a gate insulating layer 250 on the channel layer 240, and a plurality of gate electrodes 260 on the gate insulating layer 250. Spaces between the plurality of gate electrodes 260 may be filled with an insulating layer 270. However, one or more embodiments are not limited thereto, that is, the insulating layer 270 may be omitted.

[0109] The variable resistance layer 230 includes a first layer 11 and a second layer 12, the first layer 11 includes a first metal oxide material, and the second layer 12 includes a second metal oxide material having a metal valence different from that of the first metal oxide material. The second layer 12 may have a metal valence greater than that of the first layer 11. The metal oxide material in the variable resistance layer 230 and the characteristics of the variable resistance layer 230 are the same as those described above with reference to Figure 1 The description about the variable resistance layer 130 is basically the same. When metal oxide materials having different metal valences are combined, substitution between atoms occurs and oxygen vacancies are generated. Therefore, oxygen vacancies V are actively (positively) generated at the interface between the first layer 11 and the second layer 12. o , and therefore, conductive filaments can be easily formed.

[0110] Although it is shown that the second layer 12 having a larger metal valence is on the first layer 11 having a smaller metal valence in the variable resistance layer 230, one or more embodiments are not limited thereto, that is, the stacking order of the first layer 11 and the second layer 12 may be changed. That is, the first layer 11 having a smaller metal valence may be formed on the second layer 12 having a larger metal valence, and the first layer 11 may contact the channel layer 240.

[0111] The channel layer 240 may include a semiconductor material. The channel layer 240 may include, for example, polysilicon. A source electrode S and a drain electrode D may be connected to opposite ends of the channel layer 240.

[0112] The gate insulating layer 250 may include various insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0113] A voltage for turning on / off the channel layer 240 may be selectively applied to each of the plurality of gate electrodes 260 .

[0114] The variable resistance memory device 200 has a structure including an array of a plurality of memory cells MC, and each of the memory cells MC may have a structure in which a transistor and a variable resistor are connected as shown in FIG. Fig. 9The corresponding variable resistance can be set by the voltage applied to each gate electrode and the voltage between the source electrode S and the drain electrode D, and can have a value corresponding to information 1 or 0.

[0115] The following will refer to Fig.10 The operation of the variable resistance memory device 200 is described.

[0116] When a memory cell to be recorded is selected, the gate voltage value of the corresponding memory cell is adjusted so that no channel is formed, that is, the channel is turned off, and the gate voltage value of the unselected memory cell is adjusted so that the channel in the unselected memory cell is turned on.

[0117] Fig.10 The following example is shown: a gate voltage is applied to the gate electrode 260 in each memory cell so that the memory cell MC2 at the center is turned off (OFF), and the two memory cells MC1 and MC3 at the opposite sides of the memory cell MC2 are turned on (ON). When a voltage is applied between the source electrode S and the drain electrode D, a conductive path indicated by an arrow A is formed. By applying a set voltage V 设定 or reset voltage V 复位 A voltage of a value can record the desired information 1 or 0 on the selected memory cell MC2.

[0118] In the read operation, the reading of the selected memory cell can be performed similarly to the above. That is, the gate voltage applied to each of the gate electrodes 260 is adjusted so that the channel of the selected memory cell MC2 is turned off and the channels of the unselected memory cells MC1 and MC3 are turned on, and after that, the voltage V applied between the source electrode S and the drain electrode D is measured. 读取 The current flowing in the corresponding memory cell MC2 identifies the memory cell state (1 or 0).

[0119] Fig.11 is a cross-sectional view of a variable resistance memory device 201 according to another embodiment.

[0120] The variable resistance memory device 201 of the embodiment Figure 8 The variable resistance memory device 200 shown in FIG. 1 is different in that the variable resistance layer 231 includes a first layer 11, a second layer 12, and a third layer 13, and the other components of the variable resistance memory device 201 are the same as those of FIG. Figure 8 The variable resistance memory device 200 shown in FIG. 1 is substantially the same as those in FIG.

[0121] The variable resistance layer 231 includes first to third layers 11, 12, and 13. The second layer 12 at the center of the variable resistance layer 231 may include a metal oxide material having a higher metal valence than the metal oxide materials of the first and third layers 11 and 13. Alternatively, the second layer 12 may include a metal oxide material having a lower metal valence than the metal oxide materials of the first and third layers 11 and 13. The first layer 11 and the third layer 13 may include the same metal oxide material. However, one or more embodiments are not limited thereto, that is, the first layer 11 and the third layer 13 may include metal oxide materials different from each other.

[0122] The variable resistance layer 231 of the variable resistance memory device 201 according to the embodiment is provided with the metal oxide material included in the first layer 11, the second layer 12 and the third layer 13, so that a plurality of interfaces between the metal oxide materials having different metal valences are generated, and the metal valence difference at each interface can be as large as possible, such as in Figure 3 The first to third metal oxide materials may be selected so that the metal valence of the second metal oxide material in the second layer 12 at the center of the variable resistance layer 231 may be the smallest or the largest. Therefore, substitution between atoms may be actively generated, and then, oxygen vacancies may be easily generated and conductive filaments may be easily formed. The variable resistance memory device 201 according to the embodiment may have a low set voltage, for example, Figure 8 The set voltage of the variable resistance memory device 200 is smaller than the set voltage.

[0123] Fig.12 is a cross-sectional view of a variable resistance memory device 202 according to another embodiment.

[0124] The variable resistance memory device 202 of the embodiment has Fig.11 The structure of the variable resistance memory device 201 is substantially the same as that of the variable resistance layer 232 , except that the variable resistance layer 232 has a four-layer structure including a first layer 11 , a second layer 12 , a third layer 13 , and a fourth layer 14 .

[0125] Two or more metal oxide materials from among the first metal oxide material, the second metal oxide material, the third metal oxide material and the fourth metal oxide material respectively included in the first to fourth layers 11, 12, 13 and 14 may have metal valences different from each other. Moreover, adjacent layers may have metal oxide materials having metal valences different from each other. That is, the first metal oxide material and the second metal oxide material have different metal valences, the second metal oxide material and the third metal oxide material have different metal valences, and the third metal oxide material and the fourth metal oxide material have different metal valences. The first metal oxide material may be the same as the third metal oxide material. The second metal oxide material may be the same as the fourth metal oxide material.

[0126] The variable resistance layer 232 of the variable resistance memory device 202 according to the embodiment is provided with the metal oxide material included in the first layer 11, the second layer 12, the third layer 13 and the fourth layer 14, so that a plurality of interfaces between the metal oxide materials having different metal valences are generated and the metal valence difference at each interface can be as large as possible, such as in Figure 5 The same is true for the variable resistance layer 132 .

[0127] Due to the provision of the metal oxide material, the difference between the valences of the metals at the interface between the plurality of layers can be as large as possible, and oxygen vacancies caused by substitution between atoms can be sufficiently formed.

[0128] The variable resistance layer 232 may have a structure in which an interface between metal oxide materials having different metal valences is further added. In addition, since the interface in which the conductive filaments are formed by oxygen vacancies increases, the variable resistance range may also be increased.

[0129] Fig.13 is a cross-sectional view of a variable resistance memory device 500 according to another embodiment, and Fig.14 for Fig.13 FIG. 5 is a perspective view of a memory string included in a variable resistance memory device 500 . Fig.15 for Fig.13 1 is an equivalent circuit diagram of a variable resistance memory device 500 .

[0130] The variable resistance memory device 500 according to the embodiment includes a vertical NAND (VNAND) memory in which a plurality of memory cells MC each including a variable resistance metal oxide material are arranged in a vertical direction.

[0131] Reference Figures 13 to 15 , the specific structure of the variable resistance memory device 500 will be described below.

[0132] Reference Fig.13 , a plurality of cell strings CS are formed on a substrate 520 .

[0133] The substrate 520 may include a silicon material doped with a first type impurity. For example, the substrate 520 may include a silicon material doped with a p-type impurity. For example, the substrate 520 may include a p-type well (e.g., a pocket-shaped p-type well). Hereinafter, it will be assumed that the substrate 520 includes p-type silicon. However, the substrate 520 is not limited to p-type silicon.

[0134] The doping region 525 is disposed in the substrate 520. For example, the doping region 525 may be a second doping type different from the doping type of the substrate 520. For example, the doping region 525 may be an n-type. Hereinafter, it will be assumed that the doping region 525 is an n-type. However, the doping region 525 is not limited to the n-type. The doping region 525 may be a common source line CSL.

[0135] There may be k×n cell strings CS, which are as follows Fig.15 The cell strings CSij are arranged in a matrix as shown in the circuit diagram of , and may each be named CSij (1≤i≤k, 1≤j≤n) according to its position in each row and column. The cell strings CSij are each connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL.

[0136] Each of the cell strings CSij includes a memory cell MC and a string selection transistor SST. The memory cell MC and the string selection transistor SST in each of the cell strings CSij may be stacked in a height direction.

[0137] Multiple rows of cell strings CSij are respectively connected to different string selection lines SSL1 to SSLk. For example, string selection transistors SST in cell strings CS11 to CS1n are commonly connected to string selection line SSL1. String selection transistors SST in cell strings CSk1 to CSkn are commonly connected to string selection line SSLk.

[0138] Multiple columns of cell strings CS are respectively connected to different bit lines BL1 to BLn. For example, memory cells MC and string selection transistors SST in cell strings CS11 to CSk1 may be commonly connected to bit line BL1, and memory cells MC and string selection transistors SST in cell strings CS1n to CSkn may be commonly connected to bit line BLn.

[0139] For example, string selection transistors SST in cell strings CS11 to CS1n may be commonly connected to a common source line CSL1, and string selection transistors SST of cell strings CSk1 to CSkn may be commonly connected to a common source line CSLk.

[0140] Memory cells MC (or string selection transistors SST) at the same height from the substrate 520 are commonly connected to one word line WL, and memory cells MC (or string selection transistors SST) at different heights from the substrate 520 may be respectively connected to different word lines WL1 to WLn.

[0141] Fig.15 The circuit structure shown in is an example. For example, the number of rows of cell strings CS may increase or decrease. As the number of rows of cell strings CS changes, the number of string selection lines connected to the rows of cell strings CS and the number of cell strings CS connected to one bit line may also change. As the number of rows of cell strings CS changes, the number of common source lines connected to the rows of cell strings CS may also change.

[0142] The number of columns of cell strings CS may increase or decrease. As the number of columns of cell strings CS changes, the number of bit lines connected to the columns of cell strings CS and the number of cell strings CS connected to one string selection line may also change.

[0143] The height of the cell string CS may increase or decrease. For example, the number of memory cells MC stacked in each of the cell strings CS may increase or decrease. As the number of memory cells MC stacked in each of the cell strings CS changes, the number of word lines WL may also change. For example, the number of string selection transistors provided to each of the cell strings CS may increase. As the number of string selection transistors provided to each of the cell strings CS changes, the number of string selection lines or common source lines may also change. As the number of string selection transistors increases, the string selection transistors may be stacked like memory cells MC.

[0144] For example, write and read operations may be performed in row units of cell strings CS. Cell strings CS may be selected in row units through common source lines CSL and may be selected in row units through string selection lines SSL. Moreover, a voltage may be applied to the common source lines CSL in units of at least two common source lines CSL. A voltage may be applied to the common source lines CSL in units of all common source lines CSL.

[0145] In the selected row of the cell string CS, write and read operations may be performed in units of pages. A page may represent a row of memory cells MC connected to one word line WL. In the selected row of the cell string CS, memory cells MC may be selected in units of pages through the word lines WL.

[0146] The cell string CS may include a cylindrical pillar PL and a plurality of gates 560 and a plurality of insulators 570 surrounding the cylindrical pillar PL in a ring shape, such as Fig.13 That is, the plurality of gates 560 and the plurality of insulators 570 may be alternately stacked with each other along the vertical direction (Z direction).

[0147] The gates 560 may each include a metal material or a silicon material doped at a high concentration. The gates 560 are each connected to one of a word line WL and a string selection line SSL.

[0148] Insulators 570 may each include one or more of a variety of insulating materials such as silicon oxide, silicon nitride, and the like.

[0149] The pillar PL may include a plurality of layers. The outermost layer of the pillar PL may include a gate insulating layer 550. For example, the gate insulating layer 550 may include a plurality of insulating materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, etc. The gate insulating layer 550 may be conformally deposited on the pillar PL.

[0150] The channel layer 540 may be conformally deposited on the inner surface of the gate insulating layer 550. The channel layer 540 may include a semiconductor material doped with a first type of impurity. The channel layer 540 may include a silicon material doped with the same type of impurity as in the substrate 520. For example, when the substrate 520 includes a silicon material doped with p-type impurities, the channel layer 540 may also include a silicon material doped with p-type impurities. Alternatively, the channel layer 540 may include a material such as Ge, IGZO, GaAs, etc.

[0151] The variable resistance layer 530 may be disposed along an inner surface of the channel layer 540. The variable resistance layer 530 may be disposed in contact with the channel layer 540, and may be conformally deposited on the channel layer 540.

[0152] The variable resistance layer 530 changes to a high resistance state or a low resistance state according to a voltage applied thereto, and may include a first layer 11 , a second layer 12 , and a third layer 13 including metal oxide materials having different metal valences from each other.

[0153] The first layer 11, the second layer 12, and the third layer 13 of the variable resistance layer 530 may each include a metal oxide material of at least one atom selected from the group consisting of Zr, Hf, Al, Ni, Cu, Mo, Ta, Ti, W, Cr, Sr, La, Mn, Ca, Pr, and Si. The first to third layers 11, 12, and 13 may each include a metal oxide material having a band gap energy of 2 eV or more, such as one of the following: Rb 2 O、TiO 2 、BaO、ZrO 2 , CaO, HfO 2 、SrO、Sc 2 O 3 、MgO、Li 2 O、Al 2 O 3 、SiO 2 , and BeO.

[0154] The variable resistance layer 530 has a structure in which two or more metal oxide materials having different metal valences are stacked, and two adjacent layers from among the first to third layers 11, 12, and 13 may have metal oxide materials having different metal valences from each other. Figure 3 The variable resistance layer 131 and Fig.11 As described above, the variable resistance layer 231 of the embodiment of the present invention can be configured with a first metal oxide material in the first layer 11, a second metal oxide material in the second layer 12, and a third metal oxide material in the third layer 13, so that oxygen vacancies are sufficiently generated due to substitution between atoms at each interface. Therefore, the variable resistance memory device 500 can have the characteristics of low set voltage and low reset voltage.

[0155] Although the variable resistance layer 530 has a three-layer structure as an example, one or more embodiments are not limited thereto, that is, the variable resistance layer 530 may include two or more layers in which layers having different metal valences are arranged adjacent to each other. For example, in some embodiments, the variable resistance layer 530 may have a double-layer structure having only the first layer 11 and the second layer 12. Alternatively, in other embodiments, the variable resistance layer 530 may have four or more layers, for example, further including a fourth layer 14 surrounding the third layer 13.

[0156] The channel layer 540 and the variable resistance layer 530 may be in contact with the doped region 525 , ie, a common source region.

[0157] The drain 580 may be disposed on the pillar PL. The drain 580 may include a silicon material doped to the second type. For example, the drain 580 may include a silicon material doped to an n-type.

[0158] A bit line 590 may be disposed on the drain 580. The drain 580 and the bit line 590 may be connected to each other via a contact plug.

[0159] Each of the gate 560 and the regions in the gate insulating layer 550, the channel layer 540, and the variable resistance layer 530 (the regions facing each gate 560 in the horizontal direction (X direction)) is configured as a memory cell MC. That is, the memory cell MC has a circuit structure in which a transistor including the gate 560, the gate insulating layer 550, and the channel layer 540 is connected in parallel with a variable resistor provided by the variable resistance layer 530.

[0160] The above parallel connection structures are continuously arranged in the vertical direction (Z direction) to form a cell string CS. In addition, opposite ends of the cell string CS may be connected to a common source line CSL and a bit line BL, such as Fig.15When voltage is applied to the common source line CSL and the bit line BL, programming, reading and erasing operations can be performed on a plurality of memory cells MC.

[0161] For example, when a memory cell MC to be recorded is selected, the gate voltage value of the corresponding memory cell is adjusted so that no channel is formed, that is, the channel is turned off, and the gate voltage value of the unselected memory cell is adjusted so that the channel in the unselected memory cell is turned on. Therefore, the current path formed by the voltage applied to the common source line CSL and the bit line BL passes through the region of the variable resistance layer 530 in the selected memory cell MC. At this time, the applied voltage can be changed to have a set voltage V 设定 or reset voltage V 复位 A low resistance state or a high resistance state is obtained by changing the value, and desired information 1 or 0 can be recorded on the selected memory cell MC.

[0162] In the read operation, the reading of the selected memory cell can be performed similarly to the above. That is, the gate voltage applied to each of the gates 560 is adjusted so that the channel of the selected memory cell MC is turned off and the channel of the unselected memory cell MC is turned on, and after that, the voltage V applied between the common source line CSL and the bit line BL is measured. 读取 The current flowing in the corresponding memory cell MC identifies the memory cell state (1 or 0).

[0163] As described above, the variable resistance memory device 500 according to the embodiment configures the memory cell MC to include the variable resistance layer 530 in which the conductive filament can be easily formed due to the oxygen vacancies, and forms the memory device by arranging the memory cell MC. Therefore, compared with a memory device based on, for example, a phase change material or charge trapping, the variable resistance layer 530 can be relatively thin, and the variable resistance memory device 500 can have a low operating voltage. The variable resistance memory device 500 can increase density and can achieve low power consumption, thereby solving the scaling problem between memory cells in the next generation VNAND.

[0164] The variable resistance memory device 500 according to the present disclosure may be implemented in a memory system and / or as a chip-type memory block, which is to be used as a neuromorphic computing platform or for building a neural network.

[0165] Fig.16 is a block diagram of a storage system according to an embodiment.

[0166] Reference Fig.16, the storage system 1600 may include a storage controller 1601 and a storage device (non-volatile storage device) 1602. The storage controller 1601 performs a control operation on the storage device 1602. For example, the storage controller 1601 provides an address ADD and a command CMD to the storage device 1602 to perform a programming (or writing), reading and / or erasing operation on the storage device 1602. In addition, data for a programming operation and read data may be transmitted between the storage controller 1601 and the storage device 1602.

[0167] The memory device 1602 may include a memory cell array 1610 and a voltage generator 1620. The memory cell array 1610 may include a plurality of memory cells arranged on a region where a plurality of word lines and a plurality of bit lines intersect each other. The memory cell array 1610 includes a memory cell array 1610 based on the present application. Figure 1-5 The non-volatile memory cell of the embodiments in and 8-15.

[0168] The storage controller 1601 may include processing circuitry such as hardware including logic circuitry; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The storage controller 1601 may operate in response to a request from a host (not shown) and may be configured to access the storage device 1602 and control the operations discussed above (e.g., for Fig.10 1601), thereby converting the memory controller 1601 into a dedicated controller. The memory controller 1601 may generate an address ADD and a command CMD for performing a program / read / erase operation on the memory cell array 1610. Moreover, in response to a command from the memory controller 1601, the voltage generator 1620 (e.g., a power supply circuit) may generate a voltage control signal for controlling at least one voltage level used in the memory device 1602. As an example, the voltage generator 1620 may generate a voltage control signal for controlling a voltage level of a word line to read data from the memory cell array 1610 or program data on the memory cell array 1610.

[0169] In addition, the memory controller 1601 may perform a determination operation on the data read from the memory device 1602. For example, by determining the data read from the memory cell, the number of on cells and / or off cells from among the memory cells may be determined. The memory device 1602 may provide a pass / fail signal P / F to the memory controller 1601 according to the read result of the read data. The memory controller 1601 may refer to the pass / fail signal P / F and thus control the write and read operations of the memory cell array 1610.

[0170] Fig.17 A diagram illustrating a neuromorphic device and external devices connected thereto according to an embodiment.

[0171] Reference Fig.17 , the neuromorphic device 1700 may include a processing circuit 1710 and / or a memory (e.g., an on-chip memory) 1720. The neuromorphic device 1700 may include a processing circuit 1710 and / or a memory (e.g., an on-chip memory) 1720 based on the present application. Figure 1-5 and a memory device of embodiments 8-15.

[0172] In some example embodiments, the processing circuit 1710 may be configured to control functions for driving the neuromorphic device 1700. For example, the processing circuit 1710 may be configured to control the neuromorphic device 1700 by executing a program stored in the memory 1720 of the neuromorphic device 1700. In some example embodiments, the processing circuit may include hardware such as a logic circuit; a hardware / software combination such as a processor that executes software; or a combination thereof. For example, the processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1700, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. In some example embodiments, the processing circuit 1710 may be configured to read / write various data from / in the external device 1730, and / or manipulate the neuromorphic device 1700 by using the read / written data. In some embodiments, external device 1730 may include external memory and / or a sensor array having an image sensor (eg, a CMOS image sensor circuit).

[0173] In some embodiments, Fig.17The neuromorphic device in the invention can be applied to a machine learning system. The machine learning system can utilize various artificial neural network organizations and processing models such as convolutional neural networks (CNNs), deconvolutional neural networks, recurrent neural networks (RNNs) optionally including long short-term memory (LSTM) units and / or gated recurrent units (GRUs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0174] Alternatively or additionally, such a machine learning system may include other forms of machine learning models such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems; and / or combinations thereof, including ensembles such as random forests. Such machine learning models may also be used to provide a variety of services and / or applications such as image classification services, user authentication services based on biometric information or biometric data, advanced driver assistance system (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, etc., which may be executed, implemented or processed by electronic devices.

[0175] Although the variable resistance memory device has been specifically shown and described with reference to its example embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the appended claims. In the specification, many details are described in detail, but they are not provided to limit the scope of the present disclosure, but should be interpreted as illustrating the embodiments. Therefore, the scope of the present disclosure should be determined by the technical concepts set forth in the claims, rather than by the embodiments.

[0176] The variable resistance memory device can change resistance at a low applied voltage.

[0177] The variable resistance memory device can exhibit a large variable resistance range.

[0178] The variable resistance memory device can easily achieve low power consumption and high integration density.

[0179] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should typically be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A variable resistance memory device, comprising: A variable resistance layer including a first layer, a second layer and a third layer, the second layer is on the first layer, The first layer includes a first metal oxide material, The second layer includes a second metal oxide material having a metal valence different from that of the first metal oxide material, the third layer is on the second layer, the third layer comprising a third metal oxide material having a metal valence different from a metal valence of the second metal oxide material, wherein the first layer, the second layer, and the third layer each have a thickness of 10 nm or less; as well as A first conductive element and a second conductive element are on the variable resistance layer and are separated from each other so that a current path is formed in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

2. A variable resistance memory device, comprising: A support layer comprising an insulating material; a variable resistance layer on the support layer, the variable resistance layer comprising a first layer, a second layer and a third layer, The second layer is on the first layer, the first layer includes a first metal oxide material, the second layer includes a second metal oxide material having a metal valence different from that of the first metal oxide material, the third layer is on the second layer, the third layer includes a third metal oxide material having a metal valence different from that of the second metal oxide material, and the first layer, the second layer, and the third layer each have a thickness of 10 nm or less; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; as well as A plurality of gate electrodes are provided on the gate insulating layer, the plurality of gate electrodes being separated from each other and configured to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.

3. A variable resistance memory device, comprising: a variable resistance layer including a plurality of layers sequentially stacked on each other, The plurality of layers include a first layer, a second layer, and a third layer, the first layer and the second layer contacting each other and having metal oxide materials having metal valences different from each other, an interface between the first layer and the second layer including a plurality of oxygen vacancies, the third layer being on the second layer, the third layer including a third metal oxide material having a metal valence different from that of the metal oxide material of the second layer, the first layer, the second layer, and the third layer each having a thickness of 10 nm or less; a first conductive element connected to a first region of the variable resistance layer; as well as A second conductive element connected to a second region of the variable resistance layer, the second conductive element being spaced apart from the first conductive element, so that a current path is formed in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked. 4 . The variable resistance memory device according to claim 1 , wherein a difference between a metal valence of the first metal oxide material and a metal valence of the second metal oxide material is 1 or more.

5. The variable resistance memory device of claim 4, wherein a difference between a density of the first metal oxide material and a density of the second metal oxide material is 1 g / cm 3 or larger. 6 . The variable resistance memory device according to claim 1 , wherein the first layer and the third layer include the same metal oxide material.

7. The variable resistance memory device according to any one of claims 1 to 3, wherein The variable resistance layer further includes a fourth layer on the third layer, and The fourth layer includes a fourth metal oxide material having a metal valence different from a metal valence of the third metal oxide material. 8 . The variable resistance memory device of claim 7 , wherein the first metal oxide material is the same as the third metal oxide material. 9 . The variable resistance memory device of claim 7 , wherein the second metal oxide material is the same as the fourth metal oxide material. 10 . The variable resistance memory device of claim 1 , wherein the first metal oxide material and the second metal oxide material include a metal oxide material having a band gap energy of 2 eV or more.

11. The variable resistance memory device of claim 1 , wherein the first metal oxide material and the second metal oxide material each independently include one of Rb2O, TiO2, BaO, ZrO2, CaO, HfO2, SrO, Sc2O3, MgO, Li2O, Al2O3, SiO2, BeO, Nb2O5, NiO, Ta2O5, WO3, V2O5, La2O3, Gd2O3, CuO, MoO3, Cr2O3 and MnO2.

12. The variable resistance memory device according to any one of claims 1 to 3, wherein the first layer comprises HfO2, and the second layer comprises Al2O3.

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