Low-delay, low-power and high-linearity class-d modulation loop

Abstract

Low latency, low power, and high linearity class-D modulation loop. Systems and methods include a circuit having a plurality of integrator circuits arranged in series and configured to receive an input signal at a first one of the plurality of integrators and generate an output signal at a last one of the plurality of integrators, a filter arranged to receive a feedback signal including the output signal and generate a filtered feedback signal that is applied to the input signal prior to input to the first one of the plurality of integrators, and a feedback signal path configured to receive the feedback signal and apply the feedback signal to an input of a second one of the plurality of integrators. The circuit can include a class-D amplifier and / or a delta-sigma modulator. The input signal can include an analog audio signal that is for driving an amplifier of an audio speaker.

Description

Technical Field

[0001] According to one or more embodiments, this disclosure generally relates to amplifiers, and more particularly, for example, to Class D audio amplifiers with improved loop response. Background Technology

[0002] Many modern devices, such as laptops, tablets, MP3 players, and smartphones, utilize internal audio amplifiers to provide speaker and headset connectivity. Class D amplifiers are commonly used to drive these speakers and headsets. Class D amplifiers offer higher efficiency than Class AB amplifiers and meet performance criteria for mobile devices with requirements including low power consumption, linearity, and latency. Due to the miniaturization and increased performance demands of modern devices, there is a continuous need to reduce power consumption, decrease latency, and improve the linearity of audio amplifiers. Summary of the Invention

[0003] This disclosure provides systems and methods for addressing the need in the art for improved performance of audio amplifiers used in modern devices. In a Class D amplifier with multiple integrators in series, it is observed that the first integrator controls noise and distortion in the output signal because it has the highest overall gain among all integrators. Therefore, the first integrator is selected for good linearity and low noise, and typically determines the overall quiescent current of the amplifier. By selectively pre-filtering the feedback signal at the first integrator (e.g., only the first integrator), this disclosure helps to significantly reduce the loop response of the Class D amplifier. The resulting amplifier is characterized by low delay and high linearity without requiring a high-power analog operational amplifier.

[0004] The scope of this disclosure is defined by the claims, which are incorporated herein by reference. A more complete understanding of this disclosure, and the implementation of its additional advantages, will be provided to those skilled in the art by considering the following detailed description of one or more embodiments. Additional pages of the accompanying drawings, which will first be briefly described, will be referenced. Attached Figure Description

[0005] A better understanding of the aspects and advantages of this disclosure can be achieved by referring to the following accompanying drawings and the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the drawings, wherein the illustrations in the drawings are for the purpose of illustrating embodiments of the disclosure and not for the purpose of limiting embodiments of the disclosure. The components in the drawings are not necessarily to scale, but the emphasis is on clearly illustrating the principles of the disclosure.

[0006] Figure 1 The diagram illustrates a typical Class D architecture.

[0007] Figure 2 An example Class D amplifier circuit with filtered feedback according to an embodiment of the present disclosure is illustrated.

[0008] Figure 3 The illustration shows an embodiment of the present disclosure for use. Figure 2 The flowchart shows the method of using the feedback of the filter to operate the Class D amplifier circuit.

[0009] Figure 4 An example Δ-Σ modulator circuit with filtered feedback according to an embodiment of the present disclosure is illustrated.

[0010] Figure 5 An example Class D amplifier circuit with multiple filtered feedback signals is illustrated according to an embodiment of the present disclosure.

[0011] Figure 6 An example audio output stage using a Class D amplifier circuit according to an embodiment of the present disclosure is illustrated. Detailed Implementation

[0012] This disclosure provides systems and methods for addressing the need in the art for improved performance of audio amplifiers used in modern devices. In Class D amplifiers, the selection of the first-stage integrator is observed to effectively control amplifier noise and distortion because the first integrator has the highest overall gain among integrators and typically determines the amplifier's overall quiescent current. Therefore, the selection of a first integrator with good linearity and low noise will improve amplifier performance. By selectively pre-filtering the feedback signal only at the first integrator, some embodiments of this disclosure help to significantly reduce the requirements for implementing a Class D amplifier with a fast loop response. Low delay and high linearity are achieved in this disclosure without requiring a high-power analog operational amplifier.

[0013] In one embodiment, the audio amplifier circuit includes two or more stages configured to receive an audio input signal and provide an amplified audio signal to a speaker. The audio amplifier circuit reduces the power consumption of a Class D amplifier and reduces delay and distortion at the Class D output. The speaker can be implemented within a headset or other type of portable audio device. It will be understood that the circuitry and techniques described herein are applicable to various amplifier implementations in which improved performance is desired.

[0014] exist Figure 1The diagram illustrates a conventional Class D amplifier architecture. The Class D amplifier circuit 100 receives an input audio signal 102, such as an audio signal intended for output to a speaker. The input audio signal 102 is fed through multiple integrators 110A, 110B, and 110C, and then through a quantizer 112 to produce an amplified audio output signal 130. To enable operation with fast Class D signals as input, the integrators 110A-C of the Class D amplifier circuit 100 are designed with high bandwidth, resulting in a circuit with relatively high power consumption.

[0015] Adding a filter to the feedback path can relax the bandwidth of a Class D amplifier, thereby reducing overall power consumption. However, adding a filter alters the amplifier's transfer function. To produce a stable loop function with the same good loop gain as before adding the filter, the overall loop response is slowed down so that the added filter does not adversely affect the loop filter response. Therefore, in conventional designs, there are limitations on the amount of filter that can be added. Furthermore, the overall loop filter response needs to be significantly slower to accommodate the added filter.

[0016] It has been observed that the first-stage integrator (e.g., integrator 110A) in a Class D amplifier circuit has the greatest impact on noise and distortion because it has the highest overall gain among all integrators 110A-C. According to one or more embodiments of this disclosure, a Class D amplifier circuit is implemented in which the first integrator is configured for high linearity and low noise. After the first integrator is configured for acceptable performance, it can correct for problems arising from the second integrator (e.g., integrator 110B) and the third integrator (e.g., integrator 110C). In many implementations, the selection of the first integrator determines the overall quiescent current.

[0017] refer to Figure 2An embodiment of a novel Class-D amplifier architecture with selective output filtering will now be described. Class-D amplifier circuit 200 receives an input audio signal 202, such as an audio signal for output to a speaker. The input audio signal 202 is fed through multiple integrators 210A, 210B, and 210C, and then through a quantizer 212 to produce an amplified audio output signal 230. To enable operation with fast Class-D signals as input, the integrators 210A-C of the Class-D amplifier circuit 200 are designed to have high bandwidth, resulting in circuitry with relatively high power consumption. An unfiltered feedback signal 216 is subtracted from the input signals to integrators 210B and 210C by components 220B and 220C (e.g., adders), respectively. Filter 214 receives the feedback signal 216 and generates a filtered feedback signal, which is subtracted from the input audio signal 202 by component 220A (e.g., an adder) for use as input to the first integrator 210A.

[0018] In the illustrated embodiment, a feedback filter is provided only to the input of the first integrator 210A. Subsequent integrator stages 210B and 210C treat the unfiltered Class-D output as input. By way of explanation, the feedback loop comprising three integrators has a near-zero high-frequency output. Therefore, adding some filtering to the loop, as illustrated, does not adversely affect the quality of the output audio signal. Due to the filtered feedback, the first integrator experiences a smoother input and can therefore be designed with relaxed specifications. Because adding filter 214 to the input of the first integrator 210A does not have a significant impact on the main loop, the loop bandwidth and response time can be kept as fast as an unfiltered Class-D amplifier. In the presence of an additional feedback filter, Figure 2 The Class D amplifier 200 can be implemented using a lower loop delay.

[0019] refer to Figure 3 An embodiment of a method for low-latency, low-power, high-linearity Class D modulation will now be described. Process 300 begins in step 310 by receiving an audio input signal at the input of a Class D amplifier circuit having a plurality of integrators arranged in series, the plurality of integrators including a first integrator and a plurality of subsequent integrators. In step 320, an output signal is generated by the last of the plurality of subsequent integrators. In step 330, a feedback signal including the output signal is applied to the input of each of the plurality of subsequent integrators. In step 340, the feedback signal is applied to a filter to generate a filtered feedback signal. In step 350, the filtered feedback signal is applied to the audio input signal for use as the input to the first integrator.

[0020] In various embodiments, the systems, techniques, and methods described herein can be implemented with other circuitry, such as continuous ΔΣ analog-to-digital converters. Figure 4 The figure illustrates an example implementation of a ΔΣ modulator according to the present disclosure. As illustrated, the ΔΣ modulator 400 receives an input signal 402, which is fed to a first integrator 410A and then to a second integrator 410B. The output of the second integrator is input to a comparator 412 that generates the output. The output signal is fed back into the circuit via a 1-bit digital-to-analog converter 413 (DAC). The output of the 1-bit DAC 413 is subtracted from the inputs to the second integrator 410B and the comparator 412 by components 420B and 420C (e.g., adders or subtractors), respectively. The output of the 1-bit DAC is also input to a filter 414, which is configured to generate a filtered feedback signal that is subtracted from the input signal 402 by components 420A (e.g., adders or subtractors) before being input to the first integrator 410A. In other embodiments, a second filter 518 (e.g., ...) is used. Figure 5 (As illustrated in the diagram) can be added to the feedback path toward the input of the second integrator. It will be understood that the filter can be a first-order filter or include other filter orders.

[0021] refer to Figure 6 An audio output stage 600 is illustrated according to an embodiment of this disclosure. A digital signal processor 610 outputs stereo audio signals for playback on a pair of speakers 640A and 640B. Each channel of the stereo audio signal is provided to an audio digital-to-analog converter (620A and 620B), a Class D amplifier (630A and 630B) with filtered feedback (which may include a reference amplifier). Figure 2 and Figure 5 The description includes separate output paths for the Class D amplifier and the speakers (640A and 640B).

[0022] Where applicable, the various embodiments provided by this disclosure may be implemented using hardware, software, or a combination of hardware and software. Furthermore, where applicable, the various hardware and / or software components described herein may be combined into composite components comprising software, hardware, and / or both, without departing from the spirit of this disclosure. Where applicable, the various hardware and / or software components described herein may be divided into sub-components comprising software, hardware, or both, without departing from the scope of this disclosure. Furthermore, where applicable, it is contemplated that software components may be implemented as hardware components, and vice versa.

[0023] The foregoing disclosure is not intended to limit this disclosure to the precise form disclosed or any particular field of use. Therefore, it is contemplated that various alternative embodiments and / or modifications to this disclosure are possible, whether expressly described or implied herein. Having thus described embodiments of this disclosure, those skilled in the art will recognize that changes in form and detail may be made without departing from the scope of this disclosure. Therefore, this disclosure is limited only by the claims.

Claims

1. A method for amplifying an audio signal, comprising: An audio input signal is received at the input of an audio amplifier circuit comprising at least three integrators arranged in series. An output signal is generated using a quantizer, which is arranged to receive an integrated signal from the last of the at least three integrators. The output signal is filtered to generate a first filtered output signal and a second filtered output signal, respectively. The filtered feedback signal, which includes the output signal of the first filter, is applied to the first integrator of the at least three integrators; The filtered feedback signal, which includes the output signal of the second filter, is applied to the second integrator of the at least three integrators; as well as The output signal is applied to the input of each of the remaining integrators in the at least three integrators.

2. The method according to claim 1, wherein the audio amplifier circuit is a Class D amplifier.

3. An audio amplifier circuit, comprising: At least three integrator circuits are arranged in series and configured to receive an input signal at the first integrator of the at least three integrators and generate an integrated signal from the last integrator of the at least three integrators; A quantizer, which is arranged to receive the integrated signal and generate an output signal; A first filter is arranged to receive a feedback signal including the output signal and to generate a first filtered feedback signal, the first filtered feedback signal being applied to the input of the first integrator of the at least three integrators. A second filter is arranged to receive a feedback signal including the output signal and to generate a second filtered feedback signal, the second filtered feedback signal being applied to the input of the second integrator of the at least three integrators; as well as A feedback signal path configured to receive the output signal and apply the output signal to the input of the third integrator of the at least three integrators.

4. The audio amplifier circuit according to claim 3, wherein the audio amplifier circuit is a Class D amplifier.

5. The audio amplifier circuit according to claim 3, wherein the audio amplifier circuit is a Δ-Σ modulator.

6. The audio amplifier circuit according to claim 3, wherein the input signal is an analog audio signal.

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