error correction bits

Abstract

This document relates to error correction bits. A data processing apparatus is provided that includes a storage circuit that includes a plurality of lines, each of the plurality of lines including a data value. An access circuit accesses a pair of the plurality of lines at a time, the pair of the plurality of lines including an extra data value different from the data value and including a plurality of error bits that detect or correct an error in the data value in each of the pair of the plurality of lines.

Description

Technical Field

[0001] This disclosure relates to data processing, and more particularly to the storage of bits in a data processing apparatus. Background Technology

[0002] In data processing devices, storage circuitry is used to store data. While it is often desirable to increase the capacity of storage circuitry, this impacts the size of the circuitry employed and, consequently, the power consumption of that circuitry (even during idle periods). During data storage, the data can become corrupted (e.g., due to transient errors). One way to prevent this is by using check bits, which are stored separately from the data and can be used to detect and, in some cases, correct a limited number of errors in the data. However, additional storage space is generally required to store the check bits, leading to the aforementioned problems of increased circuit space and power consumption. It would be desirable to increase the effective storage capacity of the storage circuitry without simply adding additional storage cells that would result in increased circuit size and power consumption. Summary of the Invention

[0003] From the first example configuration, a data processing apparatus is provided, including: a storage circuit including multiple lines, each of the multiple lines including a data value; and an access circuit for accessing a pair of lines of the multiple lines at a time, the pair of lines including additional data values ​​different from the data values, and including multiple error bits for detecting or correcting errors in the data values ​​of each of the pairs of lines of the multiple lines.

[0004] From the second example configuration, a data processing method is provided, including: storing multiple lines, each of the multiple lines including a data value; and accessing a pair of lines of the multiple lines at a time, the pair of lines including additional data values ​​different from the data values, and including multiple error bits, the multiple error bits being used to detect or correct errors in the data values ​​of each of the pairs of lines of the multiple lines.

[0005] From the third example configuration, a data processing apparatus is provided, including: means for storing a plurality of lines, each of the plurality of lines including a data value; and means for accessing a pair of lines of the plurality of lines at a time, the pair of lines including additional data values ​​different from the data values, and including a plurality of error bits for detecting or correcting errors in the data values ​​of each of the pair of lines of the plurality of lines. Attached Figure Description

[0006] The invention will be further described by way of example only with reference to embodiments illustrated in the accompanying drawings, in which:

[0007] Figure 1 An apparatus is schematically illustrated according to some embodiments;

[0008] Figure 2A A first method in which bits can be stored in a storage circuit is illustrated according to some embodiments;

[0009] Figure 2B A second method in which bits can be stored in a storage circuit is illustrated according to some embodiments;

[0010] Figure 3 The illustration shows one way to encode MTE tags into error bits (e.g., ECC bits);

[0011] Figure 4 The generation circuit is illustrated in more detail according to some embodiments;

[0012] Figure 5 The test circuit is illustrated in more detail according to some embodiments;

[0013] Figure 6 An example of a circuit that can be used to test data values ​​in two data lines is illustrated according to some embodiments; and

[0014] Figure 7 A flowchart illustrating the process of operating the device is shown according to some embodiments. Detailed Implementation

[0015] Before discussing embodiments with reference to the accompanying drawings, the following description of the embodiments is provided.

[0016] According to an example configuration, a data processing apparatus is provided, comprising: a storage circuit including a plurality of lines, each of the plurality of lines including a data value; and an access circuit for accessing a pair of lines of the plurality of lines at a time, the pair of lines including additional data values ​​different from the data values, and including a plurality of error bits for detecting or correcting errors in the data values ​​of each of the pair of lines of the plurality of lines.

[0017] In the above aspects, storage lines (e.g., cache lines) are accessed simultaneously. That is, in response to an access request for data in one line, two separately stored storage lines are retrieved. Each line contains its own data value. Simultaneously, the pair of lines jointly contains a series of error bits. These error bits are generated by applying an error correction algorithm (e.g., a Cyclic Redundancy Check (CRC) algorithm) to the data value. With the aid of these error bits, it is possible to detect one or more bits in the data value that have been flipped (e.g., due to a transient error). In other words, if one or more bits of a data value are corrupted, it is possible to detect the error to some extent based on the error bits generated from that data value. In some cases, it may also be possible to correct the error. Due to the presence of the error bits and the fact that the storage lines are accessed in pairs, it is possible to store additional (attached) data values ​​within the pair of storage lines. This is achieved without increasing the number of bit units in the storage circuit. These additional data values ​​are distinct from the data value because they are not merely arbitrary partitions of the data value. In practice, this means that the error bits are generated based on the data value, rather than on the additional data value.

[0018] In some examples, the data processing apparatus includes a permission circuit for examining the additional data value to determine whether a user of the data value is permitted to access it. The additional data value can therefore be used by the permission circuit to determine access permission for a user of the data value, thus determining whether the user is allowed to access the data value.

[0019] In some examples, the extra data value indicates the owner of the pair of lines containing that extra value. There are several ways to use the extra data value to check whether a visitor is authorized to access the data value. However, in some examples, the extra data value indicates the owner of the pair of lines containing that extra data value. In this way, it can be assumed that only the owner of that pair of lines is authorized to access (read or write) that particular line.

[0020] In some examples, the owner is identified by an identifier associated with the execution environment. The owner of a line can be identified in several different ways. However, in some examples, the owner is indicated based on an identifier associated with the execution environment. For example, the identifier can be an identifier for a process, thread, operating system, virtual machine, CPU, virtual CPU, machine, or any other environment in which the stream of instructions is executed. Typically, such ownership can be segmented, restricting a particular application from accessing data belonging to another application. This makes it possible to restrict the use of personal or confidential information by one application, ensuring that it is only accessible to that application.

[0021] In some examples, the additional data value is the MTE tag. A Memory Tag Extension (MTE) tag is a security feature where a multi-bit tag (e.g., a 4-bit tag) is used to check access to, for example, memory pointers, ensuring that only the specific execution environment associated with the correct tag is permitted access. Specifically, when an execution environment requests memory allocation, the MTE tag associated with the current execution environment is allocated to that block of memory. From this point onward, any memory access to that region of memory must be made by an execution environment with the same tag to succeed. Access made by other execution environments may be denied.

[0022] In some examples, the error bits are ECC bits. Error Correcting Code (ECC) memory is used to detect and correct corruption in data in memory. Specifically, the data value to be stored in a line of memory is applied to an algorithm to generate a set of ECC bits. These ECC bits can be compared with the data value at any time to determine if a correspondence still exists. If no correspondence exists, it can be concluded that the data value has become corrupted. The algorithm used to generate ECC bits makes it possible to detect a finite number of errors in the data value. In particular, it is possible to detect several flipped bits in the data value. For example, the algorithm can make it possible to use ECC bits to detect up to two flipped bits in the data value. Furthermore, the ECC bits generated by the algorithm can make it possible to correct flipped bits in the data value. In other words, ECC bits may be sufficient to precisely determine which bit(s) have been flipped so that these bits can be corrected to the appropriate value. Typically, ECC bits can detect one more error than they can correct. For example, ECC bits can enable them to detect two errors in a data value and correct one error.

[0023] In some examples, the additional data value is encoded into a selected set of bits comprising at least one of the following: at least some of the error bits and at least some of the bits constituting the data value. Specifically, in some embodiments, the additional data value is encoded into at least some of the error bits and at least some of the bits constituting the data value. By encoding the additional data value into a large number of bits, it is possible to provide such encoding within a large space. When the encoding space is sufficiently large, it is possible to provide a unique encoding for each possible value of the additional data value.

[0024] In some examples, the error bits include an coded form of extra data value. There are several ways to save space to make room for the extra data value. However, in these examples, the extra data value is included within the pair of lines by encoding it within the error bits themselves. For example, the error bits can be intentionally corrupted by encoding the extra data within them. This encoding of the extra data value within the error bits means that the error bits can still be used to detect and / or correct errors in the data value.

[0025] In some examples, an extra value is encoded into a set of selected bits by inverting multiple selected bits, where the positions of the selected bits indicate the extra value. One way to encode an extra data value is by selectively inverting some of the selected bits. In particular, the positions of the inverted bits can be used to indicate the extra value. For example, inverting the first and second bits may correspond to extra value one, inverting the first and third error bits may correspond to extra value two, inverting the first and fourth error bits may correspond to extra value three, and so on. Obviously, it is not necessary for every single combination of bits to correspond to the different possible values ​​of the extra value. In particular, if there are only a finite number of possibilities for the extra value, only the inverted error bits of those many different combinations need to correspond to the different values ​​of the extra value. In some embodiments, where the encoding space is large, each possible bit in the selected bits is used for only a single possible value of the extra data value. For example, if there are eight selected bits and eight possible values ​​for the extra data value, each bit may correspond to its own value.

[0026] In some examples, the number of selected bits that are inverted is at most equal to the number of errors detectable using the error bits. By limiting the number of error bits that can be inverted to encode additional values, it is possible to continue using the error bits to detect and / or correct errors in the values. Obviously, if the number of inverted error bits exceeds the number of errors detectable using the error bits, then the error bits cannot be used to detect errors in the values. In some embodiments, the number of selected error bits that are inverted is equal to the number of errors detectable using the error bits.

[0027] In some examples, the data processing apparatus includes a test circuit for inverting at least some comparison error bits generated using data values ​​from a first line of a plurality of lines to produce inverted comparison error bits and performing a comparison of the inverted comparison error bits with error bits from the first line of the pair of lines in the plurality of lines, wherein the error bits and the inverted comparison error bits are generated from the data values ​​using the same algorithm. After the error bits are inverted, it is possible to continue using the error bits to detect or correct errors in the data values. This can be achieved by the test circuit. The comparison error bits are generated using the data values ​​and the same algorithm used to generate the error bits themselves. Under normal circumstances, if none of the error bits have been inverted, we would expect the comparison error bits to be the same as the error bits themselves, assuming no corruption. However, in this case, some of the error bits have been intentionally inverted. By inverting some of the comparison error bits to determine the match with the error bits, it is possible to determine which bits have been intentionally inverted. This, in turn, makes it possible to identify additional data values.

[0028] In some examples, the data processing apparatus includes: multiple test circuits, each inverting a different comparison error bit; and analysis circuitry for identifying the test circuit among the multiple test circuits that has inverted the comparison error bit that matches the error bit. Instead of using a single test circuit to selectively invert each combination of comparison error bits to produce multiple sets of inverted comparison error bits and thus determine which bits must have been inverted, it is possible to provide multiple test circuits, each inverting a different combination of bits. This makes it possible to test each combination of inverted comparison bits in parallel. Therefore, we can determine additional data values ​​more quickly. In practice, without any data corruption, all but one of the test circuits will produce a mismatch between the comparison error bits and the error bit. The test circuit that produces a match between its inverted comparison error bits and the error bit can be used to identify additional data values ​​encoded into the error bit.

[0029] In some examples, in response to each of the multiple test circuits producing an inverted comparison error bit that differs from the error bit, each test circuit is adapted to perform an additional comparison between an additional inverted comparison bit generated using the data value of the second line in that pair of lines and the error bit of the second line in that pair of lines, in order to determine the data value. Of course, it is possible that additional corruption has occurred to the error bit or data bit—that is, beyond the intentional corruption used to encode the additional data value. In this case, each test circuit will produce a set of inverted comparison error bits that differ from the error bit. This is because, in the case of corruption to the data value or error bit, the error bit will not correspond to the data value. In such a case, it is possible to consider the second line in that pair of lines. Since the additional data value is the same for both lines in a pair, it is possible to perform the same comparison using the data value of the second line in that pair and the error bit. Once the additional data value is determined in this way, it is possible to invert the error bit of the first line again—that is, to undo the intentional corruption of the error bit of the first line that was previously performed. This can then be used to correct and / or detect errors in the data values ​​at the front line.

[0030] In some examples, the data processing apparatus includes a generation circuit for generating error bits from data values ​​and inverting at least some of the error bits, wherein at least some of the error bits are selected based on additional data values. The generation circuit is responsible for generating error bits when data values ​​are inserted into storage circuitry. By selecting which error bits to invert, it is possible to encode different additional data values, as explained above.

[0031] In some examples, the data processing apparatus includes a first operating mode in which error bits are adapted to detect or correct errors in data values ​​in each of a pair of lines, where the data values ​​are treated as a single data value. Another way to store additional data values ​​within the storage circuit without increasing the number of bit cells in the storage circuit is to treat the two data values ​​in each of the pair of lines as a single data value and determine error bits for that single data value, rather than generating two sets of error bits, each set pointing to data values ​​in different lines. Such embodiments take advantage of the fact that the number of error bits required to detect or correct an error increases non-linearly relative to the size of the data value for which the error bits are generated. Specifically, in the case of an algorithm with a Hamming distance of four, as in the case of Single Error Correction, Double Error Detection (SECDED), eight error correction bits can be used in combination with up to 120 data bits, of which only 64 bits are used in a register storing 64 data bits and eight error bits. However, by increasing the number of error correction bits to nine, 247 data bits can be supported—two registers that jointly store 128 bits are sufficient. Therefore, by treating the pair of data values ​​in each of the pairs as a single data value, fewer error bits are needed compared to the case of two distinct data values, since a batch of 137 bits (nine error correction bits and two batches of 64 data bits) is less than two batches of 72 bits (two batches of eight error correction bits and two batches of 64 data bits). This reduces the required number of error bits, and the freed-up space can be used to store additional data values. Again, the additional data values ​​are kept distinct from the data values ​​in the sense that error bits do not cover the additional values ​​and cannot be used to detect or correct errors in the additional data values.

[0032] In some examples, in the first operating mode, the error bits are distributed across each of the pairs of lines in a multi-line configuration. That is, not all error bits are present in a single line, but can instead be distributed between two lines. In some embodiments, the division is equal, such that an equal number of bits are located in each of the two lines.

[0033] In some examples, the error bit is located at the same bit position in each of the pairs of lines. This makes it efficient in terms of routing, ensuring that the location of a specific bit with a specific function stored within each line of the storage circuit is consistent with the routing.

[0034] In some examples, the data processing apparatus includes a second operating mode, wherein the error bits in each of the pairs of lines are specific to the data values ​​stored in that pair of lines; and the data processing apparatus includes switching circuitry for switching between a first operating mode and a second operating mode. The apparatus may be able to switch between the first and second operating modes, wherein in the first operating mode the error bits treat the data values ​​in both lines as a single value, while in the second operating mode, the error bits in each line are generated based on the data values ​​in that line, excluding the influence of the data values ​​in the second line of the pair. It will be understood that in the first operating mode, while error detection and correction are still possible, this capability is limited compared to the second operating mode. Specifically, in the first operating mode, it is possible to detect or correct only X errors out of 2N bits. However, in the second operating mode, it is possible to detect or correct X errors out of N bits. However, this more limited error checking and detection capability provides more storage capacity. Therefore, by providing switching circuitry, it is possible to switch between these two operating modes depending on whether it is desirable to improve error correction and detection capabilities or to increase storage capacity. Such a desire can be determined on a case-by-case basis, but it can also be determined when the data processing device is activated. This second operating mode may therefore not use the MTE tag at all. However, in some embodiments, the second operating mode may correspond to the process described above, in which additional data (e.g., the MTE tag) is encoded within ECC bits. Alternatively, in some other embodiments, the above encoding process operates as a third operating mode.

[0035] Specific embodiments will now be described with reference to the accompanying drawings.

[0036] Figure 1 An apparatus 100 is schematically illustrated according to some embodiments. The apparatus includes a load / store unit 110 responsible for performing access operations on storage circuitry 160. Access operations issued by the load / store unit 110 are sent to an access circuit 120, which determines the specific circuits 170, 180 within storage circuitry 160 to be accessed from the access address provided by the access operation. In these embodiments, each entry (AV) of storage circuitry 170, 180 includes a set of data bits and a set of error bits. The error bits represent the block code corresponding to the data bits. Once retrieved, the data bits and error bits are passed to a test circuit 150, which tests the data bits against the error bits to determine if the data is intact. The result of this test is then passed back to the load / store unit 110 via the access circuitry 120.

[0037] In these embodiments, each entry in the storage circuit 160 utilizes a Memory Tag Extension (MTE) tag, which is a security feature used to check access requests to ensure that only the relevant execution environment is permitted to access the data. These tags are checked by the licensing circuit 140 against a corresponding tag provided as part of the access request. In this embodiment, the licensing circuit 140 forms part of the access circuitry, but in other embodiments it may be located elsewhere. If an execution environment other than the one to which a particular entry belongs (e.g., a thread, process, operating system, super-supervisor, CPU, etc.) attempts to access the entry (e.g., if a non-corresponding MTE tag is provided in the access request, or if no MTE tag is provided in the access request), the licensing circuit 140 will intervene. This may take the form of, for example, raising an exception or fault, or it may simply cause the access to be flagged. If the execution environment has permission to access the requested data, the licensing circuit 140 permits the access (e.g., read or write) to occur. It should be noted that the exact manner in which the licensing circuit 140 performs the permission check is not critical to this technology.

[0038] One way to store access information for a specific entry (AV) of storage circuit 160 is to store the associated MTE tag along with the entry. However, this requires an increase in the amount of storage space required by storage circuit 160. In particular, a large number of bits may be provided to store additional data corresponding to the MTE tag. This therefore increases the size of the circuit and also increases its power consumption.

[0039] In this embodiment, entries or lines are accessed together. For example, if an access request is made for data entry A, data entry B can also be accessed simultaneously. Similarly, if a data access request is made for line L, access circuit 120 can allow entry K to be accessed simultaneously. Because entries are accessed in pairs, it is possible to utilize the bits used to store block codes (e.g., ECC bits) more efficiently. Therefore, bits used for access permission (e.g., MTE tags) can be stored without increasing the number of required bit units. Similarly, it is possible to avoid significantly increasing circuit size or power consumption. Furthermore, this can be achieved without significantly affecting the error detection and correction capabilities via ECC codes.

[0040] A generation circuit 130 is provided to generate ECC bits and MTE tags. Therefore, the generation circuit 130 can be used to respond to write requests issued by the load / store unit when data is to be written to the storage circuit 160 along with the appropriate ECC bits and MTE tags.

[0041] In practice, it will become clear that the current embodiment is not limited to the use of MTE tags, but can be used to store various other forms of data that differ from the data used to generate error bits. Similarly, while the current embodiment focuses particularly on the use of ECC bits, the embodiment is not limited to this, and other forms of error bits may be considered.

[0042] There are several ways to access data lines in pairs to allow efficient storage of MTE bits together with ECC bits.

[0043] Figure 2A The diagram illustrates the first operating mode, which controls how bits can be used to store MTE tags. Again, a pair of lines 2n and 2n+1 are provided. Each line also contains data from bit 0 to bit 63. However, in this case, the ECC bits are generated for the data values ​​of both lines 2n and 2n+1. That is, the ECC bits are generated based on the data from bits 0-63 of line 2n and bits 0-63 of line 2n+1 (a total of 128 bits). This process leverages the fact that the number of ECC bits required for a given data item increases non-linearly with the size of that data. For example, in a SECDED code (single error correction, double error correction code), eight bits are needed to cover a 64-bit data value. However, only nine bits are needed to cover a 128-bit data value. Therefore, by generating ECC codes together for the data values ​​in lines 2n and 2n+1, fewer ECC bits are required. As a result, the remaining bits, which would have been used to store two different ECC values, can be used to store the MTE tag. For example, as... Figure 2A As shown, if the ECC bits (a total of eight bits) are evenly split across the two data lines, the MTE tag (which requires four bits) can also be evenly split across these two data lines. This leaves a single spare bit (x), which can be used for additional storage or to expand the MTE tag space.

[0044] Figure 2BThe diagram illustrates a second operating mode that controls how bits can be used to store the MTE tag. Specifically, for line 2n, bits 0-63 are used to store data. Bits 64-71 are then used to store the corresponding ECC code corresponding to the data (bits 0-63) of the same line. Therefore, the paired line 2n+1 has its own data extending from bit 0 to bit 63 and its own ECC code from bits 64 to 71 corresponding to the data in bits 0-63 of line 2n+1. These two lines are accessed together as a pair. The MTE tag will be identical for each of the two lines 2n and 2n+1 and will also be stored in each of the two lines. In these examples, the MTE tag is stored by intentionally flipping a subset of the bits in the ECC code. By selecting which bits are flipped, it is possible to encode different values ​​for the MTE tag. For example, if one combination of bits is flipped, the MTE tag will be different compared to if a second combination of bits is flipped. In this way, the MTE tag can be encoded within the ECC bits, and thus the MTE tag as an additional data value can be stored in each of lines 2n and 2n+1 without requiring additional storage bits.

[0045] It should be noted that in this example, the bits selected for encoding the MTE tag are ECC bits. However, in other embodiments, the selected bits can be data bits, or a set of data bits and a set of ECC bits. By allowing encoding to occur on a larger set of bits, it is possible to provide more possible encodings for the MTE tag. Furthermore, it is possible to make certain bits uniquely correspond to a specific MTE tag value.

[0046] It will be understood that the organization of the exact location of the ECC bits and the exact location of the MTE tag (when not encoded within the ECC bits) is arbitrary. However, by placing the relevant bits in the same position in each of the two lines, the wiring necessary to extract the relevant bits can be simplified. Of course, in some embodiments, there may be enough bits to provide all ECC bits or all MTE tag bits in a single line. However, since access to either of the two lines would require both ECC bits and MTE bits, both lines are still accessed.

[0047] It should be noted that other operating modes are also possible. For example, in some embodiments, an operating mode in which no encoding occurs can be provided for the second operating mode. Alternatively, the first operating mode can be provided in a mode in which the MTE tag is not used and in which the ECC bit is specific to the data value in each line. In other embodiments, three operating modes can be provided, including those related to... Figure 2A and 2BThe two operating modes described include an additional third operating mode in which no encoding occurs and where the MTE tag is not used. Other combinations will be apparent to those skilled in the art.

[0048] Figure 3 The diagram illustrates one method for encoding an MTE tag into ECC bits in the second operating mode. This process is performed after ECC bits have been generated for the specific data. For each different value of the MTE tag, different combinations of ECC bits are inverted, such as... Figure 3 As shown in the diagram. For example, to represent the MTE tag "6", bits 0 and 4 need to be reversed. If you want to encode the MTE tag "11", bits 0 and 5 of the ECC bits are reversed. In practice, the reversal can be achieved by reversing the ECC bits and... Figure 3 This is achieved by performing an XOR operation between the bits shown for each of the different MTE tags. Therefore, if the ECC bit is 10111011 and the MTE tag "12" is to be encoded, the operation 10111011XOR 00100010 = 10011001 can be performed.

[0049] As previously mentioned, it is possible that ECC bits and / or data bits are used to encode the MTE tag in the second operating mode, and by increasing the number of bits used for encoding, a unique inversion is possible for each encoding. Using both ECC bits and data bits allows for a unique inversion of each value of the MTE tag, which avoids confusion with shared bits.

[0050] Figure 4 A more detailed illustration is provided of the generation circuit 130 used in the second operating mode. As previously discussed, the generation circuit is used to write requests to generate ECC bits and encode additional data into the ECC bits. Figure 4 In the example shown, since the MTE tag provided by the visitor is "3", the MTE tag to be encoded is "3". For example... Figure 3 As shown, the MTE tag "3" corresponds to the inversion of bits 0 and 3. Return Figure 4The write data to be written to the storage circuit 160 passes through the generation circuit 130 of the access circuit 120. Here, the ECC generation circuit 420 is used to generate the ECC code. In this example, the ECC code is generated as an 8-bit number. Each bit is output separately and passed through inverters 430 and 440. Each original bit and its inverted form are passed to a multiplexer. Thus, a multiplexer can be used to determine whether the original bit or the inverted bit should be passed as output. In practice, this is achieved via a selection signal output by the selection circuit 470. In this example, since the MTE tag to be encoded is the value "3", this is received by the selection circuit 470, which passes a signal that causes the selection signals of two of the multiplexers 450 and 460 to select the inverted bit instead of the original bit. Thus, in the case of bits 0 and 3, the inverted form of the bit is output. In other cases, the non-inverted form of the ECC code is output. In this way, an ECC code whose bits have been selectively inverted is output, where the selected bit corresponds to a specific value of the MTE tag. It should be noted that by reversing the specific individual bits indicated by the MTE tag, it is not necessary to perform an XOR operation on the entire set of bits.

[0051] Figure 5 A more detailed illustration is provided of the test circuit 150 used in the second operating mode. The test circuit 150 can be used to check the integrity of the data. It will be understood that in the second operating mode, the ECC bits are intentionally reversed. Specifically, some bits constituting the ECC code are intentionally reversed. However, Figure 5 The circuit shown does not suffer a reduction in its error-checking capability. Specifically, data, along with the corresponding ECC code, is received from the storage circuit 160 by the test circuit 150. Here, the data and ECC code are passed to multiple test circuits 500, 510, 520, and 530. Each of these circuits inverts a different set of ECC bits stored along with the data. In practice, each test circuit will invert as follows... Figure 3Different sets of ECC bits are shown. For example, the first test circuit 500 will invert bits zero and one, while the sixteenth test circuit 530 will invert bits four and five. The data bits are then checked against the modified bits of the modified ECC code. It can be expected that in 15 or 16 cases, the ECC check will fail. However, in one of the test units 500, 510, 520, and 530, the ECC check should pass (assuming no unintentional damage has occurred). The test circuit that produces this pass therefore corresponds to the MTE tag encoded within the ECC bits. For example, if the test circuit inverts bits two and three and this results in a valid ECC check, the encoded MTE tag will be the value "5". The counting circuit 540 can be used to determine whether exactly one of the test circuits produced a valid ECC check and thus determine whether the ECC bits and data bits match. The detection circuit 530 can be used to determine which of the test circuits 500, 510, 520, and 530 caused the match to occur and convert this information into the corresponding MTE tag.

[0052] If each of test circuits 500, 510, 520, and 530 fails, or if multiple test circuits 500, 510, 520, and 530 pass, the data has become corrupted. Multiple passes can occur due to obfuscation—for example, a bit being used in multiple different inversion combinations, like... Figure 3 As in the case described above. Here, a single failure can be decoded into two potential MTE tags. Because the ECC bits have been modified, it may be impossible to use the ECC bits to detect and / or correct the corruption. However, since the data lines are accessed in pairs and since the MTE tags are identical for a pair of lines, it is possible to use the second line of the pair to correct the situation. For example, consider the case of... Figure 1 In the case of a data access request made on data line A, both data lines A and B are retrieved and passed to test circuit 150. If, during the operation of the test circuit, it is determined that the data stored on data line A is corrupted, the same procedure can be used to retrieve the MTE tag from data line B. The MTE tag can then be returned. Since the MTE tag also indicates which bits in the error bits of lines A and B have been inverted, it is possible to reverse the inversion performed on the ECC bits of line A. The inversion can then be reversed, and the reversed ECC bits can be used to detect and / or correct data values ​​according to the normal ECC procedure.

[0053] Figure 6An example of circuitry that can be used in this process is illustrated. Specifically, the previously illustrated test circuit 150 is replicated as a first test circuit 150a and a second test circuit 150b. Each of the two test circuits 150a and 150b includes the previously mentioned test circuits 500, 510, 520, and 530. The first test circuit 150a receives the requested data line, while the second test circuit 150b receives another data line forming the accessed data line pair. The first test circuit 150a outputs a pass / fail signal, a determined MTE tag, and the determined data. The second test circuit 150b outputs a pass / fail signal and an MTE tag. In practice, the MTE tags output by the first test circuit 150a and the second test circuit 150b should be the same. The data output by the first test circuit 150a is passed to a correction circuit 560, which also receives the MTE tag obtained from the second test circuit 150b. The correction circuit 560 uses the provided MTE tag to reverse any changes made to the ECC bits. This can be achieved by executing actions that are already related to... Figure 3 The bit reversal shown in the diagram is used to achieve this. Since the MTE tag has been provided to the correction circuit 560, the exact bit to be selected is known. From here, the correction circuit 560 can use the ECC bit to perform error correction and detection on the data bits. The data is then output by the correction circuit 560. In addition, the ECC signal output by the first test circuit 150a and the data component of the data are also provided to the multiplexer 570. The selection signal for the multiplexer 570 is composed of two pass signals output by each of the first test circuit 150a and the second test circuit 150b. Thus, depending on whether the ECC check performed by the first test circuit 150a passes, either the data output by the first test circuit 150a or the corrected data output by the correction circuit 560 is output by the multiplexer 570. Similarly, the combined pass signal of the MTE tags output by the first test circuit 150a and the second test circuit 150b is used to select between the two sources in order to output an MTE tag that is considered valid by the second multiplexer 580. Of course, the two multiplexers 570 and 580 can also be configured to output an error signal in response to both pass signals from the first test circuit 150a and the second test circuit 150b indicating an error. In this case, data retrieval is not possible.

[0054] Figure 7A flowchart 600 illustrating the operation of device 100 is shown. In step 602, an access request is received for a specific memory line at a given address. Specifically, an access can be made to read the requested line A. In step 604, the memory line and its paired line (e.g., line B) are retrieved. In step 606, it is determined in which operating mode device 100 is operating. In the case where the ECC bits are separated (e.g., different for each line)—the previously described "first mode"—then in step 608, the ECC bits are extracted from the requested line. In step 610, the ECC bits are selectively inverted and compared with data bits to determine if the ECC bits match data. This can be achieved, for example, by utilizing... Figure 5 The circuitry is used to implement this. In step 612, it is determined whether an ECC pass exists as a result of the comparison performed in step 610. If not, ECC bits are extracted from the other (paired) line B. In step 616, a comparison is then performed using the ECC bits (also selectively inverted) forming part of the paired line B and the data bits. In step 618, it is determined whether the comparison results in an ECC pass. If so, in step 620, the ECC bits of the requested line can be corrected. This can be achieved by inverting those ECC bits corresponding to the MTE tag obtained from the paired line again. In step 622, the combination of bits inverted to achieve the ECC pass is then converted into an MTE tag. The process then proceeds to step 636, which will be discussed below. If, in step 618, the comparison does not result in an ECC pass for any combination of bits, the process proceeds to step 624, where an exception is raised. This indicates a situation where the data value cannot be accessed. The access operation may be retried. In the worst-case scenario, the data has become corrupted and a system reset is necessary. If the comparison in step 612 results in ECC passing, the combination of bits that were reversed to enable ECC passing is converted into an MTE tag in step 626, and the process proceeds to step 636, which is discussed below.

[0055] Returning to step 606, if the operating mode is a combination of ECC codes used for the line pair (the previously described "second mode"), then in step 628, the ECC bits are extracted from the line pair. In step 630, the ECC bits are then compared. In step 632, it is determined whether the ECC bits provide passage for the data or can be used to correct the data in the event of a failure. If not, an exception is raised in step 634 because the data cannot be recovered. This may result in, for example, a system reset. If the ECC bits provide passage for the data or can be used to correct the data, then in step 636, the MTE tag is extracted and it is determined whether an MTE pass has occurred. In practice, this can be achieved by comparing the access execution environment with the MTE tag. In cases where the execution environment is associated with a processor, thread, operating system, or super-supervisor, it may be necessary to provide an identifier of the execution environment as part of the access request. In other cases, the execution environment may be obvious to access circuitry 120. For example, if the execution environment is associated with a specific processor ID, this may be known to access circuitry 120. If an MTE pass does not occur (if an MTE failure exists), an exception is raised in step 638. This exception corresponds to a permission exception because the execution environment is not permitted to access the requested data. Otherwise, in step 640, the requested line is returned.

[0056] Therefore, it can be understood that by simultaneously accessing a pair of lines in storage circuit 160 and by carefully using error bits such as ECC bits, additional storage space can be provided for extra data that does not undergo ECC bit processing. Thus, no additional storage is required for the extra data being stored. This means that circuit space can be kept small, which keeps power consumption relatively low compared to systems that must provide additional storage space. The described process has minimal impact on the ECC protection process itself. In particular, ECC bits can still be used to detect and correct errors.

[0057] In this application, the term "configured as" is used to mean that the elements of the device are configured to perform defined operations. In this context, "configuration" refers to the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform that function. "Configured as" does not mean that the elements of the device need to be changed in any way in order to provide the defined operations.

[0058] While illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these specific embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims. For example, features of the dependent claims may be combined with features of the independent claims in various ways without departing from the scope of the invention.

Claims

1. A data processing apparatus, comprising: The storage circuit includes multiple lines, each of which includes a data value; and An access circuit is configured to access one pair of lines from the plurality of lines at a time, the pair of lines including additional data values ​​different from the data value, and including a plurality of error bits for detecting or correcting errors in the data values ​​of each line in the pair of lines. The additional data value is encoded into a selected set of bits that includes at least one of the following: error bits, and at least some of the bits that constitute the data value.

2. The data processing apparatus according to claim 1, comprising: A permission circuit is used to check the additional data value to determine whether the user accessing the data value is permitted to access it.

3. The data processing apparatus according to claim 1 or 2, wherein The additional data value indicates the owner of the pair of lines containing the additional data value among the plurality of lines.

4. The data processing apparatus according to claim 3, wherein The owner is identified by an identifier associated with the execution environment.

5. The data processing apparatus according to claim 1 or 2, wherein The additional data value is the MTE tag.

6. The data processing apparatus according to claim 1 or 2, wherein Error bits are ECC bits.

7. The data processing apparatus according to claim 1, wherein The error bits include the additional data values ​​in encoded form.

8. The data processing apparatus according to claim 7, wherein The additional data value is encoded into the set of selected bits by inverting multiple selected bits, wherein, The positions of the selected bits indicate the additional data value.

9. The data processing apparatus according to any one of claims 7-8, wherein The number of the selected bits that are reversed is at most equal to the number of errors that can be detected using the error bits.

10. The data processing apparatus according to any one of claims 7-8, comprising: A test circuit is configured to invert at least some comparison error bits generated using data values ​​from a first line of the plurality of lines to produce inverted comparison error bits, and to perform a comparison of the inverted comparison error bits with the error bits in the first line of a pair of lines of the plurality of lines, wherein... The error bits and the inverted comparison error bits are generated from the data values ​​using the same algorithm.

11. The data processing apparatus according to claim 10, comprising: Multiple test circuits, wherein each test circuit inverts a different comparison error bit; and An analysis circuit is used to identify the test circuit among the plurality of test circuits that has inverted the comparison error bit that matches the error bit.

12. The data processing apparatus according to claim 11, wherein In response to each of the plurality of test circuits generating an inverted comparison error bit that is different from the error bit, each test circuit is adapted to perform an additional comparison between an additional inverted comparison bit generated using the data value of the second line of the pair of lines in the plurality of lines and the error bit of the second line of the pair of lines in the plurality of lines, in order to determine the data value.

13. The data processing apparatus according to any one of claims 7-8, comprising: A generation circuit is configured to generate the error bits from the data value and invert at least some of the error bits, wherein... At least some of the error bits were selected based on the additional data value.

14. The data processing apparatus according to claim 1 or 2, wherein The data processing device includes a first operating mode in which the error bits are adapted to detect or correct errors in data values ​​in each of the pairs of lines of the plurality of lines, wherein the data values ​​are treated as a single data value.

15. The data processing apparatus according to claim 14, wherein In the first operating mode, the error bits are distributed across each of the pairs of lines in the plurality of lines.

16. The data processing apparatus according to claim 14, wherein The error bits are located at the same bit position in each of the pairs of lines in the plurality of lines.

17. The data processing apparatus according to claim 14, wherein The data processing device includes a second operating mode in which the error bits in each of the pairs of lines in the plurality of lines are specific to the data value stored in that pair of lines in the plurality of lines; and The data processing device includes a switching circuit for switching between the first operating mode and the second operating mode.

18. A data processing method, comprising: Store multiple lines, each of which includes a data value; and One pair of lines from the plurality of lines is accessed at a time. This pair of lines includes additional data values ​​that differ from the stated data value and includes multiple error bits used to detect or correct errors in the data values ​​of each line within the pair of lines. The additional data value is encoded into a selected set of bits that includes at least one of the following: error bits, and at least some of the bits that constitute the data value.

19. A data processing apparatus, comprising: A means for storing multiple lines, each of which includes a data value; and A means for accessing a pair of lines among the plurality of lines at a time, the pair of lines including additional data values ​​different from the data value, and including a plurality of error bits for detecting or correcting errors in the data values ​​of each line in the pair of lines among the plurality of lines. The additional data value is encoded into a selected set of bits that includes at least one of the following: error bits, and at least some of the bits that constitute the data value.

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