Trench filling by reflowing the fill material

Abstract

The present disclosure relates to reflowing a fill material to perform trench filling. A method includes forming a first protruding fin and a second protruding fin above a substrate structure, wherein a trench is located between the first protruding fin and the second protruding fin, depositing a trench filling material extending into the trench, and performing a laser reflow process on the trench filling material. During the reflow process, the temperature of the trench filling material is higher than a first melting point of the trench filling material and lower than a second melting point of the first protruding fin and the second protruding fin. After the laser reflow process, the trench filling material is solidified. The method also includes patterning the trench filling material, wherein a remaining portion of the trench filling material forms part of a gate stack, and forming a source / drain region on one side of the gate stack.

Description

Technical Field

[0001] The present disclosure relates to trench filling by reflowing fill material. Background Art

[0002] In the manufacture of integrated circuits, it is necessary to fill narrow trenches with an aspect ratio greater than 2 without generating voids. One of the cases is the formation of a dummy gate, which includes forming an amorphous silicon layer filled into the trench between semiconductor fins. For this application, the entire amorphous silicon layer needs to be high quality and void-free to prevent problems that may occur during the subsequent post-gate cutting and spacer deposition processes. Traditionally, chemical vapor deposition is used to form an amorphous silicon layer. However, the resulting amorphous silicon layer has a mushroom-shaped portion on the top of the narrow trench. This is because the reaction vapor cannot penetrate into the deep trench. As a result, voids are formed in the amorphous silicon, and the voids extend into the trenches.

[0003] Typically, several methods are used to avoid creating voids. For example, a bottom-up gap filling method can be used. However, a bottom-up gap filling method requires reactants with very high selectivity. An annealing process can also be used. However, the annealing process requires a temperature higher than the initial thermal budget. Deposition and etching cycles can also be used to reduce the width and length of the gap / seam. However, this method is costly and time consuming, and the void cannot be completely removed. Summary of the invention

[0004] According to a first aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming a first protruding fin and a second protruding fin above a base structure, wherein a trench is located between the first protruding fin and the second protruding fin; depositing a trench filling material extending into the trench; performing a laser reflow process on the trench filling material, wherein, in the laser reflow process, the temperature of the trench filling material is higher than a first melting point of the trench filling material and lower than a second melting point of the first protruding fin and the second protruding fin; after the laser reflow process, solidifying the trench filling material; patterning the trench filling material, wherein a remaining portion of the trench filling material forms part of a gate stack; and forming a source / drain region on one side of the gate stack.

[0005] According to a second aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: forming an isolation region extending into a semiconductor substrate; recessing the isolation region so that a portion of the semiconductor substrate between the isolation regions protrudes higher than the recessed isolation region to form a protruding fin; depositing a silicon region, wherein the silicon region extends into a groove between the protruding fins and a void is formed in the silicon region; planarizing a top surface of the silicon region, wherein after the planarization, the void is sealed in the silicon region; reducing the size of the void by reflowing the silicon region while the void is sealed in the silicon region; and patterning the silicon region.

[0006] According to a third aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising: depositing a first material onto a protruding structure and a base layer, wherein the protruding structure protrudes higher than the base layer and a void is sealed in the first material, and wherein: the first material has a first melting point; the protruding structure includes a second material having a second melting point; and a surface area of ​​the base layer in contact with the first material includes a third material having a third melting point, and the first melting point is lower than both the second melting point and the third melting point; and reflowing the first material to eliminate the void, wherein the reflow is performed by projecting radiation onto the first material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1 to 15 Perspective and cross-sectional views illustrate intermediate stages in the formation of a fin field effect transistor (FinFET) and a corresponding trench fill process, according to some embodiments.

[0009] Figures 16 to 19 A cross-sectional view illustrates an intermediate stage in the formation of a trench fill process in accordance with some embodiments.

[0010] Fig. 20 and Fig.21 A plan view and a cross-sectional view are respectively shown in the formation of a hard mask filling a trench according to some embodiments.

[0011] Fig. 22 A process for filling a conductive via into a trench is shown in accordance with some embodiments.

[0012] Fig.23A process flow for forming a FinFET according to some embodiments is shown.

[0013] Fig.24 A process flow of a trench filling process according to some embodiments is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present disclosure. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0016] According to some embodiments, a trench filling process and a process for forming a fin field effect transistor (FinFET) using the trench filling process are provided. According to some embodiments of the present disclosure, the trench filling process includes depositing a trench filling material into the trench, and performing an annealing process to reflow the trench filling material so as to reduce or eliminate the voids in the trench. The embodiments discussed herein provide examples that enable the subject matter of the present disclosure to be made or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0017] Figures 1 to 15 FIG. 1 shows a cross-sectional view of an intermediate stage in the formation of a FinFET according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in FIG. Fig.23 The process flow shown.

[0018] exist Figure 1 In the embodiment, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The semiconductor substrate 20 may be a portion of a wafer 10 (e.g., a silicon wafer). Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon or glass substrate). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination of the foregoing.

[0019] Further references Figure 1 , a well region 22 is formed in the substrate 20. The corresponding process is shown as Fig.23 Process 202 in process flow 200 shown in FIG. According to some embodiments of the present disclosure, the well region 22 is a p-type well region formed by implanting p-type impurities into the substrate 20. The p-type impurities may be boron, indium, etc. According to other embodiments of the present disclosure, the well region 22 is an n-type well region formed by implanting n-type impurities into the substrate 20. The n-type impurities may be phosphorus, arsenic, antimony, etc. The resulting well region 22 may extend to the top surface of the substrate 20. The concentration of n-type or p-type impurities may be equal to or less than 10 18 cm -3 , for example, in 10 17 cm -3 to about 10 18 cm -3 within the range.

[0020] refer to Figure 2 , the isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. The isolation region 24 is alternatively referred to as a shallow trench isolation (STI) region hereinafter. The corresponding process is shown as follows Fig.23Process 204 in the process flow 200 shown. The portion of the substrate 20 between adjacent STI regions 24 is referred to as a semiconductor strip 26. In order to form the STI region 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20, and then patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the present disclosure, the pad oxide layer 28 is formed in a thermal oxidation process, in which the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 serves as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present disclosure, the hard mask layer 30 is formed of silicon nitride, for example, using atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), etc. A photoresist (not shown) is formed on the hard mask layer 30, and then patterned. The hard mask layer 30 is then patterned using the patterned photoresist as an etch mask to form a hard mask 30, such as Figure 2 shown.

[0021] Next, the pad oxide layer 28 and the substrate 20 are etched using the patterned hard mask layer 30 as an etch mask, and the resulting trenches in the substrate 20 are subsequently filled with (one or more) dielectric materials. A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is performed to remove excess portions of the dielectric material, and the remaining portions of the (one or more) dielectric materials are the STI regions 24. The STI regions 24 may include a liner dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The liner dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI regions 24 may also include a dielectric material above the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material above the liner dielectric may include silicon oxide.

[0022] The top surface of hard mask 30 and the top surface of STI region 24 may be substantially flush with each other. Semiconductor strips 26 are between adjacent STI regions 24. According to some embodiments of the present disclosure, semiconductor strips 26 are part of original substrate 20, and thus the material of semiconductor strips 26 is the same as the material of substrate 20. According to alternative embodiments of the present disclosure, semiconductor strips 26 are alternative strips formed by etching a portion of substrate 20 between STI regions 24 to form a groove, and performing epitaxy to re-grow another semiconductor material in the groove. Therefore, semiconductor strips 26 are formed of a semiconductor material different from the semiconductor material of substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0023] refer to Figure 3 , STI region 24 is recessed to form trench 40. Thus, the top portion of semiconductor strip 26 protrudes higher than top surface 24A of the remaining portion of STI region 24 to form protruding fin 36. The corresponding process is shown as Fig.23 Process 206 in process flow 200 is shown. Etching can be performed using a dry etching process (wherein, for example, HF3 and NH3 are used as etching gases). During the etching process, plasma can be generated. Argon can also be included. According to an alternative embodiment of the present disclosure, a wet etching process is used to perform the recessing of the STI region 24. The etching chemical can include, for example, HF.

[0024] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, thereby allowing the generation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0025] refer to Figure 4 , forming a dummy gate dielectric layer 38. The corresponding process is shown as Fig.23Process 208 in the process flow 200 shown. According to some embodiments of the present disclosure, a conformal deposition process is used to form the dummy gate dielectric layer 38, which conformal deposition process may include atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The material of the dielectric layer 38 may include silicon oxide, silicon nitride, silicon carbonitride, etc. In the case of using a conformal deposition process, the horizontal thickness of the horizontal portion and the vertical thickness of the vertical portion of the dielectric layer 38 are equal to each other or substantially equal to each other, for example, with a difference of less than about 20% of the horizontal thickness. According to some embodiments, the thickness T1 of the dielectric layer 38 is in a range between about 1 nm and about 10 nm. According to an alternative embodiment, the dielectric layer 38 is formed by oxidizing (for example, using a thermal oxidation process) the surface portion of the protruding fin 36. The resulting dielectric layer 38 will be formed on the exposed surface of the protruding fin 36, rather than the top surface of the STI region 24.

[0026] Figures 5 to 7 The formation of the dummy gate electrode layer 42 is shown, which is filled as shown in FIG. Figure 4 The trench 40 is shown. Therefore, the corresponding formation process is also called a trench filling process. Figure 5 , depositing a dummy gate electrode layer 42. The corresponding process is shown as Fig.23 Process 210 in process flow 200 shown. The dummy gate electrode layer 42 can be formed of amorphous silicon, polycrystalline silicon, or a mixture of polycrystalline silicon and amorphous silicon, or includes amorphous silicon, polycrystalline silicon, or a mixture of polycrystalline silicon and amorphous silicon, and other materials can also be used. It should be understood that although silicon is used as an example of a trench filling material, the trench filling method discussed in the present disclosure can be applied to materials other than silicon. For example, germanium or silicon germanium can be used according to some embodiments.

[0027] The dummy gate electrode layer 42 may be deposited using a conformal deposition process, which may be ALD, CVD, LPCVD, etc. The deposition may also be a non-conformal deposition process. The formation may include depositing a silicon seed layer, and then growing more silicon on the silicon seed layer. According to some embodiments of the present disclosure, a silicon-containing precursor (e.g., SiH3-N((CH-CH3)2)2) is used to deposit a silicon seed layer. After forming the silicon seed layer, a silicon-containing precursor (e.g., disilane (Si2H6), monosilane (SiH4), a mixture of disilane and monosilane, or a similar precursor) may be used to grow silicon on the seed layer. The temperature for growing a silicon layer using disilane may be in the range between about 300°C and about 450°C. The temperature for growing a silicon layer using monosilane may be in the range between about 400°C and about 600°C. Depending on the temperature, the growth rate of the dummy gate electrode layer 42, and other process conditions, the dummy gate electrode layer 42 may be an amorphous silicon layer, a polysilicon layer, or a mixture of the foregoing.

[0028] According to some embodiments in which germanium is to be deposited, the corresponding precursor includes a precursor containing germanium and hydrogen, which may be denoted as Ge x H 2x+2 (where x is an integer equal to or greater than 1), or another germanium-containing precursor. For example, the precursor may include digermane (Ge2H6), monogermane (GeH4), a mixture of digermane and monogermane, etc. When silicon germanium is to be deposited, in addition to the germanium-containing precursor, a silicon-containing precursor as described above may also be included.

[0029] According to some embodiments, the deposition of the dummy gate electrode layer 42 is a single-step deposition process, in which no additional process such as an etch-back process is inserted into the single-step deposition process. The void 41 is generated and can be completely sealed inside the dummy gate electrode layer 42. According to an alternative embodiment, the void 41 is not sealed, and the top end of the void 41 is exposed to the vacuum environment above (e.g., the internal space of the corresponding vacuum chamber). The void 41 can have a strip shape having a longitudinal direction parallel to the longitudinal direction of the protruding fin 36.

[0030] Next, refer to Figure 6 , a reflow process is performed by an annealing process 43. The corresponding process is shown as Fig.23 The process 212 in the process flow 200 is shown. In the reflow process, the dummy gate electrode layer 42 is heated from the top side using a radiation source such as a laser generator, an ultraviolet light generator, etc. The details of the reflow process will be referred to in Figures 16 to 19 4. The reflow process is discussed in detail above and is therefore not repeated here. The reflow causes the dummy gate electrode layer 42 to melt and thus flow to fill the void 41. According to some embodiments, the void 41 is completely filled and thus eliminated by the reflow process. According to alternative embodiments, the volume of the void 41 is reduced and is mostly eliminated except for leaving the seam 45, such as Figure 7 As shown. The seams 45 are indicated using dashed lines to indicate that they may or may not exist, depending on process conditions, as will be discussed in subsequent paragraphs. According to some embodiments, after the reflow process, a planarization process such as a mechanical grinding process or a CMP process is performed to planarize the top surface of the dummy gate electrode layer 42.

[0031] Also like Figure 7 As shown, a hard mask layer 44 is deposited on the dummy gate electrode layer 42. The hard mask layer 44 may be formed of or include silicon nitride, silicon oxide, silicon oxycarbon nitride, or a plurality of layers thereof. Then, for example, a patterning process is performed on the hard mask layer 44 using a patterned photoresist (not shown) as an etching mask. The resulting hard mask is referred to as a hard mask 44', as shown in FIG. Figure 8 shown.

[0032] The patterned hard mask 44' is used as an etching mask to etch the underlying dummy gate electrode layer 42 ( Figure 7 ) and a dummy gate dielectric 38. Thus, a dummy gate electrode 42' and a dummy gate dielectric 38' are formed, as shown in FIG. Figure 8 4 and are collectively referred to as dummy gate stacks 47. The corresponding process is shown as Fig.23 The process 214 in the process flow 200 is shown. The etching is performed using an anisotropic etching process. The etching of the dummy gate electrode layer 42 can be performed using a process gas including C2F6, CF4, SO2, a mixture of HBr, Cl2 and O2, or a mixture of HBr, Cl2, O2 and CF2, etc. The dummy gate electrode layer 42 can be formed of amorphous silicon, polycrystalline silicon, etc.

[0033] Next, if Fig. 9 As shown, the gate spacer 46 is formed on the sidewall of the dummy gate stack 47. The corresponding process is shown as follows Fig.23 The process 216 in the process flow 200 is shown. According to some embodiments of the present disclosure, the gate spacer 46 is formed of one or more dielectric materials (eg, silicon nitride, silicon carbonitride, etc.), and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

[0034] Next, the portion of the protruding fin 36 not covered by the dummy gate stack 47 and the gate spacer 46 is etched to obtain Fig.10 The corresponding process is shown as Fig.23 Process 218 in process flow 200 is shown. The recess may be anisotropic and thus protect portions of fin 36 directly below dummy gate stack 47 and gate spacer 46 from being etched. According to some embodiments, the top surface of recessed semiconductor strip 26 may be lower than top surface 24A of STI region 24. Thus, recess 50 is formed. Recess 50 includes portions on opposite sides of dummy gate stack 47 and portions between remaining portions of protruding fin 36.

[0035] Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing (by epitaxy) semiconductor material in the recess 50, resulting in Fig.11 The corresponding process is shown as Fig.23Process 220 in the process flow 200 shown. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, the epitaxy can be used to in-situ dope p-type or n-type impurities. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to an alternative embodiment of the present disclosure, the epitaxial region 54 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination of the foregoing, or a multilayer of the foregoing. After the groove 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and a small face can be formed. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. A void (air gap) 56 may be generated.

[0036] After the epitaxial process, the epitaxial region 54 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also indicated using reference numeral 54. According to an alternative embodiment of the present disclosure, when the epitaxial region 54 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation step is omitted.

[0037] Fig.12 1 shows a perspective view of the structure after forming a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60. The corresponding process is shown as Fig.23 Process 222 in the process flow 200 shown. CESL 58 may be formed of silicon oxide, silicon nitride, silicon carbonitride, etc., and may be formed using CVD, ALD, etc. ILD 60 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition methods. ILD 60 may be formed of an oxygen-containing dielectric material, which may be a silicon oxide-based material such as tetraethyl orthosilicate (TEOS) oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), etc. A planarization process such as a CMP process or a mechanical grinding process may be performed to make the top surfaces of ILD 60, dummy gate stack 47, and gate spacer 46 flush with each other.

[0038] Then, the hard mask 44', the dummy gate electrode 42' and the dummy gate dielectric layer 38' are removed to form trenches 62 between the gate spacers 46. Fig.13 The corresponding process is shown as Fig.23 Process 224 in process flow 200 is shown.

[0039] Fig.14 The formation of a replacement gate stack 64 is shown. The corresponding process is shown as Fig.23 Process 226 in the process flow 200 shown. The gate stack 64 includes a gate dielectric 70 and a gate electrode 72. The gate dielectric 70 may include an interfacial layer (IL, not shown separately) and a high-k dielectric layer (not shown). The IL is formed on the exposed surface of the protruding fin 36 and may include an oxide layer such as a silicon oxide layer, which is formed by thermal oxidation, chemical oxidation process, or deposition process of the protruding fin 36. The high-k dielectric layer includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9 and may be higher than about 7.0. According to some embodiments of the present disclosure, the high-k dielectric layer is formed using ALD, CVD, etc.

[0040] According to some embodiments, the gate electrode 72 includes a stack of layers, which may include a diffusion barrier layer (capping layer) and one or more work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride, which may (or may not) be doped with silicon. The work function layer determines the work function of the gate electrode and includes at least one or more layers formed of different materials. The specific material of the work function layer may be selected according to whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer above the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer, a TiN layer above the TaN layer, and a TiAl-containing layer above the TiN layer. After depositing the capping layer and the work function layer, an adhesion layer may be formed, which may be another TiN layer. CVD may be used to form the adhesion layer. A metal filling region is then formed on the stacked layers, and the trench 62 ( Fig.13 ). The formation of the metal-filled region can be achieved by CVD, ALD, physical vapor deposition (PVD), etc., and the metal-filled region can be formed of or include cobalt, tungsten, the aforementioned alloys, or other metals or metal alloys.

[0041] Next, planarization such as a CMP process or a mechanical grinding process is performed so that the top surface of the gate stack 64 is coplanar with the top surface of the ILD 60. In a subsequent process, the gate stack 64 is etched back so that a groove is formed between the opposing gate spacers 46. Next, a hard mask 74 is formed over the replacement gate stack 64. The corresponding process is shown as follows. Fig.23Process 228 in process flow 200 is shown. According to some embodiments of the present disclosure, the formation of hard mask 74 includes a deposition process to form a blanket dielectric material, and a planarization process to remove excess dielectric material over gate spacers 46 and ILD 60. Hard mask 74 may be formed of, for example, silicon nitride or other similar dielectric materials.

[0042] Fig.15 Some features formed in subsequent processes are shown, which may include source / drain contact plugs 76, source / drain silicide regions 78, and gate contact plugs 80. The corresponding process is shown as Fig.23 The process 230 of the process flow 200 is shown. The details of the process are not discussed here, and thus the FinFET 82 is formed.

[0043] Figures 16 to 19 1 shows a cross-sectional view of an intermediate stage in a trench filling process according to some embodiments, wherein a trench filling material (eg, silicon) is filled into the trench. The corresponding process flow is shown as follows Fig.24 It should be understood that the dummy gate electrode layer 42 ( Figure 7 ) is formed Figures 16 to 19 Application of the process shown in .

[0044] Fig.16 The formation of a substrate structure 110 including a groove 114 according to some embodiments is shown. The corresponding process is shown as Fig.24 Process 302 in process flow 300 is shown. A strip 112 is formed extending into base structure 110. Strip 112 may be an elongated strip when viewed from the top, and Fig.16 The plane shown in is perpendicular to the longitudinal direction of the strips 112. Some portions of the strips 112 protrude higher than the top surface of the base structure 110 to form protruding fins 113. The grooves 114 are between the protruding fins 113. According to some embodiments of the present disclosure, the aspect ratio (ratio of depth to width) of the grooves 114 is greater than 2, and may be greater than 3, and may also be between about 3 and about 10.

[0045] The substrate structure 110 includes a surface region 116 and a lower portion 118. It should be understood that each of the surface region 116 and the protruding fin 113 can be formed of a homogeneous material, or can have a multilayer (and / or multi-region) structure including multiple layers and / or regions formed of different materials. For example, the protruding fin 113 may include one or more materials including SiO2, SiN, HfO2, TiN, W, crystalline silicon, TaN and / or any combination of the foregoing. The surface region 116 may include one or more materials including SiO2, HfO2, TiN, TaN, W and / or any combination of the foregoing. The protruding fin 113 and the surface region 116 can be formed using a method selected from the following: sputtering, CVD or ALD, flowable CVD (FCVD), ECP evaporation, PVD, etc.

[0046] According to some embodiments of the present disclosure, Figures 16 to 19 The trench filling process shown is used to form Figure 7 The dummy gate electrode layer 42 is shown. Therefore, Figures 16 to 19 The wafer 10' corresponds to Figure 7 Wafer 10 in. Fig.16 The protruding fin 113 in may correspond to Figure 7 The protruding fin 36 is combined with the portion of the dummy gate dielectric 38 on the protruding fin 36. The base structure 110 corresponds to the collection of the STI region 24, the bulk substrate 20, and the semiconductor strip 26, and may correspond to the following: Figure 7 Surface region 116 may correspond to STI region 24. The trench fill material 120 ( Fig.19 ) corresponds to Figure 7 The dummy gate electrode layer 42 in.

[0047] It should be understood that Figure 7 The trench filling process is an example of a structure on which the trench filling process is performed, and the trench filling process according to the embodiments of the present disclosure may be performed on other structures. For example, the trench filling process may be performed in a front-end-of-line (FEOL) process (including a process for forming a transistor and a process before forming the transistor) or in a back-end-of-line (BEOL) process (a process performed after forming the transistor including forming an interconnect structure).

[0048] refer to Fig.17 , a deposition process is performed to deposit the trench filling material 120. The corresponding process is shown as Fig.24Process 304 in the process flow 300 shown. The trench filling material 120 can be a semiconductor material, a conductive material such as a metal material, a dielectric material, etc. For example, the trench filling material 120 can include pure or substantially pure amorphous silicon (e.g., having a silicon atomic percentage greater than about 95%), pure or substantially pure amorphous germanium (e.g., having a germanium atomic percentage greater than about 95%), silicon germanium, copper, similar materials, or any combination of the foregoing. Depending on the material of the trench filling material 120, the deposition process can be performed using CVD, PVD, PECVD, ALD, LPCVD, or other applicable materials. When formed from or including silicon, germanium, or silicon germanium, the formation process and corresponding precursors can be as described in reference to Figure 5 The deposition is performed until the top surface of the trench filling material 120 is higher than the top surface of the protruding fin 113. According to some embodiments, the trench filling material 120 is deposited in a continuous process without other processes such as an etching process, an annealing process, etc. being inserted into the deposition process of the trench filling material 120. The deposition process may be performed in a vacuum environment or in open air.

[0049] Due to the high aspect ratio of trench 114, voids 122 may be created in trench fill material 120. The top ends of voids 122 may be closed, so that voids 122 may be completely sealed in trench fill material 120. In these embodiments, voids 122 are vacuum voids or air gaps. According to alternative embodiments, there may be some or all of voids 122 that have top ends exposed to the external environment. According to some embodiments, the width W1 of voids 122 is greater than about 1 nm, and the height H1 of voids 122 is greater than about 3 nm.

[0050] According to some embodiments, protruding fin 113 (and strip 112) has a first melting point MP113, and surface region 116 has a second melting point MP116. When protruding fin 113 includes multiple layers (or regions) formed of different materials, melting point MP113 is the melting point of the layer / region having the lowest melting point in protruding fin 113. Similarly, when surface region 116 includes more than one layer / region formed of different materials, melting point MP116 is the melting point of the layer / region having the lowest melting point in surface region 116. For example, among the candidate materials for forming protruding fin 113, SiO2 has a melting point of 1,710°C, crystalline silicon has a melting point of 1,412°C, and SiN has a melting point of 1,900°C. Among the candidate materials for forming the surface region 116, HfO2 has a melting point of 2,758°C, tungsten has a melting point of 3,422°C, TiN has a melting point of 2,930°C, and TaN has a melting point of 3,090°C.

[0051] The trench filling material 120 has a third melting point MP120 that is lower than both the melting points MP113 and MP116. For example, among the candidate materials for forming the trench filling material 120, crystalline germanium has a melting point of 937°C, amorphous silicon has a melting point in a range between about 1,000°C and about 1,100°C, amorphous germanium has a melting point of about 700°C, amorphous SiGe has a melting point between 700°C and about 1,100°C, and copper has a melting point of 1,083°C. In addition, both the differences (MP113-MP120) and (MP116-MP120) may be high enough to provide sufficient process margin to ensure that the surface region 116 and the protruding fin 113 are not melted in the subsequent reflow of the trench filling material 120. For example, both the differences (MP113 - MP120) and (MP116 - MP120) may be greater than about 100 °C, and may be within a range between about 100 °C and about 300 °C.

[0052] refer to Fig.18 , a local heating process 124 is performed so that, for example, the trench filling material 120 is reflowed. The corresponding process is shown as Fig.24 Process 308 in the process flow 300 shown. The local heating process 124 can be performed using an energy source 126, which can be a radiation source, such as a laser generator, an ion beam generator, an electron beam generator, a UV light generator, etc. Throughout the specification, the term "local heating" refers to a process in which the top portion of each wafer 10' (the top portion includes the trench filling material 120) is heated to a temperature equal to or higher than the melting point MP120, while the bottom portion 118 of the wafer 10' (if heated) is at a temperature below the melting point MP120. The bottom portion of the wafer 10' may not be directly heated, or may be heated as discussed in subsequent paragraphs. Throughout the specification, the local heating process 124 is also referred to as a reflow process 124.

[0053] According to some embodiments, the local heating process is performed using a pulsed laser, which may be a XeCl laser, an ArF laser, a KrF laser, a ruby ​​laser, etc. The laser energy may be about 0.1 mJ / cm 2 and about 10mJ / cm 2The pulse duration is shorter than about 1 microsecond and may be in the range between about 10ns and about 990ns, and the pulse applied to the portion of the trench filling material 120 may be a single pulse or a combination of multiple pulses. According to some embodiments, the pulsed laser is applied to an area of ​​the corresponding wafer, and the spot size of the laser may cover a portion of one die, one die, or multiple dies. For example, a pulsed laser may be applied to an area of ​​the wafer 10 to melt the trench filling material 120 in the area, and then move to the next area to repeat the pulsed laser melting process. The pulsed laser melting process is performed area by area until all areas of the wafer 10' are covered. According to alternative embodiments, a reflow process is performed using an ion beam, an electron beam, a laser beam, or the like, which may be used to scan the wafer 10'. In the reflow process, the trench filling material 120 is heated to a temperature in the range between about 300°C and about 1,300°C, and the temperature is equal to or higher than the melting point MP120, and lower than both the melting points MP113 and MP116.

[0054] According to some embodiments, wherein Fig.17 The embodiments in the Figure 5 In the example embodiment, the trench filling material 120 is the gate electrode layer 42, and Fig.18 The reflow process 124 is Figure 6 The reflow process shown in 43.

[0055] During the reflow process, at least the upper portion of the trench filling material 120, and possibly all of it, is melted. Throughout the reflow process, the protruding fins 113 (and the lower portion of the strip 112), the surface area 116, and the lower portion 118 remain solid and unmelted. In order to eliminate or at least significantly reduce the void 122, the melted portion extends at least to the bottom of the void 122, and may extend to the bottom of the trench filling material 120. Simulation results show that the depth of the melted portion is related to several factors including energy density, pulse length, etc. The absorption depth of the laser is about 10nm, and the portion of the trench filling material 120 above this depth directly receives the laser energy, and the deeper portion of the trench filling material 120 receives energy from the corresponding upper portion by conduction. As the energy density increases, the surface portion within the absorption depth receives more energy, and the lower portion is also able to receive more energy (by conduction), and therefore a higher temperature can be achieved in the lower portion. For example, at an energy density of about 0.4J / cm 2 In the case of , the portion of the trench filling material 120 reaching a temperature of 1,170° C. or higher may have a depth between about 115 nm and about 135 nm. In comparison, at an energy density of about 0.44 J / cm 2In the case of , the portion of the trench filling material 120 that reaches 1,290° C. (which causes complete melting of the crystalline silicon) or higher may have a depth between about 135 nm and about 155 nm. 2 In the case of , the portion of the trench fill material 120 reaching a temperature of 2,600° C. or higher may have a depth between about 135 nm and about 155 nm. This indicates that as the energy density increases, a higher temperature and a greater melting depth may be achieved.

[0056] The pulsed laser has an energy profile in the laser pulse (rather than having a fixed power density value throughout the pulse), where the laser energy density gradually increases to a peak value after the laser pulse starts, and then decreases to zero. At a given energy density, as the pulse duration increases, the energy profile causes the melted portion of the trench filling material 120 to extend downward until the deepest point is reached, and then the trench filling material 120 cools and solidifies from the bottom to the top. Therefore, the reflow process is adjusted so that when the melted portion reaches the lowest level, the bottom of the melted portion is at least flush with the bottom of the void 122, and may be lower than the bottom of the void 122.

[0057] According to some embodiments, in the reflow process, all of trench filling material 120 is completely melted. According to alternative embodiments, in the reflow process, an upper portion of trench filling material 120 that is higher than the bottom of void 122 is completely melted, while a lower portion that is lower than the bottom of void 122 is partially melted or remains solid. When the lower portion is partially melted, it means that the partially melted portion includes a liquid mixed with a solid.

[0058] Further references Fig.18 , a temperature adjustment unit 125 is provided, which can be placed under and in contact with the wafer 10'. The temperature adjustment unit 125 is used to adjust the temperature of the wafer 10' by heating the wafer 10' or cooling the wafer 10'. The corresponding process is shown as follows Fig.24 Process 306 in process flow 300 is shown. Temperature regulating unit 125 may include heat exchange unit 126 configured to heat or cool wafer 10'. According to an alternative embodiment, temperature regulating unit 125 is not provided, and wafer 10' does not receive additional cooling or heating other than the heating received from energy source 126. Therefore, process 306 is shown in a dashed box to indicate that the process may or may not be performed.

[0059] According to some embodiments, the temperature regulating unit 125 is a heating unit, and the heat exchange unit 127 is a heater, which may be a heating coil or include a heating coil. The temperature regulating unit 125 may heat the wafer 10', and the temperature of the trench filling material 120 is preheated to a temperature lower than the melting point MP120. Since the heating is a global heating process for heating the entire wafer 10', the temperatures of the protruding fins 113 and the surface area 116 are also heated. The trench filling material 120 is heated to a temperature Temp124 by the temperature regulating unit 125. According to some embodiments, the temperature difference (MP120-Temp124) is low enough to make the reflow process fast and easy, and high enough to keep the thermal budget caused by global heating small. Therefore, the laser reflow process is well suited for the front end of line (FEOL), middle end of line (MELO), and back end of line (BEOL) processes. According to some embodiments, the temperature difference (MP120-Temp124) is in a range between about 100°C and about 300°C. The heating process using the temperature adjustment unit 125 may be started before or simultaneously with the start time of the local heating process 124. Since the wafer 10' has reached a higher temperature, when the local heating process 124 is started, the temperature of the trench filling material 120 is close to the melting point MP120, and thus the reflow process is easier.

[0060] According to alternative embodiments, the temperature regulating unit 125 (heating unit according to these embodiments) does not include a coil but is also a radiation source configured to heat the wafer 10 ′ from the side opposite to the side of the energy source 126 (eg, the bottom side as shown).

[0061] According to an alternative embodiment, the temperature regulating unit 125 is a cooling unit, and the heat exchange unit 127 is a cooler, which may be a cooling conduit or may include a cooling conduit in which a coolant (e.g., cooled deionized water, cooled oil, cooled air, etc.) is conducted. The trench filling material 120 is cooled to a temperature below room temperature (e.g., below 21° C.) by the temperature regulating unit 125. Since the cooling is a global cooling process for cooling the entire wafer 10', when the local heating process 124 is started, the temperature of the protruding fins 113 and the surface area 116 is also reduced. According to some embodiments, the cooling reduces the temperature of the wafer 10' by about 50° C. to about 100° C. The cooling process using the temperature regulating unit 125 may be started before (or at the same time as) the start time of the local heating process because cooling takes longer than heating. Cooling may prevent the surface area 116 and the protruding fins 113 from melting.

[0062] Fig.19The resulting trench fill material 120 is shown after a reflow process 124. According to some embodiments, due to the mass flow of the trench fill material 120 during the reflow process, the void 122 is completely removed and no seam is left. According to alternative embodiments, the seam 128 may exist. The width W2 and height H2 of the void 122 are smaller than the width W1 and the height H1, respectively. Fig.17 ). For example, the width W2 may be less than about 1 nm, and may be less than about 20% of the width W1. Experimental results have revealed that the reflow process does not cause significant oxidation of the trench fill material 120 due to the short duration of the reflow process. After the reflow process 124, the trench fill material 120 is solidified. The corresponding process is shown as Fig.24 Process 310 of process flow 300 is shown. Solidification may be achieved by allowing wafer 10' to cool naturally, or may be performed with the assistance of temperature regulation unit 125, which includes a cooler according to some embodiments.

[0063] It should be understood that the trench filling process including the reflow process can be used to form other structures. Fig. 20 and Fig.21 In some embodiments shown, the surface region 116 is part of a conductive layer or a semiconductor layer, which may be formed of doped silicon, aluminum, nickel, etc. The trench filling material 120 is a hard mask layer, which may be formed of amorphous silicon, amorphous germanium, a silicon-germanium alloy, etc. Figures 16 to 19 The trench filling material 120 is deposited by the process shown in the figure, so that the resulting trench filling material 120 has no or substantially no voids. Then, the trench filling material 120 is patterned, for example, by a photolithography process, to form a Fig. 20 and Fig.21 The structure shown. In subsequent processing, the trench filling material 120 is used as a hard mask to pattern the surface region 116.

[0064] Fig. 22 An alternative embodiment is shown in which the surface region 130 is a conductive layer such as a silicide region, a metal layer, etc. The protruding fin 113 may be a dielectric fin. The trench fill material 120 forms a conductive via, which may be formed of or include copper or other low melting point conductive materials. The trench fill material 120 may be formed of a conductive material such as Figures 16 to 19 The processes shown are deposited and then patterned, for example, by photolithography processes. In these processes, the trench fill material 120 is heated to a temperature below the melting point of the trench fill material 120 and above the melting points of the protruding fins 113 and the surface region 116 to reduce or eliminate voids.

[0065] Embodiments of the present disclosure may be applied to other applications, for example, to improve step coverage. Fig.17 The structure shown in Fig.17 The protruding structure on the left part (similar to 113) and is not included in Fig.17 When the trench filling material 120 is deposited, the trench filling material 120 according to these embodiments may or may not have a void. However, a reflow process 124 may still be performed so that a first portion of the trench filling material 120 on top of the protruding structure 113 flows toward a second portion of the trench filling material 120 on the base structure 110. The height difference between the top surfaces of the first portion and the second portion is reduced.

[0066] Embodiments of the present disclosure have several advantageous features. By performing a reflow process, voids in the deposited trench fill material can be completely eliminated or significantly reduced. Step coverage can be improved. The method has low cost and high throughput.

[0067] According to some embodiments of the present disclosure, a method includes: forming a first protruding fin and a second protruding fin over a base structure, wherein a trench is located between the first protruding fin and the second protruding fin; depositing a trench filling material extending into the trench; performing a laser reflow process on the trench filling material, wherein, in the laser reflow process, the temperature of the trench filling material is higher than a first melting point of the trench filling material and lower than a second melting point of the first protruding fin and the second protruding fin; after the laser reflow process, causing the trench filling material to be solidified; patterning the trench filling material, wherein a remaining portion of the trench filling material forms a portion of a gate stack; and forming a source / drain region on one side of the gate stack. In an embodiment, before the reflow process, there is a void in the trench filling material, and after the reflow process, the size of the void is at least reduced. In an embodiment, after the reflow process, the void is eliminated. In an embodiment, the first protruding fin and the second protruding fin are formed of crystalline silicon, and the trench filling material includes amorphous silicon. In an embodiment, the method further includes, after the trench filling material is solidified, planarizing the trench filling material; and patterning the trench filling material to form strips. In an embodiment, the method further includes forming gate spacers on the sidewalls of the strips; removing the strips to form additional trenches between the gate spacers; and forming a replacement gate stack in the additional trenches. In an embodiment, the substrate structure includes a surface dielectric region, wherein the trench filling material contacts the surface dielectric region, and wherein, in the reflow process, the temperature of the trench filling material is further below the third melting point of the surface dielectric region. In an embodiment, the method further includes heating or cooling the substrate structure and the trench filling material during the reflow process. In an embodiment, heating or cooling the substrate structure and the trench filling material begins before starting the reflow process. In an embodiment, heating or cooling the substrate structure and the trench filling material begins at the same time as the reflow process begins.

[0068] According to some embodiments of the present disclosure, a method includes: forming an isolation region extending into a semiconductor substrate; recessing the isolation region so that a portion of the semiconductor substrate between the isolation regions protrudes higher than the recessed isolation region to form a protruding fin; depositing a silicon region, wherein the silicon region extends into a trench between the protruding fins and a void is formed in the silicon region; planarizing a top surface of the silicon region, wherein the void is sealed in the silicon region after planarization; reducing the size of the void when the void is sealed in the silicon region; and patterning the silicon region. In an embodiment, the silicon region includes amorphous silicon. In an embodiment, reducing the size of the void includes a reflow process to reflow the silicon region. In an embodiment, the silicon region includes a first portion above the bottom of the void and a second portion below the bottom of the void, and the reflow process causes the first portion to be melted and the second portion to remain solidified throughout the reflow process. In an embodiment, in the reflow process, the silicon region is heated to a temperature higher than a first melting temperature of the silicon region and lower than a second melting point of the protruding fin and the isolation region. In an embodiment, before reducing the size of the void, the void is completely sealed inside the silicon region.

[0069] According to some embodiments of the present disclosure, a method includes: depositing a first material onto a protruding structure and a base layer, wherein the protruding structure protrudes higher than the base layer and a void is sealed in the first material, and wherein the first material has a first melting point; the protruding structure includes a second material having a second melting point; and a surface area of ​​the base layer in contact with the first material includes a third material having a third melting point, and the first melting point is lower than both the second melting point and the third melting point; and reflowing the first material to eliminate the void, wherein the reflow is performed by projecting radiation on the first material. In an embodiment, the radiation includes a pulsed laser. In an embodiment, the radiation is projected on the first material for a period of time shorter than 1 microsecond. In an embodiment, both the first material and the second material include silicon.

[0070] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0071] Example 1. A method for forming a semiconductor structure, comprising: forming a first protruding fin and a second protruding fin above a base structure, wherein a trench is located between the first protruding fin and the second protruding fin; depositing a trench filling material extending into the trench; performing a laser reflow process on the trench filling material, wherein, in the laser reflow process, the temperature of the trench filling material is higher than a first melting point of the trench filling material and lower than a second melting point of the first protruding fin and the second protruding fin; after the laser reflow process, allowing the trench filling material to be solidified; patterning the trench filling material, wherein a remaining portion of the trench filling material forms part of a gate stack; and forming a source / drain region on one side of the gate stack.

[0072] Example 2. The method of Example 1, wherein voids exist in the trench fill material before the laser reflow process, and wherein a size of the voids is at least reduced after the laser reflow process.

[0073] Example 3. The method of Example 2, wherein the void is eliminated after the laser reflow process.

[0074] Example 4. The method of Example 1, wherein the first and second protruding fins are formed of crystalline silicon, and the trench fill material comprises amorphous silicon.

[0075] Example 5. The method according to Example 1 further includes:

[0076] After the trench fill material is solidified, the trench fill material is planarized, wherein patterning the trench fill material is performed on the planarized trench fill material.

[0077] Example 6. The method according to Example 5, further comprising:

[0078] forming gate spacers on sidewalls of the gate stack;

[0079] removing the gate stack to form additional trenches between the gate spacers; and

[0080] A replacement gate stack is formed in the additional trench.

[0081] Example 7. A method according to Example 1, wherein the substrate structure includes a surface dielectric region, wherein the trench filling material contacts the surface dielectric region, and wherein, during the laser reflow process, the temperature of the trench filling material is further lower than a third melting point of the surface dielectric region.

[0082] Example 8. The method of Example 1, further comprising: heating or cooling the substrate structure and the trench filling material during the laser reflow process.

[0083] Example 9. The method of Example 8, wherein heating or cooling the base structure and the trench filling material is initiated before initiating the laser reflow process.

[0084] Example 10. The method of Example 8, wherein heating or cooling the base structure and the trench fill material begins at the same time as the laser reflow process begins.

[0085] Example 11. A method for forming a semiconductor structure, comprising:

[0086] forming an isolation region extending into the semiconductor substrate;

[0087] Recessing the isolation regions so that a portion of the semiconductor substrate between the isolation regions protrudes higher than the recessed isolation regions to form protruding fins;

[0088] depositing a silicon region, wherein the silicon region extends into the trench between the protruding fins and a void is formed in the silicon region;

[0089] planarizing a top surface of the silicon region, wherein after the planarizing, the void is sealed in the silicon region;

[0090] reducing the size of the void by reflowing the silicon region while the void is sealed in the silicon region; and

[0091] The silicon region is patterned.

[0092] Example 12. The method of Example 11, wherein the silicon region comprises amorphous silicon.

[0093] Example 13. The method of Example 11, wherein in the reflow, the silicon region is heated to a temperature that is higher than a first melting temperature of the silicon region and lower than a second melting point of the protruding fin and the isolation region.

[0094] Example 14. The method of Example 11, wherein the void is completely sealed inside the silicon region before reducing the size of the void.

[0095] Example 15. The method of Example 11, wherein reducing the size of the void comprises a laser reflow process to reflow the silicon region.

[0096] Example 16. The method of Example 11, wherein the silicon region includes a first portion above the bottom of the void and a second portion below the bottom of the void, and the reflow process causes the first portion to be melted and the second portion to remain solidified throughout the reflow.

[0097] Example 17. A method for forming a semiconductor structure, comprising: depositing a first material onto a protruding structure and a base layer, wherein the protruding structure protrudes higher than the base layer and a void is sealed in the first material, and wherein: the first material has a first melting point; the protruding structure includes a second material having a second melting point; and a surface area of ​​the base layer in contact with the first material includes a third material having a third melting point, and the first melting point is lower than both the second melting point and the third melting point; and reflowing the first material to eliminate the void, wherein the reflow is performed by projecting radiation onto the first material.

[0098] Example 18. The method of Example 17, wherein the radiation comprises a pulsed laser.

[0099] Example 19. The method of Example 17, wherein the radiation is projected onto the first material for a period of time shorter than 1 microsecond.

[0100] Example 20. The method of Example 17, wherein both the first material and the second material include silicon.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first protruding fin and a second protruding fin over the base structure, wherein a trench is located between the first protruding fin and the second protruding fin; depositing a trench fill material extending into the trench; performing a laser reflow process on the trench filling material, wherein, in the laser reflow process, a temperature of the trench filling material is higher than a first melting point of the trench filling material and lower than a second melting point of the first protruding fin and the second protruding fin; While the laser reflow process is being performed, adjusting the temperature of the substrate structure using a temperature adjustment unit, wherein the temperature adjustment unit is below the substrate structure; After the laser reflow process, allowing the trench filling material to solidify; patterning the trench fill material, wherein a remaining portion of the trench fill material forms part of a gate stack; and Source / drain regions are formed on one side of the gate stack.

2. The method according to claim 1, wherein: Prior to the laser reflow process, voids exist in the trench fill material, and after the laser reflow process, the voids are at least reduced in size.

3. The method according to claim 2, wherein: After the laser reflow process, a seam is created.

4. The method according to claim 1, wherein: The first and second protruding fins are formed of crystalline silicon, and the trench fill material includes amorphous silicon.

5. The method according to claim 1, further comprising: After the trench filling material is solidified, the trench filling material is planarized, wherein the patterning is performed on the planarized trench filling material.

6. The method according to claim 5, further comprising: forming gate spacers on sidewalls of the gate stack; removing the gate stack to form additional trenches between the gate spacers; as well as A replacement gate stack is formed in the additional trench.

7. The method according to claim 1, wherein: The substrate structure includes a surface dielectric region, wherein the trench filling material contacts the surface dielectric region, and wherein, in the laser reflow process, a temperature of the trench filling material is further lower than a third melting point of the surface dielectric region.

8. The method according to claim 1, wherein: Regulating the temperature of the base structure may include heating or cooling.

9. The method according to claim 8, wherein: The laser reflow process is performed from a top side of the substrate structure, and wherein adjusting the temperature of the substrate structure includes heating the substrate structure.

10. The method according to claim 8, wherein: Regulating the temperature of the base structure includes cooling the base structure.

11. A method for forming a semiconductor structure, comprising: forming an isolation region extending into the semiconductor substrate; Recessing the isolation regions so that a portion of the semiconductor substrate between the isolation regions protrudes higher than the recessed isolation regions to form protruding fins; depositing a silicon region, wherein the silicon region extends into the trench between the protruding fins and a void is formed in the silicon region; planarizing a top surface of the silicon region, wherein after the planarizing, the void is sealed in the silicon region; In a case where the void is sealed in the silicon region, reducing a size of the void by reflowing the silicon region, wherein reducing the void comprises: heating the silicon region using an energy source, wherein the energy source is above the silicon region; and heating or cooling the semiconductor substrate using a temperature regulating unit, wherein the temperature regulating unit is below the semiconductor substrate; and The silicon region is patterned.

12. The method according to claim 11, wherein: Reducing the gap includes applying heat using the temperature regulating unit.

13. The method according to claim 11, wherein: Reducing the gap includes cooling using the temperature regulating unit.

14. The method according to claim 11, wherein: Prior to reducing the size of the void, the void is completely sealed within the silicon region.

15. The method according to claim 11, wherein: Reducing the size of the void includes a laser reflow process to reflow the silicon region.

16. The method according to claim 11, wherein: The silicon region includes a first portion above a bottom of the void and a second portion below the bottom of the void, and the reflow process causes the first portion to be melted and the second portion to remain solidified throughout the reflow.

17. A method for forming a semiconductor structure, comprising: A first material is deposited onto the protruding structure and the base layer, wherein the protruding structure protrudes higher than the base layer and voids are in the first material, and wherein: The first material has a first melting point; The protruding structure includes a second material having a second melting point; and a surface area of ​​the substrate layer in contact with the first material includes a third material having a third melting point, and the first melting point is lower than both the second melting point and the third melting point; reflowing the first material to minimize the void, wherein the reflowing is performed by projecting radiation onto the first material, and wherein after the reflowing, the void becomes a seam in the first material; and While the radiation is projected onto the first material, the temperature of the base layer and the protruding structure is adjusted using a temperature adjustment unit, wherein the temperature adjustment unit is below the base layer.

18. The method according to claim 17, wherein: The radiation comprises a pulsed laser.

19. The method according to claim 17, wherein: The seam has a width of less than about 1 nm.

20. The method according to claim 17, wherein: The first material and the second material both include silicon.

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