Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same. A semiconductor device comprises: a source / drain region, a body region, a first gate structure, and a second gate structure. The source / drain region and the body region are located in a substrate. The first gate structure and the second gate structure are located above the substrate. The source / drain region and the body region are located on opposite sides of the first gate structure. The second gate structure is spaced apart from the first gate structure. The source / drain region, the body region, and the first gate structure are located on the same side of the second gate structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking has also increased the complexity of processing and manufacturing ICs, and for these advances to be achieved, similar developments in IC processing and manufacturing are expected. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a source / drain region located in a substrate; a body region located in the substrate; a first gate structure located above the substrate, wherein the source / drain region and the body region are located on opposite sides of the first gate structure; and a second gate structure located above the substrate and spaced apart from the first gate structure, wherein the source / drain region, the body region and the first gate structure are located on the same side of the second gate structure.

[0004] According to another embodiment of the present disclosure, a semiconductor device is provided, including: an active region, including: a first source / drain region and a second source / drain region, the first source / drain region and the second source / drain region are spaced apart from each other; and a first body region and a second body region, the first body region and the second body region are spaced apart from each other; a first gate structure, located above the active region and between the first source / drain region and the first body region; and a second gate structure, located above the active region and between the first body region and the second body region.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming an active region in a substrate; forming a first gate structure and a second gate structure above the active region, wherein the first gate structure and the second gate structure comprise the same material and extend in different directions; forming a source / drain region and a first body region in the active region and on opposite sides of the first gate structure; and replacing the second gate structure with a third gate structure, wherein the first gate structure and the third gate structure comprise different materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A-Figure 10E A method for fabricating a semiconductor device at various stages according to some embodiments of the present disclosure is shown.

[0008] Fig.11 is a flow chart of a method for forming a semiconductor device according to some embodiments of the present disclosure.

[0009] Fig. 12A is a top view of a semiconductor device according to some embodiments of the present disclosure.

[0010] Fig. 12B It is along Fig. 12A A cross-sectional view taken along line BB in FIG. Fig. 12C It is along Fig. 12A Cross-sectional view taken along line CC in FIG.

[0011] Fig.12D It is along Fig. 12A A cross-sectional view taken along line DD in FIG.

[0012] Fig.12E It is along Fig. 12A A cross-sectional view taken along line EE in FIG.

[0013] Fig.12F It is along Fig. 12A Cross-sectional view taken along line FF in FIG.

[0014] Figures 13A-13D is a top view of a semiconductor device according to some embodiments of the present disclosure.

[0015] Fig.14A is a layout diagram of an integrated circuit without conductive traces according to some embodiments of the present disclosure.

[0016] Fig. 14B is a layout diagram of an integrated circuit having conductive traces according to some embodiments of the present disclosure.

[0017] Fig.15A is a layout diagram of an integrated circuit without conductive traces according to some embodiments of the present disclosure.

[0018] Fig. 15B is a layout diagram of an integrated circuit having conductive traces according to some embodiments of the present disclosure.

[0019] Fig.16A is a layout diagram of an integrated circuit without conductive traces according to some embodiments of the present disclosure.

[0020] Fig. 16B is a layout diagram of an integrated circuit having conductive traces according to some embodiments of the present disclosure.

[0021] Fig.17 is a layout diagram of an integrated circuit according to some embodiments of the present disclosure.

[0022] Fig.18 is a layout diagram of an integrated circuit according to some embodiments of the present disclosure.

[0023] Fig.19 is a flowchart of a method for generating an IC layout diagram according to some embodiments of the present disclosure.

[0024] Fig. 20 is a block diagram of an IC device design system according to some embodiments of the present disclosure.

[0025] Fig.21 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0027] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0028] As used herein, "approximately," "about," "roughly," or "substantially" generally means within 20 percent, or within 10 percent, or within 5 percent of a given value or range. The values ​​given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "roughly," or "substantially" can be inferred.

[0029] Embodiments of the present disclosure relate to semiconductor devices and methods for forming semiconductor devices having an H-shaped gate structure. The embodiments are discussed below in the context of forming a planar transistor having an active region in a bulk silicon substrate.

[0030] Figure 1A-Figure 10E A method for manufacturing a semiconductor device at various stages according to some embodiments of the present disclosure is shown. Figure 1A and Figure 1B ,in, Figure 1A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, and Figure 1B It is along Figure 1A BB in FIG. A substrate 110 is provided. In some embodiments, the substrate 110 is a silicon substrate. Alternatively, the substrate 110 may include another basic semiconductor, for example, germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0031] In yet another alternative, substrate 110 is a semiconductor on insulator (SOI), for example, a buried dielectric layer. In some embodiments, the SOI substrate includes a layer of semiconductor material 116 (e.g., silicon) formed on an insulator layer 114. Insulator layer 114 may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. Insulator layer 114 is disposed on semiconductor substrate 112 (e.g., a silicon or glass substrate). In some embodiments, semiconductor substrate 112 includes a p-type silicon substrate (p-substrate). For example, a p-type dopant is introduced into semiconductor substrate 112 to form a p-substrate.

[0032] refer to Figure 2A and Figure 2B ,in, Figure 2A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, and Figure 2B It is along Figure 2A. A plurality of isolation structures 120 (e.g., shallow trench isolation (STI)) are formed in the semiconductor material 116 of the substrate 110 to separate various devices. The formation of the isolation structure 120 may include etching trenches in the substrate 110 and filling the trenches with an insulator material (e.g., silicon oxide, silicon nitride, or silicon oxynitride). The filled trenches may have a multilayer structure, for example, a thermal oxide liner layer filling the trenches with silicon nitride. In some embodiments, the isolation structure 120 may be created using the following process sequence: for example, growing a liner oxide, forming a low pressure chemical vapor deposition (LPCVD) nitride layer, patterning the STI opening using a photoresist and a mask, etching trenches in the substrate 110, optionally growing a thermal oxide trench liner to improve the trench interface, filling the trenches with CVD oxide, and using chemical mechanical planarization (CMP) to remove excess dielectric layers. The isolation structure 120 defines at least one active area 118 in the substrate 110. For example, isolation structure 120 surrounds active region 118. It should be noted that Figure 2A The arrangement of the active region 118 in FIG. 1 is illustrative and should not limit the scope of the present disclosure.

[0033] refer to Figure 3A and Figure 3B ,in, Figure 3A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, and Figure 3B It is along Figure 3A The interface layer 130 is formed to cover the active region 118 (and in some embodiments, the isolation structure 120). For clarity, the interface layer 130 is Figure 3B is shown in and Figure 3A . In some embodiments, the dummy dielectric layer 130 may include silicon dioxide, silicon nitride, a high-κ dielectric material, or other suitable materials. In various examples, the dummy dielectric layer 130 may be deposited by an ALD process, a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, a PVD process, or other suitable processes. For example, the dummy dielectric layer 130 may be used to prevent damage to the active region 118 by subsequent processes (e.g., subsequent formation of a dummy gate structure).

[0034] Subsequently, dummy gate stacks 140a, 140b, and 140c are formed over the dummy dielectric layer 130. Dummy gate stacks 140a and 140c are formed over the active region 118, and dummy gate stack 140b is formed over the isolation structure 120. Each dummy gate stack 140a, 140b, and 140c includes a gate structure 142a (or 142b or 142c), a liner layer 144 formed over the gate structure 142a (or 142b or 142c), and a hard mask layer 146 formed over the liner layer 144. In some embodiments, a dummy gate layer (not shown) may be formed over the dummy dielectric layer 130, and a liner layer 144 and a hard mask layer 146 may be formed over the dummy gate layer. Then, the dummy gate layer is patterned using the liner layer 144 and the hard mask layer 146 as masks to form gate structures 142a-142c. Thus, the gate structures 142a, 142b, 142c, the liner layer 144, and the hard mask layer 146 are referred to as dummy gate stacks 140a, 140b, and 140c. In some embodiments, the gate structures 142a-142c may be made of polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), or other suitable materials. The liner layer 144 may be made of silicon dioxide or other suitable materials, and the hard mask layer 146 may be made of silicon nitride or other suitable materials. Note that Figure 3A The arrangement of the dummy gate stacks 140 a , 140 b , and 140 c in FIG. 1 is illustrative and should not limit the scope of the present disclosure.

[0035] exist Figure 3A and Figure 3B In the embodiment, the dummy gate stacks 140a, 140b, and 140c are separated from each other. The dummy gate stack 140c extends in a different direction than the dummy gate stacks 140a and 140b. For example, the dummy gate stack 140c extends in the x-direction, and the dummy gate stacks 140a and 140b extend in the y-direction. Figure 3A and Figure 3B As shown in , the z direction is parallel to the normal of the substrate 110, the x direction is the direction in which the dummy gate stack 140c extends, and the y direction is a direction orthogonal to the z direction and the x direction. One of the dummy gate stacks 140c is located between the dummy gate stacks 140a and one of the dummy gate stacks 140b. In addition, at least a portion of the dummy gate stack 140a is located directly above the active region 118, and at least a portion of each of the dummy gate stacks 140c is located directly above the active region 118. In contrast, the dummy gate stack 140b does not overlap with the active region 118 and is located directly above the isolation structure 120.

[0036] refer to Figure 4A and Figure 4B ,in, Figure 4A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, and Figure 4B It is along Figure 4A BB in FIG. 1 is a cross-sectional view taken along line BB in FIG. Portions of the dummy dielectric layer 130 not covered by the dummy gate stacks 140a, 140b, and 140c are removed to expose the active region 118 (and the isolation structure 120). Then, a spacer structure 150 is formed at least on opposite sides of the dummy gate stacks 140a, 140b, and 140c. For clarity, the spacer structure 150 is not shown in FIG. Figure 4B is shown in Figure 4A The spacer structure 150 may include a sealing spacer and a main spacer (not shown). The spacer structure 150 includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiC x O y N z , or a combination thereof. The sealing spacer is formed on the sidewalls of the dummy gate stacks 140a, 140b, and 140c, and the main spacer is formed on the sealing spacer. A deposition method such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric pressure chemical vapor deposition (SACVD) can be used to form the spacer structure 150. The formation of the spacer structure 150 can include blanket forming a spacer layer, and then performing an etching operation to remove a horizontal portion of the spacer layer. The remaining vertical portion of the spacer layer forms the spacer structure 150.

[0037] refer to Figure 5A-5D ,in, Figure 5A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, and Figure 5B It is along Figure 5A A cross-sectional view taken along line BB in FIG. Figure 5C It is along Figure 5A A cross-sectional view taken along line CC in FIG. Figure 5D It is along Figure 5ADD in FIG. 1 is a cross-sectional view taken along line DD in FIG. Source / drain regions 102a and 102b are formed in an active region 118 of substrate 110. Specifically, source / drain regions 102a and 102b are formed on one side of dummy gate stack 140c. In some embodiments, source / drain regions 102a and 102b are formed by ion implantation, diffusion technology, or other suitable technology. For example, in a photolithography process or other suitable process, a first mask is used to pattern a photoresist layer. An exemplary photolithography process may include processing operations of photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development, and hard baking. Ion implantation using dopants may be performed to form source / drain regions 102a and 102b in active region 118. In some embodiments, the source / drain regions 102 a and 102 b are N-type doped regions, and the dopant implanted into the source / drain regions 102 a and 102 b may be arsenic, phosphorus, or other suitable materials.

[0038] exist Figure 5C , because the dummy gate stack 140a is used as a mask to implant the source / drain regions 102a and 102b, the source / drain regions 102a and 102b are not formed directly under the dummy gate stack 140a and are separated by the dummy gate stack 140a. The source / drain regions 102a and 102b may be source / drain regions of a transistor, and a region of the active region 118 directly under the dummy gate stack 140a and between the source / drain regions 102a and 102b is referred to as a channel of the transistor.

[0039] Subsequently, body regions 104a and 104b are formed in the active region 118 of the substrate 110. Specifically, the body regions 104a and 104b are formed on the other side of the dummy gate stack 140c. In some embodiments, the body regions 104a and 104b are formed by ion implantation, diffusion technology, or other suitable technology. For example, in a photolithography process or other suitable process, a second mask is used to pattern the photoresist layer. An exemplary photolithography process may include processing operations of photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, development, and hard baking. Ion implantation using dopants may be performed to form body regions 104a and 104b in the active region 118. Note that the formation order of the above-mentioned source / drain regions 102a-102b and body regions 104a-104b is an example and should not limit the present disclosure. In some other embodiments, the source / drain regions 102a-102b may be formed after forming the body regions 104a-104b. In some embodiments, the body regions 104a and 104b are P-type doped regions, and the dopant implanted into the body regions 104a and 104b may be boron, boron difluoride (BF 2) or other suitable materials.

[0040] exist Figure 5D In the embodiment, because the dummy gate stack 140c is used as a mask to implant the source / drain regions 102a-102b and the body regions 104a-104b, the source / drain regions 102a and 102b and the body regions 104a-104b are not formed directly below the dummy gate stack 140c and are separated by the dummy gate stack 140c. The body regions 104a-104b may be referred to as the body regions of the transistor. The source / drain regions 102a-102b and the body regions 104a-104b have different conductivity types. In addition, as Figure 5A As shown, the body regions 104a-104b are separated from each other by the dummy gate stack 140a. In some embodiments, each source / drain region 102a-102b has a length L1 in the y-direction, and each body region 104a-104b has a length L2 that is less than the length L1.

[0041] refer to Figure 6A-6D ,in, Fig. 6A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, and Figure 6B It is along Fig. 6A A cross-sectional view taken along line BB in FIG. Figure 6C It is along Fig. 6A A cross-sectional view taken along line CC in FIG. Fig.6D It is along Fig. 6A A cross-sectional view taken along line DD in FIG. A plurality of metal alloy layers 160 are formed over the source / drain regions 102a-102b and the body regions 104a-104b, respectively. For clarity, the metal alloy layers 160 are Figure 6C-D is shown in Fig. 6A 118 is omitted. For example, a metal layer is formed above the active area 118. Then, an annealing process is performed on the metal layer to form a metal alloy layer 160. If the active area 118 is made of silicon, the annealing process is also called a silicide process. The silicide process converts the surface portion of the active area 118 into a silicide contact (i.e., the metal alloy layer 160 in this example). The silicide contact remains above the active area 118, and unreacted metal is removed from other areas. In some embodiments, the metal alloy layer 160 can be made of NiSi or other suitable materials.

[0042] refer to Figure 7A-7D ,in, Fig. 7A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, and Figure 7B It is along Fig. 7AA cross-sectional view taken along line BB in FIG. Figure 7C It is along Fig. 7A A cross-sectional view taken along line CC in FIG. Fig.7D It is along Fig. 7A A contact etch stop layer (CESL) 170 is conformally formed on the Figure 6A-6D For clarity, CESL 170 is shown above the Figure 7B-7D is shown in Fig. 7A In some embodiments, CESL 170 may be one or more stress layers. In some embodiments, CESL 170 has tensile stress and is composed of Si 3 N 4 In some other embodiments, the CESL 170 includes a material such as oxynitride. In still other embodiments, the CESL 170 may have a composite structure including a plurality of layers, for example, a silicon nitride layer covering a silicon oxide layer. The CESL 170 may be formed using plasma enhanced CVD (PECVD), however, other suitable methods may also be used, for example, low pressure CVD (LPCVD), atomic layer deposition (ALD), etc.

[0043] Then, a first interlayer dielectric (ILD) 175 is formed on the CESL 170. The first ILD 175 may be formed by chemical vapor deposition (CVD), high-density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the first ILD 175 includes silicon oxide. In some other embodiments, the first ILD 175 may include silicon oxynitride, silicon nitride, or a low-k material. Subsequently, a planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed to make the top surface of the first ILD 175 flush with the top surface of the gate structures 142a, 142b, and 142c. That is, the gate structures 142a, 142b, and 142c are exposed from the first ILD 175. In some other embodiments, the planarization process makes the top surface of the first ILD 175 flush with the top surface of the hard mask layer 146.

[0044] refer to Figure 8A-8D ,in, Fig. 8A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, and Figure 8B It is along Fig. 8A A cross-sectional view taken along line BB in FIG. Figure 8C It is along Fig. 8A A cross-sectional view taken along line CC in FIG. Fig.8D It is along Fig. 8AA cross-sectional view taken along line DD in FIG. 1 is a cross-sectional view taken along line DD in FIG. 1. A replacement gate (RPG) process scheme is adopted. In the RPG process scheme, a dummy polysilicon gate (in this example, Figure 7A-7D The gate structures 142a and 142b are then replaced with metal gates. Figure 7A-7D A mask layer is formed over the structure of , and the mask layer is patterned to form a patterned mask layer. The patterned mask layer exposes gate structures 142a and 142b, but covers gate structure 142c. That is, the RPG process replaces gate structures 142a and 142b with metal gate structures.

[0045] Subsequently, the gate structures 142a and 142b are removed to form openings 152 having the spacer structures 150 as their sidewalls, respectively. The gate structures 142a and 142b may be removed by dry etching, wet etching, or a combination of dry etching and wet etching. For example, the wet etching process may include exposure to a solution containing a hydroxide (e.g., ammonium hydroxide), deionized water, and / or other suitable etchant solutions.

[0046] refer to Figure 9A-9D ,in, Fig.9A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, and Fig. 9B It is along Fig.9A A cross-sectional view taken along line BB in FIG. Fig. 9C It is along Fig. 9C A cross-sectional view taken along line CC in FIG. Fig.9D It is along Fig.9A A cross-sectional view taken along line DD in FIG. Figures 8A-8C ), and at least one metal layer is formed in the opening 152 and on the gate dielectric layer 182. Subsequently, a chemical mechanical planarization (CMP) process is performed to planarize the metal layer and the gate dielectric layer 182 to form metal gate structures 180a and 180b in the opening 152, respectively. That is, Fig. 7A The gate structure 142a in is replaced by a metal gate structure 180a, and Fig. 7AThe gate structure 142b in the embodiment is replaced by a metal gate structure 180b. Each metal gate structure 180a and 180b includes a gate dielectric layer 182 and a metal gate electrode 184 located above the gate dielectric layer 182. The metal gate electrode 184 may include a metal layer 185 (e.g., (one or more) work function metal layers and (one or more) capping layers), (one or more) filling layers 186, and / or other suitable layers desired in the metal gate structure. The work function metal layer may include a p-type work function metal. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 、MoSi 2 、TaSi 2 、NiSi 2 , other suitable p-type work function materials, or combinations thereof. The work function metal layer may have multiple layers. The work function metal layer(s) may be deposited by CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, the cap layer in the metal gate electrode may include a refractory metal and its nitride (e.g., TiN, TaN, W 2 N, TiSiN, TaSiN). The cap layer may be deposited by PVD, CVD, metal organic chemical vapor deposition (MOCVD) ALD, etc. In some embodiments, the filling layer 186 in the metal gate electrode may include tungsten (W). The filling layer 186 may be deposited by ALD, PVD, CVD, or other suitable processes.

[0047] refer to Figure 10A-10E ,in, Fig. 10A is a top view of a semiconductor device at various stages of manufacture according to some embodiments of the present disclosure, Fig. 10B is along Fig. 10A A cross-sectional view taken along line BB in FIG. Fig. 10C It is along Fig. 10A A cross-sectional view taken along line CC in FIG. Fig. 10D It is along Fig. 10A A cross-sectional view taken along line DD in FIG. Fig. 10E It is along Fig. 10A A plurality of contacts 190 are formed over the memory cell source / drain regions 102a-102b and body regions 104a-104b. For example, Fig.9A A second ILD layer 177 is formed over the structure in the embodiment of the present invention, and a plurality of openings are formed in the first ILD 175 and the second ILD 177. Then, a conductive material is filled in the openings. Excessive portions of the conductive material are removed to form contacts 190 that are respectively in contact with the metal alloy layer 160. The contacts 190 may be made of tungsten, aluminum, copper, or other suitable materials.

[0048] exist Fig. 10A In the embodiment of the present invention, the semiconductor device can be a body-contacted MOS device and includes an active region 118, metal gate structures 180a and 180b, and a gate structure 142c. The metal gate structure 180a is referred to as an intrinsic gate and extends in the y direction. The gate structure 142c is referred to as a non-intrinsic gate and extends in the x direction. For example, the metal gate structure 180a and the gate structure 142c are substantially orthogonal to each other. The metal gate structure 180b is referred to as a dummy gate structure. Portions of the metal gate structure 180a and the gate structure 142c are located directly above the active region 118, and the metal gate structure 180b is located directly above the isolation structure 120. In some embodiments, the active region 118 has opposite sides 118a and 118b, and the metal gate structure 180a extends beyond the opposite sides 118a and 118b of the active region 118.

[0049] like Fig. 10A and Fig. 10B As shown, one of the gate structures 142c is located between one of the metal gate structures 180b and the metal gate structure 180a to form an H shape. The metal gate structures 180a and 180b are electrically isolated from the gate structure 142c. That is, the metal gate structures 180a and 180b are spaced apart from the gate structure 142c by the spacer structure 150. A portion of the spacer structure 150 is located between the metal gate structure 180a (or 180b) and the gate structure 142c, and is in contact with the metal gate structure 180a (or 180b) and the gate structure 142c. In some embodiments, the metal gate structure 180a is a functional gate that is electrically connected to an (electrically) conductive trace (see, e.g., Fig. 14B ), and the gate structure 142c is floating. That is, in some embodiments, there are no vias (and conductive traces) connected to the gate structure 142c.

[0050] The metal gate structures 180a and 180b have substantially the same gate spacing. That is, the distance P1 between one of the metal gate structures 180b and the metal gate structure 180a and the distance P2 between the other of the metal gate structures 180b and the metal gate structure 180a are substantially the same. In addition, the metal gate structures 180a and 180b have substantially the same width. That is, the width W1 of the metal gate structure 180a is substantially the same as the width W2 of the metal gate structure 180b.

[0051] like Fig. 10A and Fig. 10CAs shown, the active region 118 includes source / drain regions 102a and 102b. The source / drain regions 102a and 102b are located on opposite sides of the metal gate structure 180a, and the channel (i.e., the portion of the active region 118 located directly below the metal gate structure 180a) is located between the source / drain regions 102a and 102b and directly below the metal gate structure 180a. Two of the contacts 190 are located above the source / drain regions 102a and 102b, respectively. In addition, the source / drain regions 102a and 102b have the same conductivity type, for example, N-type in this example.

[0052] like Fig. 10A and Fig. 10E As shown, the active region 118 also includes body regions 104a and 104b. The body regions 104a and 104b are located on opposite sides of the metal gate structure 180a. The other two of the contacts 190 are located above the body regions 104a and 104b, respectively. In addition, the body regions 104a and 104b have the same conductivity type, for example, P type in this example.

[0053] like Fig. 10A and Fig. 10D As shown, the source / drain regions 102a and the body regions 104a are spaced apart from each other and are located on opposite sides of one of the gate structures 142c. Each source / drain region 102a-102b has a length L1 in the y-direction, and each body region 104a-104b has a length L2 that is less than the length L1. The body regions 104a-104b and the source / drain regions 102a-102b have different conductivity types. The source / drain regions 102a, the body regions 104a, and one gate structure 142c are located on the same side of the metal gate structure 180a, and the source / drain regions 102b, the body regions 104b, and another gate structure 142c are located on the other side of the metal gate structure 180a. Fig. 10A , the source / drain region 102a and the body region 104a are arranged along the y direction. Similarly, the source / drain region 102b and the body region 104b are arranged along the y direction.

[0054] Fig.11is a flow chart of a method M for forming a semiconductor device according to some embodiments of the present disclosure. Although method M is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from the order shown, and / or the actions may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at separate times, or may be performed simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0055] At block S12 , an active region is formed in the substrate. Figure 1A-Figure 2B A top view and a cross-sectional view of some embodiments corresponding to the actions in block S12 are shown. At block S14, an extrinsic gate and an intrinsic gate are formed over the substrate, wherein the intrinsic gate has a constant gate pitch. Figure 3A and Figure 3B A top view and a cross-sectional view of some embodiments corresponding to the actions in block S14 are shown. Figure 3A In the embodiment of the present invention, gate structures 142a and 142b may be referred to as intrinsic gates, and gate structure 142c may be referred to as an extrinsic gate. At block S16, the intrinsic gates are replaced with metal gate structures. Figures 8A-9B A top view and a cross-sectional view of some embodiments corresponding to the actions in block S16 are shown.

[0056] Fig. 12A is a top view of a semiconductor device according to some embodiments of the present disclosure, Fig. 12B is along Fig. 12A A cross-sectional view taken along line BB in FIG. Fig. 12C It is along Fig. 12A A cross-sectional view taken along line CC in FIG. Fig.12D It is along Fig. 12A A cross-sectional view taken along line DD in FIG. Fig.12E It is along Fig. 12A A cross-sectional view taken along line EE in FIG. Fig.12F It is along Fig. 12A Cross-sectional view taken along line FF in FIG. Fig. 12A and Fig. 10A The difference between the semiconductor devices in FIG. 140 and FIG. 141 relates to the arrangement of the gate structure 142 c. Figures 12A-12F In the embodiment, the semiconductor device includes a single gate structure 142c located between one of the metal gate structures 180b and the metal gate structure 180a. Fig. 10AIn the case shown in FIG. 1 , the source / drain region 102 b and the body region 104 b are connected to each other through the metal alloy layer 160. Figures 12A-12F Other relevant structural details of the semiconductor device and Figure 10A-10E The semiconductor devices in FIG. 1 are the same or similar, and therefore, a description thereof will not be repeated hereinafter.

[0057] FIG. 13A to FIG. 13D is a top view of a semiconductor device according to some embodiments of the present disclosure. Fig.13A, the semiconductor device includes metal gate structures 180aa, 180ab, 180ac, 180ba, and 180bb; gate structures 142ca, 142cb, 142cc, and 142cd; source / drain regions 102a, 102b, 102c, and 102d; and body regions 104a, 104b, 104c, and 104d. The metal gate structures 180aa, 180ab, 180ac, 180ba, and 180bb extend in the y direction, and the gate structures 142ca, 142cb, 142cc, and 142cd extend in the x direction. The metal gate structures 180aa, 180ab, and 180ac are located between the metal gate structures 180ba and 180bb. The gate structure 142ca is located between the metal gate structures 180aa and 180ba, the gate structure 142cb is located between the metal gate structures 180aa and 180ab, the gate structure 142cc is located between the metal gate structures 180ab and 180ac, and the gate structure 142cd is located between the metal gate structures 180ac and 180bb. Adjacent metal gate structures 180aa, 180ab, 180ac, 180ba, and 180bb have substantially the same gate spacing. That is, the distance P3 is substantially the same as the distance P4, the distance P4 is substantially the same as the distance P5, and / or the distance P5 is substantially the same as the distance P6. Source / drain regions 102a and 102b are located on opposite sides of metal gate structure 180aa, source / drain regions 102b and 102c are located on opposite sides of metal gate structure 180ab, and source / drain regions 102c and 102d are located on opposite sides of metal gate structure 180ac. Body regions 104a and 104b are located on opposite sides of metal gate structure 180aa, body regions 104b and 104c are located on opposite sides of metal gate structure 180ab, and body regions 104c and 104d are located on opposite sides of metal gate structure 180ac. Source / drain region 102a and body region 104a are located on opposite sides of gate structure 142ca, source / drain region 102b and body region 104b are located on opposite sides of gate structure 142cb, source / drain region 102c and body region 104c are located on opposite sides of gate structure 142cc, and source / drain region 102d and body region 104d are located on opposite sides of gate structure 142cd. Contacts 190 are located above source / drain regions 102a-102d and body regions 104a-104d, respectively.

[0058] Fig. 13B and Fig.13A The difference between the semiconductor devices in the embodiment relates to the gate structure 142cc (see Fig.13A ) exists. Fig. 13BIn FIG. 1 , the gate structure 142cc is omitted, so that the source / drain regions 102c and the body region 104c are electrically and physically connected (eg, by a metal alloy layer formed thereon). Fig. 13C and Fig.13A The difference between the semiconductor devices in FIG. 142 and FIG. 142 relates to gate structures 142cb and 142cd (see Fig.13A ) exists. Fig. 13C , gate structures 142cb and 142cd are omitted, so that the source / drain region 102b and the body region 104b are electrically and physically connected (e.g., by a metal alloy layer formed thereon), and the source / drain region 102d and the body region 104d are electrically and physically connected (e.g., by another metal alloy layer formed thereon). Fig.13D and Fig.13A The difference between the semiconductor devices in FIG. 142 relates to gate structures 142cb and 142cc (see Fig.13A ) exists. Fig.13D , gate structures 142cb and 142cc are omitted, so that the source / drain region 102b and the body region 104b are electrically and physically connected (e.g., by a metal alloy layer formed thereon), and the source / drain region 102c and the body region 104c are electrically and physically connected (e.g., by another metal alloy layer formed thereon). Figures 13A-13D Other relevant structural details of the semiconductor device in Fig. 10A The semiconductor devices in FIG. 1 are the same or similar, and therefore, a description thereof will not be repeated hereinafter.

[0059] Notice, Figures 13A-13D The arrangement of gate structures 142ca, 142cb, 142cc, and 142cd in is illustrative and should not limit the scope of the present disclosure. In some embodiments, at least one of gate structures 142ca, 142cb, 142cc, or 142cd is omitted, and the corresponding source / drain regions and body regions are electrically connected to each other.

[0060] Fig. 10A (or Fig. 12A ) can be applied to various integrated circuits / circuit units to increase wiring flexibility. Fig.14A is a layout diagram of an integrated circuit 300 without conductive traces according to some embodiments of the present disclosure, and Fig. 14Bis a layout diagram of an integrated circuit 300 with conductive traces according to some embodiments of the present disclosure. Integrated circuit 300 is an INVD1 circuit. The layout diagram of integrated circuit 300 includes active areas 318a and 318b; metal gate structures 380a and 380b; gate structures 342ca and 342cb; contact 390; and conductive traces VSS, VDD, T1, and ZN. Active areas 318a and 318b are spaced apart from each other. Gate structures 342ca and 342cb are located between one of metal gate structures 380b and metal gate structure 380a.

[0061] Source / drain region 302a and body region 304a are electrically connected to each other, source / drain region 302c and body region 304c are electrically connected to each other, source / drain regions 302a and 302b are located on opposite sides of metal gate structure 380a, body regions 304a and 304b are located on opposite sides of metal gate structure 380a, source / drain regions 302c and 302d are located on opposite sides of metal gate structure 380a, and body regions 304c and 304d are located on opposite sides of metal gate structure 380a. Source / drain region 302b and body region 304b are located on opposite sides of gate structure 342ca, and source / drain region 302d and body region 304d are located on opposite sides of gate structure 342cb. Contacts 390 are located above source / drain regions 302b and 302d and body regions 304a-304d, respectively. Conductive trace VDD is coupled to body regions 304 a and 304 b , conductive trace VSS is coupled to body regions 304 c and 304 d , conductive trace T1 is coupled to metal gate structure 380 a through vias 395 , and conductive trace ZN is coupled to source / drain regions 302 b and 302 d through contacts 390 .

[0062] Notice, Fig.14A and Fig. 14B The structure / material / formation process of the active regions 318a and 318b, the metal gate structures 380a and 380b, the gate structures 342ca and 342cb, and the contact 390 are similar to Fig. 10A The active region 118, metal gate structures 180a and 180b, gate structure 142c, and contact 190 in FIG. 1 are similar or identical, and therefore, a description thereof will not be repeated hereinafter.

[0063] Fig.15A is a layout diagram of an integrated circuit 400 without conductive traces according to some embodiments of the present disclosure, and Fig. 15B4 is a layout diagram of an integrated circuit 400 with conductive traces according to some embodiments of the present disclosure. Integrated circuit 400 is a ND2D1 circuit. The layout diagram of integrated circuit 400 includes active areas 418a and 418b; metal gate structures 480aa, 480ab, 480ba, and 480bb; gate structures 442ca, 442cb, and 442cc; contact 490; and conductive traces VSS, VDD, A1, A2, and ZN. Active areas 418a and 418b are spaced apart from each other. Gate structures 442ca and 442cb are located between metal gate structures 480aa and 480ab, and gate structure 442cc is located between metal gate structures 480ab and 480bb.

[0064] Source / drain region 402a and body region 404a are electrically connected to each other, source / drain region 402c and body region 404c are electrically connected to each other, and source / drain region 402d and body region 404d are electrically connected to each other. Source / drain region 402b and body region 404b are located on opposite sides of gate structure 442ca, source / drain region 402e and body region 404e are located on opposite sides of gate structure 442cb, and source / drain region 402f and body region 404f are located on opposite sides of gate structure 442cc. Contacts 490 are located above source / drain regions 402b and 402f and body regions 404a-404f, respectively. Conductive trace VDD is coupled to body regions 404a, 404b, and 404c, conductive trace VSS is coupled to body regions 404d, 404e, and 404f, conductive trace A1 is coupled to metal gate structure 480ab through one of vias 495, conductive trace A2 is coupled to metal gate structure 480aa through another of vias 495, and conductive trace ZN is coupled to source / drain regions 402b and 402f.

[0065] Notice, Fig.15A and Fig. 15B Active regions 418a and 418b in; metal gate structures 480aa, 480ab, 480ba and 480bb; gate structures 442ca, 442cb and 442cc; and the structure / material / formation process of contact 490 and Fig. 10A The active region 118, metal gate structures 180a and 180b, gate structure 142c, and contact 190 in FIG. 1 are similar or identical, and therefore, a description thereof will not be repeated hereinafter.

[0066] Fig.16A is a layout diagram of an integrated circuit 500 without conductive traces according to some embodiments of the present disclosure, and Fig. 16Bis a layout diagram of an integrated circuit 500 with conductive traces according to some embodiments of the present disclosure. Integrated circuit 500 is an AOI22D1 circuit. The layout diagram of integrated circuit 500 includes active areas 518a and 518b; metal gate structures 580aa, 580ab, 580ac, 580ad, 580ba, and 580bb; gate structures 542ca, 542cb, 542cc, 542cd, 542ce, and 542cf; contact 590; and conductive traces VSS, VDD, A1, A2, B1, B2, and ZN. Active areas 518a and 518b are spaced apart from each other. Gate structure 542ca is located between metal gate structures 580ba and 580aa, gate structure 542cb is located between metal gate structures 580ab and 580ac, gate structure 542cc is located between metal gate structures 580ad and 580bb, gate structure 542cd is located between metal gate structures 580aa and 580ab, gate structure 542ce is located between metal gate structures 580ab and 580ac, and gate structure 542cf is located between metal gate structures 580ac and 580ad.

[0067] The source / drain region 502b and the body region 504b are electrically connected to each other, the source / drain region 502d and the body region 504d are electrically connected to each other, the source / drain region 502f and the body region 504f are electrically connected to each other, and the source / drain region 502j and the body region 504j are electrically connected to each other. Source / drain region 502a and body region 504a are located on opposite sides of gate structure 542ca, source / drain region 502c and body region 504c are located on opposite sides of gate structure 542cb, source / drain region 502e and body region 504e are located on opposite sides of gate structure 542cc, source / drain region 502g and body region 504g are located on opposite sides of gate structure 542cd, source / drain region 502h and body region 504h are located on opposite sides of gate structure 542ce, and source / drain region 502i and body region 504i are located on opposite sides of gate structure 542cf. Contacts 590 are located over source / drain regions 502a, 502c, 502d, 502e, and 502h and body regions 504a-504j, respectively. Conductive trace VDD is coupled to body regions 504a, 504b, 504c, 504d, and 504e, conductive trace VSS is coupled to body regions 504f, 504g, 504h, 504i, and 504j, conductive trace A1 is coupled to metal gate structure 580ac through via 597, conductive trace 501, and via 595, conductive trace A2 is coupled to metal gate structure 580ad through another via 595, conductive trace B1 is coupled to metal gate structure 580ad through another via 597, conductive trace 501, and via 595, conductive trace A2 is coupled to metal gate structure 580ad through another via 595, conductive trace B1 is coupled to metal gate structure 580ac through another via 597, conductive trace 501, and via 595, conductive trace A2 is coupled to metal gate structure 580ad through another via 595, conductive trace B1 is coupled to metal gate structure 580ad through another via 597, conductive trace A2 ... Via 597, conductive trace 503, and another via 595 are coupled to metal gate structure 580ab, conductive trace B2 is coupled to metal gate structure 580aa through another via 595, conductive trace ZN is coupled to source / drain regions 502d and 502h through another via 597 and conductive traces 505 and 507, and source / drain region 502a is coupled to source / drain regions 502c and 502e through internal conductive trace 509. In some embodiments, conductive traces A2, B2, 501, 503, 505, 507, 509, VDD, and VSS may be in the same level (e.g., M0 level), and conductive traces A1, B1, and ZN may be in another level (e.g., M1 level).

[0068] Notice, Fig.16A and Fig. 16B The structure / material / formation process of the active regions 518a and 518b, the metal gate structures 580aa-580ad and 580ba-580bb, the gate structures 542ca-542cf, and the contact 590 are similar to Fig. 10AThe active region 118, metal gate structures 180a and 180b, gate structure 142c, and contact 190 in FIG. 1 are similar or identical, and therefore, a description thereof will not be repeated hereinafter.

[0069] Fig.17 6 is a layout diagram of an integrated circuit 600 according to some embodiments of the present disclosure. Integrated circuit 600 is an SDFQD1 circuit. Integrated circuit 600 includes a plurality of active regions (e.g., active region 618), metal gate structures (e.g., metal gate structures 680), gate structures (e.g., gate structures 642), contacts (e.g., contacts 690), and conductive traces (e.g., conductive traces VDD, VSS, D, SI, OP, SE, and Q). For example, Fig.17 As shown, the OD portion corresponds to the active area, the G1 portion corresponds to the metal gate structure, the G2 portion corresponds to the gate structure, the MD portion corresponds to the contact, the M0 portion corresponds to the conductive traces at the M0 level (e.g., conductive traces VDD and VSS), the V0 portion corresponds to the through-holes interconnecting the metal gate structure and the conductive traces at the M0 level, the M1 portion corresponds to the conductive traces at the M1 level (e.g., conductive traces D, SI, OP, SE, and Q), and the V1 portion corresponds to the through-holes interconnecting the conductive traces at the M0 and M1 levels.

[0070] The conductive trace VDD is coupled to some of the body regions in the active region, and the conductive trace VSS is coupled to the remaining body regions. Adjacent metal gate structures have substantially the same gate pitch, and the gate structures are respectively located between adjacent metal gate structures to form an H shape. The conductive traces may be at different levels (e.g., M0 and M1 levels). Fig.17 Other relevant structural details of the semiconductor device in Figure 10A-10E The semiconductor devices in FIG. 1 are the same or similar, and therefore, a description thereof will not be repeated hereinafter.

[0071] Fig.18 7 is a layout diagram of an integrated circuit 700 according to some embodiments of the present disclosure. The integrated circuit 700 includes a plurality of active regions (e.g., active region 718), metal gate structures (e.g., metal gate structures 780), gate structures (e.g., gate structures 742), contacts (e.g., contacts 790), and conductive traces (e.g., conductive traces VDD and VSS). For example, Fig.18As shown, the OD portion corresponds to the active area, the G1 portion corresponds to the metal gate structure, the G2 portion corresponds to the gate structure, the MD portion corresponds to the contact, the M0 portion corresponds to the conductive traces at the M0 level (for example, the conductive traces VDD and VSS), the V0 portion corresponds to the through-holes interconnecting the metal gate structure and the conductive traces at the M0 level, the M1 portion corresponds to the conductive traces at the M1 level, and the V1 portion corresponds to the through-holes interconnecting the conductive traces at the M0 and M1 levels.

[0072] The conductive trace VDD is coupled to some of the body regions in the active region, and the conductive trace VSS is coupled to the remaining body regions. In some embodiments, the conductive trace VDD has a fishbone structure. Adjacent metal gate structures have substantially the same gate spacing, and the gate structures are respectively located between adjacent metal gate structures to form an H shape. The conductive traces can be at different levels (e.g., M0 and M1 levels). Fig.18 Other relevant structural details of the semiconductor device in Figure 10A-10E The semiconductor devices in FIG. 1 are the same or similar, and therefore, a description thereof will not be repeated hereinafter.

[0073] Fig.19 is a flowchart of a method 1900 for generating an IC layout diagram according to some embodiments of the present disclosure. In some embodiments, generating an IC layout diagram includes generating the above reference Figure 14A to Figure 18 One of the layout diagrams 300, 400, 500, 600, or 700 discussed is manufactured based on the generated IC layout diagram. In some embodiments, generating the IC layout diagram is part of operating an IC manufacturing system as part of manufacturing IC devices (e.g., memory circuits, logic devices, processing devices, signal processing circuits, etc.).

[0074] In some embodiments, some or all of method 1900 is performed by a processor of a computer. In some embodiments, some or all of method 1900 is performed by a processor of a computer. Fig. 20 The processor 2002 of the IC device design system 2000 discussed above is executed. Some or all of the operations of the method 1900 can be performed as a computer program in a design studio (e.g., as described below). Fig.21 The design process performed in the design room 2120) discussed.

[0075] In some embodiments, the operation of method 1900 is to Fig.19 In some embodiments, the operations of method 1900 are performed simultaneously and / or in a sequence similar to that described in the description. Fig.19 In some embodiments, one or more operations are performed before, between, during, and / or after performing one or more operations of method 1900.

[0076] At operation 1910, a first gate structure is arranged on an active area. Arranging the first gate structure includes: arranging the first gate structure with a substantially constant gate spacing along the x-direction; and arranging the first gate structure as an intrinsic gate of a transistor. At operation 1920, a second gate structure is arranged between two adjacent first gate structures. Arranging the conductive portion of the second conductive layer includes: arranging the second gate structure as a non-intrinsic gate of a transistor. At operation 1930, in some embodiments, the source / drain region is arranged on the opposite side of one of the first gate structures. Arranging the source / drain region includes: arranging the source / drain region as a source / drain region of a transistor. At operation 1940, in some embodiments, the body region is arranged on the opposite side of the first gate structure. Arranging the body region includes arranging the body region as a body region of a transistor, and one of the body regions and one of the source / drain regions are located on opposite sides of the second gate structure.

[0077] At operation 1950, in some embodiments, an IC layout diagram is generated. The IC layout diagram includes a first gate structure, a second gate structure, a source / drain region, and a body region, arranged as discussed above with reference to operations 1910-1940. In some embodiments, generating the IC layout diagram includes: storing the IC layout diagram in a storage device. In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in a non-volatile computer-readable memory or a cell library such as a database, and / or includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in the storage device includes: storing the IC layout diagram in a non-volatile computer-readable memory or a cell library such as a database, and / or includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in the storage device includes: storing the IC layout diagram in a storage device via a memory device as described below with reference to Fig. 20 The network 2014 of the IC device design system 2000 discussed stores IC layout drawings.

[0078] In operation 1960, in some embodiments, at least one of one or more semiconductor masks or at least one component in a layer of a semiconductor device is manufactured based on the IC layout diagram. Fig.21 The manufacture of one or more semiconductor masks, or at least one component in a layer of a semiconductor device, is discussed.

[0079] In operation 1970, in some embodiments, one or more manufacturing operations are performed based on the IC layout diagram. In some embodiments, performing the one or more manufacturing operations includes performing one or more photolithography exposures based on the IC layout diagram. Fig.21 Discussion One or more manufacturing operations (eg, one or more photolithography exposures) are performed based on the IC layout.

[0080] By executing some or all of the operations of method 1900, an IC layout diagram and a corresponding semiconductor device (e.g., as shown in FIG. 1 ) are generated. Figure 1A-Figure 10E and Figure 12A-Figure 18 As discussed), various embodiments include an H-shaped gate structure, thereby improving the layout density of the semiconductor device.

[0081] Fig. 20 is a block diagram of an IC device design system 2000 according to some embodiments of the present disclosure. Fig.19 One or more operations of the discussed method 1900 may be implemented using the IC device design system 2000 according to some embodiments.

[0082] In some embodiments, IC device design system 2000 is a computing device that includes a hardware processor 2002 and a non-transitory computer-readable storage medium 2004. Non-transitory computer-readable storage medium 2004 is encoded with (i.e., stores) computer program code (i.e., a set of executable instructions 2006) (among other things). The hardware processor 2002 executes the instructions 2006 (at least in part) to represent the IC device design system, which implements, for example, the above-referenced Fig.19 Part or all of method 1900 (hereinafter, the proposed process and / or method) is discussed.

[0083] The processor 2002 is electrically coupled to the non-transitory computer-readable storage medium 2004 via a bus 2008. The processor 2002 is also electrically coupled to an I / O interface 2010 via the bus 2008. A network interface 2012 is also electrically connected to the processor 2002 via the bus 2008. The network interface 2012 is connected to a network 2014, so that the processor 2002 and the non-transitory computer-readable storage medium 2004 can be connected to external elements via the network 2014. The processor 2002 is configured to execute instructions 2006 encoded in the non-transitory computer-readable storage medium 2004 so that the IC device design system 2000 can be used to perform part or all of the proposed process and / or method. In one or more embodiments, the processor 2002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific IC (ASIC), and / or a suitable processing unit.

[0084] In one or more embodiments, the non-transitory computer-readable storage medium 2004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or device). For example, the non-transitory computer-readable storage medium 2004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In one or more embodiments using optical disks, the non-transitory computer-readable storage medium 2004 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0085] In one or more embodiments, the non-transitory computer-readable storage medium 2004 stores instructions 2006 configured to enable the IC device design system 2000 to perform a portion or all of the proposed process and / or method. In one or more embodiments, the non-transitory computer-readable storage medium 2004 also stores information that facilitates the execution of a portion or all of the proposed process and / or method. In various embodiments, the non-transitory computer-readable storage medium 2004 stores one or a combination of at least one IC layout design drawing 2020 or at least one design specification 222, each as described above with reference to Figure 1A-Figure 10E and Figure 12A-Figure 18 discussed.

[0086] The IC device design system 2000 includes an I / O interface 2010. The I / O interface 2010 is coupled to an external circuit. In various embodiments, the I / O interface 2010 includes one or a combination of a keyboard, a keypad, a mouse, a trackball, a trackpad, a display, a touch screen, and / or a cursor direction key, for transmitting information and commands to and / or from the processor 2002.

[0087] The IC device design system 2000 also includes a network interface 2012 coupled to the processor 2002. The network interface 2012 allows the IC device design system 2000 to communicate with a network 2014 (one or more other computer systems are connected to the network 2014). The network interface 2012 includes a wireless network interface (e.g., BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA); or a wired network interface (e.g., ETHERNET, USB, or IEEE-1364). In one or more embodiments, part or all of the proposed process and / or method is implemented in two or more systems 2000.

[0088] The IC device design system 2000 is configured to receive information through the I / O interface 2010. The information received through the I / O interface 2010 includes one or a combination of at least one design rule instruction, at least one standard set, at least one design rule, at least one DRM, and / or other parameters for processing by the processor 2002. The information is transmitted to the processor 2002 via the bus 2008. The IC device design system 2000 is configured to send and / or receive information related to the user interface via the I / O interface 2010.

[0089] In some embodiments, part or all of the proposed processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the proposed processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the proposed processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the proposed processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, a software application such as that available from CADENCEDESIGN SYSTEMS, Inc. is used. or other appropriate layout generation tools to generate IC layout drawings.

[0090] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs, RAMs, memory cards), etc. One or more.

[0091] Through can be used to achieve Fig.19 The IC device design system 2000 and the non-transitory computer-readable storage medium (eg, the non-transitory computer-readable storage medium 2004) implement the above-referenced method 1900 and Fig.19 Benefits of discussion.

[0092] Fig.21 21 is a block diagram of an IC manufacturing system 2100 and an IC manufacturing process associated therewith according to some embodiments of the present disclosure. In some embodiments, based on a layout design, the IC manufacturing system 2100 is used to manufacture at least one of (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor IC.

[0093] exist Fig.21In the embodiment, the IC manufacturing system 2100 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 2160, such as design room 2120, mask room 2130, and IC manufacturer / fabricator ("fab") 2150. The entities in the system 2100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design room 2120, mask room 2130, and IC manufacturer 2150 are owned by a single larger company. In some embodiments, two or more of the design room 2120, mask room 2130, and IC manufacturer 2150 coexist in a common facility and use common resources.

[0094] Design studio (or design team) 2120 Based on the above reference Figure 1A-Figure 10E and Figure 12A-Figure 18 Discussed Fig.19 The IC design layout diagram (or design) 2122 is generated using method 1900. The IC design layout diagram 2122 includes various geometric patterns that correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of the IC device 2160 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout diagram 2122 includes various IC features, such as active areas, gate electrodes, sources and drains, metal lines or vias for interconnecting between layers, and openings for bonding pads (to be formed on a semiconductor substrate (e.g., a silicon wafer) and various metal layers arranged on the semiconductor substrate). The design room 2120 implements appropriate design processes (including those described in reference to above). Figure 1A-Figure 10E and Figure 12A-Figure 18 Discussed Fig.19 The method 1900 of the present invention is used to form an IC design layout diagram 2122. The design process includes one or more of a logic design, a physical design, or a layout and routing. The IC design layout diagram 2122 is presented in one or more data files with geometric pattern information. For example, the IC design layout diagram 2122 can be expressed in a GDSII file format or a DFII file format.

[0095] The mask chamber 2130 includes data preparation 2132 and mask manufacturing 2144. The mask chamber 2130 uses the IC design layout drawing 2122 to manufacture one or more masks 2145 that will be used to manufacture various layers of the IC device 2160 based on the IC design layout drawing 2122. The mask chamber 2130 performs mask data preparation 2132, wherein the IC design layout drawing 2122 is converted into a representational data file ("RDF"). The mask data preparation 2132 provides the RDF to the mask manufacturing 2144. The mask manufacturing 2144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, for example, a mask (modulator) 2145 or a semiconductor wafer 2153. The design layout drawing 2122 is manipulated by the mask data preparation 2132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer 2150. In Fig.21 , mask data preparation 2132 and mask manufacturing 2144 are shown as separate elements. In some embodiments, mask data preparation 2132 and mask manufacturing 2144 are collectively referred to as mask data preparation.

[0096] In some embodiments, mask data preparation 2132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other processing effects, etc. OPC adjusts IC design layout 2122. In some embodiments, mask data preparation 2132 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0097] In some embodiments, mask data preparation 2132 includes a mask rule checker (MRC) that checks an IC design layout 2122 that has been processed in OPC using a set of mask creation rules that contain certain geometry and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 2122 to compensate for constraints during mask fabrication 2144, which may undo some of the modifications performed by the OPC in order to satisfy the mask creation rules.

[0098] In some embodiments, mask data preparation 2132 includes a lithography process check (LPC), which simulates a process that will be implemented by IC manufacturer 2150 to manufacture IC device 2160. LPC simulates the process based on IC design layout 2122 to create a simulated manufacturing device, such as IC device 2160. Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after the simulated manufacturing device has been created by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 2122.

[0099] It should be understood that the above description of mask data preparation 2132 has been simplified for clarity. In some embodiments, data preparation 2132 includes additional features such as logic operations (LOPs) to modify IC design layout 2122 according to manufacturing rules. In addition, the processing applied to IC design layout 2122 during data preparation 2132 can be performed in a variety of different orders.

[0100] After mask data preparation 2132 and during mask manufacturing 2144, a mask 2145 or a set of masks 2145 are manufactured based on the modified IC design layout 2122. In some embodiments, mask manufacturing 2144 includes performing one or more photolithography exposures based on the IC design layout 2122. In some embodiments, an electron beam (e-beam) or a plurality of e-beam mechanisms are used to form a pattern on a mask (photomask or reticle) 2145 based on the modified IC design layout 2122. The mask 2145 can be formed using various techniques. In some embodiments, the mask 2145 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) that has been coated on a wafer is blocked by the opaque area and passes through the transparent area. In one example, a binary mask version of mask 2145 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 2145 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 2145, various features in a pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The (one or more) masks generated by mask manufacturing 2144 are used in various processes. For example, such (one or more) masks are used in ion implantation processes to form various doped regions in semiconductor wafer 2153, are used in etching processes to form various etched regions in semiconductor wafer 2153, and / or are used in other suitable processes.

[0101] IC manufacturer 2150 includes wafer fabrication 2152. IC manufacturer 2150 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturer 2150 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing of multiple IC products (front-end (FEOL) manufacturer), while a second manufacturing facility may provide back-end manufacturing for interconnection and packaging of IC products (back-end (BEOL) manufacturer), and a third manufacturing facility may provide other services for the foundry business.

[0102] The IC manufacturer 2150 uses (one or more) masks 2145 manufactured by the mask chamber 2130 to manufacture the IC device 2160. Therefore, the IC manufacturer 2150 at least indirectly uses the IC design layout 2122 to manufacture the IC device 2160. In some embodiments, the semiconductor wafer 2153 is manufactured by the IC manufacturer 2150 using (one or more) masks 2145 to form the IC device 2160. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based at least indirectly on the IC design layout 2122. The semiconductor wafer 2153 includes a silicon substrate or other suitable substrate having a material layer formed thereon. The semiconductor wafer 2153 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0103] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages in this article, and no specific advantages are required for all embodiments. One advantage is that the metal gate structure (i.e., the intrinsic gate) has a constant gate spacing and a constant width. In this way, the density of the transistor can be increased. Another advantage is that the gate structure (i.e., the non-intrinsic gate) is used as a mask to implant the source / drain region and the body region so that the source / drain region and the body region can be spaced apart from each other. In addition, the intrinsic gate and the non-intrinsic gate can be patterned together so that the non-intrinsic gate does not complicate the manufacturing process for forming the semiconductor device. In addition, the intrinsic gate and the non-intrinsic gate are spaced apart from each other, and the non-intrinsic gate is floating. With such a configuration, the non-intrinsic gate eliminates the floating body effect and does not affect the electrical properties of the adjacent source / drain region and the body region.

[0104] According to some embodiments, a semiconductor device includes: a source / drain region, a body region, a first gate structure, and a second gate structure. The source / drain region and the body region are located in a substrate. The first gate structure and the second gate structure are located above the substrate. The source / drain region and the body region are located on opposite sides of the first gate structure. The second gate structure is spaced apart from the first gate structure. The source / drain region, the body region, and the first gate structure are located on the same side of the second gate structure.

[0105] According to some embodiments, a semiconductor device includes: an active region, a first gate structure, and a second gate structure. The active region includes a first source / drain region and a second source / drain region and a first body region and a second body region. The first source / drain region and the second source / drain region are spaced apart from each other, and the first body region and the second body region are spaced apart from each other. The first gate structure is located above the active region and between the first source / drain region and the first body region. The second gate structure is located above the active region and between the first body region and the second body region.

[0106] According to some embodiments, a method for manufacturing a semiconductor device includes: forming an active region in a substrate. Forming a first gate structure and a second gate structure above the active region. The first gate structure and the second gate structure include the same material and extend in different directions. Forming a source / drain region and a first body region in the active region and on opposite sides of the first gate structure. Replacing the second gate structure with a third gate structure. The first gate structure and the third gate structure include different materials.

[0107] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments or examples introduced herein and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0108] Example 1. A semiconductor device comprising: a source / drain region located in a substrate; a body region located in the substrate; a first gate structure located above the substrate, wherein the source / drain region and the body region are located on opposite sides of the first gate structure; and a second gate structure located above the substrate and spaced apart from the first gate structure, wherein the source / drain region, the body region and the first gate structure are located on the same side of the second gate structure.

[0109] Example 2. The semiconductor device of Example 1, wherein the first gate structure and the second gate structure include different materials.

[0110] Example 3. The semiconductor device of Example 1, wherein the second gate structure includes metal and the first gate structure does not contain metal.

[0111] Example 4. The semiconductor device of Example 1, wherein the first gate structure and the second gate structure extend in different directions.

[0112] Example 5. The semiconductor device of Example 1, wherein the second gate structure extends in a first direction, and the source / drain regions and the body region are arranged along the first direction.

[0113] Example 6. The semiconductor device according to Example 1 further includes: a spacer structure located between the first gate structure and the second gate structure.

[0114] Example 7. The semiconductor device of Example 6, wherein the spacer structure contacts the first gate structure and the second gate structure.

[0115] Example 8. The semiconductor device of Example 1 further includes: a dummy gate structure, wherein the source / drain region, the body region, and the first gate structure are located between the dummy gate structure and the second gate structure.

[0116] Example 9. The semiconductor device of Example 8, wherein the dummy gate structure and the first gate structure comprise different materials.

[0117] Example 10. The semiconductor device of Example 8, wherein the first gate structure and the second gate structure are floating.

[0118] Example 11. A semiconductor device, comprising: an active region, comprising: a first source / drain region and a second source / drain region, the first source / drain region and the second source / drain region being spaced apart from each other; and a first body region and a second body region, the first body region and the second body region being spaced apart from each other; a first gate structure, located above the active region and between the first source / drain region and the first body region; and a second gate structure, located above the active region and between the first body region and the second body region.

[0119] Example 12. The semiconductor device of Example 11, wherein the second gate structure is further located between the first source / drain region and the second source / drain region.

[0120] Example 13. The semiconductor device of Example 11, wherein the first gate structure and the second gate structure include different materials.

[0121] Example 14. The semiconductor device of Example 11, further comprising: a metal alloy layer in contact with the second source / drain region and the second body region.

[0122] Example 15. The semiconductor device of Example 11, wherein the active region has opposite sides, and the second gate structure extends beyond the opposite sides of the active region.

[0123] Example 16. A method for manufacturing a semiconductor device, comprising: forming an active region in a substrate; forming a first gate structure and a second gate structure above the active region, wherein the first gate structure and the second gate structure comprise the same material and extend in different directions; forming a source / drain region and a first body region in the active region and on opposite sides of the first gate structure; and replacing the second gate structure with a third gate structure, wherein the first gate structure and the third gate structure comprise different materials.

[0124] Example 17. The method of Example 16, wherein the first gate structure is free of metal.

[0125] Example 18. The method of Example 16, wherein the third gate structure comprises metal.

[0126] Example 19. The method of Example 16, further comprising: forming a second body region in the active region such that the first body region and the second body region are located on opposite sides of the second gate structure.

[0127] Example 20. The method of Example 16 further includes: forming a spacer structure, wherein the spacer structure is located between the first gate structure and the second gate structure and contacts the first gate structure and the second gate structure.

Claims

1. A semiconductor device, include: a source / drain region, located in the substrate; a body region located in the substrate; a first gate structure located above the substrate, wherein the source / drain regions and the body region are located on opposite sides of the first gate structure; and a second gate structure located above the substrate and spaced apart from the first gate structure, wherein the source / drain region, the body region, and the first gate structure are located on a same side of the second gate structure, The second gate structure includes metal, and the first gate structure does not contain metal.

2. The semiconductor device according to claim 1, in, The first gate structure and the second gate structure include different materials.

3. The semiconductor device according to claim 1, in, The first gate structure and the second gate structure extend in different directions.

4. The semiconductor device according to claim 1, in, The second gate structure extends in a first direction, and the source / drain regions and the body region are arranged along the first direction.

5. The semiconductor device according to claim 1, further comprising: include: The spacer structure is located between the first gate structure and the second gate structure.

6. The semiconductor device according to claim 5, in, The spacer structure contacts the first gate structure and the second gate structure.

7. The semiconductor device according to claim 1, further comprising: include: A dummy gate structure, wherein the source / drain region, the body region, and the first gate structure are located between the dummy gate structure and the second gate structure.

8. The semiconductor device according to claim 7, in, The dummy gate structure and the first gate structure include different materials.

9. The semiconductor device according to claim 7, in, The first gate structure and the second gate structure are floating.

10. A semiconductor device, include: Active areas include: a first source / drain region and a second source / drain region, the first source / drain region and the second source / drain region being spaced apart from each other; and a first body region and a second body region, the first body region and the second body region being spaced apart from each other; a first gate structure located above the active region and between the first source / drain region and the first body region; a second gate structure located above the active region and between the first body region and the second body region; and A metal alloy layer is in contact with the second source / drain region and the second body region.

11. The semiconductor device according to claim 10, in, The second gate structure is further located between the first source / drain region and the second source / drain region.

12. The semiconductor device according to claim 10, in, The first gate structure and the second gate structure include different materials.

13. The semiconductor device according to claim 10, in, The active region has opposite sides, and the second gate structure extends beyond the opposite sides of the active region.

14. A method for manufacturing a semiconductor device, include: forming an active region in a substrate; forming a first gate structure and a second gate structure over the active region, wherein the first gate structure and the second gate structure comprise the same material and extend in different directions; forming source / drain regions and a first body region in the active region and on opposite sides of the first gate structure; and The second gate structure is replaced with a third gate structure, wherein the first gate structure and the third gate structure include different materials.

15. The method according to claim 14, in, The first gate structure does not contain metal.

16. The method according to claim 14, in, The third gate structure includes metal.

17. The method according to claim 14, further comprising: include: A second body region is formed in the active region such that the first body region and the second body region are located on opposite sides of the second gate structure.

18. The method according to claim 14, further comprising: include: A spacer structure is formed between and in contact with the first gate structure and the second gate structure.

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