Integrated circuit device and method for manufacturing the same

Abstract

Various embodiments of the present disclosure relate to an integrated circuit device and a method for manufacturing the same. A dielectric composite that fills the area between resistance switching random access memory cells and changes height to align with the top of both the taller resistance switching random access memory cells and the shorter resistance switching random access memory cells is used to solve the problem of forming a top electrode via that provides consistent results in a device including resistance switching random access memory cells of different heights. An etch stop layer can be formed over the dielectric composite to provide an equal thickness of etch-resistant dielectric over both the taller resistance switching random access memory cells and the shorter resistance switching random access memory cells. The dielectric composite extends the etch stop layer laterally away from the resistance switching random access memory cells to maintain separation between the via opening and the side of the resistance switching random access memory cells even when the via opening is misaligned.

Description

Technical Field

[0001] Some embodiments of the present application relate to an integrated circuit device and a method for manufacturing the same. Background Art

[0002] Resistance switching random access memory (RSR) has a simple structure, low operating voltage, high speed, good durability and complementary metal oxide semiconductor (CMOS) process compatibility. RSR is the most promising alternative to provide a small-scale alternative to traditional flash memory. RSR is widely used in devices such as optical disks and non-volatile memory arrays.

[0003] A resistive switching RAM cell stores data in a material layer that can be induced to undergo a phase change. A phase change can be induced in all or part of the layer to switch between a high resistance state and a low resistance state. The resistance state can be queried and interpreted as representing a "0" or a "1". In a typical resistive switching RAM cell, the data storage layer comprises an amorphous metal oxide. When sufficient voltage is applied, a metal bridge is induced to form across the data storage layer, which results in a low resistance state. The metal bridge can be destroyed and the high resistance state restored by applying a short, high current density pulse that melts or otherwise destroys all or part of the metal structure. The data storage layer cools rapidly and remains in a high resistance state until a low resistance state is induced again. Summary of the invention

[0004] Some embodiments of the present application provide an integrated circuit (IC) device, comprising: a substrate; a metal interconnect structure formed on the substrate; a plurality of resistance switching random access memory (resistance switching RAM) cells formed within the metal interconnect structure, each of the plurality of resistance switching random access memory cells comprising a bottom electrode, a top electrode, and a resistance switching structure located between the bottom electrode and the top electrode; and a via connecting the top electrode to the metal interconnect structure, wherein the via passes through a low dielectric constant dielectric layer; wherein the plurality of resistance switching random access memory cells comprise a smaller cell and a larger cell; the smaller cell is shorter in height than the larger cell; and any dielectric layer separating the top electrode from the low dielectric constant dielectric layer has an equal thickness over the larger cell and the smaller cell.

[0005] In addition, other embodiments of the present application provide an integrated circuit (IC) device, comprising: a substrate; a metal interconnect structure formed on the substrate; a plurality of resistance switching random access memory (resistance switching RAM) cells formed within the metal interconnect structure, each of the plurality of resistance switching random access memory cells comprising a bottom electrode, a top electrode, and a resistance switching structure located between the bottom electrode and the top electrode; and a via connecting the top electrode to the metal interconnect structure, wherein the via passes through a low-k dielectric layer and an etch stop layer; wherein the plurality of resistance switching random access memory cells comprise smaller cells and larger cells; the etch stop layer is located between the low-k dielectric layer and the resistance switching random access memory cells; the smaller cells are lower in height than the larger cells; and for each of the plurality of resistance switching random access memory cells, the etch stop layer extends laterally away from the resistance switching random access memory cell, including any sidewall spacers associated with the resistance switching random access memory cell.

[0006] In addition, other embodiments of the present application provide a method for manufacturing an integrated circuit (IC) device, comprising: forming a metal interconnect layer over a semiconductor substrate including a storage area and a peripheral area; forming a resistance switching random access memory (resistance switching RAM) cell over the metal interconnect layer in the storage area, wherein the resistance switching random access memory cell includes a taller cell and a shorter cell; depositing a first dielectric layer over the resistance switching random access memory cell; depositing a second dielectric layer over the first dielectric layer; and performing chemical mechanical polishing to leave a surface including a top electrode of the taller cell, a top electrode of the shorter cell, and the second dielectric layer in an area between the resistance switching random access memory cells; wherein the chemical mechanical polishing causes the taller cell to be higher than the shorter cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present teachings will be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A cross-sectional view of an integrated circuit (IC) having a resistance-switching RAM cell according to some aspects of the present teachings is shown.

[0009] Figure 2 Another cross-sectional view of an integrated circuit (IC) having a resistance-switching RAM cell according to some aspects of the present teachings is shown.

[0010] Figures 3 to 20 A series of cross-sectional views showing an integrated circuit according to some aspects of the present teachings undergoing a manufacturing process according to some aspects of the present teachings.

[0011] Fig.21A A possible layout of an array of resistance-switching RAM cells in a device according to the present teachings is shown.

[0012] Fig. 21B Another possible layout of an array of resistance-switching RAM cells in a device according to the present teachings is shown.

[0013] Fig. 22 A flow chart of a manufacturing process according to some aspects of the present teachings is presented. DETAILED DESCRIPTION

[0014] This teaching provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact.

[0015] One challenge in manufacturing devices with resistance switching RAM is forming vias that land on the top electrodes of the resistance switching RAM cells. An etch stop layer may be deposited over the resistance switching RAM cells and used when forming the openings for the vias through the interlayer dielectric layer that covers the resistance switching RAM cells. The alignment of the openings with the resistance switching RAM cells is not perfect, and the openings may extend over the edges of some resistance switching RAM cells. If the etch stop layer conforms to the shape of the resistance switching RAM cells, etching to expose the electrodes at the top of the resistance switching RAM cells may etch through the sides of some resistance switching RAM cells and cause defects.

[0016] When the resistance switching RAM cells are provided in different sizes, the challenges of forming the via openings increase. When the resistance switching RAM cells are provided in different sizes, the resistance switching RAM cell height may vary due to etch loading effects. The height variation may result in a thickness variation of the dielectric above the resistance switching RAM cell.

[0017] According to the present teachings, the problem of forming a top electrode via that provides consistent results in a device including resistance switching RAM cells of different heights is solved using a dielectric composite that fills the area between resistance switching random access memory cells and varies in height to align with the top of both the taller resistance switching RAM cells and the shorter resistance switching RAM cells. An etch stop layer can be formed over the dielectric composite to provide an equal thickness of etch resistant dielectric over the taller resistance switching RAM cells and the shorter resistance switching RAM cells. The dielectric composite extends the etch stop layer laterally away from the resistance switching RAM cells to maintain separation between the via opening and the resistance switching RAM cell side even when the via opening is misaligned.

[0018] In some aspects of the present teachings, the dielectric composite includes a first dielectric layer and a second dielectric layer. The second dielectric layer is not adjacent to the resistance switching RAM cell, but is found in a region between the resistance switching RAM cell and is spaced apart from the resistance switching RAM cell. The second dielectric layer is found along a diagonal between cells in the resistance switching RAM cell array. The second dielectric layer rests on top of the first dielectric layer and has an upper surface that is substantially aligned with the top of the shorter resistance switching RAM cell. This second dielectric layer can control a chemical mechanical polishing (CMP) process performed prior to forming an etch stop layer. The CMP process can cause the dielectric composite to be sufficiently recessed to expose the tops of both the higher resistance switching RAM cell and the shorter resistance switching RAM cell. The second dielectric layer can prevent the CMP process from causing the electrode to be dished or the dielectric composite to be overly recessed in a region adjacent to the resistance switching RAM cell.

[0019] In a process according to the present teachings, after forming a resistance switching RAM cell, a first dielectric layer is conformally formed over the resistance switching RAM cell. The first dielectric layer can be produced by plasma enhanced atomic layer deposition or another process that allows precise control of the layer thickness. A second dielectric layer can then be deposited over the first dielectric layer. In some of these teachings, the total thickness of the first and second dielectric layers is slightly less than the height of the smaller resistance switching RAM cell, but less than the amount of thickness below the top electrode of the smaller resistance switching RAM cell. Spin coating can be used to provide a flat upper surface, and a non-selective etch-back process can be used to thin the dielectric composite and make its upper surface flatter. The etch-back process can remove the second dielectric layer from the area above the resistance switching RAM cell. A CMP process can then be implemented to expose the top electrodes of both the smaller resistance switching RAM cell and the larger resistance switching RAM cell without significantly recessing the sidewall spacers of the larger resistance switching RAM cell.

[0020] Figure 1A cross-sectional view of a portion of an integrated circuit device 100 including a memory cell 107 according to some aspects of the present teachings is shown. Each memory cell 107 includes a bottom electrode 125, a metal tunneling junction (MTJ) 140, and a top electrode 111. The MTJ 140 includes a first ferromagnet 123, an insulator 121, and a second ferromagnet 119. A first sidewall spacer 115 is formed around the resistance switching RAM cell 107 at the level of the top electrode 111. A second spacer 117 is formed around the resistance switching RAM cell 107 outside the first sidewall spacer 115 and extends downward over the sides of the MTJ 140. The resistance switching RAM cell 107 is surrounded by a dielectric fill layer 113. A dielectric top layer 112 is formed over the dielectric fill layer 113 in a region laterally spaced apart from the resistance switching RAM cell 107. An etch stop layer 109 is disposed over the dielectric top layer 112, the dielectric fill layer 113, and the top electrode 111.

[0021] The top electrode 111 is coupled to the metal feature 101 in the metal interconnect layer 149 through the top electrode vias 105, 151. The metal feature 101 and the top electrode vias 105, 151 are surrounded by the interlayer dielectric layer 103. In some of these teachings, the interlayer dielectric layer 103 is a low dielectric constant (κ) dielectric layer. In some of these teachings, the interlayer dielectric layer 103 is an extremely low dielectric constant dielectric layer. The top electrode vias 105, 151 pass through the dielectric layer 103 and the etch stop layer 109 before landing on the top electrode 111. The bottom electrode 125 is coupled to the metal feature 141 in the metal interconnect layer 135 through the bottom electrode via 127. The bottom electrode via 127 is surrounded by the etch stop layer 137 and the interface layer 139. The metal feature 141 is surrounded by the matrix of the interlayer dielectric 143.

[0022] Figure 2 A cross-sectional view 200 of another portion of the integrated circuit device 100 is shown. The cross-sectional view 200 focuses on the area from the metal interconnect layer 135 to the metal interconnect layer 149, and includes a portion of the first storage area 129 including the resistance switching RAM cell 107, a portion of the second storage area 131 including the resistance switching RAM cell 153, and a portion of the peripheral area 133. The resistance switching RAM cell 107 shown may be one of the first array of resistance switching RAM cells, and the resistance switching RAM cell 153 shown may be one of the second array of resistance switching RAM cells. The height 110 of the resistance switching RAM cell 107 is greater than the height 114 of the resistance switching RAM cell 153.

[0023] The difference between height 114 and height 110 may be attributed to the difference in thickness between the top electrode 111 of the resistive switching RAM cell 107 and the top electrode 111 of the resistive switching RAM cell 153. The other layers of these resistive switching RAM cells 107, 153 may have equal thickness. The resistive switching RAM cells 107, 153 are aligned at their bottoms, where the difference between height 114 and height 110 is equal to the difference in distance between the top of the resistive switching RAM cell 107 and the resistive switching RAM cell 153 from the substrate 202. In some of these teachings, the difference between height 114 and height 110 is of the same order of magnitude as the thickness of the etch stop layer 109. In some of these teachings, the difference between height 114 and height 110 is one-half or more than one-half the thickness of the etch stop layer 109.

[0024] The combination of the thickness 142h of the dielectric fill layer 113 and the thickness 144 of the dielectric top layer 112 is slightly less than or equal to the height 114 of the resistance switching RAM cell 153. Therefore, except in the immediate vicinity of the taller resistance switching RAM cell (e.g., the resistance switching RAM cell 107), the upper surface 142 of the dielectric top layer 112 is substantially aligned with the upper surface 138 of the resistance switching RAM cell 153. Even around the resistance switching RAM cell 107, the dielectric top layer 112 drops down to a height where its upper surface 142 is substantially aligned with the top of the shorter resistance switching RAM cell 153 and flattens out.

[0025] Fig.21A 1 shows a top view of an array of memory cells 107 in device 100. Memory cells 107 are shown as square, but the edges may be rounded. Memory cells 107, 153 may also be disk-shaped, or have another shape in accordance with the present teachings. Fig.21A As shown, in some embodiments, the dielectric top layer 112 is spaced apart from the memory cells 107 and forms islands along diagonal lines between cells in the array of memory cells 107 . Fig. 21B An alternative layout 2101 is provided for the case where the memory cells 107 are circular. In the alternative layout 2101, the dielectric top layer 112 is still spaced apart from the memory cells 107 and located in the areas between the memory cells 107, but due to the difference in size, the dielectric top layer 112 is not limited to the diagonal lines between the memory cells in the array.

[0026] Reference again Figure 1, metal interconnect layer 135 and metal interconnect layer 149 are part of a metal interconnect structure 218 disposed on substrate 202. Metal interconnect layer 135 may be a third metal interconnect layer on substrate 202, and metal interconnect layer 149 may be a fourth metal interconnect layer. Metal interconnect structure 218 also includes first metal interconnect layer 108, metal interconnect layer 118, and may include additional interconnect layers above the illustrated interconnect layers. In some of these teachings, as shown, memory cells 107, 153 are located between metal interconnect layer 135 and metal interconnect layer 149. In some of these teachings, memory cells 107, 153 are located between metal interconnect layer 149 and a fifth metal interconnect layer. In general, memory cells 107, 153 may be located between any adjacent pair of metal interconnect layers.

[0027] The substrate 202 may be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate, or the like. One or more shallow trench isolation (STI) regions 204 or oxide-filled trenches may be provided in or on the substrate 202. A pair of word line transistors 206 may be located between the shallow trench isolation regions 204. The word line transistors 206 may include a gate 210 that may function as a word line. The gate 210 is separated from the substrate 202 by a word line dielectric layer 212. Source / drain regions 214, 216 of the word line transistors 206 may be formed in or on the substrate 202. Metal features 217 in the metal interconnect layer 118 or elsewhere in the metal interconnect structure 218 may be coupled to the source / drain regions 216 and function as source lines. The bottom electrode 125 may be coupled to the source / drain regions 214 through the via 203. Metal features 101 in metal interconnect layer 149 or some other metal interconnect layer above memory cell 107 may be used as bit lines. The illustrated control structure of memory cells 107, 153 in integrated circuit device 100 is one of many possible control structures that may be used to connect and operate memory cells 107, 153. Integrated circuit devices according to the present teachings are not limited in terms of control structures.

[0028] The metal interconnect structure 218 is a product of back-end-of-line (BEOL) processing. The metal interconnect layers 108, 118, 135, 149 and the metal features 101, 141, 217 of the vias 105, 127, 151, 203 may be formed of metals such as copper, aluminum, gold, tungsten, titanium nitride, or the like. The interlayer dielectric layers 103, 143 may be low-k dielectrics or very low-k dielectrics. Low-k dielectrics are materials with a dielectric constant less than that of SiO2. The dielectric constant of SiO2 is about 3.9. Examples of low-k dielectrics include organosilicate glass (OSG), such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also known as fluorinated silica glass (FSG)), organic polymer low-k dielectrics, and porous silicate glass. Very low dielectric constant dielectrics are materials with a dielectric constant of about 2.1 or less. Very low dielectric constant dielectric materials are generally low dielectric constant dielectric materials formed into a porous structure. Porosity reduces the effective dielectric constant.

[0029] Each layer in the memory cells 107, 153 may include multiple layers having various compositions. The bottom electrode via 127 may be titanium nitride or a similar material, or another suitable conductive material. In some examples, the thickness of the bottom electrode via 127 is between about To date The diffusion barrier layer may separate the bottom electrode via 127 from the metal feature 141. The barrier layer may be, for example, tantalum nitride or the like. In some examples, the thickness of the barrier layer is between about To date within the range.

[0030] The bottom electrode 125 is a conductive material such as tantalum, titanium, platinum, gold, iridium, tungsten, nickel, ruthenium, copper, titanium nitride, tantalum nitride, tungsten silicide, combinations thereof, etc. In some of these teachings, the thickness of the bottom electrode 125 is between about To date In some of these teachings, the thickness of the bottom electrode 125 is between about To date These exemplary thicknesses and other exemplary dimensions given herein are for a certain manufacturing node. For other manufacturing nodes, the exemplary dimensions may be scaled accordingly.

[0031] The first ferromagnetic body 123 and the second ferromagnetic body 119 of the MTJ 140 are ferromagnetic materials. The ferromagnetic materials include cobalt-iron-boron (Co xThe first ferromagnet 123 and the second ferromagnet 119 may be made of different materials. In some embodiments, both the first ferromagnet 123 and the second ferromagnet 119 are Co x Fe y B z , but the atomic ratio (x, y, z) between the first ferromagnet 123 and the second ferromagnet 119 may be different. The first ferromagnet 123 and the second ferromagnet 119 may be formed by any suitable process. Examples of suitable processes may include electroplating, electroless plating, sputtering, chemical vapor deposition (CVD), or another applicable process.

[0032] The insulator 121 is a dielectric layer. Examples of materials that can be used for the insulator 121 include magnesium oxide (MgO), aluminum oxide (Al x O y ), titanium oxide (TiO x ), or similar materials. In some embodiments, the insulator 121 is magnesium oxide. The insulator 121 can be formed by any suitable process. Suitable processes can be chemical vapor deposition (CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), spin coating, or similar processes.

[0033] A top electrode 111 is disposed over the MTJ 140. The top electrode 111 may include a liner formed of tungsten or the like. The top electrode 111 may include one or more layers of a metal or metal compound, such as titanium, titanium nitride, tantalum, tantalum nitride, or the like. In some of these teachings, the thickness of the top electrode 111 in the larger resistance switching RAM cell 107 is between about 1000 Å and about 5000 Å. To date In some of these teachings, the thickness of the top electrode 111 in the larger resistance switching RAM cell 107 is between about To date within the range.

[0034] In some of these teachings, the thickness of the top electrode 111 in the lower resistance switching RAM cell 153 is about To date is less than its thickness in the larger resistance switching RAM cell 107. In some of these teachings, the thickness of the top electrode 111 in the smaller resistance switching RAM cell 153 is about To date Less than its thickness in the larger resistance switching RAM cell 107. In some of these teachings, the thickness of the top electrode 111 in the smaller resistance switching RAM cell 153 is 90% or less than its thickness in the larger resistance switching RAM cell 107. In some of these teachings, the thickness of the top electrode 111 in the smaller resistance switching RAM cell 153 is 80% or less than its thickness in the larger resistance switching RAM cell 107.

[0035] During operation of the memory cell 107, 153, a voltage is applied between the top electrode 111 and the bottom electrode 125. Depending on the voltage applied, the voltage can be used to assess whether the memory cell 107 is in a low resistance state or a high resistance state, or to place the memory cell 107, 153 in a high resistance state or a low resistance state.

[0036] MTJ 140 is a resistance switching structure associated with a resistance switching random access memory. Memory cells 107, 153 may be any type of resistance switching random access memory. Examples of resistance switching random access memory include, but are not limited to, oxygen shift memory (oxygen random access memory (OxRAM)), conductive bridging random access memory (CBRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase-change memory (PCM), carbon nanotube random access memory (NRAM), or the like. Various layers of various thicknesses and compositions may replace MTJ 140 in memory cells 107, 153 to provide resistance switching structures associated with these various types of resistance switching random access memories. For example, instead of the MTJ 140 , the memory cells 107 , 153 may include an amorphous oxide layer that reversibly forms a conductive bridge, and may also include an active metal layer that alternately supplies and receives ions from the amorphous oxide layer.

[0037] Figures 3 to 20 A series of cross-sectional views 300 through 2000 are provided showing an integrated circuit device according to the present teachings at various stages of fabrication according to a process according to the present teachings. Figures 3 to 20The description is made with respect to a series of actions, but it will be understood that in some cases, the order of the actions may be changed and that the series of actions may be applied to structures other than those shown. In some embodiments, some of these actions may be omitted in whole or in part. Furthermore, it will be understood that Figures 3 to 20 The illustrated structure is not limited to the manufacturing method but may exist independently as a structure separate from the method.

[0038] like Figure 3 As shown in the cross-sectional view 300 of , an etch stop layer 137 and an interface layer 139 are formed on the metal interconnect layer 135. The metal interconnect layer 135 can be formed by any suitable process. Examples of suitable processes include a damascene process and a dual damascene process. The etch stop layer 137 can be, for example, silicon carbide (SiC), or the like. The interface layer 139 can be, for example, silicon dioxide (SiO2). These layers can also be or include other dielectrics, such as silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or the like. The combined thickness of the etch stop layer 137 and the interface layer 139 can be between 1000 and 2000. arrive In some embodiments, the combined thickness of the etch stop layer 137 and the interface layer 139 is between arrive In some embodiments, the combined thickness of the etch stop layer 137 and the interface layer 139 is less than For example The etch stop layer 137 and the interface layer 139 may be formed by any suitable process or combination of processes.

[0039] like Figure 4 As shown in the cross-sectional view 400 of FIG. 4 , a mask 403 may be formed over the etch stop layer 137 and the interface layer 139, and the mask 403 may be used to form an opening 401 through the etch stop layer 137 and the interface layer 139. The opening 401 is located over the metal feature 141 of the metal interconnect layer 135. The mask 403 may be a photoresist mask patterned using photolithography. The opening 401 may be formed using any suitable etching process, such as plasma etching.

[0040] like Figure 5 As shown in the cross-sectional view 500 of , the mask 403 may be stripped and a conductive material layer 501 may be deposited to fill the opening 401. Figure 6 As shown in the cross-sectional view 600 of , the conductive material layer 501 may be planarized to form the through hole 127. As previously described, a diffusion barrier layer may be deposited before the bulk of the material layer 501. The conductive material layer 501 may be formed by any suitable growth or deposition process. The planarization process may be chemical mechanical polishing (CMP) or any other suitable planarization process.

[0041] like Figure 7 As shown in the cross-sectional view 700, the Figure 6 A resistive switching RAM cell stack 701 is formed on the surface of the structure shown in the cross-sectional view 600 of FIG. In this example, the resistive switching RAM cell stack 701 includes a bottom electrode layer 713, an MTJ layer 705, and a top electrode layer 703. The MTJ layer 705 includes a first ferromagnetic layer 711, an insulating layer 709, and a second ferromagnetic layer 707. The bottom electrode layer 713, the various layers of the MTJ layer 705, and the top electrode 111 can be formed by any suitable process or combination of processes. In some of these teachings, the thickness of the resistive switching RAM cell stack 701 is between about To date In some of these teachings, the thickness of the resistive switching RAM cell stack 701 is between about To date within the range.

[0042] like Figure 8 As shown in the cross-sectional view 800 of FIG. 8 , a mask 801 may be formed over the resistive switching RAM cell stack 701, and the mask 801 may be used to pattern the top electrode layer 703 to define the top electrode 111 of the resistive switching RAM cell 107, 153. The patterning may use any suitable etching process, such as plasma etching, or the like. In some embodiments, the MTJ layer 705 or another resistive switching structure is used as an etch stop for this process.

[0043] like Fig. 9 As shown in the cross-sectional view 900 of , a first sidewall spacer 115 may be formed adjacent to the top electrode 111. Forming the first sidewall spacer 115 may include depositing a spacer material and etching. The spacer material may be one or more layers of any suitable one or more dielectric materials. Materials suitable for the first sidewall spacer 115 include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like. The material may be deposited by any suitable one or more processes. Suitable processes may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. The etching process may include plasma etching or any other suitable etching process that selectively removes the thinnest spacer material relative to the vertical surface.

[0044] The etch that forms the sidewall spacers 115 may thin the hard mask 801 over the resistive switching RAM cells 107, 153. Fig. 9As shown in cross-sectional view 900 of FIG. 1 , the hard mask 801 over the smaller resistance switching RAM cell 153 may be thinned more than the hard mask 801 over the larger resistance switching RAM cell 107. One reason for the different degrees of thinning may be an "etch loading effect." The etch loading effect may occur during a processing stage during which more material around the larger resistance switching RAM cell 107 reacts with the etchant than around the smaller resistance switching RAM cell 153. The greater amount of reacting material results in a faster consumption of the etchant, resulting in a reduced concentration of the etchant around the resistance switching RAM cell 107.

[0045] like Fig.10 As shown in the cross-sectional view 1000 of , an etch may be performed using the hard mask 801 and the first sidewall spacer 115 as a mask to pattern the MTJ layer 705 to define the MTJ 140 for the resistance switching RAM cells 107, 153. The etch process may be a plasma etch. The bottom electrode layer 713 may provide an etch stop for this etch process. During this etch process, the hard mask 801 may be further thinned, and the etch loading effect may cause this thinning to be greater for the hard mask 801 over the resistance switching RAM cell 153 than for the hard mask 801 over the resistance switching RAM cell 107.

[0046] like Fig.11 As shown in the cross-sectional view 1100, Fig.10 A second spacer layer 1101 is deposited on the structure shown in the cross-sectional view 1000 of . The second spacer layer 1101 may be one or more layers of any suitable one or more dielectric materials. Materials suitable for the second spacer layer 1101 include, but are not limited to, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or similar materials. The materials may be deposited by any suitable one or more processes. Suitable processes may be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or similar processes. The second spacer layer 1101 may be the same material as the first sidewall spacer 115 or a different material. In some embodiments, the second spacer layer 1101 is silicon oxynitride (SiON) and the first sidewall spacer 115 is silicon nitride (SiN).

[0047] like Fig.12As shown in the cross-sectional view 1200 of FIG. 1 , the second spacer layer 1101 is etched to form the second sidewall spacer 117. The etching process may include plasma etching or any other suitable etching process that selectively removes the thinnest spacer material in the upper and lower directions. This etching process may also thin the hard mask 801 above the resistance switching RAM cell 153 to a greater extent than the hard mask 801 above the resistance switching RAM cell 107.

[0048] like Fig.13 As shown in the cross-sectional view 1300 of , etching can be performed to pattern the bottom electrode layer 713 to define the bottom electrode 125 of the resistance switching RAM cell 107, 153. At the beginning of this process, the hard mask 801, the first sidewall spacer 115 and the second sidewall spacer 117 can be used as a mask. The etching process can be a plasma etch. In some of these teachings, during this etching process, the hard mask 801 is completely removed to expose the top electrode 111. The top electrode 111 can be the same or similar material as the bottom electrode layer 713. Therefore, once the hard mask 801 is removed, etching can be started to thin the top electrode 111. To the extent that the hard mask 801 is thinner above the resistance switching RAM cell 153 than above the resistance switching RAM cell 107, the etching of the top electrode 111 of the resistance switching RAM cell 153 will start earlier and proceed further than the etching of the top electrode 111 of the resistance switching RAM cell 107. This can result in a small difference in thickness between the hard mask 801 above the resistance switching RAM cell 107 and the hard mask 801 above the resistance switching RAM cell 153, thereby resulting in a relatively large difference in thickness between the top electrode 111 of the resistance switching RAM cell 107 and the top electrode 111 of the resistance switching RAM cell 153.

[0049] like Fig.14 As shown in the cross-sectional view 1400, Fig.13 Multiple layers of various materials are formed on the structure shown in the cross-sectional view 1300 of . These layers may include a dielectric fill layer 113, a dielectric top layer 112, an oxide layer 1401, and a bottom anti-reflective coating (BARC) 1403. The dielectric fill layer 113 may be a dielectric, such as silicon dioxide (SiO2), or the like. The dielectric top layer 112 may be a dielectric having a different composition than the dielectric top layer 112. The dielectric top layer 112 may be, for example, silicon oxynitride (SiON), silicon nitride (SiN), silicon cyanide (SINC), silicon oxycarbide (SiOC), etc. In some of these teachings, the dielectric top layer 112 is silicon oxynitride (SiON). The oxide layer 1401 is an optional layer, which may be, for example, silicon dioxide (SiO2), or the like.

[0050] In some of these teachings, the dielectric fill layer 113 and the dielectric top layer 112 are deposited to a thickness where the upper surface 138 of the top electrode 111 of the smaller resistance switching RAM cell 153 is aligned with (at its height) the dielectric top layer 112 in the peripheral region 133. The alignment may be aligned with the middle of the dielectric top layer 112 or the top of the dielectric top layer 112. On the other hand, the upper surface 142 of the dielectric top layer 112 in the peripheral region 133 may be lower than the height of the top surface 136 of the larger resistance switching RAM cell 107.

[0051] In some of these teachings, the thickness of the dielectric fill layer 113 is between about To date In some of these teachings, the thickness of the dielectric fill layer 113 is between about To date In some of these teachings, the thickness of the dielectric top layer 112 is between about To date In some of these teachings, the thickness of the dielectric top layer 112 is between about To date In some of these teachings, the thickness of the dielectric top layer 112 is between about To date within the range.

[0052] The dielectric fill layer 113 and the dielectric top layer 112 may be deposited by any suitable process or combination of processes. In some of these teachings, the dielectric fill layer 113 and the dielectric top layer 112 are formed by an atomic layer deposition (ALD) process, such as plasma-enhanced atomic layer deposition (PEALD). ALD allows precise control of layer thickness. The oxide layer 1401 may also be formed by ALD. The BARC 1403 may be an organic material applied by a spin coating process to form a flat upper surface.

[0053] like Fig.15 As shown in the cross-sectional view 1500, a non-selective etch back process can be used to make Fig.14 The surface of the structure shown in the cross-sectional view 1400 of FIG. 1400 is recessed. This etch-back process may remove most or all of the BARC 1403. The oxide layer 1401 may help determine the endpoint of this etch-back process.

[0054] like Fig.16As shown in the cross-sectional view 1600 of FIG. 1 , chemical mechanical polishing (CMP) can be used to expose the top electrodes 111 of both the smaller resistance switching RAM cell 153 and the larger resistance switching RAM cell 107. The CMP process can stop on the dielectric top layer 112 in an area away from the resistance switching RAM cells 107, 153, such as the peripheral area 133. In some of these teachings, the CMP process uses a slurry that provides a much higher etch rate for the dielectric top layer 112 and the dielectric fill layer 113 than the top electrode 111, wherein the CMP process has little effect on the thickness of the top electrode 111.

[0055] Since the top electrode 111 is not significantly recessed, the first sidewall spacers 115 and the second sidewall spacers 117 are not significantly affected by the CMP process. The top electrode 111 of the larger resistance switching RAM cell 107 remains thicker than the top electrode 111 of the smaller resistance switching RAM cell 153. The CMP process can recess the dielectric top layer 112 until the upper surface 142 of the dielectric top layer 112 in the area away from the larger resistance switching RAM cell 107 is located at or below the upper surface 138 of the resistance switching RAM cell 153. In some of these teachings, the CMP leaves the upper surface 142 at approximately the same height as the upper surface 138. The portion of the dielectric top layer 112 that remains after the CMP process is spaced apart from the resistance switching RAM cells 107, 153.

[0056] In some of these teachings, the CMP process is 100 times or more selective for removing SiO2 than it is for removing the metal of the top electrode 111. In some of these teachings, the CMP process is ten times or more selective for removing SiON or other materials forming the dielectric top layer 112 than it is for removing the metal of the top electrode 111. In some of these teachings, the desired selectivity is provided by performing the CMP using a slurry containing ceria. In some of these teachings, the slurry does not contain silicon dioxide.

[0057] like Fig.17 As shown in the cross-sectional view 1700, Fig.16An etch stop layer 109 is formed on the structure shown in the cross-sectional view 1600 of FIG. The etch stop layer 109 can be any suitable dielectric. Examples of dielectrics suitable for the etch stop layer 109 include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or the like. In some of these teachings, the etch stop layer 109 is silicon nitride (SiN). The etch stop layer 109 can be formed by any suitable one or more processes. Suitable processes can be chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like.

[0058] As shown in the cross-sectional view 1700, the etch stop layer 109 may directly contact the top electrodes 111 of both the smaller resistance switching RAM cell 153 and the larger resistance switching RAM cell 107. The etch stop layer 109 may have an equal thickness over the smaller resistance switching RAM cell 153 and the larger resistance switching RAM cell 107. The dielectric fill layer 113 separates the etch stop layer 109 from the second sidewall spacers 117, except for a small area that may be very close to the top of the resistance switching RAM cells 107, 153. The dielectric fill layer 113 causes the etch stop layer 109 to extend outward from both the smaller resistance switching RAM cell 153 and the larger resistance switching RAM cell 107, and outward from the first sidewall spacers 115 and the second sidewall spacers 117, rather than bowing downwardly in conformity with the shape of the resistance switching RAM cells 107, 153 and their associated first sidewall spacers 115 and the second sidewall spacers 117. In some of these teachings, the etch stop layer 109 gradually slopes downward as it extends away from the larger resistance switching RAM cell 107 and flattens at a height proximate the smaller resistance switching RAM cell 153. In some of these teachings, the etch stop layer 109 flattens at a height above the MTJ 140.

[0059] like Fig.17 As further shown in the cross-sectional view 1700 of FIG. 1 , a photoresist 1701 may be formed on the etch stop layer 109 in the first storage area 129 and the second storage area 131. Fig.18 As shown in the cross-sectional view 1800 of , the etch stop layer 109 may be removed from the peripheral region 133 using the photoresist 1701. Subsequently, the dielectric top layer 112 and the dielectric fill layer 113 may also be etched from the peripheral region 133 using the photoresist 1701 and / or the etch stop layer 109 as a mask. The photoresist 1701 may be stripped during or after this etching.

[0060] like Fig.19 As shown in the cross-sectional view 1900, Fig.18An interlayer dielectric layer 103 is formed on the structure shown in the cross-sectional view 1800 of FIG. The interlayer dielectric layer 103 may be a low-k dielectric or an ultra-low-k dielectric formed by any suitable process. In some of these teachings, the etch stop layer 109 is the only layer separating the top electrode 111 from the interlayer dielectric layer 103. In some of these teachings, immediately after deposition, the height difference between the first storage area 129 and the peripheral area 133 of the interlayer dielectric layer 103 is between about 100 and 100 mm. To date In some of these teachings, the height difference between the interlayer dielectric layer 103 and the first storage area 129 and the peripheral area 133 is between about To date within the range.

[0061] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 2 , the surface of the interlayer dielectric layer 103 can be planarized. Planarization can include a combination of processes. The combination of processes can include mask etching to remove most of the excess interlayer dielectric layer 103 from the first storage area 129 and the second storage area 131, and then polishing to produce a flat surface. In some of these teachings, planarization is achieved only by polishing.

[0062] Fig. 22 A flow chart of a process 2200 according to some aspects of the present teachings is provided. According to the present teachings, the process 2200 can be used to produce integrated circuit devices. Although the process 2200 is described and described in this article as a series of actions or events, it will be understood that the described order of these actions or events should not be interpreted as having a restrictive meaning. For example, some actions can occur in different orders and / or occur synchronously with other actions or events other than the actions or events described and / or described herein. In addition, it may not be required to use all the described actions to implement one or more aspects or embodiments of the description herein. In addition, one or more actions described herein can be implemented with one or more separate actions and / or stages.

[0063] The process 2200 begins with front-end-of-line (FEOL) processing and activity 2201 of forming several metal interconnect layers 108, 118, 135 and depositing an etch stop layer 137 and an interface layer 139 to produce, for example, Figure 3 Action 2203 of the structure such as the structure shown in the cross-sectional view 300.

[0064] The process 2200 continues with an act 2205 of forming and patterning the mask 403 and an act 2207 of etching to form the opening 401 in the etch stop layer 137 and the interface layer 139, as shown in FIG. Figure 4As shown in the cross-sectional view 400 of FIG. 2209, a material layer 501 is deposited to fill the opening 401. Figure 5 As shown in the cross-sectional view 500 of FIG. 2211, the material layer 501 outside the opening 401 is planarized to remove the material layer 501, thereby forming the through hole 127, as shown in FIG. Figure 6 600. Material 501 and other metal layers may be formed by any suitable process. Suitable processes may include electroplating, electroless plating, sputtering, chemical vapor deposition (CVD), or the like.

[0065] Action 2213 is to form a resistive switching RAM cell stack 701, such as Figure 7 As shown in the cross-sectional view 700 of FIG. 701 , the resistive switching RAM cell stack 701 may include a bottom electrode layer 711 , a resistive switching layer 705 and a top electrode layer 703 . The resistive switching layer 705 may be a metal tunnel junction layer 705 . The metal tunnel junction layer may include a first ferromagnetic layer 711 , an insulator layer 709 and a second ferromagnetic layer 707 .

[0066] Action 2215 is to form a resistive switching RAM cell hard mask 801. Action 2217 is to pattern the top electrode 111 from the top electrode layer 703 using the resistive switching RAM cell hard mask 801, such as Figure 8 shown.

[0067] Action 2219 is to form a first sidewall spacer 115 adjacent to the top electrode 111, such as Fig. 9 This may include depositing a layer of spacer material and then etching to leave remaining portions of the spacer material, thereby forming first sidewall spacers 115 .

[0068] Action 2221 is to etch the resistance switching layer 705 to form a resistance switching structure, e.g. Fig.10 MTJ 140 is shown. The resistive switching RAM cell hard mask 801 and the first sidewall spacers 115 may define the pattern of this etching.

[0069] Action 2223 is to form second sidewall spacers 117. This may include depositing Fig.11 The spacer material layer 1101 is then etched to form a spacer as shown. Fig.12 The second sidewall spacer 117 is shown.

[0070] Action 2225 is to perform etching to pattern the bottom electrode 125 from the bottom electrode layer 713, such as Fig.132219, 2221, and 2223. In some of these teachings, this etch also removes the remaining portion of the resistance switching RAM cell hard mask 801 and exposes the top electrode 111. One or more etches of actions 2217, 2219, 2221, and 2223 can have the hard mask 801 thinned to a greater extent over the smaller resistance switching RAM cell 153 than over the larger resistance switching RAM cell 107. As a result, action 2225 can make the smaller resistance switching RAM cell 153 shorter than the larger resistance switching RAM cell 107.

[0071] Action 2229 is to deposit a dielectric filling layer 113 and a dielectric top layer 112 on the resistance switching RAM cells 107 and 153, such as Fig.14 Action 2231 is to deposit BARC 1403 to form a flat surface, also as shown Fig.14 Action 2233 is a non-selective etch-back process to recess the surface, such as Fig.15 The non-selective etch back process of action 2233 can remove various materials from the top of the device while making the surface nearly flat.

[0072] Action 2235 is a CMP process with low selectivity to the top electrode 111. Action 2235 re-exposes the top electrodes 111 of both the larger resistance switching RAM cell 107 and the smaller resistance switching RAM cell 153, as shown in FIG. Fig.16 Action 2235 does not substantially shorten the larger resistance switching RAM cell 107 or the smaller resistance switching RAM cell 153, and causes the two sized cells to have different heights. The CMP process may stop on the dielectric top layer 112 in the peripheral region 133. In some of these teachings, the CMP process uses a ceria slurry.

[0073] Action 2239 is to form an etch stop layer 109 on the surface produced by the CMP process of action 2235, such as Fig.17 As shown. Action 2241 is to form Fig.17 The mask shown in FIG. 1 is used, and etching is performed to remove the etch stop layer 109, the dielectric filling layer 113 and the dielectric top layer 112 from the peripheral region 133, as shown in FIG. Fig.18 shown.

[0074] Action 2243 is to deposit an interlayer dielectric layer 103, such as Fig.19 As shown. Action 2245 is to planarize the interlayer dielectric layer 103, as shown. Fig. 20 shown.

[0075] Action 2247 is to form an opening through the interlayer dielectric layer 103 and the etch stop layer 109 and backfill with metal to form vias 105, 151, 145 and metal features 101, such as Figure 2Action 2249 is to complete BEOL processing and additional processing to form a device such as integrated circuit device 100.

[0076] Some aspects of the present teachings relate to an integrated circuit (IC) device comprising: a substrate; a metal interconnect structure formed on the substrate; and a plurality of resistance switching random access memory (resistance switching RAM) cells formed within the metal interconnect structure. Each resistance switching RAM cell comprises a bottom electrode, a top electrode, and a resistance switching structure located between the bottom electrode and the top electrode. A via connects the top electrode to the metal interconnect structure. The via passes through a low-k dielectric layer. The plurality of resistance switching random access memory cells comprises a smaller cell and a larger cell. The smaller cell is shorter in height than the larger cell. Any dielectric layer separating the top electrode from the low-k dielectric layer has an equal thickness over the larger cell and the smaller cell.

[0077] According to some embodiments, an etch stop layer separates the top electrode from the low-k dielectric layer.

[0078] According to some embodiments, the amount by which the smaller unit is lower in height than the larger unit is of the same order of magnitude as the thickness of the etch stop layer.

[0079] According to some embodiments, the smaller unit is lower in height than the larger unit by an amount that is at least one quarter of the thickness of the etch stop layer.

[0080] According to some embodiments, wherein: the resistance switching random access memory cells form one or more arrays in a storage region; the etch stop layer overlies a second dielectric layer in the storage region; the second dielectric layer is located between the resistance switching random access memory cells in one of the arrays, but is spaced apart from each of the resistance switching random access memory cells in the array.

[0081] According to some embodiments, the second dielectric layer forms islands located diagonally between the resistance-switching random access memory cells in the array.

[0082] According to some embodiments, wherein for each of the RSRAM cells, the etch stop layer extends laterally away from the RSRAM cell, including any sidewall spacers associated with the RSRAM cell.

[0083] Some aspects of the present teachings relate to an integrated circuit (IC) device comprising: a substrate; a metal interconnect structure formed on the substrate; and a plurality of resistance switching random access memory (resistance switching RAM) cells formed within the metal interconnect structure. Each resistance switching RAM cell comprises a bottom electrode, a top electrode, and a resistance switching structure located between the bottom electrode and the top electrode. A via through a low-k dielectric layer connects the top electrode to the metal interconnect structure. The plurality of resistance switching RAM cells comprises a smaller cell and a larger cell, wherein the height of the smaller cell is lower than the height of the larger cell. For each of the plurality of resistance switching RAM cells, the etch stop layer extends laterally away from the resistance switching RAM cell and any sidewall spacers associated with the resistance switching RAM cell.

[0084] According to some embodiments, the etch stop layer is flattened at a height of the smaller cells between the resistance switching random access memory cells in the array of larger cells.

[0085] According to some embodiments, wherein: a first dielectric layer fills the space between the resistance switching random access memory cells in the array; and a second dielectric layer is located on top of the first dielectric layer and below the etch stop layer in the area between the resistance switching random access memory cells in the array.

[0086] According to some embodiments, the second dielectric layer is present midway between diagonally adjacent resistance-switching random access memory cells in the array.

[0087] According to some embodiments, the etch stop layer is planarized over the second dielectric layer.

[0088] Some aspects of the present teachings relate to a method of manufacturing an integrated circuit (IC) device. The method includes: forming a metal interconnect layer over a semiconductor substrate including a storage area and a peripheral area; and forming a resistance switching random access memory (resistance switching RAM) cell over the metal interconnect layer in the storage area. The resistance switching RAM cell includes a taller cell and a shorter cell. The method also includes: depositing a first dielectric layer over the resistance switching RAM cell; depositing a second dielectric layer over the first dielectric layer; and performing chemical mechanical polishing to leave a surface including a top electrode of the taller cell, a top electrode of the shorter cell, and the second dielectric layer in a region between the resistance switching RAM cells. The chemical mechanical polishing leaves the taller cell higher than the shorter cell.

[0089] According to some embodiments, the chemical mechanical polishing stops on the second dielectric layer in the peripheral region.

[0090] According to some embodiments, a top portion of the second dielectric layer in the peripheral region before the chemical mechanical polishing is located below a top portion of the taller cell after the chemical mechanical polishing.

[0091] According to some embodiments, wherein a combined thickness of the first dielectric layer and the second dielectric layer in the peripheral region after the chemical mechanical polishing is less than or equal to a height of the shorter cell after the chemical mechanical polishing.

[0092] According to some embodiments, the method further includes depositing an etch stop layer over the surface left by the chemical mechanical polishing.

[0093] According to some embodiments, the method further includes: removing the first dielectric layer, the second dielectric layer and the etch stop layer from the peripheral area; depositing an interlayer dielectric on the etch stop layer in the storage area and the peripheral area, wherein the removal of the first dielectric layer, the second dielectric layer and the etch stop layer from the peripheral area causes a height variation of the interlayer dielectric layer between the storage area and the peripheral area; and polishing to eliminate the height variation.

[0094] According to some embodiments, the chemical mechanical polishing includes polishing with a slurry including ceria.

[0095] According to some embodiments, the method further includes: depositing a spin-on coating on the second dielectric layer; and before the chemical mechanical polishing, performing an etching process, wherein the etching process recesses the spin-on coating and removes the second dielectric layer from above the resistance switching random access memory cell.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present teachings. Those skilled in the art should know that they can easily use the present teachings as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present teachings, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present teachings.

Claims

1. An integrated circuit device, characterized in that: include: substrate; A metal interconnect structure formed on the substrate; A plurality of resistance switching random access memory cells are formed in the metal interconnect structure, each resistance switching random access memory cell of the plurality of resistance switching random access memory cells comprising a bottom electrode, a top electrode and a resistance switching structure located between the bottom electrode and the top electrode; as well as a via connecting the top electrode to the metal interconnect structure, wherein the via passes through a low-k dielectric layer; wherein the plurality of resistance switching random access memory cells include smaller cells and larger cells; The smaller unit is shorter in height than the larger unit; and Any dielectric layer separating the top electrode from the low-k dielectric layer has equal thickness over the larger cell and the smaller cell.

2. The integrated circuit device according to claim 1, wherein: An etch stop layer separates the top electrode from the low-k dielectric layer.

3. The integrated circuit according to claim 2, characterized in that The amount by which the smaller cell is lower in height than the larger cell is of the same order of magnitude as the thickness of the etch stop layer.

4. The integrated circuit according to claim 2, characterized in that The smaller unit is lower in height than the larger unit by an amount that is at least one quarter of the thickness of the etch stop layer.

5. The integrated circuit according to claim 2, characterized in that: in: The plurality of resistance-switching random access memory cells form one or more arrays in a storage region, including a first array; The etch stop layer overlies the second dielectric layer in the storage region; The second dielectric layer is located between the resistance-switching random access memory cells in the first array in the array, but is spaced apart from each of the resistance-switching random access memory cells in the first array.

6. The integrated circuit according to claim 5, characterized in that The second dielectric layer forms islands located diagonally between the resistance switching random access memory cells in the first array.

7. The integrated circuit according to claim 2, characterized in that: For each of the plurality of resistance-switching random access memory cells, the etch stop layer extends laterally away from the resistance-switching random access memory cell, including any sidewall spacers associated with the resistance-switching random access memory cell.

8. An integrated circuit device, characterized in that: include: substrate; A metal interconnect structure formed on the substrate; A plurality of resistance switching random access memory cells are formed in the metal interconnect structure, each resistance switching random access memory cell of the plurality of resistance switching random access memory cells comprising a bottom electrode, a top electrode and a resistance switching structure located between the bottom electrode and the top electrode; as well as a via connecting the top electrode to the metal interconnect structure, wherein the via passes through a low-k dielectric layer and an etch stop layer; wherein the plurality of resistance switching random access memory cells include smaller cells and larger cells; The etch stop layer is located between the low-k dielectric layer and the resistance switching random access memory cell; The height of the smaller unit is lower than that of the larger unit; and For each of the plurality of resistance-switching random access memory cells, the etch stop layer extends laterally away from the resistance-switching random access memory cell, including any sidewall spacers associated with the resistance-switching random access memory cell.

9. The integrated circuit device according to claim 8, characterized in that The etch stop layer is flattened at the height of the smaller cells between the larger cells in the array of larger cells.

10. The integrated circuit according to claim 9, characterized in that in: A first dielectric layer fills the spaces between the larger cells in the array; and A second dielectric layer is located on top of the first dielectric layer and below the etch stop layer in areas between the larger cells in the array.

11. The integrated circuit according to claim 10, characterized in that The second dielectric layer is present intermediate between diagonally adjacent larger cells in the array.

12. The integrated circuit according to claim 10, characterized in that The etch stop layer is planarized over the second dielectric layer.

13. A method for manufacturing an integrated circuit device, characterized in that: include: forming a metal interconnect layer on the semiconductor substrate including the storage region and the peripheral region; forming a resistance switching random access memory cell over the metal interconnect layer in the storage region, wherein the resistance switching random access memory cell comprises a taller cell and a shorter cell; depositing a first dielectric layer over the resistance switching random access memory cell; depositing a second dielectric layer over the first dielectric layer; and performing chemical mechanical polishing to leave a surface including the top electrode of the taller cell, the top electrode of the shorter cell, and the second dielectric layer in the region between the resistance switching random access memory cells; The chemical mechanical polishing causes the taller unit to be taller than the shorter unit.

14. The method according to claim 13, characterized in that The chemical mechanical polishing stops on the second dielectric layer in the peripheral region.

15. The method according to claim 13, characterized in that A top portion of the second dielectric layer in the peripheral region before the chemical mechanical polishing is below a top portion of the taller cell after the chemical mechanical polishing.

16. The method according to claim 13, characterized in that A combined thickness of the first dielectric layer and the second dielectric layer in the peripheral region after the chemical mechanical polishing is less than or equal to a height of the shorter cell after the chemical mechanical polishing.

17. The method according to claim 13, characterized in that Also included is depositing an etch stop layer over the surface left by the chemical mechanical polishing.

18. The method according to claim 17, characterized in that Also includes: removing the first dielectric layer, the second dielectric layer, and the etch stop layer from the peripheral region; depositing an interlayer dielectric over the etch stop layer in the memory region and the peripheral region, wherein the removing of the first dielectric layer, the second dielectric layer, and the etch stop layer from the peripheral region results in a height variation of the interlayer dielectric between the memory region and the peripheral region; and Polishing is performed to eliminate the height variations.

19. The method according to claim 13, characterized in that The chemical mechanical polishing includes polishing with a slurry containing ceria.

20. The method according to claim 13, characterized in that Also includes: depositing a spin-on coating over the second dielectric layer; and Prior to the chemical mechanical polishing, an etching process is performed that recesses the spin-on coating and removes the second dielectric layer from over the resistance switching random access memory cell.

21. An integrated circuit device, characterized in that: include: substrate; A metal interconnect structure formed on the substrate; memory cells, within the metal interconnect structure, each of the memory cells comprising a bottom electrode, a top electrode, and a data storage layer between the bottom electrode and the top electrode; as well as an oxide layer located between the memory cells; a dielectric layer directly on the oxide layer; wherein the memory cell comprises a first cell having a first height and a second cell having a second height; A combined thickness of the oxide layer and the dielectric layer is less than or equal to the second height.

22. The integrated circuit according to claim 21, characterized in that Also includes: Etch stop layer; The etch stop layer is located above the top electrode of the first cell, the top electrode of the second cell, and the dielectric layer, and is in contact with the top electrode of the first cell, the top electrode of the second cell, and the dielectric layer.

23. The integrated circuit according to claim 22, characterized in that The difference between the first height and the second height is at least one quarter of the thickness of the etch stop layer.

24. The integrated circuit according to claim 21, characterized in that The dielectric layer includes silicon oxynitride (SiON), silicon nitride (SiN), silicon cyanide (SINC), or silicon oxycarbide (SiOC).

25. The integrated circuit according to claim 21, characterized in that The dielectric layer forms islands between the memory cells.

26. The integrated circuit according to claim 21, characterized in that The oxide layer is raised adjacent to the memory cell such that the oxide layer laterally separates the dielectric layer from the memory cell.

27. The integrated circuit according to claim 21, characterized in that Also includes: Etch stop layer; The bottom of the etch stop layer is vertically aligned with the top of the first unit adjacent to the first unit and is vertically aligned with the top of the second unit adjacent to the second unit.

28. The integrated circuit according to claim 27, characterized in that The etch stop layer is directly above the dielectric layer and in contact with the dielectric layer.

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