Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising a first region and a second region; forming a field oxide layer on the substrate in the first region; forming a drift region in the substrate in the first region; forming a gate structure on a portion of the substrate in the first region and a portion of the substrate in the second region, wherein the gate structure covers a portion of the drift region and a portion of the surface of the field oxide layer; forming an ion doping region in the drift region below the field oxide layer exposed by the gate structure, wherein the doping ion type of the ion doping region is opposite to the doping ion type of the drift region. The semiconductor structure formed by the method can maintain a high breakdown voltage while reducing the on-resistance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the development of semiconductor technology, power integrated circuits (PIC) are continuously used in many fields. Laterally double-diffused metal oxide semiconductor transistors (LDMOS) have the characteristics of high operating voltage, simple process, and easy process compatibility with complementary metal oxide semiconductors (CMOS). Therefore, they are widely used in power integrated circuits as power devices.

[0003] The emergence of LDMOS solves the problem of insufficient high-voltage bearing capacity of traditional MOSFET, mainly by adding a low-doped drift region between the channel and the highly doped drain to reduce the voltage. Therefore, the breakdown voltage of LDMOS mainly depends on the width and doping concentration of the drift region. When a higher breakdown voltage is required, the width of the drift region should be increased or the doping concentration of the drift region should be reduced. However, the increase in the width of the drift region and the decrease in the doping concentration will lead to an increase in the on-resistance; conversely, if the width of the drift region is reduced or the doping concentration of the drift region is increased in order to reduce the on-resistance, the breakdown voltage will be reduced.

[0004] Therefore, how to reduce the on-resistance through reasonable design while maintaining the breakdown voltage to meet the requirements is an urgent problem to be solved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so that the semiconductor device has a higher breakdown voltage while reducing the on-resistance.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region; forming a field oxide layer on the substrate in the first region; forming a drift region in the substrate in the first region; forming a gate structure on a portion of the substrate in the first region and a portion of the substrate in the second region, and the gate structure covers a portion of the drift region and a portion of the surface of the field oxide layer; forming an ion doping region in the drift region below the field oxide layer exposed by the gate structure, the doping ion type of the ion doping region being opposite to the doping ion type of the drift region.

[0007] Optionally, when the thickness of the field oxide layer is less than the thickness of the gate structure, the method for forming the ion doped region includes: using an ion implantation process to implant ions into the drift region below the field oxide layer exposed by the gate structure.

[0008] Optionally, when the thickness of the field oxide layer is greater than the thickness of the gate structure, the method for forming the ion doping region includes: forming a mask layer on the substrate, the mask layer covering the gate structure, the drift region and the surface of the field oxide layer; etching the mask layer to form an opening, the opening exposing the surface of the field oxide layer exposed by the gate structure; and using an ion implantation process to implant ions along the opening into the drift region below the field oxide layer exposed by the gate structure.

[0009] Optionally, the method for forming the field oxide layer includes: forming a pad oxide layer and a silicon nitride layer in sequence on the surface of the substrate; etching the pad oxide layer and the silicon nitride layer to form a field oxide opening, wherein the field oxide opening exposes a portion of the substrate in the first region; and forming the field oxide layer on the substrate along the field oxide opening using a local oxidation process.

[0010] Optionally, before forming the gate structure, the method further includes: forming a body region in the substrate in the second region, wherein the doping ion type of the body region is opposite to the doping ion type of the drift region.

[0011] Optionally, after forming the gate structure, it also includes: forming a source and a drain in the substrate on both sides of the gate structure, the source is located in the body region, the drain is located in the drift region, and the field oxide layer is located between the gate structure and the drain.

[0012] Optionally, the semiconductor structure is an N-type semiconductor structure, the doping ion type of the drift region is N-type ions, and the doping ion type of the ion-doped region is P-type ions.

[0013] Optionally, the semiconductor structure is a P-type semiconductor structure, the doping ion type of the drift region is P-type ions, and the doping ion type of the ion-doped region is N-type ions.

[0014] Optionally, the N-type ions include phosphorus, arsenic, antimony, sulfur or selenium ions, and the P-type ions include boron, indium or gallium ions.

[0015] A semiconductor structure formed by the above method includes: a substrate, the substrate including a first region and a second region; a field oxide layer, located on a portion of the substrate in the first region; a drift region, located in the substrate in the first region, and the field oxide layer covers a portion of the drift region; a gate structure, located on a portion of the substrate in the first region and a portion of the substrate in the second region, and the gate structure covers a portion of the drift region and a portion of the surface of the field oxide layer; an ion doping region, located in the drift region below the field oxide layer exposed by the gate structure, and the doping ion type of the ion doping region is opposite to the doping ion type of the drift region.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0017] An ion doping region is formed in the drift region below the field oxide layer exposed by the gate structure, and the doping ion type of the ion doping region is opposite to the doping ion type of the drift region, so that the ion doping concentration of the drift region in the region where the ion doping region is formed is reduced, thereby improving the breakdown voltage of the semiconductor device. In addition, due to the modulation effect of the gate, the carriers flow on the surface of the drift region close to the gate structure in the region covered by the gate structure, and the distribution of carriers in the region of the drift region not covered by the gate structure is relatively uniform. The change of ion doping concentration in the region of the drift region covered by the gate structure has a greater impact on the on-resistance. Therefore, forming an ion doping region in the drift region below the field oxide layer exposed by the gate structure can reduce the impact on the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 to Figure 2 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0019] As can be seen from the background technology, for LDMOS, the doping concentration and width of the drift region are the most important characteristic parameters, which are closely related to the on-resistance and breakdown voltage of LDMOS. However, the on-resistance and breakdown voltage in LDMOS are contradictory indicators. If the on-resistance is reduced by increasing the doping concentration of the drift region or reducing the width of the drift region, the breakdown voltage will also be reduced, making LDMOS unable to meet the requirements of high voltage resistance; conversely, reducing the doping concentration of the drift region or increasing the width of the drift region can increase the breakdown voltage, but at the same time it will increase the on-resistance.

[0020] In order to solve the above technical problems, the inventor has provided a method for forming a semiconductor structure after research, wherein an ion doping region is formed in the drift region below the field oxide layer exposed by the gate structure, the ion doping type of the ion doping region is opposite to the ion doping type of the drift region, and the ions in the drift region are neutralized by the inverse ions to reduce the ion doping concentration of the drift region in this region, thereby improving the breakdown voltage of the semiconductor device. The semiconductor structure subsequently forms a source and drain on both sides of the gate structure, the drain is located in the drift region, and the field oxide layer is located between the gate structure and the drain. The breakdown voltage of the semiconductor device is mainly affected by the electric field strength from the drain to the end of the gate structure on the field oxide layer, so the change in the ion doping concentration of the drift region below the field oxide layer exposed by the gate structure has a greater impact on the breakdown voltage. In addition, due to the modulation effect of the gate, the area of ​​the drift region covered by the gate structure has carriers flowing on the surface of the drift region close to the gate structure, and the distribution of carriers in the area of ​​the drift region not covered by the gate structure is relatively uniform, and the change in the ion doping concentration of the drift region covered by the gate structure has a greater impact on the on-resistance. Therefore, an ion doping region is formed in the drift region below the field oxide layer exposed by the gate structure, so that the semiconductor device can have a lower on-resistance and a higher breakdown voltage.

[0021] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] Figure 1 to Figure 2 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0023] refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a first region I and a second region II.

[0024] In this embodiment, the first region I and the second region II are adjacent regions, wherein the first region I is used to subsequently form a drift region, and the second region II is used to subsequently form a body region.

[0025] In this embodiment, the substrate 100 is used to form an N-type semiconductor; specifically, the N-type semiconductor is an N-type LDMOS. In other embodiments, the substrate 100 can also be used to form a P-type semiconductor.

[0026] In this embodiment, the substrate 100 is a silicon substrate; in other embodiments, the substrate may also be a germanium substrate, a silicon-germanium substrate or a silicon carbide substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0027] Continue to refer Figure 1, a field oxide layer 200 is formed on the substrate 100 in the first region I.

[0028] In this embodiment, the material of the field oxide layer 200 is silicon oxide.

[0029] In this embodiment, the method of forming the field oxide layer 200 includes:

[0030] A pad oxide layer (not shown) and a silicon nitride layer (not shown) are sequentially formed on the surface of the substrate 100. The pad oxide layer is formed to prevent the silicon nitride layer from causing stress damage to the surface of the substrate 100.

[0031] In this embodiment, the pad oxide layer 210 is silicon dioxide.

[0032] The pad oxide layer and the silicon nitride layer are etched to form a field oxide opening (not shown), wherein the field oxide opening exposes a portion of the substrate 100 in the first region I.

[0033] It should be noted that before etching the pad oxide layer and the silicon nitride layer, a photoresist is first spin-coated on the silicon nitride layer (not shown), and is exposed and developed using a mask that defines the field oxide layer area to form a patterned photoresist layer, and then the pad oxide layer and the silicon nitride layer are etched using the patterned photoresist layer as a mask.

[0034] After the field oxide opening is formed, the field oxide layer 200 is formed on the exposed substrate 100 along the field oxide opening by using a local oxidation process.

[0035] Continue to refer Figure 1 , a drift region 300 is formed in the substrate 100 in the first region I.

[0036] In this embodiment, the field oxide layer 200 covers a portion of the drift region 300 .

[0037] In this embodiment, the method for forming the drift region 300 includes: forming a first graphic layer (not shown) on the substrate 100 in the first region I, wherein the first graphic layer exposes the substrate 100 in the first region I; using the first graphic layer as a mask, performing an ion implantation process on the substrate 100 in the first region I to form the drift region 300 in the substrate 100 in the first region I; and removing the first graphic layer.

[0038] In this embodiment, the material of the first pattern layer is photoresist. After the drift region 300 is formed, the first pattern layer is removed by wet stripping or ashing process.

[0039] In this embodiment, the ion doping concentration of the drift region 300 can be determined according to actual process conditions. Since the on-resistance of a semiconductor device is related to the ion doping concentration of the drift region, a high ion doping concentration of the drift region 300 is beneficial to reducing the on-resistance.

[0040] In other embodiments, the on-resistance may also be reduced by reducing the width of the drift region 300 .

[0041] Continue to refer Figure 1 , a body region 400 is formed in the substrate 100 in the second region II, and the doping ion type of the body region 400 is opposite to the doping ion type of the drift region 300 .

[0042] In this embodiment, the method for forming the body region 400 includes: forming a second graphic layer (not shown) on the substrate 100 in the second region II, the second graphic layer exposing the substrate 100 in the second region II; using the second graphic layer as a mask, performing an ion implantation process on the substrate 100 in the second region II to form a body region 300 in the substrate 100 in the second region II; and removing the second graphic layer.

[0043] In this embodiment, the material of the second pattern layer is photoresist, and after the body region 400 is formed, the second pattern layer is removed by wet stripping or ashing process.

[0044] It should be noted that, in other embodiments, the body region may be formed first and then the drift region.

[0045] In this embodiment, the substrate 100 is used to form an N-type semiconductor. Accordingly, the doping ion type of the drift region 300 is N-type, and the doping ion type of the body region 400 is P-type.

[0046] In this embodiment, the doping ions of the drift region 300 are phosphorus ions; in other embodiments, the doping ions of the drift region 300 may also be arsenic ions, antimony ions, sulfur ions or selenium ions.

[0047] In this embodiment, the doping ions of the body region 400 are boron ions; in other embodiments, the doping ions of the body region 400 may also be indium ions or gallium ions.

[0048] Continue to refer Figure 1 A gate structure 500 is formed on a portion of the substrate 100 in the first region I and a portion of the substrate 100 in the second region II, and the gate structure 500 covers a portion of the drift region 300 and a portion of the surface of the field oxide layer 200 .

[0049] In this embodiment, the gate structure 500 includes a gate oxide layer 510 located on the substrate 100 and a gate layer 520 located on the gate oxide layer 510 ; the material of the gate layer 520 is a polysilicon layer.

[0050] Specifically, the steps of forming the gate structure 520 include: forming a gate oxide film on the substrate 100; forming a gate film on the gate oxide film; forming a third graphic layer (not shown) on the gate film, wherein the third graphic layer covers a portion of the substrate 100 in the first region I and a portion of the substrate 100 in the second region II, and also covers a portion of the gate film above the field oxide layer 200; using the third graphic layer as a mask, sequentially etching the gate film and the gate oxide film until the substrate 100 or the field oxide layer 200 is exposed, to form a patterned gate oxide layer 510 and a gate layer 520, wherein the gate oxide layer 510 and the gate layer 520 constitute the gate structure 500.

[0051] In this embodiment, the material of the third pattern layer is photoresist. After the gate structure 500 is formed, the third pattern layer is removed by wet stripping or ashing process.

[0052] It should be noted that after the gate structure 500 is formed, a sidewall spacer 530 is further formed on the sidewall of the gate structure 500 .

[0053] Continue to refer Figure 1 After the gate structure 500 is formed, a source 110 and a drain 120 are formed in the substrate 100 on both sides of the gate structure 500 , the source 110 is located in the body region 400 , the drain 120 is located in the drift region 300 , and the field oxide layer 200 is located between the gate structure 500 and the drain 120 .

[0054] The type of doping ions in the source 110 and the drain 120 is the same as the type of doping ions in the drift region 300 .

[0055] Specifically, the method for forming the source 110 and the drain 120 includes: forming a patterned fourth pattern layer (not shown) on the substrate 100, wherein the fourth pattern layer exposes the areas corresponding to the source 110 and the drain 120; using the fourth pattern layer as a mask, performing a heavy doping process on the substrate 100 to form the source 110 and the drain 120; and removing the fourth pattern layer.

[0056] In this embodiment, the material of the fourth pattern layer is photoresist. After the source electrode 110 and the drain electrode 120 are formed, the fourth pattern layer is removed by wet stripping or ashing process.

[0057] refer to Figure 2 The ion doping region 600 is formed in the drift region 300 below the field oxide layer 200 exposed by the gate structure 500 , and the doping ion type of the ion doping region 600 is opposite to the doping ion type of the drift region 300 .

[0058] In this embodiment, the ion doping region 600 is formed in the drift region 300. Since the P-type ions in the ion doping region 600 can neutralize the N-type ions in the drift region 300, the ion doping concentration of the drift region 300 can be reduced, thereby improving the breakdown voltage of the semiconductor device. When the on-resistance is reduced by increasing the concentration of the drift region or reducing the width of the drift region, the resulting reduction in breakdown voltage can be compensated, and a relatively high breakdown voltage can still be maintained.

[0059] It should be noted that there are two situations for reducing the ion doping concentration of the drift region 300: in the first situation, the injected anti-type ions are relatively small, and the N-type ions in the drift region of the original area of ​​the ion-doped region are not completely neutralized, so the ion-doped region 600 formed is an N-type ion region with reduced concentration; in the second situation, the injected anti-type ions are relatively large, and the N-type ions in the drift region of the original area of ​​the ion-doped region are completely neutralized, so the ion-doped region 600 formed is a P-type ion region with relatively low concentration.

[0060] Furthermore, because the breakdown voltage is mainly determined by the electric field strength from the drain 120 to the end of the gate structure 500 on the field oxide layer 200, the drift region concentration in this area, that is, the doping concentration of the drift region 300 below the field oxide layer 200 exposed by the gate structure 500, has a greater influence on the breakdown voltage. By forming the ion doping region 600 in the drift region 300 below the field oxide layer 200 exposed by the gate structure 500 and reducing the drift region ion doping concentration in this area, the breakdown voltage of the semiconductor device can be more effectively improved.

[0061] Furthermore, because the area of ​​the drift region 300 covered by the gate structure 500 has carriers flowing on the surface of the drift region close to the gate structure 500 due to the modulation effect of the gate, if the ion doping area 600 is formed in the drift region 300 covered by the gate structure 500, the flow of carriers will be greatly affected, which is equivalent to a greater impact on the on-resistance, that is, the on-resistance will be greatly increased, which is not conducive to the performance of the semiconductor device. The distribution of carriers in the area of ​​the drift region 300 not covered by the gate structure 500 is relatively uniform, so forming the ion doping area 600 in the drift region 300 below the field oxide layer 200 exposed by the gate structure 500 can reduce the impact on the on-resistance.

[0062] In this embodiment, the substrate 100 is used to form an N-type semiconductor. Accordingly, the doping ion type of the drift region 300 is N-type, and the doping ion type of the ion doping region 600 is P-type.

[0063] In other embodiments, the substrate 100 may be used to form a P-type semiconductor. Accordingly, the doping ion type of the drift region 300 is P-type, and the doping ion type of the ion-doped region 600 is N-type.

[0064] In this embodiment, the doping ions of the ion-doped region 600 are boron ions; in other embodiments, the doping ions of the ion-doped region 600 may also be indium ions or gallium ions.

[0065] In this embodiment, when the thickness of the field oxide layer 200 is smaller than the thickness of the gate structure 500 , an ion implantation process is used to implant P-type ions into the drift region 300 below the field oxide layer exposed by the gate structure.

[0066] Because the ion doping region 600 is limited to be formed only in the drift region below the field oxide layer 200 exposed by the gate structure 500, when the thickness of the field oxide layer 600 is less than the thickness of the gate structure 500, the injection energy used enables the ions to penetrate the field oxide layer 600 but cannot penetrate the polysilicon layer 520 and the gate oxide layer 510 in the gate structure 500, and ion injection can be performed without the need for an additional mask layer.

[0067] Furthermore, the formed ion doped region 600 is close to the lower surface of the field oxide layer 200 and has a relatively narrow thickness. This is because, in the drift region not covered by the gate structure, the carriers flow in a relatively uniform distribution, and only a narrow layer of ion doped region is formed in the drift region close to the lower surface of the field oxide layer 200, which can reduce the impact on the flow of carriers in the drift region, which is equivalent to reducing the impact on the on-resistance of the device, and while increasing the breakdown voltage, the on-resistance is increased as much as possible.

[0068] In other embodiments, when the thickness of the field oxide layer 200 is greater than the thickness of the gate structure 500 , in order to prevent the injected counter ions from penetrating the field oxide layer 200 while also penetrating the gate structure 500 , an additional mask layer is required before performing the ion implantation process.

[0069] Specifically, the method for forming the ion-doped region 600 includes: forming a mask layer (not shown) on the substrate 100, the mask layer covering the gate structure 500, the drift region 300 and the surface of the field oxide layer 200; etching the mask layer to form an opening, the opening exposing the surface of the field oxide layer 200 exposed by the gate structure 500; and using an ion implantation process to implant ions along the opening into the drift region 300 below the field oxide layer 200 exposed by the gate structure 500.

[0070] The material of the mask layer is photoresist. After the ion implantation is completed, the mask layer is removed by wet stripping or ashing process.

[0071] In this embodiment, the reason why the ion-doped region 600 is formed last is that when forming other structures, such as a gate structure, a heat treatment process will be performed, and the heat treatment will cause the inversion ions of the ion-doped region 600 to diffuse deeper or wider, so that the formed ion-doped region cannot meet the requirements.

[0072] Continue to refer Figure 2 The present invention further provides a semiconductor structure, comprising: a substrate 100, wherein the substrate 100 comprises a first region I and a second region II; a field oxide layer 200, located on a portion of the substrate 100 in the first region I; a drift region 300, located in the substrate 100 in the first region I, and the field oxide layer 200 covers a portion of the drift region 300; a gate structure 500, located on a portion of the substrate 100 in the first region I and a portion of the substrate 100 in the second region II, and the gate structure 500 covers a portion of the drift region 300 and a portion of the surface of the field oxide layer 200; an ion doping region 600, located in the drift region 300 below the field oxide layer 200 exposed by the gate structure 500, and the doping ion type of the ion doping region 600 is opposite to the doping ion type of the drift region 300.

[0073] In this embodiment, the substrate 100 is a silicon substrate; in other embodiments, the substrate may also be a germanium substrate, a silicon-germanium substrate or a silicon carbide substrate, a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0074] In this embodiment, the material of the field oxide layer 200 is silicon oxide.

[0075] In this embodiment, the semiconductor structure further includes a body region 400 , and the body region 400 is located in the substrate 100 in the second region II. The doping ion type of the body region 400 is opposite to the doping ion type of the drift region 300 .

[0076] In this embodiment, the substrate 100 is used to form an N-type semiconductor. Accordingly, the doping ion type of the drift region 300 is N-type, and the doping ion type of the body region 400 is P-type.

[0077] In this embodiment, the doping ions of the drift region 300 are phosphorus ions; in other embodiments, the doping ions of the drift region 300 may also be arsenic ions, antimony ions, sulfur ions or selenium ions.

[0078] In this embodiment, the doping ions of the body region 400 are boron ions; in other embodiments, the doping ions of the body region 400 may also be indium ions or gallium ions.

[0079] In this embodiment, the gate structure 500 includes a gate oxide layer 510 located on the substrate 100 and a gate layer 520 located on the gate oxide layer 510 ; the material of the gate layer 520 is a polysilicon layer.

[0080] In this embodiment, the semiconductor structure further includes a sidewall spacer 530 , and the sidewall spacer 530 covers the sidewall of the gate structure 500 .

[0081] In this embodiment, the semiconductor structure also includes: a source 110 and a drain 120 located in the substrate 100 on both sides of the gate structure 500, the source 110 is located in the body region 400, the drain 120 is located in the drift region 300, and the field oxide layer 200 is located between the gate structure 500 and the drain 120.

[0082] The type of doping ions in the source 110 and the drain 120 is the same as the type of doping ions in the drift region 300 .

[0083] In this embodiment, the doping ion type of the ion doping region 600 is P type; in other embodiments, the doping ion type of the ion doping region 600 is N type.

[0084] In this embodiment, the doping ions of the ion-doped region 600 are boron ions; in other embodiments, the doping ions of the ion-doped region 600 may also be indium ions or gallium ions.

[0085] The semiconductor structure described in this embodiment includes an ion doping region 600 located in the drift region 300 below the field oxide layer 200 exposed by the gate structure 500, and the doping ion type of the ion doping region 600 is opposite to the doping ion type of the drift region 300. By neutralizing the N-type ions in the drift region 300 with the P-type ions in the ion doping region 600, the ion doping concentration of the drift region 300 below the field oxide layer 200 exposed by the gate structure 500 is reduced. Since the ion doping concentration of the drift region 300 below the field oxide layer 200 exposed by the gate structure 500 has a greater impact on the breakdown voltage of the semiconductor device and a smaller impact on the on-resistance, the breakdown voltage can be effectively increased without increasing the on-resistance as much as possible.

[0086] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a first region and a second region; forming a field oxide layer on the substrate in the first region; forming a drift region in the substrate in the first region; forming a gate structure on a portion of the substrate in the first region and a portion of the substrate in the second region, wherein the gate structure covers a portion of the drift region and a portion of the surface of the field oxide layer; An ion doping region is formed in the drift region below the field oxide layer exposed by the gate structure, and the ion doping region is only formed below the field oxide layer exposed by the gate structure, and the doping ion type of the ion doping region is opposite to the doping ion type of the drift region.

2. The method for forming a semiconductor structure according to claim 1, wherein: When the thickness of the field oxide layer is less than the thickness of the gate structure, the method for forming the ion doping region includes: using an ion implantation process to implant ions into the drift region below the field oxide layer exposed by the gate structure.

3. The method for forming a semiconductor structure according to claim 1, wherein: When the thickness of the field oxide layer is greater than the thickness of the gate structure, the method for forming the ion doping region includes: Forming a mask layer on the substrate, wherein the mask layer covers the gate structure, the drift region and a surface of the field oxide layer; Etching the mask layer to form an opening, wherein the opening exposes the surface of the field oxide layer exposed by the gate structure; An ion implantation process is adopted to implant ions along the opening into the drift region below the field oxide layer exposed by the gate structure.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method of forming the field oxide layer comprises: forming a pad oxide layer and a silicon nitride layer in sequence on the surface of the substrate; Etching the pad oxide layer and the silicon nitride layer to form a field oxygen opening, wherein the field oxygen opening exposes a portion of the substrate in the first region; The field oxide layer is formed on the substrate along the field oxide opening by using a local oxidation process.

5. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the gate structure, the method further includes: forming a body region in the substrate of the second region, wherein the doping ion type of the body region is opposite to the doping ion type of the drift region.

6. The method for forming a semiconductor structure according to claim 5, wherein: After forming the gate structure, the method further includes: forming a source and a drain in the substrate on both sides of the gate structure, wherein the source is located in the body region, the drain is located in the drift region, and the field oxide layer is located between the gate structure and the drain.

7. The method for forming a semiconductor structure according to claim 1, wherein: The semiconductor structure is an N-type semiconductor structure, the doping ion type of the drift region is N-type ions, and the doping ion type of the ion-doped region is P-type ions.

8. The method for forming a semiconductor structure according to claim 1, wherein: The semiconductor structure is a P-type semiconductor structure, the doping ion type of the drift region is P-type ions, and the doping ion type of the ion-doped region is N-type ions.

9. The method for forming a semiconductor structure according to claim 7 or 8, characterized in that: The N-type ions include phosphorus, arsenic, antimony, sulfur or selenium ions, and the P-type ions include boron, indium or gallium ions.

10. A semiconductor structure, characterized in that: include: a substrate comprising a first region and a second region; A field oxide layer, located on a portion of the substrate in the first region; A drift region is located in the substrate of the first area, and the field oxide layer covers a portion of the drift region; A gate structure, located on a portion of the substrate in the first region and a portion of the substrate in the second region, and the gate structure covers a portion of the drift region and a portion of the field oxide layer surface; An ion doped region, wherein the ion doped region is only located in the drift region below the field oxide layer exposed by the gate structure, and the doping ion type of the ion doped region is opposite to the doping ion type of the drift region.

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