Electronic device and operating method of electronic device

Abstract

Disclosed is an electronic device including: a unit interval detector including a plurality of delay units, and receiving a first signal, a second signal, and a third signal, and detecting a code indicating a unit interval from the first signal, the second signal, and the third signal; a clock recovery circuit generating a clock signal from the first signal, the second signal, and the third signal in response to the code; and a data recovery circuit generating a first received signal, a second received signal, and a third received signal from the first signal, the second signal, and the third signal in response to the code and the clock signal. A total delay amount of the delay units is smaller than a length of the unit interval, and the unit interval detector performs a multi-stage detection operation including a coarse detection and a fine detection by using the delay units.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0001641, filed on January 6, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the inventive concept described herein relate to a storage device, and more specifically, to an electronic device that includes an embedded clock for recovering clock signals from data. Background Technology

[0004] Various protocols are being used and developed for data communication between different devices. Currently, the C-PHY protocol is being developed as one of these protocols. A key feature of C-PHY is that separate clock signals are not exchanged between different devices.

[0005] A C-PHY transmitter can combine a data signal with an embedded clock and transmit the combined signal. A C-PHY receiver is configured to recover the clock signal from the received signal and to recover the data from the received signal using the clock signal.

[0006] Multiple delay elements can be used to recover the clock signal from the received signal. As the frequency range allowed by the C-PHY increases, the number of delay elements required for the C-PHY receiver also increases. This increase in the number of delay elements may lead to an increase in the size of the C-PHY receiver and the associated cost. Summary of the Invention

[0007] Embodiments of the present invention provide an electronic device for recovering a clock signal by using a reduced number of delay elements, and a method for operating the electronic device.

[0008] According to an exemplary embodiment, an electronic device includes: a unit interval detector comprising a plurality of delay units, and receiving a first signal, a second signal, and a third signal, and detecting a code indicating a unit interval from the first signal, the second signal, and the third signal; a clock recovery circuit, in response to the code, generating a clock signal from the first signal, the second signal, and the third signal; and a data recovery circuit, in response to the code and the clock signal, generating a first received signal, a second received signal, and a third received signal from the first signal, the second signal, and the third signal. The total delay of the plurality of delay units is less than the length of the unit interval, and the unit interval detector performs multi-level detection operations, including coarse detection and fine detection, by using the plurality of delay units.

[0009] According to an exemplary embodiment, an electronic device includes: a first delay unit including a first delay element and at least one second delay element connected in sequence, receiving a first signal switching between a high level and a low level and delaying the first signal to output as a second signal; a second delay unit including at least two third delay elements connected in sequence, receiving the second signal from the first delay unit and delaying the second signal to output as a third signal; a counter that performs a counting operation synchronously with the third signal and outputs a first code as a result of the counting operation; a first decision block connected to the first delay unit that detects a rising edge or a falling edge of a first internal signal from the first delay unit synchronously with a falling edge of the first signal, and outputs a first bit as a detection result of the rising edge or falling edge of the first internal signal; a second decision block connected to the second delay unit that detects a rising edge or a falling edge of a second internal signal from the second delay unit synchronously with a falling edge of the first signal, and outputs a second bit as a detection result of the rising edge or falling edge of the second internal signal; and an encoder that generates a second code from the first bit and the second bit. The second signal is fed back to the first delay element via an inverter.

[0010] According to an exemplary embodiment, an operating method of an electronic device includes: receiving a first signal that switches between a high level and a low level; generating a second signal that switches between the high level and the low level in response to the first signal, the period of the second signal being less than the period of the first signal; counting the number of times the second signal passes through a delay loop including a first delay unit and a second delay unit when the first signal is at a high level, and generating a first code as a result of the counting; detecting the position of the rising edge or falling edge of the second signal on the delay loop synchronously with the falling edge of the first signal, and generating a second code as a result of the detection; and combining the first code and the second code to generate a third code as a result of the combination. Attached Figure Description

[0011] The above and other objects and features of the present invention will become clear from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings.

[0012] Figure 1 An electronic device is shown as an embodiment of a concept according to the present invention.

[0013] Figure 2 A multi-stage unit interval detector according to an embodiment of the present invention is shown.

[0014] Figure 3 A first delay element according to an embodiment of the present invention is shown.

[0015] Figure 4 A second delay element according to an embodiment of the present invention is shown.

[0016] Figure 5 Examples of the first, second, and third signals are shown.

[0017] Figure 6 The shapes of the fourth to eighth signals are shown when the feedback loop of the sixth signal is absent.

[0018] Figure 7 Examples of the fourth to eighth signals of a multi-stage unit-interval detector, including the feedback loop of the sixth signal, are shown.

[0019] Figure 8 An example of the signal waveform when 24 delay units are operating is shown to more clearly illustrate the technical concept of the invention.

[0020] Figure 9 An example of the output of the three second delay elements of the delay unit that outputs the eleventh signal is shown.

[0021] Figure 10 An operational method for a multi-stage unit interval detector according to an embodiment of the present invention is shown.

[0022] Figure 11 A method for detecting the length of the high-level interval of the fourth signal, based on the first example, is conceptually illustrated.

[0023] Figure 12 A method for detecting the length of the high-level interval of a fourth signal, according to an embodiment of the present invention, is conceptually illustrated.

[0024] Figure 13 A clock recovery circuit according to an embodiment of the present invention is shown.

[0025] Figure 14 A data recovery circuit according to an embodiment of the present invention is shown.

[0026] Figure 15 A block diagram of an electronic device according to an example embodiment of the present invention is shown. Detailed Implementation

[0027] Embodiments of the inventive concept are described below in detail and clearly to enable those skilled in the art to readily implement the inventive concept.

[0028] Figure 1 An electronic device according to an embodiment of the concept of the present invention is shown. Reference Figure 1 The electronic device system may include a first electronic device 100 and a second electronic device 200.

[0029] The first electronic device 100 can transmit signals to the second electronic device 200 via the first signal line SL1, the second signal line SL2, and the third signal line SL3. The first signal line SL1, the second signal line SL2, and the third signal line SL3 can form a lane and can transmit signals that are related to each other and change (or are switched).

[0030] The first electronic device 100 may include a signal generator 110, a first transmitter 120, a second transmitter 130, and a third transmitter 140. The signal generator 110 may generate signals to be transmitted via the first signal line SL1, the second signal line SL2, and the third signal line SL3.

[0031] The first transmitter 120, the second transmitter 130, and the third transmitter 140 can be connected to the first signal line SL1, the second signal line SL2, and the third signal line SL3 respectively via the first terminal 121, the second terminal 131, and the third terminal 141.

[0032] The first transmitter 120, the second transmitter 130, and the third transmitter 140 can transmit signals according to one of various communication protocols. For example, the first transmitter 120, the second transmitter 130, and the third transmitter 140 can transmit signals according to C-PHY protocols, including C-PHY v2.0 defined by the Mobile Industrial Processor Interface (MIPI). The MIPI C-PHY is an embedded clock link, providing great flexibility to reallocate channels within the link. It also provides low-latency transitions between high-speed and low-power modes. The MIPI C-PHY achieves this by deviating from conventional differential signaling techniques on two-wire channels and introducing approximately 2.28 bits / symbol tri-phase symbol encoding to transmit data symbols on three-wire channels, or "trios," where each trio includes an embedded clock. Three trios operating at 9 Gsym / s achieve a peak data rate of approximately 41 Gbps through a nine-wire interface.

[0033] The second electronic device 200 can receive signals via the first signal line SL1, the second signal line SL2, and the third signal line SL3. The second electronic device 200 may include a first receiver 210, a second receiver 220, a third receiver 230, a multi-level unit interval detector 240, a clock recovery circuit 250, a data recovery circuit 260, and a signal processor 270.

[0034] The first receiver 210, the second receiver 220, and the third receiver 230 can receive signals from the first signal line SL1, the second signal line SL2, and the third signal line SL3 respectively through the first terminal 211, the second terminal 221, and the third terminal 231. The first receiver 210 can output the difference between the signal received from the first signal line SL1 through the first terminal 211 and the signal received from the second signal line SL2 through the second terminal 221 as the first signal S1.

[0035] The second receiver 220 can output the difference between the signal received from the second signal line SL2 via the second terminal 221 and the signal received from the third signal line SL3 via the third terminal 231 as the second signal S2. The third receiver 230 can output the difference between the signal received from the third signal line SL3 via the third terminal 231 and the signal received from the first signal line SL1 via the first terminal 211 as the third signal S3.

[0036] The multi-level unit interval detector 240 can receive a first signal S1, a second signal S2, and a third signal S3. The multi-level unit interval detector 240 can detect unit intervals from the first signal S1, the second signal S2, and the third signal S3. For example, a unit interval can be an interval comprising one symbol for each of the first signal S1, the second signal S2, and the third signal S3.

[0037] For example, based on the C-PHY protocol, the first transmitter 120, the second transmitter 130, and the third transmitter 140 may have a preamble interval before transmitting symbols containing data. During the preamble interval, the first transmitter 120, the second transmitter 130, and the third transmitter 140 may transmit signals for detecting unit intervals.

[0038] A multi-level unit interval detector 240 can detect unit intervals from a first signal S1, a second signal S2, and a third signal S3 during a preamble interval. The multi-level unit interval detector 240 may include multiple delay elements "D". Hereinafter, the multiple delay elements "D" may include a first delay element D' and a second delay element "D" connected in series. As used herein, "element" may refer to "circuit". The multi-level unit interval detector 240 can detect unit intervals by using multiple delay elements "D". The multi-level unit interval detector 240 can output a code [n:0] as information about the length of the unit interval. The code [n:0] may have a resolution of (n+1) bits.

[0039] In an embodiment, the total delay of the delay element "D" can be shorter than the length of the unit interval. The multi-level unit interval detector 240 can be implemented in a multi-level structure in which the delay element includes a coarse detection level and a fine detection level, wherein the total delay of the coarse detection level is shorter than the length of the unit interval. The multi-level unit interval detector 240 can generate code [n: 0] based on the multi-level structure of the delay element "D".

[0040] The clock recovery circuit 250 can receive the first signal S1, the second signal S2, the third signal S3, and the code [n: 0]. The clock recovery circuit 250 can recover the clock signal CLK from the first signal S1, the second signal S2, and the third signal S3 using the code [n: 0].

[0041] Based on the C-PHY protocol, the first transmitter 120, the second transmitter 130, and the third transmitter 140 can transmit signals including data, wherein a clock signal is incorporated into the signals. The incorporated clock signal may include an embedded clock. The embedded clock may also appear at the first signal S1, the second signal S2, and the third signal S3.

[0042] In each unit interval, when one of the first signal S1, the second signal S2, and the third signal S3 transitions, the clock recovery circuit 250 can allow the clock signal CLK to transition to a high level. Subsequently, when the remaining signals of the first signal S1, the second signal S2, and the third signal S3 transition at the same symbol interval, the clock recovery circuit 250 can maintain the level of the clock signal CLK without requiring any transition of the clock signal CLK.

[0043] For example, clock recovery circuit 250 can identify the length of the unit interval from the code [n:0], such as 1UI (unit interval). Clock recovery circuit 250 can maintain the level of clock signal CLK by shielding clock signal CLK for a given time period ranging from 0.3UI to 0.6UI after the clock signal CLK transitions in each unit interval.

[0044] After a given time has elapsed, the clock recovery circuit 250 allows the clock signal CLK to transition to a low level. In other words, the clock recovery circuit 250 can generate the clock signal CLK, the period of which corresponds to a unit interval.

[0045] The data recovery circuit 260 can receive a first signal S1, a second signal S2, a third signal S3, and a code [n: 0]. The data recovery circuit 260 can delay the first signal S1, the second signal S2, and the third signal S3 based on the code [n: 0]. For example, the data recovery circuit 260 can adjust the delay amount to facilitate latching the first signal S1, the second signal S2, and the third signal S3. For example, the delay amount can be 0.5 UI or a similar value.

[0046] The data recovery circuit 260 can latch the delayed first signal S1, the delayed second signal S2, and the delayed third signal S3 synchronously with the clock signal CLK. The data recovery circuit 260 can output the latched results as the first received signal RS1, the second received signal RS2, and the third received signal RS3.

[0047] The signal processor 270 can receive a first received signal RS1, a second received signal RS2, and a third received signal RS3. The signal processor 270 can operate in response to the first received signal RS1, the second received signal RS2, and the third received signal RS3.

[0048] In one embodiment, the first electronic device 100 may be an application processor (AP), and the second electronic device 200 may be a display device. In another example, the first electronic device 100 may be an image sensor, and the second electronic device 200 may be an application processor (AP).

[0049] exist Figure 1 The diagram shows a channel including a first signal line SL1, a second signal line SL2, and a third signal line SL3. However, the first electronic device 100 and the second electronic device 200 can communicate with each other through two or more channels.

[0050] Figure 2 A multi-level unit interval detector 300 according to an embodiment of the present invention is shown. The multi-level unit interval detector 300 may be... Figure 1 Multi-stage unit-interval detector 240. Reference. Figure 1 and Figure 2 The multi-level unit interval detector 300 may include logic gate 310, first delay unit 321 to fourth delay unit 324, first decision block 331 to fourth decision block 334, first inverter 340, second inverter 350, counter 360 and encoder 370.

[0051] Logic gate 310 can receive a first signal S1, a second signal S2, and a third signal S3. Logic gate 310 can perform an XOR operation on the first signal S1, the second signal S2, and the third signal S3. For example, logic gate 310 can perform the operation during the preamble interval.

[0052] Logic gate 310 can output the result of the operation as a fourth signal S4. For example, the fourth signal S4 can be in the form of a clock signal that periodically switches (or transitions) between high and low levels.

[0053] The first delay unit 321 can receive the fourth signal S4. The first delay unit 321 may include a first delay element D' and two second delay elements "D" arranged or connected in sequence. The first delay element D' can generate an internal clock signal in response to the fourth signal S4, the period of which is shorter than the period of the fourth signal S4. The switching timing of the internal clock signal (e.g., a first switching timing) may be delayed relative to the switching timing of the fourth signal S4 (e.g., a first switching timing).

[0054] The first delay element D' can receive the inverted forms of the fourth signal S4 and the sixth signal S6 (i.e., the signal generated by inverting the sixth signal S6 through the first inverter 340). When the fourth signal S4 is high and the inverted version of the sixth signal S6 is low, the first delay element D' can output a low-level internal clock signal. When the fourth signal S4 is high and the inverted version of the sixth signal S6 is high, the first delay element D' can output a high-level internal clock signal.

[0055] The two second delay elements "D" of the first delay unit 321 can delay and output an internal clock signal. The first delay unit 321 can output a delayed signal as a fifth signal S5. The second delay unit 322 can receive the fifth signal S5. The second delay unit 322 may include three second delay elements "D" arranged or connected in sequence. The second delay unit 322 can output a delayed signal as a sixth signal S6. The sixth signal S6 can be fed back to the first delay element D' of the first delay unit 321.

[0056] The third delay unit 323 can receive the sixth signal S6. The third delay unit 323 may include three second delay elements "D" arranged or connected in sequence. The third delay unit 323 can output a delayed signal as the seventh signal S7. The fourth delay unit 324 can receive the seventh signal S7. The fourth delay unit 324 may include three second delay elements "D" arranged or connected in sequence. The fourth delay unit 324 can output a delayed signal as the eighth signal S8.

[0057] The first decision block 331 can receive the outputs of the first delay element D' and the two second delay elements "D" of the first delay unit 321. The first decision block 331 can perform the decision synchronously with the fourth signal S4. The first decision block 331 can determine at the decision time whether there is a rising edge of the internal clock signal in the first delay unit 321.

[0058] When it is determined that there is a rising edge of the internal clock signal in the first delay unit 321 at the determination time point, the first determination block 331 can output a first code signal C1 with logic "1". When it is determined that there is no rising edge of the internal clock signal in the first delay unit 321 at the determination time point, the first determination block 331 can output a first code signal C1 with logic "0".

[0059] The second decision block 332 can receive the outputs of the three second delay elements "D" of the second delay unit 322. Similar to the first decision block 331, the second decision block 332 can synchronously determine with the fourth signal S4 whether there is a rising edge of the internal clock signal in the second delay unit 322 at the decision time point, and can output the second code signal C2 as the result of the determination.

[0060] The third decision block 333 can receive the outputs of the three second delay elements "D" of the third delay unit 323. Similar to the first decision block 331, the third decision block 333 can synchronously determine with the fourth signal S4 whether there is a rising edge of the internal clock signal in the third delay unit 323 at the decision time point, and can output the third code signal C3 as the result of the determination.

[0061] The fourth decision block 334 can receive the outputs of the three second delay elements "D" of the fourth delay unit 324. Similar to the first decision block 331, the fourth decision block 334 can determine, synchronously with the fourth signal S4, whether there is a rising edge of the internal clock signal in the fourth delay unit 324 at the decision time point, and can output the fourth code signal C4 as the result of the determination.

[0062] The second inverter 350 inverts the eighth signal S8, and its output can be fed to the counter 360. The counter 360 can perform a counting operation synchronously with the output of the second inverter 350 (e.g., its rising edge). In some examples, the counter 360 can perform a counting operation synchronously with the eighth signal S8. The counter 360 can receive a fourth signal S4. When the fourth signal S4 is high, the counter 360 can perform a counting operation.

[0063] Counter 360 can output a count value as a first code CD[n:2] synchronously with the falling edge of the fourth signal S4. The first code CD[n:2] can include information related to the number of times the internal clock signal passes through the first delay unit 321 to the fourth delay unit 324. The first code CD[n:2] can be the result of a coarse detection and can consist of consecutive bits including the most significant bit MSB (e.g., C[n]) in the bits of code [n:0].

[0064] Encoder 370 can receive first code signals C1 to fourth code signals C4 from first decision blocks 331 to fourth decision blocks 334. Encoder 370 can generate a second code CD[1:0] from the first code signals C1 to the fourth code signals C4. For example, when the number of delay units is greater than 2 i-1 And equal to or less than 2 i In this case, the second code can consist of "i" bits.

[0065] Because Figure 2 The diagram shows the first delay unit 321 to the fourth delay unit 324, so the second code CD[1:0] can consist of two bits. At the falling edge of the fourth signal S4 (e.g., the decision time point), the second code CD[1:0] can include the position information of the rising edge of the internal clock signal, for example, information related to the delay unit in the first delay unit 321 to the fourth delay unit 324 where the rising edge of the internal clock signal exists.

[0066] The second code CD[1:0] can be the result of fine detection. The second code CD[1:0] can consist of consecutive bits, including the least significant bit (LSB) of the bits in code [n:0].

[0067] As described above, the multi-level unit interval detector 240 generates an internal clock signal with a period shorter than that of the input clock signal (e.g., the fourth signal S4) by forming a feedback loop using one of the output signals (i.e., the intermediate signal) of the delay units 321 to 324. The multi-level unit interval detector 240 can perform coarse detection by counting the number of times the internal clock signal passes through the first delay unit 321 to the fourth delay unit 324.

[0068] Similarly, the multi-level unit interval detector 240 can perform fine detection by detecting the position of the rising edge of the internal clock signal from the first delay unit 321 to the fourth delay unit 324 at the decision time point.

[0069] exist Figure 2An example is shown where the number of delay units is "4" and the number of decision blocks is "4", but the inventive concept is not limited thereto. For example, the number of delay units and the number of decision blocks can be modified or changed differently. Based on the characteristics of a C-PHY protocol with a variable range from 1 GHz to 6 GHz, each of the number of delay units and the number of decision blocks can be fixed at "24". In an embodiment, the number of delay units belonging to the preceding stage of the signal included in the feedback loop can be equal to the number of delay units belonging to the following stage of the signal.

[0070] In an embodiment, the multi-level unit interval detector 240 can be interpreted as including a first delay unit (or a group of delay elements) and a second delay unit (or a group of delay elements). The first delay unit receives the fourth signal S4 and includes sub-delay units (e.g., the first delay unit 321 and the second delay unit 322), and the second delay unit receives the sixth signal S6 and includes sub-delay units (e.g., the third delay unit 323 and the fourth delay unit 324).

[0071] Considering that the number of times the internal clock signal passes through the first delay unit 321 to the fourth delay unit 324 is counted by the counter 360, the first delay unit 321 to the fourth delay unit 324 can be interpreted as forming a delay loop.

[0072] An embodiment is shown in which counter 360 performs a counting operation synchronously with the falling edge of the eighth signal S8 when inverter 350 is provided. Alternatively, an odd number of inverters may be added between counter 360 and the fourth delay unit 324. However, as an option, inverter 350 of the multi-stage unit interval detector 300 may be omitted (or removed). For example, when inverter 350 between counter 360 and the fourth delay unit 324 is omitted, counter 360 may perform a counting operation synchronously with the rising edge of the eighth signal S8.

[0073] In some examples, when the second code CD[1:0] is generated from the first code signal C1 and the second code signal C2, the counter 360 may output a count value as the first code CD[n:2] as a result of a counting operation in response to the output of the eighth signal S8. In some examples, when the second code CD[1:0] is generated from the first code signal C1 and the second code signal C2, the counter 360 may output a count value as the first code CD[n:2] as a result of a counting operation in response to the output of the second inverter 350.

[0074] Figure 3 A first delay element D' according to an embodiment of the present invention is shown. (Reference) Figure 2 and Figure 3The first delay element D' may include a first logic gate LG1, a second logic gate LG2 and a third logic gate LG3.

[0075] The first logic gate LG1 can perform a NAND operation on the output of the first inverter 340 and the fourth signal S4. That is, when the fourth signal S4 is high and the sixth signal S6 is low, the first logic gate LG1 can output a low level.

[0076] Each of the second logic gate LG2 and the third logic gate LG3 can be an inverter. The output of the second logic gate LG2 can be output to the second delay element "D" of the first delay unit 321, and the output of the third logic gate LG3 can be output to the first decision block 331.

[0077] Figure 4 A second delay element "D" is shown according to an embodiment of the concept according to the present invention. Reference Figure 2 and Figure 4 The second delay element "D" may include the fourth logic gate LG4, the fifth logic gate LG5, the sixth logic gate LG6, and the seventh logic gate LG7.

[0078] The fourth logic gate LG4 can perform a NAND operation on a low level VL. That is, the fourth logic gate LG4 can output a high level. The fifth logic gate LG5 can perform a NAND operation on the output of the fourth logic gate LG4 (i.e., a high level) and the output of the first delay element D' or the second delay element "D".

[0079] When the output of the first delay element D' or the second delay element "D" is low, the fifth logic gate LG5 can output a high level. When the output of the first delay element D' or the second delay element "D" is high, the fifth logic gate LG5 can output a low level.

[0080] Each of the sixth logic gate LG6 and the seventh logic gate LG7 can be an inverter. The output of the sixth logic gate LG6 can be output to the corresponding delay element "D" or the second inverter 350, and the output of the seventh logic gate LG7 can be output to the corresponding decision blocks of the first decision blocks 331 to the fourth decision blocks 334.

[0081] Figure 5 An example of the first signal S1, the second signal S2, and the third signal S3 is shown. (Reference) Figure 2 and Figure 5 During the preamble interval, only one of the first signal S1, the second signal S2, and the third signal S3 changes within a unit interval UI. Furthermore, as the unit interval UI repeats, the first signal S1, the second signal S2, and the third signal S3 change alternately.

[0082] The fourth signal S4 is the result of an XOR operation performed on the first signal S1, the second signal S2, and the third signal S3. The fourth signal S4 can be in the form of a clock signal, with half a cycle corresponding to a unit interval UI.

[0083] Figure 6 The diagram illustrates the shapes of signals S4 through S8 when the feedback loop for the sixth signal S6 is absent. (Reference) Figure 2 and Figure 6 When there is no feedback loop for the sixth signal S6, the fifth signal S5 can be delayed relative to the fourth signal S4 by a total delay of up to three delay elements (i.e., one first delay element D' and two second delay elements "D").

[0084] When the feedback loop of the sixth signal S6 is not present, the sixth signal S6 can be delayed relative to the fifth signal S5 by a total delay of up to three delay elements (i.e., three second delay elements "D"), the seventh signal S7 can be delayed relative to the sixth signal S6 by a total delay of up to three delay elements (i.e., three second delay elements "D"), and the eighth signal S8 can be delayed relative to the seventh signal S7 by a total delay of up to three delay elements (i.e., three second delay elements "D").

[0085] Figure 7 An example of the fourth to eighth signals S8 of a multi-stage unit-interval detector 240, including a feedback loop for the sixth signal S6, is shown. (Reference) Figure 2 and Figure 7 At the first time T1, the rising edge of the fourth signal S4 can occur. The first delay element D' can receive the low-level sixth signal S6 and the high-level fourth signal S4 through the inverter 340, and can output a high level.

[0086] At a second time T2, which is a total delay of up to three delay elements (i.e., one first delay element D' and two second delay elements) relative to the first time T1, a rising edge may appear in the fifth signal S5.

[0087] At a third time T3, with a total delay of up to three delay elements (i.e., three second delay elements "D") relative to the second time T2, a rising edge may occur in the sixth signal S6. The rising edge of the sixth signal S6 can be fed back to the first delay element D' of the first delay unit 321 via the inverter 340. The first delay element D' of the first delay unit 321 can output a low level in response to the rising edge of the sixth signal S6 at the third time T3.

[0088] At a fourth time T4, which is delayed by a total of up to three delay elements (i.e., one first delay element D' and two second delay elements "D") relative to the third time T3, a falling edge may appear in the fifth signal S5. At a fifth time T5, which is delayed by a total of up to three delay elements (i.e., three second delay elements "D") relative to the fourth time T4, a falling edge may appear in the sixth signal S6.

[0089] The falling edge of the sixth signal S6 can be fed back to the first delay element D' of the first delay unit 321 via the inverter 340. The first delay element D' of the first delay unit 321 can output a high level in response to the falling edge of the sixth signal S6 at the fifth time T5. At the sixth time T6, which is delayed by up to three delay elements (i.e., one first delay element D' and two second delay elements "D") relative to the fifth time T5, a rising edge can occur in the fifth signal S5.

[0090] For example, the fifth signal S5 can be in the form of an internal clock signal that switches between high and low levels, wherein the period of this internal clock signal is shorter than the period of the fourth signal S4. The sixth signal S6, the seventh signal S7, and the eighth signal S8 can be generated by sequentially delaying the internal clock signal that is the fifth signal S5.

[0091] The falling edge of the fifth signal S5, which occurs at the seventh time T7, can reflect the falling edge of the fourth signal S4. When the fourth signal S4 is at a high level, the first delay element D' can generate an internal clock signal that transitions between high and low levels, the period of which is shorter than the period of the fourth signal S4.

[0092] When a feedback loop is formed by using the middle of the first delay unit 321 to the fourth delay unit 324 (for example, by using the sixth signal S6), the period of the internal clock signal can be the same as or similar to the total delay of the first delay unit 321 to the fourth delay element 321.

[0093] The falling edge of the fourth signal S4 can be the decision time point "TD". At the decision time point "TD", the multi-level unit interval detector 240 can output the coarse detection result by using the count value of the output counter 360 as the first code CD[n:2]. At the decision time point TD, the multi-level unit interval detector 240 can output the fine detection result by using the encoded value of the output encoder 370 as the second code CD[1:0]. In some examples, the encoder 370 can be an adder.

[0094] When inverter 350 is present, counter 360 can perform an incrementing count operation CNTU synchronously with the falling edge of the eighth signal S8. Therefore, at the decision time TD, the first code CD[n:2] can indicate the value "0". The first code CD[n:2] being "0" can mean that code [n:0] can be generated by one of the first decision blocks 331 to the fourth decision block 334.

[0095] When inverter 350 is absent, counter 360 can perform an incrementing count operation synchronously with the rising edge of the eighth signal S8. Therefore, at the decision time TD, the first code CD[n:2] can indicate a value of "0". The first code CD[n:2] being "0" can mean that the rising edge of the fourth signal S4 has passed through 4 delay units.

[0096] Figure 8 An example of the signal waveform when eight delay units (e.g., 24 delay elements "D") are operated is shown to more clearly illustrate the technical concept of the invention. Reference Figure 2 and Figure 8 Assume the multi-stage unit-interval detector 300 includes 8 delay units. The first delay unit among the 8 delay units can receive the fourth signal S4. Assume the 8 delay units output the fifth signal S5 to the twelfth signal S12.

[0097] The middle of the eight delay units (i.e., the output of the fourth delay unit) can be the eighth signal S8. Assume the eighth signal S8 is fed back to the first delay element D' of the first delay unit. Similar to the reference... Figure 7 The given description states that the fifth signal S5 to the twelfth signal S12 can be in the form of clock signals with a period shorter than that of the fourth signal S4, and can be in the form of sequential delays.

[0098] In some examples, when inverter 350 is present, counter 360 can perform an incrementing count operation CNTU synchronously with the falling edge of the twelfth signal S12. Therefore, at the decision time TD, the first code CD[n:2] can indicate the value "1". The first code CD[n:2] being "1" can mean that the rising edge of the fourth signal S4 passes through 8 delay units (e.g., 1 first delay element D' and 23 second delay elements "D") 1.5 times, that is, through 36 delay elements "D".

[0099] In some examples, when inverter 350 is absent, counter 360 can perform an incrementing count operation CNTU synchronously with the rising edge of the twelfth signal S12. Therefore, at the decision time TD, the first code CD[n:2] can indicate the value "2". The first code CD[n:2] being "2" can mean that the rising edge of the fourth signal S4 passes through 8 delay units twice, that is, through 48 delay elements "D".

[0100] Here, the first code CD[n:2], which indicates a value of "1" or "2", can be expressed as a 3-bit binary code.

[0101] In some embodiments, the counter 360 may receive the twelfth signal S12 and its inverted signal, and may perform an incrementing counting operation synchronously with the twelfth signal S12 and its inverted signal.

[0102] For example, when a fine code is selected among the fifth signal S5 to the eighth signal S8, the code [n: 0] can be determined by using the count value obtained from the inverted signal using the twelfth signal S12.

[0103] Although not shown, the eight decision blocks can detect the rising edge of the internal clock signal. Since a feedback loop is formed by using the middle (or center of the delay loop) of the eight delay units (i.e., by using the eighth signal S8), the period of the internal clock signal can be equal to the total delay of the eight delay units. Therefore, at the decision time TD, only one rising edge can exist in the eight delay units.

[0104] In other examples, when inverter 350 is not present, the eight decision blocks can detect the falling edge of the internal clock signal.

[0105] In the embodiment, at the determination time point TD, such as Figure 8 As shown, the seventh signal S7 can be at a high level, while the eleventh signal S11 can be at a low level. Therefore, it can be determined that the rising edge of the internal clock signal exists in the delay unit of the output seventh signal S7, and the falling edge of the internal clock signal exists in the delay unit of the output eleventh signal S11.

[0106] Figure 9 An example of the output of the three second delay elements "D" of the delay unit that outputs the seventh signal S7 is shown. (Reference) Figure 2 , Figure 8 and Figure 9The eleventh signal S7 can be the output of the second delay element "D" placed in the third delay unit corresponding to the seventh signal S7. The 7_2 signal S7_2 can be the output of the second delay element "D" placed in the second delay unit corresponding to the seventh signal S7. The 7_2 signal S7_2 can be ahead of the seventh signal S7 by up to one delay element "D".

[0107] Signal S7_1 can be the output of the second delay element "D" placed in the first delay unit corresponding to the seventh signal S7. Signal S7_1 can be delayed relative to signal S7_2 by up to one second delay element "D".

[0108] At the determination time TD, signals S7_1 and S7_2 are at a high level, while signal S7 is at a low level. Therefore, it can be determined that the rising edge of the internal clock signal exists between the second placed second delay element "D" and the third placed second delay element "D".

[0109] Figure 10 The operation method of a multi-stage unit interval detector 300 according to an embodiment of the present invention is shown. (Reference) Figure 2 and Figure 10 In operation S110, the multi-level unit interval detector 300 can perform coarse detection, wherein a first code CD[n:2] is generated by counting the number of times the internal clock signal passes through the delay loop.

[0110] In operation S120, the multi-level unit interval detector 300 can determine the position of the rising edge of the internal clock signal within the delay loop and can generate the second code CD[1:0]. In operation S130, the multi-level unit interval detector 300 can combine the first code CD[n:2] and the second code CD[1:0] to generate code [n:0].

[0111] Figure 11 A method for detecting the length of the high-level interval of the fourth signal S4 is conceptually illustrated according to another example. (Reference) Figure 11 The delay loop DL can have a total delay greater than the length of the high-level interval of the fourth signal S4 (e.g., the length of a unit interval UI). The length of the high-level interval of the fourth signal S4 can be determined by inputting the fourth signal S4 into the delay loop DL and determining the position where the rising edge and falling edge of the fourth signal S4 are placed synchronously on the delay loop DL.

[0112] according to Figure 11In this method, the total delay of the delay loop DL may have to be longer than the length of the high-level interval of the fourth signal S4. The C-PHY protocol defines the use of frequencies in the range of 1 GHz to 6 GHz. Therefore, the total delay of the delay loop DL may have to be longer than half a period of 1 GHz. Figure 11 The method requires too many delay elements when detecting UI at unit intervals, and also has the problems of increased size and cost.

[0113] Figure 12 A method for detecting the length of the high-level interval of the fourth signal S4 is conceptually illustrated according to an embodiment of the present invention. (Reference) Figure 12 The total delay of the delay loop DL can be determined regardless of the length of the high-level interval of the fourth signal S4 (i.e., the length of the unit interval UI).

[0114] An internal clock signal with a period shorter than that of the fourth signal S4 can be generated from the fourth signal S4. This internal clock signal is input to the delay circuit DL. The rising edge of the internal clock signal being output at the twelfth signal S12 indicates that the internal clock signal passes through the delay circuit DL once. The first delay circuit DL through which the internal clock signal passes can be the first delay circuit DLP1.

[0115] The fact that the rising edge of the internal clock signal is output for the second time at the twelfth signal S12 indicates that the internal clock signal passes through the delay loop DL again. The delay loop DL through which the internal clock signal passes for the second time can be the second delay loop DLP2. That is, the number of times the internal clock signal passes through delay loops DLP1 and DLP2 can be counted by counting the edges of the internal clock signal output at the twelfth signal S12 up to the determination time point TD.

[0116] The length of the high-level interval of the fourth signal S4 can be determined by adding the total delay of the first delay loop DLP1 and the second delay loop DLP2 to the total delay on the third delay loop DLP3 associated with the rising edge of the internal clock signal during the third delay loop DLP3. In an embodiment, the multi-level unit interval detector 300 can determine the length of a longer unit interval by increasing the resolution of the counter 360 (i.e., the number of bits to be counted).

[0117] According to the present invention, the length of a unit interval can be determined by using a limited number of delay elements (e.g., delay elements whose total delay is less than the length of the shortest unit interval defined in the C-PHY protocol). Therefore, the number of delay elements can be reduced, and the size and cost of the multi-stage unit interval detector 300 can be reduced.

[0118] Figure 13A clock recovery circuit 400 according to an embodiment of the present invention is shown. Figure 13 The clock recovery circuit 400 may be included in Figure 1 The clock recovery circuit 250 is used. (Reference) Figure 1 and Figure 13 The clock recovery circuit 400 may include logic circuitry capable of generating a clock signal CLK based on transitions occurring at the first signal S1, the second signal S2, and the third signal S3. For example, the logic circuitry may include first to sixth flip-flops 411, 412, 421, 422, 431, and 432, and first to fourth logic gates 440, 450, 460, and 470.

[0119] The first flip-flop 411 and the second flip-flop 412 can output a logic value (e.g., logic value "1") that is logic high VH in response to the transition of the first signal S1. The first logic gate 440 can combine the outputs of the first flip-flop 411 and the second flip-flop 412. Therefore, when the first signal S1 transitions, the first logic gate 440 can output the logic value "1".

[0120] The third flip-flop 421 and the fourth flip-flop 422 can output a logic value (e.g., logic value "1") high in response to the transition of the second signal S2. The second logic gate 450 can combine the outputs of the third flip-flop 421 and the fourth flip-flop 422. Therefore, when the second signal S2 transitions, the second logic gate 450 can output the logic value "1".

[0121] The fifth flip-flop 431 and the sixth flip-flop 432 can output a logic value (e.g., logic value "1") high in response to the transition of the third signal S3. The third logic gate 460 can combine the outputs of the fifth flip-flop 431 and the sixth flip-flop 432. Therefore, when the third signal S3 transitions, the third logic gate 460 can output the logic value "1".

[0122] The fourth logic gate 470 can combine the outputs of the first logic gate 440, the second logic gate 450, and the third logic gate 460. Therefore, the fourth logic gate 470 can output the logic value "1" in response to transitions occurring at the first signal S1, the second signal S2, and the third signal S3. However, the fourth logic gate 470 can also output the logic value "1" in response to a first transition of the first signal S1, the second signal S2, and the third signal S3, and can be unaffected by transitions after the first transition.

[0123] The fourth logic gate 470 can output a clock signal CLK generated by the first to sixth flip-flops 411, 412, 421, 422, 431 and 432, and the first to fourth logic gates 440, 450, 460 and 470. For example, the logic value "1" of the clock signal CLK output from the fourth logic gate 470 can provide the first edge (e.g., rising edge) of the clock signal CLK.

[0124] Delay circuit 480 can receive the clock signal CLK output from fourth logic gate 470. Delay circuit 480 can delay the received signal to output a reset signal RST. Delay circuit 480 can receive the clock signal CLK and can include delay elements "D" connected or arranged in sequence.

[0125] The first through sixth flip-flops 411, 412, 421, 422, 431, and 432 can be reset in response to the reset signal RST. When the first through sixth flip-flops 411, 412, 421, 422, 431, and 432 are reset, the first through fourth logic gates 440, 450, 460, and 470 can output a logic value of "0". The logic value "0" of the clock signal CLK output from logic gate 470 can provide a second edge (e.g., a falling edge) for the clock signal CLK. Therefore, the clock signal CLK can have a second edge in response to the reset signal RST.

[0126] The delay amount of the delay element "D" in the delay circuit 480 can be adjusted based on the code [n:0]. For example, the delay amount of each delay element "D" in the delay circuit 480 can be equal to... Figure 2 The delay amount of the first delay element D' or the second delay element "D". The code [n:0] can represent 1 / 3 of the length of the unit interval UI and the number of delay units. The delay circuit 480 can output the reset signal RST by delaying the clock signal CLK by up to the total delay amount of the delay elements "D" of the delay circuit 480.

[0127] From multi-level unit interval detector 300 (reference) Figure 2 The length of the unit interval UI can be three times the total delay of the delay elements "D" of the delay circuit 480. Therefore, the total delay of the delay circuit 480 can be 1 / 3 of the length of the unit interval UI. In other words, a masking interval of 0.33 UI can be ensured by the delay circuit 480.

[0128] Taking into account the delay of the circuitry used to generate the clock signal CLK, the clock recovery circuit 400 can ensure a masking interval of 0.35 UI. For example, the masking interval can be ensured without any individual component or circuitry by setting the ratio of the delay of the delay unit in the multi-level unit interval detector 300 to the delay of the delay circuit 480 in the clock recovery circuit 400 to 3:1.

[0129] In the embodiments, based on Figure 11 In the case of detecting the unit interval UI using the illustrated method, the number of delay elements in the delay circuit 480 can be one-third of the number of delay elements in the multi-level unit interval detector 300. However, in the case of detecting the unit interval UI using the method based on an embodiment of the present invention, the number of delay elements in the delay circuit 480 can be greater than one-third of the number of delay elements in the multi-level unit interval detector 300. In some embodiments, the number of delay elements in the delay circuit 480 can be greater than the number of delay elements in the multi-level unit interval detector 300.

[0130] Figure 14 A data recovery circuit 500 according to an embodiment of the present invention is shown. Figure 14 The data buffer circuit 500 may be included in Figure 1 In the data recovery circuit 260. (Refer to...) Figure 1 and Figure 14 The data recovery circuit 500 may include a first delay circuit 510, a second delay circuit 520 and a third delay circuit 530, as well as a first flip-flop 540, a second flip-flop 550 and a third flip-flop 560.

[0131] The data recovery circuit 500 can delay the first signal S1, the second signal S2, and the third signal S3 respectively through the first delay circuit 510, the second delay circuit 520, and the third delay circuit 530. Each of the first delay circuit 510, the second delay circuit 520, and the third delay circuit 530 can include a delay element "D". The first delay circuit 510, the second delay circuit 520, and the third delay circuit 530 can delay the first signal S1, the second signal S2, and the third signal S3 respectively based on the code [n: 0]. The code [n: 0] can represent 1 / 3 of the length of the unit interval UI.

[0132] For example, each delay element "D" in delay circuits 510, 520, and 530 can have the same characteristics as... Figure 2The delay amount of the first delay element D' or the second delay element "D" is equal to the delay amount of the first delay element D' or the second delay element "D". The first delay circuit 510, the second delay circuit 520 and the third delay circuit 530 can delay the first signal S1, the second signal S2 and the third signal S3 by up to the total delay amount of the delay elements "D", the number of delay elements "D" is equal to the number of delay units indicated by the code [n:0]. Therefore, the delay amount of each of the first delay circuit 510, the second delay circuit 520 and the third delay circuit 530 can be 1 / 3 of the length of the unit interval UI.

[0133] The data recovery circuit 500 may include logic circuitry capable of generating received signals RS1, RS2, and RS3. For example, the logic circuitry may include a first flip-flop 540, a second flip-flop 550, and a third flip-flop 560. The first flip-flop 540, the second flip-flop 550, and the third flip-flop 560 may respectively receive delayed first signals S1, second signals S2, and third signals S3. Each of the first flip-flop 540, the second flip-flop 550, and the third flip-flop 560 may receive a clock signal CLK from the clock recovery circuit 400.

[0134] Each of the first flip-flop 540, the second flip-flop 550, and the third flip-flop 560 can operate in response to a clock signal CLK (e.g., in response to the first edge of the clock signal CLK). For example, the first flip-flop 540, the second flip-flop 550, and the third flip-flop 560 can latch delayed first signals S1, second signals S2, and third signals S3 respectively in response to the clock signal CLK. As a result of the latching operation, the first flip-flop 540, the second flip-flop 550, and the third flip-flop 560 can output a first received signal RS1, a second received signal RS2, and a third received signal RS3 respectively.

[0135] For reference Figure 13 The rising edge of the clock signal CLK is aligned with the start time of the unit interval UI. In the data recovery circuit 500, each of the first signal S1, the second signal S2, and the third signal S3 can be delayed by up to 0.35 UI or more. Therefore, the edge of the clock signal CLK can be aligned within a stable interval, rather than within varying intervals of the delayed first signal S1, the second signal S2, and the third signal S3, and the first received signal RS1, the second received signal RS2, and the third received signal RS3 can be successfully latched.

[0136] For reference Figure 13The number of delay elements in each of the first delay circuit 510, the second delay circuit 520, and the third delay circuit 530 may be greater than one-third of the number of delay elements in the multi-level unit interval detector 300. In some embodiments, the number of delay elements in each of the first delay circuit 510, the second delay circuit 520, and the third delay circuit 530 may be greater than the number of delay elements in the multi-level interval detector 300.

[0137] Figure 15 An electronic system 1000 according to another embodiment of the concept of the present invention is shown. The electronic device 1000 can be implemented using a data processing device capable of using or supporting the interface protocol proposed by the MIPI Alliance. For example, the electronic device 1000 can be one of electronic devices such as a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a smartphone, a tablet computer, and a wearable device.

[0138] Electronic device 1000 may include application processor 1100, display 1220, and image sensor 1230. Application processor 1100 may include DigRF master device 1110, Display Serial Interface (DSI) master 1120, Camera Serial Interface (CSI) master 1130, physical layer 1140, and Universal Flash Host-Controller Interface (UFS HCI) 1150.

[0139] DSI host 1120 can communicate with DSI device 1225 of display 1220 in accordance with DSI specifications. For example, a serializer SER can be implemented in DSI host 1120, and a deserializer DES can be implemented in DSI device 1225. For example, DSI can use the physical layer defined in the C-PHY specification, and DSI host 1120 can communicate with DSI device 1225 through three or more communication lines. See reference... Figures 1 to 14 As described, the DSI host 1120 and / or DSI device 1225 may include a delay unit including a feedback loop and may be configured to determine the unit interval UI through coarse and fine detection.

[0140] CSI host 1130 can communicate with CSI device 1235 of image sensor 1230 in accordance with CSI. For example, deserializer DES can be implemented in CSI host 1130, and serializer SER can be implemented in CSI device 1235. For example, CSI can use the physical layer defined in the C-PHY specification, and CSI host 1130 can communicate with CSI device 1235 through three or more communication lines. See reference... Figures 1 to 14As described, the CSI host 1130 and / or CSI device 1235 may include a delay unit containing a feedback loop and may be configured to determine the unit interval UI through coarse and fine detection.

[0141] Electronic device 1000 may also include a radio frequency (RF) chip 1240 that communicates with application processor 1100. RF chip 1240 may include a physical layer 1242, a DigRF slave device 1244, and an antenna 1246. For example, the physical layer 1242 of RF chip 1240 and the physical layer 1140 of application processor 1100 may exchange data with each other in accordance with the DigRF interface proposed by the MIPI Consortium. In some embodiments, where physical layers 1242 and 1140 communicate with each other through three or more communication lines, physical layer 1242 and / or physical layer 1140 may include delay units including feedback loops and may be configured to determine the unit interval UI through coarse and fine detection.

[0142] Electronic device 1000 may also include working memory 1250 and embedded / card-type storage device 1255. Working memory 1250 may temporarily store data that has been or will be processed by application processor 1100. Working memory 1250 may include volatile memory (e.g., static random access memory (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM)) and / or non-volatile memory (e.g., flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM)).

[0143] Embedded / card-based storage device 1255 can store data provided from application processor 1100, or can provide stored data to application processor 1100. Embedded / card-based storage device 1255 may include non-volatile memory that can store data regardless of whether it is powered on.

[0144] For example, the embedded / card storage device 1255 can communicate with the application processor 1100 in accordance with the UFS communication protocol. In this example, the application processor 1100 can handle communication with the embedded / card storage device 1255 via UFS HCI 1150. In some embodiments, where the embedded / card storage device 1255 communicates with the application processor 1100 via three or more communication lines, the embedded / card storage device 1255 and / or the application processor 1100 may include a delay unit including a feedback loop and may be configured to determine the unit interval UI through coarse and fine detection.

[0145] Electronic device 1000 can communicate with external devices / systems via communication modules such as WiMAX 1260, WLAN 1262, and UWB 1264. Electronic device 1000 may also include a speaker 1270 and a microphone 1275 for processing voice information. Electronic device 1000 may also include a Global Positioning System (GPS) device 1280 for processing location information. Electronic device 1000 may also include a bridging chip 1290 for managing connections with peripheral devices.

[0146] In the above embodiments, components according to the inventive concept are described using the terms "first," "second," "third," etc. However, the terms "first," "second," "third," etc., can be used to distinguish components from each other and do not limit the inventive concept. For example, the terms "first," "second," "third," etc., do not imply any form of order or numerical meaning.

[0147] In the above embodiments, the term "block" is used to describe components of embodiments based on the present invention. These blocks can be implemented using various hardware devices, such as integrated circuits, application-specific integrated circuits (ASCIs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs), firmware driven in the hardware device, software such as applications, or a combination of hardware devices and software. Furthermore, these blocks may include circuits implemented using semiconductor elements in integrated circuits or circuits registered as intellectual property (IP).

[0148] According to the present invention, coarse and fine detection are performed by using a reduced number of delay elements, and the unit interval of the received signal is determined by combining the results of the coarse and fine detection. Therefore, an electronic device for recovering a clock signal by using a reduced number of delay elements and a method for operating the electronic device are provided.

[0149] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. An electronic device, comprising: A unit interval detector includes multiple delay units and is configured to receive a first signal, a second signal, and a third signal, and detect a code indicating a unit interval from the first signal, the second signal, and the third signal; A clock recovery circuit is configured to generate a clock signal from the first signal, the second signal, and the third signal in response to the code. as well as The data recovery circuit is configured to generate a first receive signal, a second receive signal, and a third receive signal from the first signal, the second signal, and the third signal in response to the code and the clock signal. Wherein, the total delay of the plurality of delay units is less than the length of the unit interval, and The unit interval detector is configured to perform multi-level detection operations, including coarse detection and fine detection, by using the plurality of delay units.

2. The electronic device according to claim 1, wherein, The unit interval detector is also configured to: A fourth signal is generated from the first signal, the second signal, and the third signal, wherein half the period of the fourth signal is equal to the length of the unit interval. In response to the fourth signal, an internal clock signal is generated from the plurality of delay units, the period of the internal clock signal being shorter than the period of the fourth signal, and When the fourth signal is high, the coarse detection is performed by counting the number of times the internal clock signal is switched.

3. The electronic device according to claim 2, wherein, The unit interval detector is also configured to: The fine detection is performed by detecting the position of the rising edge of the internal clock signal at the falling edge of the fourth signal, or The fine detection is performed by detecting the position of the falling edge of the internal clock signal at the falling edge of the fourth signal.

4. The electronic device according to claim 2, wherein, The plurality of delay units include: a first delay unit that receives the fourth signal; and a second delay unit that follows the first delay unit. The output of the first delay unit is fed back to the first delay element placed in the first delay unit via an inverter.

5. The electronic device according to claim 4, wherein, The first placed first delay element is configured to output a low level when the fourth signal is high and the output of the inverter is low.

6. The electronic device according to claim 1, wherein, Each of the plurality of delay units includes three delay elements. The unit interval detector detects the first code through the coarse detection, and The unit interval detector detects the second code through the fine detection.

7. The electronic device according to claim 6, wherein, The clock recovery circuit includes a second delay element. The clock recovery circuit is configured as follows: The clock signal is allowed to transition at a first time point when one of the first signal, the second signal, and the third signal transitions; and The clock signal level is maintained for a period of time corresponding to the total delay of the delay elements in the second delay element, the total delay of the delay elements in the second delay element being adjusted by a code composed of the first code and the second code.

8. The electronic device according to claim 7, wherein, The number of the second delay element is greater than 1 / 3 of the total number of delay elements in the plurality of delay units.

9. The electronic device according to claim 6, wherein, The data recovery circuit includes a second delay element. The data recovery circuit is configured as follows: The first signal, the second signal, and the third signal are delayed by up to the total delay of the delay elements in the second delay element, the total delay of the delay elements in the second delay element being adjusted by a code composed of the first code and the second code; and The first signal, the second signal, and the third signal are latched synchronously with the clock signal.

10. The electronic device according to claim 9, wherein, The number of the second delay element is greater than 1 / 3 of the total number of delay elements in the plurality of delay units.

11. The electronic device according to claim 1, wherein, The first signal, the second signal, and the third signal are received in accordance with the C-PHY protocol.

12. The electronic device of claim 2, wherein the unit interval detector further comprises: A logic gate is configured to generate the fourth signal by performing an XOR operation on the first signal, the second signal, and the third signal; The feedback loop is configured to input the output of the first delay unit in the delay unit to a first delay element in the first delay unit and generate an internal clock signal; A counter is configured to output the result of the coarse detection by performing a counting operation in sync with the output of a second delay unit following the first delay unit among the plurality of delay units; The first determination block is configured to detect the rising edge or falling edge of the internal clock signal from the first delay unit; The second determination block is configured to detect the rising edge or falling edge of the internal clock signal from the second delay unit; as well as The encoder is configured to encode the decision results of the first decision block and the second decision block, and output the result of the fine detection.

13. An electronic device, comprising: The first delay unit includes a first delay element and at least one second delay element connected in sequence, and is configured to receive a first signal switching between a high level and a low level and delay the first signal to output it as a second signal; The second delay unit includes at least two third delay elements connected in sequence and is configured to receive the second signal from the first delay unit and delay the second signal to output it as a third signal. The counter is configured to perform a counting operation synchronously with the third signal and output a first code as the result of the counting operation; A first determination block is connected to the first delay unit and is configured to detect the rising or falling edge of a first internal signal from the first delay unit in sync with the falling edge of the first signal, and output a first bit as the detection result of the rising or falling edge of the first internal signal. The second determination block is connected to the second delay unit and is configured to detect the rising or falling edge of the second internal signal from the second delay unit in sync with the falling edge of the first signal, and output a second bit as the detection result of the rising or falling edge of the second internal signal. as well as The encoder is configured to generate a second code from the first bit and the second bit. The second signal is fed back to the first delay element via an inverter.

14. The electronic device according to claim 13, wherein, The first code and the second code form a third code, which indicates the length of the interval during which the first signal is at a high level. Wherein, the first code includes the most significant bit of the bits in the third code, and The second code includes the least significant bit of the bits in the third code.

15. The electronic device according to claim 13, wherein, The counter is configured to perform a counting operation when the first signal is high.

16. The electronic device according to claim 13, wherein, When the first signal is at a high level and the second signal is at a high level, the first delay element outputs a low level.

17. The electronic device according to claim 13, further comprising: The logic gate is configured to receive a fourth signal, a fifth signal, and a sixth signal, and to generate the first signal by performing an XOR operation on the fourth signal, the fifth signal, and the sixth signal.

18. A method of operating an electronic device, comprising: Receive the first signal that switches between high and low levels; In response to the first signal, a second signal is generated that switches between the high level and the low level, the period of the second signal being shorter than the period of the first signal; The number of times the second signal passes through the delay loop, including the first delay unit and the second delay unit, when the first signal is at a high level is counted, and a first code is generated as the result of the count; The position of the rising or falling edge of the second signal on the delay loop is detected synchronously with the falling edge of the first signal, and a second code is generated as the result of the detection. as well as The first code and the second code are combined to produce a third code as the result of the combination.

19. The operating method according to claim 18, wherein, Generating the second signal includes: When the first signal is at a high level and the output signal of the first delay unit is at a low level, the second signal is adjusted to a low level.

20. The operating method according to claim 18, further comprising: The system receives a third signal, a fourth signal, and a fifth signal, and generates the first signal by performing an XOR operation on the third signal, the fourth signal, and the fifth signal. as well as The clock signal is allowed to change when one of the third, fourth, and fifth signals changes, and the level of the clock signal is maintained in response to the third code.

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