System and method for improving matching in a signal converter

Abstract

A signal converter includes a first converter, a second converter, a signal generator, and a controller. The first converter generates a first analog signal from a digital signal, and the second converter generates a second analog signal from the digital signal. The signal generator outputs a converted analog signal based on the first analog signal and the second analog signal. The controller generates one or more control signals to change a power state of at least one of the first converter and the second converter. The change in power state suppresses even harmonics.

Description

Technical Field

[0001] The example embodiments disclosed herein generally involve controlling signal conversion between different domains. Background Technology

[0002] Many circuit applications require signal conversion between the digital and analog domains. These conversions are typically performed using sigma-delta modulators. For example, sigma-delta modulators can be used to convert analog input signals into high-resolution digital signals. These operations are useful for clock generation and filtering in communication systems.

[0003] However, the analog-to-digital conversion performed in existing trigonometric modulators introduces significant distortion that adversely affects the operation of the host circuitry. The noise is primarily attributable to mismatch occurring at the output of the digital-to-analog converter located in the modulator feedback loop. This mismatch introduces nth-order harmonics, transients, or other forms of spurious signals into the converter output, degrading its performance.

[0004] Various attempts have been made to control distortion in trigonometric integrator converters. One attempt involves using a data-weighted averaging (DWA) algorithm to perform noise shaping. However, the DWA algorithm has been shown to introduce noise. Other attempts involve using excessive amounts of additional switches, amplifiers, and / or other circuit components, which also introduce noise, increase power consumption, and in some cases require matching. Although these effects occur in trigonometric integrator converters, they can also occur in other types of converters and circuits that perform signal conversion, which can become distorted due to mismatch and other reasons. Summary of the Invention

[0005] According to one or more embodiments, a signal converter includes: a first converter configured to generate a first analog signal based on a digital signal; a second converter configured to generate a second analog signal based on the digital signal; a signal generator configured to output a converted analog signal based on the first analog signal and the second analog signal; and a controller configured to generate one or more control signals to change the power state of at least one of the first and second converters, the change in power state being used to suppress harmonics in the converted analog signal. The one or more control signals can toggle the power state of at least one of the first and second converters to suppress the generation of harmonics. The one or more control signals can change the power state of the first and second converters at different periods.

[0006] The signal generator may include a selector coupled between the output node and the first and second converters, wherein the controller generates one or more third control signals to control the selection state of the selector in synchronization with the changing power states of the first and second converters in the different cycles. In a first selection state, the first converter can be selected and the second converter cannot be selected, and in a second selection state, the first converter cannot be selected and the second converter can be selected. The one or more control signals may toggle the power state of the second converter in the first selection state and toggle the power state of the first converter in the second selection state.

[0007] The first signal converter may include a first resistor ladder, and the second signal converter may include a second resistor ladder. The controller may be configured to compare the amplitude of the digital signal with a predetermined value and generate one or more control signals based on the comparison result to change the power supply state of at least one of the first and second converters. When the amplitude of the digital signal is greater than the predetermined value, the signal generator may output the converted analog signal. The predetermined value may be based on a predetermined ratio between distortion and harmonic suppression in the converted analog signal.

[0008] According to one or more embodiments, a signal conversion method includes: generating a first analog signal based on a digital signal; generating a second analog signal based on the digital signal; outputting a converted analog signal based on the first analog signal and the second analog signal; and controlling the generation of one or more control signals to change the power supply state of at least one of the first and second converters, thereby suppressing harmonics in the converted analog signal. The one or more control signals may toggle the power supply state of at least one of the first and second converters to suppress the generation of harmonics. The one or more control signals may change the power supply state of the first and second converters at different periods.

[0009] Outputting the converted analog signal may include generating one or more third control signals to control the selection state of a selector coupled between the output node and the first and second converters. The selection state is controlled synchronously with the power states of the first and second converters changing in the different cycles. The first analog signal may be generated by the first converter, and the second analog signal may be generated by the second converter. In a first selection state, the first converter may be selected and the second converter may not be selected; in a second selection state, the first converter may not be selected and the second converter may be selected.

[0010] The one or more control signals can toggle the power state of the second converter in the first selection state and toggle the power state of the first converter in the second selection state. The method may include comparing the amplitude of the digital signal with a predetermined value and generating the one or more control signals based on the comparison result to change the power state of at least one of the first and second converters. When the amplitude of the digital signal is greater than the predetermined value, the converted analog signal may be output. The predetermined value may be based on a predetermined ratio between distortion and harmonic suppression in the converted analog signal. Attached Figure Description

[0011] Additional objects and features of the invention will become more apparent from the following detailed description taken in conjunction with the drawings and the appended claims. Although several exemplary embodiments are shown and described, in each figure, the same reference numerals identify the same parts, in the figures:

[0012] Figure 1 An embodiment of a signal converter is shown;

[0013] Figure 2 An embodiment of a signal converter is shown;

[0014] Figure 3 An embodiment of a method for performing signal conversion is shown;

[0015] Figure 4 An embodiment of a method for performing signal conversion is shown;

[0016] Figure 5 An example of a timing diagram for performing signal conversion is shown;

[0017] Figures 6A to 6D Examples of different states of a signal converter are shown; and

[0018] Figure 7 An embodiment of a trigonometric integral modulator is shown. Detailed Implementation

[0019] It should be understood that the figures are schematic only and not drawn to scale. It should also be understood that the same reference numerals are used throughout the figures to indicate the same or similar parts.

[0020] The descriptions and figures illustrate the principles of various exemplary embodiments. It will thus be understood that those skilled in the art will be able to design various arrangements that, while not explicitly described or illustrated herein, embody the principles of the invention and are included within its scope. Furthermore, all examples cited herein are primarily intended for explicit educational purposes to aid the reader in understanding the principles of the invention and the concepts provided by the inventors to deepen the understanding of the art, and all examples should be considered as not being limited to such specific cited examples and conditions. Additionally, unless otherwise specified (e.g., “or additionally” or “or in alternatives”), the term “or” as used herein refers to a non-exclusive or (i.e., and / or). Furthermore, the various exemplary embodiments described herein are not necessarily mutually exclusive, as some exemplary embodiments can be combined with one or more other exemplary embodiments to form new exemplary embodiments. For example, descriptive terms such as “first,” “second,” and “third” are not intended to limit the order of the elements discussed, but are used to distinguish one element from the next and are generally interchangeable. Values ​​such as maximum or minimum values ​​may be predetermined and can be set to different values ​​depending on the application.

[0021] Figure 1 An embodiment of a signal converter 100 is shown, which generates a converted signal that conforms to DAC and impedance matching when fed back or otherwise input to host circuitry. In one example application, the signal converter may be included in the feedback path of a trigonometric modulator acting as the host circuitry. Embodiments relating to such applications are discussed below. However, the signal converter can be applied to other types of host circuitry, including flash analog-to-digital converters or other types of host circuitry that require signal conversion operations.

[0022] refer to Figure 1 The signal converter includes a first resistor ladder 10, a second resistor ladder 20, and a signal generator 30. The first resistor ladder 10 includes one or more resistors with predetermined resistance values, which are coupled in series with each other and in parallel to the same output node N1. Depending on, for example, the intended application and / or the amplitude range of the analog signal to be generated, the resistance values ​​may be the same or different from each other. The resistors in the first resistor ladder may correspond to each value of an M-bit input signal 5 (not mentioned in the diagram), schematically shown as DAC_In. For example, for an M-bit input signal 5, the first resistor ladder may include N=2 series-coupled resistors. M One resistor.

[0023] The first resistor ladder 10 generates an analog signal from a digital input by coupling the ends of the ladder to at least one of a first set of power supply voltages 40 and at least one of a second set of power supply voltages 50, and then selectively connecting resistors in the ladder based on individual bit values ​​of the M-bit input signal. In one embodiment, the first set of power supply voltages 40 may include a first power supply voltage and a second power supply voltage. The first power supply voltage may have a relatively high predetermined value, and the second power supply voltage may have a relatively low predetermined value. For example, the first power supply voltage may represent the upper limit of the amplitude range of the analog signal to be generated, and the second power supply voltage may represent the lower limit of the amplitude range of the analog signal (e.g., ground or some other reference value). The second set of power supply voltages 50 may include a third power supply voltage and a fourth power supply voltage. In one embodiment, the third power supply voltage and the fourth power supply voltage may correspond to the first power supply voltage and the second power supply voltage in the first set of power supply voltages 40, respectively.

[0024] Selective connection of the resistors can be achieved, for example, by coupling a corresponding switch between each resistor and the output of the ladder. For instance, a bit with a logic one value can close the switch, and a bit with a logic zero value can open the switch. In another embodiment, the opposite may be true—a logic zero can close the switch and a logic one can open the switch. Therefore, input signals with different bit values ​​will selectively connect different combinations of resistors in the first resistor ladder, thereby generating a first analog signal 11 with an amplitude based on the digital input signal.

[0025] To generate an analog signal at output node N1, a first different combination of power supply voltages from the first group of power supply voltages 40 and the second group of power supply voltages 50 is connected to a resistor ladder. For example, when a first power supply voltage with a relatively high value from the first group of 40 is connected to a first end of the resistor ladder, a fourth power supply voltage with a relatively low value from the second group of 50 is connected to a second end of the resistor ladder. Conversely, when a second power supply voltage with a relatively low value from the first group of 40 is connected to a first end of the resistor ladder, a third power supply voltage with a relatively high value from the second group of 50 is connected to a second end of the resistor ladder. Thus, the opposite ends of the ladder are connected to different power supply values, but the connection arrangement of the power supply voltages can be reversed according to one or more embodiments to achieve DAC and resistor matching.

[0026] The second resistor ladder 20 can be constructed in a manner similar to the first resistor ladder. For example, in one embodiment, the number of resistors in the second resistor ladder can be the same as the number of resistors in the first resistor ladder, and they can be connected to its output node N2 via a corresponding number of switches. Because the second resistor ladder also receives a digital input signal 5 (not shown in the diagram), the resistors in the second resistor ladder can be selectively connected to the output node N2 via switches based on the same bit value.

[0027] In addition to these features, the second ladder also includes (or is coupled to) a third group of power supply voltages 60 and a fourth group of power supply voltages 70. In one embodiment, the third group of power supply voltages may include the same power supply voltages as those in the first group of power supply voltages 40 (e.g., the first and second power supply voltages), and the fourth group of power supply voltages may include the same power supply voltages as those in the second group of power supply voltages (e.g., the third and fourth power supply voltages). Similarly, in one embodiment, the resistance values ​​of the resistors in the second resistor ladder 20 may be the same as the resistance values ​​of the corresponding resistors in the first resistor ladder 10. Likewise, the first and second voltage values ​​connected to the first resistor ladder may also be connected to the second resistor ladder. Through the connection of the power supply voltages in the third and fourth groups and the selective connection of the resistor switches, the second resistor ladder generates a second analog signal 21 at node N2.

[0028] Therefore, in one embodiment, the second resistor ladder can generate an analog signal with the same amplitude as the analog signal generated by the first resistor ladder. Furthermore, the waveform of the analog signal generated by the second resistor ladder can be the same as or different from the waveform of the analog signal generated by the first resistor ladder. (The waveforms are the same, not reversed.)

[0029] Controller 90 generates three control signals to control the operation of the signal converter. The first set of control signals, FCS1, controls the connection arrangement of the power supply voltages in the first set of power supply voltages 40 and the second set of power supply voltages 50 to the corresponding ends of the first resistor ladder. The first set of control signals, FCS1, may include a single signal for controlling the connection of the different power supply voltages in the first set 40 and the second set 50 (e.g., by using appropriate intervention logic), or may include multiple switching signals for controlling the connection status of the corresponding power supply voltages in these sets.

[0030] The second set of control signals FCS2 controls the connection arrangement of the power supply voltages in the third set of power supply voltages 60 and the fourth set of power supply voltages 70 to the corresponding ends of the second resistor ladder. The second set of control signals FCS2 may include a single signal for controlling the connection of the different power supply voltages in the third set 60 and the fourth set 70 (e.g., by using appropriate intervention logic), or may include multiple switching signals for controlling the connection state of the corresponding power supply voltages in these sets.

[0031] The third set of control signals, FCS3, controls the operation of selector 30. In one embodiment, selector 30 can selectively connect one or both of the first analog signal 11 and the second analog signal 21 output from the resistor array to generate the converted digital output signal 80 DAC_Out of the signal converter. The third set of control signals, FCS3, can be a single control signal for controlling the selection of one or both of the first analog signal 11 and the second analog signal 21 (with or without intervention logic), or it can include multiple signals for controlling the connection state of each of the first and second analog signals to generate the digital output signal 80. In one embodiment, for the purpose of DAC and resistor matching (or otherwise reducing distortion) in the host circuitry, the third set of control signals, FCS3, is synchronized or otherwise coordinated with the first set of control signals, FCS1, and the second set of control signals, FCS2, based on a flip-flop method.

[0032] In one embodiment, controller 90 executes instructions stored in memory 95 to generate toggle control signals and / or perform other operations of a signal converter. The memory can be any type of non-transitory computer-readable medium, and the instructions stored in said medium can cause the controller to perform the operations of the embodiments described herein. The controller can be a processor or other type of computing device, examples of which are described in more detail below.

[0033] Figure 2 It can be shown that can be considered Figure 1 More specific examples (but not the only) of embodiments of the signal converter are shown. In other embodiments, Figure 1 Signal converters can be different Figure 2 Implemented as shown.

[0034] refer to Figure 2 The signal converter 200 includes a first resistor ladder 110, a second resistor ladder 120, and a signal generator 130. The first resistor ladder 110 can also be referred to as a first digital-to-analog converter (DAC1), and the second resistor ladder 120 can also be referred to as a second digital-to-analog converter (DAC2). The first and second DACs can be considered together to form a signal converter that improves the signal-to-noise ratio and distortion rate of the host circuit receiving the converted analog signal output.

[0035] The first resistor ladder 110 includes a plurality of first resistors 1111 to 111 connected in series between the first switching circuit 140 and the second switching circuit 150. N Each resistor in the first step is connected to a corresponding number of switches 1151 to 115. NCoupled to output node N1. In this embodiment, the resistors in the first resistor ladder have resistance values ​​2R1 to 2R that can be the same or different. 2N This depends on, for example, the quantization performed to generate the digital input signal.

[0036] In operation, the first resistor ladder 110 is based on switches 1151 to 1152. N The state of the digital input signal, along with the states of the first switching circuit 140 and the second switching circuit 150, generates a first analog signal 181 at node N1. Switches 1151 to 115 are controlled based on the logic bit values ​​of the digital input signal. N The state of the input digital signal. For example, as previously described, the logic value of each bit of the input digital signal controls the state of the corresponding switch in the switch, such as a logic 1 value closing the switch and a logic 0 value opening the switch. Therefore, the M-bit input digital signal is decoded and connected to bits B1, B2, B3, ..., BN-2, BN-1, BN. The first bit B1 controls the state of switch 1151, the second bit B2 controls the state of switch 1152, ..., the last bit BN controls the state of switch 1151. N The state.

[0037] The first switching circuit 140 includes a first switch 141 and a second switch 142, respectively coupled to a first power supply voltage and a second power supply voltage. In this embodiment, the first power supply voltage is a high voltage (Vdd), and the second power supply voltage is a low voltage (Gnd). The state of the first switch 141 can be controlled based on the first control signal FCS1(1) in a first set of toggle control signals FCS1 output from a controller, such as a controller that can be connected to... Figure 1 The controller 90 corresponds to this. The state of the second switch 142 can be controlled based on the second control signal FCS1(2) from the first set of toggle control signals from the controller. The control signals FCS1(1) and FCS1(2) can control the first switch and the second switch to be in an alternating state.

[0038] The second switching circuit 150 includes a third switch 151 and a fourth switch 152, respectively coupled to a third power supply voltage and a fourth power supply voltage. In this embodiment, the third power supply voltage is a low voltage (gnd), and the fourth power supply voltage is a high voltage (vdd). The state of the third switch 151 can be controlled based on the third control signal FCS1(3) in the first set of toggle control signals FCS1 output from the controller, and the state of the fourth switch 152 can be controlled based on the fourth control signal FCS1(4) in the first set of toggle control signals. The control signals FCS1(3) and FCS1(4) can control the third and fourth switches to be in an alternating state.

[0039] Furthermore, in one embodiment, a first set of switching control signals is generated by a controller, causing the first switching circuit 140 and the second switching circuit 150 to connect the respective ends of the first resistor ladder to different power supply voltages during a predetermined operating cycle, as will be discussed in more detail below. For example, when the first switching circuit 140 connects a high power supply voltage (Vdd) to a first end of the first resistor ladder, the second switching circuit 150 connects a low power supply voltage (GND) to a second end of the first resistor ladder, and vice versa.

[0040] The second resistor ladder 120 includes a plurality of second resistors 1211 to 121 connected in series between the third switching circuit 160 and the fourth switching circuit 170. N Each resistor in the second step is connected to a corresponding number of switches 1251 to 125. N Coupled to output node N2. In this embodiment, the resistors in the second ladder 120 have the same resistance values ​​2R1 to 2R as the resistors in the first ladder 110. 2N However, the resistors in the second ladder are arranged in a different order, for example, resistors 1211 to 121. N The resistors in the second ladder are arranged in reverse order relative to those in the first ladder. In another embodiment, due to mismatch between the ladders, the resistance value of one or more of the second resistors in the second ladder may differ from the resistance value of one or more of the first resistors in the first ladder.

[0041] In operation, the second resistor ladder 120 is based on switch 1251 to 125. N The states of the digital input signals, along with the states of the third and fourth switching circuits 160 and 170, generate a second analog signal 182 at node N2. This signal controls switches 1251 to 125 based on the logic bit values ​​of the digital input signals. N The state of the switch 1251 is controlled by applying the bit value of the input signal in reverse order, corresponding to the reverse order arrangement of the second resistor. Thus, for example, bit value B1 is applied to control the state of switch 1251 to selectively connect the second resistor 2R1 arranged at the second end of the second ladder.

[0042] The third switching circuit 160 includes a first switch 161 and a second switch 162, respectively coupled to a first power supply voltage (Vdd) and a second power supply voltage (Gnd). The state of the first switch 161 can be controlled based on the first control signal FCS2(1) in the second set of toggle control signals FCS2 output from the controller. The state of the second switch 162 can be controlled based on the second control signal FCS2(2) in the second set of toggle control signals from the controller. Control signals FCS2(1) and FCS2(2) can control the first switch 161 and the second switch 162 to be in an alternating state.

[0043] The fourth switching circuit 170 includes a third switch 171 and a fourth switch 172, respectively coupled to a third power supply voltage (gnd) and a fourth power supply voltage (vdd). The state of the third switch 171 can be controlled based on the third control signal FCS2(3) in the second set of toggle control signals FCS2 output from the controller, and the state of the fourth switch 172 can be controlled based on the fourth control signal FCS2(4) in the second set of toggle control signals. The control signals FCS2(3) and FCS2(4) can control the third and fourth switches to be in an alternating state. Although the power supply voltages are described in this embodiment as corresponding to gnd and vdd, in another embodiment the power supply voltages can be positive and negative voltages.

[0044] Furthermore, in one embodiment, a second set of switching control signals is generated by the controller, causing the third switching circuit 160 and the fourth switching circuit 170 to connect the respective ends of the second resistor ladder to different power supply voltages during a predetermined operating cycle, as will be discussed in more detail below. For example, when the third switching circuit 160 connects a high power supply voltage (Vdd) to the first end of the second resistor ladder, the fourth switching circuit 170 connects a low power supply voltage (GND) to the second end of the second resistor ladder, and vice versa.

[0045] In some applications, the number of resistors in each resistor ladder may differ from the number of decoded bits in the input digital signal. For example, the number of bits in the input digital signal may be less than the number of resistors in each of the first and second ladders. To allow this, switches 115 and 125 can be in the off state by default. Because only bits with a logic value of one close the corresponding resistor switch, the signal converter can convert any digital signal to a maximum of N bits corresponding to the number of resistors in each of the first and second ladders. Thus, for example, if N = 5, the signal converter can convert a 3-bit input digital signal exactly as easily as converting a 5-bit input digital signal, and without any modification to the ladder resistors due to the one-to-one correspondence of the resistor switches and the default off state of these switches.

[0046] Signal generator 130 may be an output node, a signal selector, or another type of circuitry or logic that generates a converted analog signal based on one or more analog signals output from a first resistor ladder and a second resistor ladder. In one embodiment, signal generator 130 includes a first switch 131 and a second switch 132 connected in parallel. The first switch 131 is coupled to the output node N1 of the first resistor ladder 110 to receive a first analog signal 181. The second switch 132 is coupled to the output node N2 of the second resistor ladder 120 to receive a second analog signal 182. Switches 131 and 132 are controlled by a third set of toggle control signals FCS3(2) and FCS3(1) generated by a controller and synchronized with the first and second set of toggle control signals.

[0047] Figure 3 Showing the control for example Figure 1 or Figure 2 An embodiment of the signal converter method is shown. For illustrative purposes, it will be used in contrast to... Figure 2 The method is described in the context of a signal converter.

[0048] In this embodiment, the DAC matching algorithm is initiated and controlled based on one or more operating conditions, at least some of which are based on the magnitude of the input digital signal received from the host circuitry. The magnitude of the input digital signal can allow the method to address different cancellation problems. For example, noise can be a major problem for relatively small input digital signals. Conversely, distortion can be a major problem for relatively large input digital signals. The method can be implemented by compromising (or balancing) noise and distortion for different magnitudes (e.g., amplitude) of the input digital signal.

[0049] For example, for relatively small input digital signals, the method can generate a toggle control signal to connect two resistor ladders, thereby generating an output analog signal DAC_out. Connecting the two ladders reduces the resistance and, consequently, reduces noise that would otherwise be generated if the method were not performed. For relatively large input digital signals, the method can generate the toggle control signal according to a toggle DAC matching algorithm, thereby reducing distortion by avoiding any transient effects in the output analog signal DAC_Out.

[0050] refer to Figure 3The method includes, at 310, comparing the magnitude (e.g., value or amplitude) of the input digital signal with a predetermined value. The predetermined value may indicate, for example, a certain amplitude of the analog signal corresponding to the input digital signal. As indicated above, for some applications, when the input digital signal has a correspondingly large amplitude (e.g., greater than the predetermined value X), considering distortion may be more important than considering impedance. Conversely, for input digital signals with correspondingly small amplitudes (e.g., less than or equal to the predetermined value X), reducing impedance may be more important than reducing distortion.

[0051] At 320, when the magnitude of the input digital signal is less than a predetermined value X, the matching algorithm is not initiated. Accordingly, the controller generates a third set of toggle control signals to cause selector 130 to connect the first analog signal 181 and the second analog signal 182 to the output node of the signal converter. This can be achieved, for example, by generating toggle control signals FSC3(1) and FCS3(2) whose values ​​are capable of closing both switches 131 and 132. In this case, the output analog signal DAC_Out is generated based on the analog signals output from both the first resistor ladder 110 and the second resistor ladder 120.

[0052] In one embodiment, the predetermined value X can be a value based on a proportional relationship between distortion and noise. For example, the value X could indicate a level where the effect caused by distortion is greater than the effect caused by noise in the host circuitry. In one embodiment, the value X can be determined to correspond to a level where distortion begins to control the noise generated in the host circuitry due to the conversion. In some cases, there may be some hysteresis in the value X. For example, this can be done to prevent the matching algorithm from turning on and off without stopping when the analog output equals the value X. Operation 310 can then be repeated for the next input digital signal. Because the ladders are connected in parallel, the amplitude generated at the output node corresponds to the amplitude of any one of the resistor ladder outputs; for example, the outputs of individual resistor ladders are not added together.

[0053] At 330, when the magnitude of the input digital signal is less than a predetermined value X, this may indicate that the effect of noise on the host circuitry is greater than that of distortion, or that there is some other level difference between the two effects. When this occurs, a matching algorithm is initiated to start DAC matching, which will reduce distortion, for example, by suppressing Nth-order even harmonics.

[0054] At 340, for example, a matching algorithm is run via controller 90 of the signal converter. The matching algorithm can be run based on a predetermined cycle of operating phases. These phases indicate different connection states of the power supply voltages of the first and second resistor ladders, synchronized with different switching states of the selector. These states are controlled to perform a toggling operation that suppresses additional distortion that may occur due to the conversion of the input digital signal to the output analog signal DAC_Out. According to one embodiment, the toggling operation involves changing or alternating the power supply voltages connected to corresponding ends of one or more of the first and second resistor ladders. Once the matching algorithm is executed, the resulting analog signal DAC_Out is output to the host circuitry. Examples of toggling operations performed by the matching algorithm are discussed below.

[0055] At 350, the amplitude of the converted digital signal compared in operation 310 is again compared with a predetermined value X. If this amplitude is still greater than the value X, the matching algorithm is run again for the input digital signal. If the amplitude of the converted digital signal is less than the predetermined value X, the method returns to perform operation 310 for the next input digital signal. In one embodiment, the controller 90 may include a comparator for comparing the amplitude of the converted digital signal with the predetermined value X.

[0056] Figure 4 An embodiment of a method for performing a matching algorithm is shown. See also... Figure 5 Describe this method, Figure 5 This illustrates operation based on the three sets of flip control signals previously described. Figure 2 An example of a timing diagram for a signal converter. The timing diagram is arranged according to multiple stages of a predetermined cycle, which is implemented to remove distortions (e.g., transients, Nth-order harmonics, and other spurious signals) that cause resistance mismatch in the host circuit.

[0057] refer to Figure 4 and 5 The initial operation 410 of the method includes: determining that the input digital signal is greater than a predetermined value X (operation 310), and then starting the matching algorithm (operation 320). Once the matching algorithm starts, it is run, for example, via the controller 90 of the signal converter.

[0058] A predetermined cycle is initiated to control the connection state of the power supply voltage and the switching state of the selector. These states are controlled relative to a digital clock signal 510 in the timing diagram. The start of the matching algorithm corresponds to a clock signal period (0) that occurs before the first stage of the cycle. The clock signal period (0) can also be... Figure 3This corresponds to operation 330 in the example. In this example, the predetermined cycle includes multiple stages for controlling the connection and switching states of the signal converter. In another embodiment, the cycle may have a different number of stages.

[0059] In 420, during clock signal cycle (0), the input digital signal is input to the first and second steps. A single logic bit closes the corresponding switch. For example, for a circuit with 2... 3 A three-bit input digital signal of the first resistor ladder, having a logic value of 1, closes the corresponding switches 1151 to 1158 in the first resistor ladder, while the remaining switches 115 remain in their default open state. Similarly, a logic value of one bit of the input digital signal closes the corresponding switches 1251 to 1258 in the second resistor ladder, while the remaining switches 125 remain in their default open state.

[0060] The first set of flip control signals, FSC1, controls the connection of the first power supply voltage (Vdd) to the top end of the first resistor ladder 110 via closed switch (sw1) 141, and controls the connection of the third power supply voltage (gnd) to the bottom end of the first resistor ladder via closed switch (sw3) 151. The second set of flip control signals, FCS2, controls the connection of the first power supply voltage (Vdd) to the top end of the second resistor ladder 120 via closed switch (sw6) 161, and controls the connection of the third power supply voltage (gnd) to the bottom end of the second resistor ladder via closed switch (sw8) 171. Therefore, at the start of the matching algorithm, the first and second flip control signals connect the same power supply voltage arrangement in both ladders in the unflipped state.

[0061] Figure 5 The switching state of selector 130 at the start of the matching algorithm is also shown. During clock signal cycle (0), the third set of toggle control signals FCS3 controls the selector to select the first analog signal output 181 and the second analog signal output 182 from the two ladders to generate the initial state of the output (converted) analog signal DAC_Out. This is achieved by closing the two switches 131 and 132 of the selector synchronously with the aforementioned connection state of the power supply voltages of the first and second ladders. Figure 5 The timing diagram shows the connection status of the power supply voltage and the switching status of the selector.

[0062] For example, in Figure 5 During clock signal period (0), the first resistor ladder is indicated as connected (DAC1 connected = 1) and in an unflipped state (DAC1 flipped = 0). Similarly, the second resistor ladder is indicated as connected (DAC2 connected = 1) and in an unflipped state (DAC2 flipped = 0). Figure 6AAn example circuit diagram is shown, which illustrates the connection and switching states of the signal converter during clock signal cycle (0).

[0063] At 430, during clock signal cycle (1), the first phase of the cycle begins with switches 115 and 125 still connected as previously described. (These switches can remain connected in the same configuration throughout the cycle.) However, the third toggle control signal FCS3 causes the selector to disconnect the second resistor ladder by opening switch 132 and to keep the first resistor ladder connected by keeping switch 131 closed. Additionally, the first resistor ladder is kept in an un-toggled state by maintaining the value of the toggle control signal FCS1. However, the value of the toggle control signal FCS2 changes to put the second resistor ladder in a toggle state relative to the power supply voltage of the second resistor ladder.

[0064] In the timing diagram, the states of the signal converters in the first stage are indicated by DAC1 connected = 1, DAC1 toggled = 0, DAC2 connected = 0, and DAC2 toggled = 1. During this clock cycle, the selector and power switch closed are indicated as dacl_out (indicating that only the first analog signal from the first resistor ladder is output through the selector), sw1, sw3, sw5, and sw7. Disconnecting and toggling the second resistor ladder while the first resistor ladder is still connected to the output prevents any spikes at the signal converter output, which in turn prevents a reduction in signal distortion in the host circuitry. Figure 6B An example circuit diagram is shown, which illustrates the connection and switching states of the signal converter during the clock signal cycle (1).

[0065] At 440, during clock signal cycle (2), the second phase of the cycle begins with switches 115 and 125 still connected as previously described. A third toggle control signal FCS3 causes the selector to reconnect the second resistor ladder by closing switch 132. Thus, in the second phase, the first and second resistor ladders are reconnected. However, the second toggle control signal FCS2 keeps the second resistor ladder in the toggle state, and the first toggle control signal FCS1 keeps the first resistor ladder in the untoggle state. In the timing diagram, this is indicated by DAC1 connected = 1, DAC1 toggle = 0, DAC2 connected = 1, and DAC2 toggle = 0, and the selector and power switch closed during this clock signal cycle are indicated as dac1_out, dac2_out, sw1, sw3, sw5, and sw7. (In interpreting the timing diagram, it should be understood that the connection signal has only a logic one value when asserted. The connection state will remain until the connection signal is asserted again, at which point the corresponding ladders are in complementary states.)

[0066] At 450, during clock signal cycle (3), the third phase of the cycle begins with switches 115 and 125 still connected as previously described. A third toggle control signal FCS3 causes the selector to disconnect the first resistor ladder by opening switch 131 and to maintain the connection of the second resistor ladder by keeping switch 132 closed. Additionally, the switching arrangement of the power supply voltage for the first resistor ladder changes to a toggle state. This is achieved by generating a first toggle control signal FCS1 to close switches 142 and 152 and open switches 141 and 151. The second toggle control signal FCS2 maintains the same value as in the second phase (clock signal cycle (2)).

[0067] In the timing diagram, the states of the signal converters in the third stage are indicated by DAC1 connected = 0, DAC1 toggled = 1, DAC2 connected = 1, and DAC2 toggled = 0. During this clock cycle, the selector and power switch closed are indicated as dac2_out (indicating that only the first analog signal from the first ladder is output through the selector), sw2, sw4, sw5, and sw7. Therefore, in the third stage, both resistor ladders are toggled, and only the second ladder is connected to the output node. Figure 6C An example circuit diagram is shown, which illustrates the connection and switching states of the signal converter during the clock signal cycle (3).

[0068] At 460, during clock signal cycle (4), the fourth phase of the cycle begins with switches 115 and 125 still connected as previously described. The third toggle control signal FCS3 causes the selector to reconnect the first resistor ladder by disconnecting switch 131 and to maintain the connection of the second resistor ladder by keeping switch 132 closed. Thus, in the fourth phase, both ladders are reconnected. However, the switching arrangement of the power supply voltages for both the first and second resistor ladders is in a toggle state. This is achieved by generating the first toggle control signal FCS1 and the second toggle control signal FCS2 with the same values ​​as in the third phase (clock signal cycle (3)).

[0069] In the timing diagram, the state of the signal converter in the fourth stage is indicated by DAC1 connected = 1, DAC1 flipped = 0, DAC2 connected = 1, and DAC2 flipped = 0, and the selector and power switch closed during this clock signal cycle are indicated as dac1_out, dac2_out, sw2, sw4, sw5, and sw7. Figure 6D An example circuit diagram is shown, which illustrates the connection and switching states of the signal converter during the clock signal cycle (3).

[0070] At 470, during clock signal cycle (5), toggle control signals FCS1, FCS2, and FCS3 are generated to disconnect the second resistor ladder, change the switching state of the second ladder to the un-toggled state, and maintain the connection of the first resistor ladder in the toggled state. In the timing diagram, the state of the signal converters during clock signal cycle (5) is indicated by DAC1 connected = 1, DAC1 toggle = 0, DAC2 connected = 0, and DAC2 toggle = 1, and the selector and power switch closed during this clock cycle are indicated as dac1_out, sw2, sw4, sw6, and sw8.

[0071] At 480, during clock signal cycle (6), toggle control signals FCS1, FCS2, and FCS3 are generated to connect the first resistor ladder and the second resistor ladder, and the switching states of the first and second ladders are maintained, such that the first resistor ladder is in the toggle state and the second resistor ladder is in the non-toggle state. In the timing diagram, the state of the signal converters during clock signal cycle (6) is indicated by DAC1 connected = 1, DAC1 toggle = 0, DAC2 connected = 1, and DAC2 toggle = 1, and the selector and power switch closed during this clock cycle are indicated as dac1_out, dac2_out, sw2, sw4, sw6, and sw8.

[0072] At 490, during clock signal cycle (7), toggle control signals FCS1, FCS2, and FCS3 are generated to disconnect the first resistor ladder and maintain the connection of the second resistor ladder, changing the switching state of the first resistor ladder to the un-toggle state and maintaining the switching state of the second ladder in the un-toggle state. In the timing diagram, the state of the signal converters during clock signal cycle (7) is indicated by DAC1 connected = 0, DAC1 toggle = 1, DAC2 connected = 1, and DAC2 toggle = 0, and the selector and power switch closed during this clock cycle are indicated as dac2_out, sw1, sw3, sw6, and sw8.

[0073] After the seventh clock signal cycle, Figure 3 In operation 350, the output analog signal DAC_Out is checked again against a predetermined value X. If the output analog signal is still greater than the value X, the matching algorithm is executed again in the same loop for the same input digital signal, starting from the clock signal period (0) as previously described. (The algorithm runs on a lower clock, followed by the input digital signal.)

[0074] According to the foregoing embodiments, the power supply voltages of the first and second resistor ladders are switched synchronously with the switching state of the selector, reducing or eliminating the transmission of distortion generated by the signal converter to the host circuit. This distortion can take the form of even harmonics, transients, and / or other stray signals. Furthermore, the foregoing embodiments control the trade-off between distortion and noise based on various circuit conditions (including but not limited to the magnitude of the digital input signal).

[0075] In some cases, different connection and switching states may result in slightly different output voltages. By cycling through different configurations, an average value can be generated for the cycle, which is more accurate than any single value for any individual state throughout the cycle.

[0076] Figure 7 An example of a trigonometric integrator modulator, including a signal converter, is shown as an implementation of the embodiments described herein. Such modulators can be used in wireless transceivers and other circuitry. In this example, a fourth-order trigonometric integrator modulator is implemented using a 5-bit feedback signal converter with a bandwidth of 225 kHz and a signal-to-noise ratio distortion of 88 dB. While this type of trigonometric integrator modulator is one possible application for signal converters, other embodiments may relate to other types of trigonometric integrator modulators or other applications where signal conversion will be performed.

[0077] refer to Figure 7 The signal converter includes a loop filter 710, an analog-to-quantizer 720, and a feedback loop 730. The loop filter 710 performs noise shaping on the input analog signal 701, and the resulting signal is input to the analog-to-quantizer. The quantizer 720 can be an N-stage multi-bit data converter that generates a digital signal that is fed back to the loop filter through the feedback loop 730.

[0078] The feedback loop may include digital logic 732 in the form of a digital one-hot encoder and a signal converter 735. The one-hot encoder converts an M-bit digital signal received by the feedback loop 730 into a digital value having only one high (logic 1) bit and the remaining bits being low (logic 0) bits. The digital signal generated by the one-hot encoder is input to the signal converter 735, which may be a digital-to-analog signal converter according to embodiments described herein. The analog signal DAC_Out generated by the signal converter 735 is input to a loop filter. In one embodiment, the amplitude of the digital signal output from the multi-bit quantizer 720 may be controllable, allowing it to be selected on silicon.

[0079] In one embodiment, a computer-readable medium stores instructions to generate switching, connecting, and other control signals as described herein. The computer-readable medium can be, for example, any type of read-only memory or random access memory, including, for example, on the same chip or circuit board that includes other portions of a signal converter and / or delta-integral modulator. Instructions stored in the medium (e.g., memory 95) can cause a processor corresponding to controller 90 to perform the operations of the method embodiments described herein.

[0080] According to one or more embodiments of the foregoing examples, a signal converter is provided to improve feedback matching in a host circuit. In one embodiment, a matching algorithm is implemented to reduce distortion in the form of Nth-order even harmonics, transients, and / or other spurious signals, or to reduce performance distortion. Alternatively, one or more embodiments can be implemented without using the DWA algorithm, excessive switching, amplifiers, and other features that have proven to act as additional noise sources. Therefore, the system and method embodiments described herein can, for example, improve the overall operation of their host circuitry by increasing signal distortion rate and reducing power consumption. In one embodiment, the signal converter can be used in a multi-bit trigonometric integrator modulator.

[0081] The controllers, modulators, filters, quantizers, integrators, encoders, selectors, and other signal generation and signal processing features disclosed herein may be implemented in logic, including, for example, hardware, software, or both. When implemented at least partially in hardware, the controllers, modulators, filters, quantizers, integrators, encoders, selectors, and other signal generation and signal processing features may be any of a variety of integrated circuits, including but not limited to application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations of logic gates, system-on-a-chip (SoCs), microprocessors, or other types of processing or control circuitry.

[0082] When implemented at least partially in software, controllers, modulators, filters, quantizers, integrators, encoders, selectors, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing, for example, codes or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or any other element besides those described herein. Because the algorithms underlying the formation of the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the method embodiments can transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0083] However, these benefits, advantages, solutions to problems, and any elements that may make any benefit, advantage, or solution occur or become more apparent should not be construed as essential, necessary, or fundamental features of any or all claims. The invention is defined solely by the appended claims, including any amendments made during the pending period of this application and all equivalents of those published claims.

[0084] While various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects of various exemplary embodiments, it should be understood that the invention is open to other exemplary embodiments, and the details of the invention allow for modifications in various obvious aspects. Variations and modifications can be made, as will be readily apparent to those skilled in the art, while remaining within the spirit and scope of the invention. Therefore, the foregoing disclosure, description, and drawings are for illustrative purposes only and are not intended to limit the invention in any way, which is defined solely by the claims.

Claims

1. A signal converter, characterized in that, include: A first converter, configured to generate a first analog signal based on a digital signal; A second converter, configured to generate a second analog signal based on the digital signal; A signal generator configured to output a converted analog signal based on the first analog signal and the second analog signal; as well as A controller configured to generate one or more control signals to change the power state of at least one of the first and second converters, the change in power state being used to suppress harmonics in the converted analog signal.

2. The signal converter according to claim 1, characterized in that, The one or more control signals will toggle the power state of at least one of the first and second converters to suppress the generation of harmonics.

3. The signal converter according to claim 1, characterized in that, The one or more control signals will change the power state of the first converter and the second converter in different cycles.

4. The signal converter according to claim 3, characterized in that, The signal generator includes: A selector, coupled between the output node and the first converter and the second converter. The controller generates one or more third control signals to control the selection state of the selector in sync with the power states that change during the different cycles of the first and second converters.

5. The signal converter according to claim 4, characterized in that: In the first selection state, the first converter is selected and the second converter is not selected, and In the second selection state, the first converter is not selected and the second converter is selected.

6. The signal converter according to claim 5, characterized in that, The one or more control signals toggle the power state of the second converter in the first selection state and toggle the power state of the first converter in the second selection state.

7. The signal converter according to claim 1, characterized in that: The first converter includes a first resistor ladder, and The second converter includes a second resistor ladder.

8. The signal converter according to claim 1, characterized in that, The controller is configured to: The amplitude of the digital signal is compared with a predetermined value, and Based on the comparison results, one or more control signals are generated to change the power state of at least one of the first converter and the second converter.

9. The signal converter according to claim 8, characterized in that, When the amplitude of the digital signal is greater than the predetermined value, the signal generator will output the converted analog signal.

10. A signal conversion method, characterized in that, include: A first analog signal is generated from the digital signal by a first converter; A second analog signal is generated from the digital signal by a second converter; The converted analog signal is output based on the first analog signal and the second analog signal; as well as The generation of one or more control signals is controlled to change the power supply state of at least one of the first converter and the second converter, thereby suppressing harmonics in the converted analog signal.

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