Integrated circuit with metal stop ring located outside scribe seal

Abstract

An integrated circuit having a metal stop ring located outside a scribe seal is disclosed. An integrated circuit (IC) die (300) includes a substrate (110) having circuitry (180) configured for at least one function, the substrate including metal interconnect layers thereon, the metal interconnect layers including a top metal interconnect layer (M5) and a bottom metal interconnect layer (M1), and having a passivation layer (185) on the top metal interconnect layer. A scribe street (305) surrounds a perimeter of the IC die, the scribe street including a scribe seal (120) utilizing at least two of the plurality of metal interconnect layers, an inner metal meander stop ring (130) including at least a top metal interconnect layer located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap (131). An outer metal meander stop ring (135) including at least the top metal interconnect layer is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap (132).

Description

Technical Field

[0001] This disclosure relates to laser-based wafer dicing for semiconductor wafers, and more specifically, to scribe sealing arrangements for semiconductor dies on the laser-diced wafer. Background Technology

[0002] Semiconductor dies are typically manufactured by dicing a semiconductor substrate, usually referred to as a "wafer," which comprises multiple semiconductor dies of predetermined die sizes, into individual dies. The diameter of the "wafer" is typically at least 6 inches (approximately 150 mm), such as 8 inches (approximately 200 mm) or 12 inches (approximately 300 mm). During wafer dicing, adhesive dicing tape is typically attached to the back surface of the wafer to prevent it from scattering, and then a mechanical saw is typically used to dice the wafer from the front to individualize the semiconductor die.

[0003] Mechanical dicing saws typically provide a die pitch of approximately 40 μm, making the die pitch, known as the scribing ridges between semiconductor dies, wide enough for this type of cutting. The scribing ridges can include metal-containing test structures (e.g., insert structures). During dicing, a dicing tape attached to the back surface of the wafer is slightly cut into its surface, but not completely through, leaving the semiconductor die still on the dicing tape. After individualization, the dicing tape is expanded using a wafer expander, which disperses the individual dies to better enable a die picker to pick up the semiconductor dies one by one from the dicing tape. The semiconductor dies are then transferred to subsequent assembly steps, such as die bonding steps, where they are attached using die attachment materials.

[0004] Laser saws are known to be a replacement for mechanical saws for wafer dicing. Compared to mechanical saws, laser saws achieve narrower die separations; for laser beams with a diameter of 2 μm to 3 μm, the scribe lines are typically only about 6 μm wide. Ablation lasers, which ablate substrate material, are known for laser dicing, wherein the laser beam is focused at the surface of the wafer, and the substrate material is removed by evaporation during the laser dicing process.

[0005] In laser cutting, the sawing process causes spalling and cracking within the scribe line (also known as the kerf). To prevent or reduce the propagation of such cracks, it is known to design the scribe line to ensure that remaining material surrounds the active region of the chip, which includes circuitry with a scribe seal structure defining the outer edge of the scribe line adjacent to the active region, also known as the main die region. The scribe seal comprises a multilayer stack of metal interconnects and an interlayer dielectric (ILD) material, wherein the filled metal vias between metal interconnect layers laterally adjacent to the scribe line at a distance greater than the kerf are referred to herein as metal plugs. When the wafer is sawn along the scribe line, the scribe seal remains around the outer edge of each individual semiconductor chip.

[0006] "Stealth" laser dicing is also known, utilizing subsurface wafer irradiation, which uses a pulsed laser beam at a wavelength transmitted into the wafer thickness to create embedded cracks in the scribe lines of the wafer. For silicon wafers, near-infrared (near IR) lasers are used in stealth laser dicing due to silicon's undesirable absorption of shorter wavelengths (e.g., visible light). Embedded cracks generated by stealth laser dicing are known to extend non-linearly in a so-called zigzag pattern (or moving pattern) due to uneven lateral movement of the laser dicing line along the top-side substrate (such as silicon) and the metal layer where the crack defect is located. For circuit reliability considerations, if the zigzag pattern is determined to reach the scribe seal anywhere along its perimeter, the semiconductor die is typically rejected because nothing prevents the zigzag of laser damage from reaching the main die region inside the scribe seal. It is known that a filled metal array comprising an overlapping two-dimensional (2D) array of metal cubes is positioned outside the scribe seal to control the zigzag of laser damage. Summary of the Invention

[0007] The present invention is provided in a simplified form to introduce a brief selection of the disclosed concepts further described in the detailed description, including the accompanying drawings. This invention is not intended to limit the scope of the claimed subject matter.

[0008] The disclosed aspects recognize that conventional arrays of overlapping filler metal squares used to control zigzag (or displacement) of crystal damage from laser cutting during laser individualization do not prevent zigzags from reaching the scribing seal, as described above, resulting in circuit yield loss. Zigzags may sometimes terminate in the filler metal, or at other times reach the scribing seal and cause yield loss.

[0009] The disclosed aspect includes an integrated circuit (IC) die comprising a substrate having a semiconductor surface layer having circuitry configured for at least one function, the semiconductor surface layer comprising a plurality of metal interconnect stages / layers thereon, including a top metal interconnect layer and a bottom metal interconnect layer, and having a passivation dielectric layer on the top metal interconnect layer. A scribe seal utilizing at least two of the plurality of metal interconnect layers surrounds the periphery of the IC die, the periphery defining the edge of a main die region. The scribe seal typically comprises alternating metal interconnect layers coupled vertically (in the thickness direction of the die) through the ILD layer using metal plungers.

[0010] One disclosed aspect includes an IC having two metallic zigzag stop rings. An inner metallic zigzag stop ring, comprising at least a top metallic interconnect layer, is located outside a scratch seal, wherein the scratch seal and the inner metallic zigzag stop ring are separated by a first separation gap. An outer metallic zigzag stop ring, comprising at least a top metallic interconnect layer, is located outside the inner metallic stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

[0011] Another disclosed aspect includes an IC having only a single metal zigzag stop ring. In this respect, the metal zigzag stop ring consists only of a top metal interconnect layer, or only of a top metal interconnect layer and a metal interconnect layer immediately below the top metal interconnect layer. Attached Figure Description

[0012] Now refer to the accompanying drawings, which are not necessarily drawn to scale, in which:

[0013] Figure 1A The illustration shows a top perspective view of an example IC die with a scratched seal and continuous inner and outer bend stop rings, according to an example aspect.

[0014] Figure 1B The diagram shows a top perspective view of an example IC die according to an example aspect, the IC die having a scribe seal and a discontinuous inner zigzag stop ring and a discontinuous outer zigzag stop ring separated by a gap, wherein each of the respective metal zigzag stop rings comprises a plurality of segments, which are staggered from one another and overlap one another when viewed from a direction perpendicular to the length direction of the segments.

[0015] Figure 2 This is a depiction of a portion of a wafer with scribe lines according to an example aspect, the scribe lines comprising a continuous inner metal zigzag stop ring and an outer metal zigzag stop ring ring, wherein a passivation layer trench is present near the center of the scribe lines.

[0016] Figure 3AA cross-sectional view of an IC with a scribe line is shown according to an example aspect. The scribe line includes a scribe seal, an inner metal zigzag stop ring, and an outer metal zigzag stop ring, each including multiple metal interconnect layers connected by metal plungers.

[0017] Figure 3B A cross-sectional view of an IC with a scribe line is shown according to an example aspect. The scribe line includes a scribe seal comprising multiple metal interconnect layers connected by a metal plunger, and an inner metal zigzag stop ring and an outer metal zigzag stop ring, each consisting only of a top metal interconnect layer.

[0018] Figure 3C A simplified cross-sectional view of an IC with a scribe line is shown according to an example aspect. The scribe line includes a scribe seal comprising multiple metal interconnect layers connected by a metal plunger, and a single zigzag stop ring consists only of the top metal interconnect layer shown as M5.

[0019] Figure 4 This is a flowchart illustrating the steps in an example method for manufacturing an IC die according to an example aspect, the IC die having an inner metal zigzag stop ring and an outer metal zigzag stop ring outside a scribe seal.

[0020] Figure 5 This is a flowchart illustrating the steps in an example method for manufacturing an IC die having only a single metal bend stop ring, wherein the metal bend stop ring consists only of a top metal interconnect layer, or only of a top metal interconnect layer and a metal interconnect layer immediately below the top metal interconnect layer. Detailed Implementation

[0021] Referring to the accompanying drawings, in which similar reference numerals are used to denote similar or equivalent elements. The illustrated order of actions or events should not be considered limiting, as some actions or events may occur in different orders and / or simultaneously with other actions or events. Furthermore, according to this disclosure, implementing a method may not require certain illustrated actions or events.

[0022] Figure 1AThe illustration shows a top perspective view of an example IC die 100 with a scribe line 105, which includes a scribe seal 120, an inner zigzag stop ring 130, and an outer zigzag stop ring 135, both of which are continuous surrounding structures enclosing the entire IC die 100. The scribe seal 120 includes at least two of a plurality of metal interconnect layers, but as described above, typically includes all metal interconnect layers coupled together by a metal plunger passing through the ILD. The inner metal zigzag stop ring 130 and the outer metal zigzag stop ring 135, located outside the scribe seal 120, comprise a substrate having a semiconductor surface layer (see [reference]). Figure 2 The circuit on the substrate 110, which includes transistors and other circuit elements configured for at least one function, includes a plurality of metal interconnect layers thereon, including a top metal interconnect layer and a bottom metal interconnect layer, wherein the top metal interconnect layer has a passivation layer 185 comprising a dielectric material.

[0023] The passivation layer 185 is shown as transparent over the inner zigzag stop ring 130 and the outer zigzag stop ring 135 to expose the top metal interconnect layers of the inner zigzag stop ring 130 and the outer zigzag stop ring 135. As used herein, "ring" refers to a continuous surrounding structure having a shape including, for example, a circle or generally circular, elliptical, rectangular, or square shape, or the disclosed ring may also include multiple segments with gaps between these segments (see description below). Figure 1B These segments collectively define a shape, which may include, for example, a circle or substantially a circle, an ellipse, a rectangle, or a square.

[0024] The scratched seal 120 and the inner metal zigzag stop ring 130 are separated by a first separation gap 131. The inner metal zigzag stop ring 130 and the outer metal zigzag stop ring 135 are separated by a second separation gap 132, wherein both the inner and outer metal zigzag stop rings comprise continuous circumferential rings. Both the inner and outer metal zigzag stop rings 130 and 135 are typically 1 μm to 3 μm wide, such as 2 μm wide. The first and second separation gaps 131 and 132 are also typically 1 μm to 3 μm wide, such as 2 μm wide.

[0025] As described above, during stealth laser dicing, the laser beam can be approximately 2 μm to 3 μm wide, and it is typically incident on the back side of the wafer. The laser beam is internally (deeply) focused near the center of the scribe line on the wafer, which typically contains silicon. Stealth laser dicing does not remove any material within the scribe line. The stealth laser dicing process causes the semiconductor material, which typically contains silicon, to crack only internally, and die separation is achieved by stretching a dicing tape below the top side of the wafer after the stealth laser dicing process.

[0026] Figure 1B The diagram shows a top perspective view of an example IC die 150, which has a scribble seal 120 and a discontinuous inner zigzag stop ring 130' and a discontinuous outer zigzag stop ring 135', each comprising multiple segments that are staggered from one another and overlap each other when viewed perpendicular to the length direction of the segments. The inner metal zigzag stop ring 130' includes multiple first segments (shown as 130a), and the outer metal zigzag stop ring 135' includes multiple second segments.

[0027] The etched seal 120 and the inner metal zigzag stop ring 130' are separated by a first separation gap 131. The inner metal zigzag stop ring 130' and the outer metal zigzag stop ring 135' are separated by a second separation gap 132. The first plurality of segments 130a lie above the gap between (overlapping) the second plurality of segments 135a, and the second plurality of segments 135a lie above the gap between the first plurality of segments 130a. As used herein, the length of a "segment" is at least twice its width, thus geometrically distinguishing it from a conventional filled metal block.

[0028] Figure 2 This is a depiction of a portion of a wafer 200 including a substrate 110, showing four IC dies 220a, 220b, 220c, and 220d, shown as “main dies,” wherein the wafer 200 includes scribe lines 205 between the IC dies. The scribe lines 205 shown include continuous inner metal bend stop rings 130 and continuous outer metal bend stop rings 135. Near the center of the scribe line 205 is a passivation trench 280, shown as a “PO trench.”

[0029] Figure 3A A simplified cross-sectional view of IC 300 is shown, which includes: a substrate 110 having a scribe line 305 including a scribe line seal 120 and an inner metal bend stop ring 130 and an outer metal bend stop ring 135, each stop ring including a plurality of metal interconnect layers. These metal interconnect layers are shown as metal 1 (M1) to metal 5 (M5), where M1 is a bottom metal layer and M5 is a top metal layer. Adjacent metal interconnect layers are coupled to each other by metal plungers 167 extending through the thickness of ILD layers (shown as ILD1, ILD2, ILD3, and ILD4). A circuit 180 formed in the substrate 110 is shown, having nodes coupled to bonding pads, where a single bonding pad is shown as a bonding pad 181 provided by layer M5.

[0030] The passivation layer 185, also known as the passivation protection layer (PO) on the top surface of IC 300, contains bonding pads 181 exposed for electrical contact with nodes on IC 300 as needed. As previously described, a separation gap 131 is provided between the scribe seal 120 and the inner metal bend stop ring 130, and a separation gap 132 is provided between the inner metal bend stop ring 130 and the outer metal bend stop ring 135; these two separation gaps are substantially parallel to each other. Both separation gaps 131 and 132 are typically approximately 2 μm to 3 μm wide.

[0031] Figure 3B A simplified cross-sectional view of IC 350 with a scribe line 305′ is shown. This scribe line includes a scribe seal 120, which comprises multiple metal interconnect layers connected by metal plungers 167 passing through the ILD layer. Both the inner metal zigzag stop ring 130′ and the outer metal zigzag stop ring 135′ are composed solely of the top metal interconnect layer shown as M5.

[0032] Figure 3C A simplified cross-sectional view of an IC 380 with a scribe line 305″ is shown. This scribe line includes a scribe seal 120 comprising multiple metal interconnect layers connected by metal plungers 167, and a single zigzag stop ring 130″ consisting only of the top metal interconnect layer, shown as M5. The IC 380 reflects the understanding that a zigzag stop ring typically does not need to include a complete metal stack (meaning all metal interconnect layers) to perform its intended function, which differs from that of a scribe seal as described above. Conventional scribe seals are configured as rings and include all metal layers to prevent mechanical stress during mechanical cutting from causing cracks in the region associated with the active circuitry (active metal) of the IC die and beneath the active metal of the IC die.

[0033] However, the scribing seal also serves to prevent "chip outs" from entering the same area. This is why a conventional scribing seal includes all metal interconnect layers. In the case of stealth laser dicing associated with the disclosed aspect, it has been recognized that there is no risk of chip outs, therefore it is not necessary to include each metal interconnect layer as in a scribing seal. In the case of stealth laser dicing, cracks in the crystal can propagate to the surface of the wafer, then zigzag along the wafer surface and / or cause the passivation dielectric to peel off into the die region. Crack lines are prevented from entering the main die region using only the top metal (or top metal interconnect layer, and at most optionally, a metal interconnect layer immediately below the top metal interconnect layer). Stealth laser dicing is considered to introduce no risk of mechanical cracking beneath the metal interconnects in the main die region; therefore, the disclosed zigzag stop does not require additional layers of these metal interconnects.

[0034] Figure 4 This is a flowchart illustrating the steps of an example method 400 for manufacturing an IC die according to an example aspect, the IC die having an inner metal bend stop ring and an outer metal bend stop ring outside a scribe seal. Step 401 includes providing a substrate having a semiconductor surface layer having a plurality of IC dies, each IC die having circuitry configured for at least one function in the semiconductor surface layer, and scribe lines located between adjacent IC dies among the plurality of IC dies. Step 402 includes forming a metal stack having a plurality of metal interconnect layers thereon, the plurality of metal interconnect layers including a top metal interconnect layer and a bottom metal interconnect layer, and having a passivation layer on the top metal interconnect layer. Forming multiple metal interconnect layers includes steps 403 and 404. Step 403 includes forming a scribing seal in a scribing channel using at least two of the multiple metal interconnect layers surrounding the periphery of the multiple IC dies. Step 404 includes forming an inner metal zigzag stop ring and an outer metal zigzag stop ring outside the scribing seal. The inner metal zigzag stop ring is separated from the scribing seal through a first separation gap, and the outer metal zigzag stop ring is separated from the inner metal zigzag stop ring through a second separation gap.

[0035] Method 400 may further include etching a passivation layer in a portion of the scribing path between adjacent stop rings in the outer metal zigzag stop ring to provide trenches in the passivation layer. The method may also further include stealth laser cutting focused in depth within the scribing path to create embedded crystal damage within the scribing path.

[0036] Figure 5This is a flowchart illustrating the steps of an example method 500 for manufacturing an IC die having only a single metal bend stop ring, wherein the metal bend stop ring is composed only of a top metal interconnect layer, or only of a top metal interconnect layer and a metal interconnect layer immediately below the top metal interconnect layer. Step 501 includes providing a substrate having a semiconductor surface layer having a plurality of IC dies, each IC die having circuitry configured for at least one function in the semiconductor surface layer, and scribe lines located between adjacent IC dies among the plurality of IC dies. Step 502 includes forming a metal stack having a plurality of metal interconnect layers thereon, the plurality of metal interconnect layers comprising at least four layers, including a top metal interconnect layer and a bottom metal interconnect layer, and having a passivation layer on the top metal interconnect layer. Forming multiple metal interconnect layers includes steps 503 and 504. Step 503 includes forming a scribing seal in a scribing channel using at least two of the multiple metal interconnect layers surrounding the periphery of the multiple IC dies. Step 504 includes forming a single metal zigzag stop ring outside the scribing seal. The single metal zigzag stop ring is separated from the scribing seal by a separation gap. The single metal zigzag stop ring is composed of a top metal interconnect layer and at most a metal interconnect layer immediately below the top metal interconnect layer.

[0037] A single metal bend stop ring may consist solely of the top metal interconnect layer. Method 500 may further include stealth laser cutting focused in depth within a scribing channel of the substrate to create embedded crystal damage within the scribing channel. The single bend stop ring may be a continuous loop surrounding the IC die.

[0038] The disclosed aspects can be integrated into various assembly processes to form a variety of different packaged semiconductor devices and related products. The assembly may include a single semiconductor die or multiple semiconductor dies, such as configurations including multiple stacked semiconductor dies. Various packaging substrates can be used. The semiconductor die may include various elements and / or include various layers thereon, including barrier layers, dielectric layers, device structures, active elements, and passive elements, including source regions, drain regions, bit lines, bases, emitters, collectors, wires, conductive vias, etc. Furthermore, the semiconductor die can be formed using various processes including bipolar, insulated-gate bipolar transistor (IGBT), CMOS, BiCMOS, and MEMS.

[0039] Those skilled in the art will understand that many variations of the disclosed aspects are possible within the scope of the claimed invention, and that further additions, deletions, substitutions, and modifications can be made to the above aspects without departing from the scope of this disclosure.

Claims

1. An integrated circuit die, i.e., an IC die, comprising: A substrate having a semiconductor surface layer having circuitry configured for at least one function, the semiconductor surface layer including a plurality of metal interconnect layers thereon, the metal interconnect layers including a top metal interconnect layer and a bottom metal interconnect layer, and having a passivation layer comprising a dielectric material on the top metal interconnect layer; The scribe lines surrounding the periphery of the IC die, the scribe lines including: A scribing seal, wherein the scribing seal utilizes at least two of the plurality of metal interconnect layers; An internal metal bend stop ring, the internal metal bend stop ring comprising at least the top metal interconnect layer located outside the scribe seal, wherein the scribe seal and the internal metal bend stop ring are separated by a first separation gap, and An outer metal zigzag stop ring, the outer metal zigzag stop ring including at least the top metal interconnect layer located outside the inner metal zigzag stop ring, wherein the outer metal zigzag stop ring and the inner metal zigzag stop ring are separated by a second separation gap.

2. The IC die according to claim 1, wherein, Both the inner metal zigzag stop ring and the outer metal zigzag stop ring are continuous surrounding rings.

3. The IC die according to claim 1, wherein, Both the inner metal zigzag stop ring and the outer metal zigzag stop ring are discontinuous rings. The inner metal zigzag stop ring has a first plurality of segments, and the outer metal zigzag stop ring has a second plurality of segments. The first plurality of segments are located above the gaps between the second plurality of segments, and the second plurality of segments are located above the gaps between the first plurality of segments.

4. The IC die according to claim 1, further comprising a passivation trench region, the passivation trench region not including a passivation layer of a continuous surrounding ring configured to be located outside the outer metal bend stop ring.

5. The IC die according to claim 1, wherein, The inner metal bend stop ring and the outer metal bend stop ring include at least one of the plurality of metal interconnect layers in addition to the top metal interconnect layer.

6. The IC die according to claim 1, wherein, Both the inner and outer metal zigzag stop rings are 1 μm to 3 μm wide.

7. The IC die according to claim 1, wherein, The inner metal bend stop ring and the outer metal bend stop ring are substantially parallel to each other and extend only along the periphery of the IC die.

8. An integrated circuit die, i.e., an IC die, comprising: A substrate having a semiconductor surface layer having circuitry configured for at least one function, the semiconductor surface layer including a plurality of metal interconnect layers thereon, the plurality of metal interconnect layers including at least four metal interconnect layers, including a top metal interconnect layer and a bottom metal interconnect layer, and having a passivation layer comprising a dielectric material on the top metal interconnect layer; The scribe lines surrounding the periphery of the IC die, the scribe lines including: A scribing seal, the scribing seal utilizing at least two of the plurality of metal interconnect layers, and A single metal zigzag stop ring is located outside the scratched seal, the scratched seal being composed of a top metal interconnect layer and at most a metal interconnect layer immediately below the top metal interconnect layer, wherein the scratched seal and the single metal zigzag stop ring are separated by a separation gap.

9. The IC die according to claim 8, wherein, The single metal zigzag stop ring is composed solely of the top metal interconnect layer.

10. The IC die according to claim 8, wherein, The single metal zigzag stop ring comprises a continuous surrounding ring.

11. A method for manufacturing an integrated circuit die, i.e., an IC die, comprising: A substrate having a semiconductor surface layer is provided, the semiconductor surface layer having a plurality of IC dies, each of the IC dies having circuitry configured for at least one function in the semiconductor surface layer, and scribe lines located between adjacent IC dies in the plurality of IC dies; A metal stack is formed, the metal stack including a plurality of metal interconnect layers thereon, the plurality of metal interconnect layers including a top metal interconnect layer and a bottom metal interconnect layer, and having a passivation layer on the top metal interconnect layer, the formation of the plurality of metal interconnect layers including: At least two of the plurality of metal interconnect layers are used to form scribe seals around the periphery of the plurality of IC dies in the scribe lines, and An inner metal beveled stop ring and an outer metal beveled stop ring are formed on the outside of the scribed seal. The internal metal bend stop ring is separated from the etched seal through a first separation gap. Furthermore, the outer metal bend stop ring is separated from the inner metal bend stop ring through a second separation gap.

12. The method of claim 11, further comprising etching the passivation layer in a portion of the scribing path between two adjacent outer metal zigzag stop rings to provide trenches in the passivation layer.

13. The method of claim 11, further comprising stealth laser cutting focused in depth within the scribing path to create embedded crystal damage within the scribing path.

14. The method according to claim 11, wherein, Both the inner and outer metal zigzag stop rings are 1 μm to 3 μm wide.

15. The method according to claim 11, wherein, Both the inner and outer metal zigzag stop rings are discontinuous rings. The inner metal zigzag stop ring has a first plurality of segments, and the outer metal zigzag stop ring has a second plurality of segments, wherein the first plurality of segments are located above the gaps between the second plurality of segments, and wherein the second plurality of segments are located above the gaps between the first plurality of segments.

16. A method for manufacturing an integrated circuit die, i.e., an IC die, comprising: A substrate having a semiconductor surface layer is provided, the semiconductor surface layer having a plurality of IC dies, each IC die having circuitry configured for at least one function in the semiconductor surface layer, and scribe lines located between adjacent IC dies in the plurality of IC dies; A metal stack is formed, the metal stack including a plurality of metal interconnect layers thereon, the plurality of metal interconnect layers including at least four layers, including a top metal interconnect layer and a bottom metal interconnect layer, and having a passivation layer on the top metal interconnect layer, the formation of the plurality of metal interconnect layers including: At least two of the plurality of metal interconnect layers are used to form scribe seals around the periphery of the plurality of IC dies in the scribe lines, and A single metal zigzag stop ring is formed on the outside of the scribed seal, the single metal zigzag stop ring being separated from the scribed seal by a separation gap, wherein the single metal zigzag stop ring is composed of the top metal interconnect layer and at most a metal interconnect layer immediately below the top metal interconnect layer.

17. The method according to claim 16, wherein, The single metal zigzag stop ring is composed solely of the top metal interconnect layer.

18. The method of claim 16, further comprising a stealth laser cut focused in depth in the scribing path of the substrate to create embedded crystal damage in the scribing path.

19. The method of claim 16, wherein, The individual metal zigzag stop ring is 1 μm to 3 μm wide.

20. The method of claim 16, wherein, The single metal bend stop ring is a continuous loop surrounding the IC die.

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