Electronic devices, methods of manufacturing the same, and memory devices including the same

Abstract

Electronic devices including a dielectric layer having a crystal orientation that is adjusted, methods of manufacturing the electronic devices, and memory devices including the electronic devices are provided. The electronic devices include a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes grains having a crystal orientation that is aligned. The dielectric layer includes grains having a crystal orientation that is aligned in the same direction as the crystal orientation of the seed layer.

Description

Technical Field

[0001] This disclosure relates to electronic devices and methods of manufacturing them, and more specifically, to electronic devices including dielectric layers having adjusted crystal orientations and methods of manufacturing the electronic devices. Background Technology

[0002] Silicon-based electronic devices according to related technologies are limited in terms of their operating characteristics and improvements for scaling down. For example, when the operating voltage and current characteristics of silicon-based logic transistors according to related technologies are measured, the known subthreshold swing (SS) is limited to approximately 60 mV / dec. Furthermore, as the size of logic transistors decreases, it may be difficult to reduce the operating voltage to 0.8 V or less due to the above limitations. Therefore, as the power density in silicon-based logic transistors increases, there may be limitations in the scaling down of logic transistors. Summary of the Invention

[0003] An electronic device including a dielectric layer and a method for manufacturing the electronic device are provided, the dielectric layer having an adjusted crystal orientation.

[0004] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0005] According to one aspect of the embodiments, an electronic device includes: a substrate; a seed layer on the substrate, the seed layer including grains having an aligned crystal orientation; a dielectric layer on the seed layer, the dielectric layer including grains having a crystal orientation aligned in the same direction as the crystal orientation of the seed layer; and an electrode on the dielectric layer.

[0006] The source, drain, and channel layer between the source and drain can be located on or on the upper surface of the substrate, and the channel layer can be located at the position corresponding to the electrode. The electrode can be the gate electrode.

[0007] The channel layer may include at least one of Si, Ge, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional semiconductor materials, quantum dots, and organic semiconductors.

[0008] The seed layer may include at least one of oxides, nitrides, chalcogenides, and two-dimensional insulating materials.

[0009] The oxide may include oxides of at least one of Y, Si, Al, Hf, Zr, La, Mo, W, Ru, and Nb. The oxide may also include dopants.

[0010] The seed layer can have a thickness of about 0.5 nm to about 3 nm.

[0011] The dielectric layer may include ferroelectric materials.

[0012] The dielectric layer may include an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr. The dielectric layer may also include a dopant.

[0013] The dielectric layer can have a thickness of about 0.5 nm to about 20 nm.

[0014] The crystal orientation of the grains in the seed layer and the dielectric layer can have <111> orientation.

[0015] According to another aspect of the embodiments, in an electronic device, the electrode may be a first electrode and the substrate may be a second electrode.

[0016] According to another aspect of the embodiments, a method of manufacturing an electronic device includes: preparing a substrate having a channel layer therein; forming a seed layer on the channel layer, the seed layer including grains having an aligned crystal orientation; forming a dielectric layer on the seed layer, the dielectric layer including grains having a crystal orientation aligned in the same direction as the crystal orientation of the seed layer; and forming a gate electrode on the dielectric layer.

[0017] The formation of the seed layer may include depositing a first amorphous dielectric material layer on the channel layer and crystallizing the deposited first amorphous dielectric material layer.

[0018] The formation of the seed layer may include transferring grains with an aligned crystal orientation onto the channel layer.

[0019] The dielectric layer can be formed by depositing a second amorphous dielectric material layer on a seed layer and crystallizing the deposited second amorphous dielectric material layer, the dielectric layer comprising grains having a crystal orientation in the same direction as the crystal orientation of the seed layer.

[0020] The dielectric layer may include ferroelectric materials.

[0021] The dielectric layer may include an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr. The dielectric layer may also include a dopant.

[0022] Electronic devices can be capacitors and can have residual polarization.

[0023] Electronic devices may be included as part of a storage device, which includes a transistor and electronic devices in contact with the source region of the transistor.

[0024] Electronic devices may include an amorphous dielectric layer between the seed layer and the substrate.

[0025] Electronic devices may include a crystalline dielectric layer having a crystal orientation different from the orientation of the seed layer between the seed layer and the substrate. Attached Figure Description

[0026] The above and other aspects, features and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 This is a cross-sectional view of an electronic device according to an example embodiment.

[0028] Figure 2 yes Figure 1 Enlarged cross-sectional view of the seed layer and dielectric layer.

[0029] Figure 3 This is a graph showing the effect of improving the subthreshold swing (SS) characteristics of an electronic device according to an example embodiment.

[0030] Figure 4 This is a cross-sectional view of an electronic device according to another example embodiment.

[0031] Figure 5 This is a cross-sectional view of an electronic device according to another example embodiment.

[0032] Figure 6 This is a cross-sectional view of an electronic device according to another example embodiment.

[0033] Figure 7 This is a cross-sectional view of an electronic device according to another example embodiment.

[0034] Figure 8A This is a graph showing a comparison between the capacitance of a general electronic device and the capacitance of an electronic device according to an example embodiment.

[0035] Figure 8B This is a graph showing a comparison between the residual polarization of a general electronic device and the residual polarization of an electronic device according to an example embodiment.

[0036] Figures 9A to 9D It is a cross-sectional view used to describe a method of manufacturing an electronic device according to an embodiment.

[0037] Figure 10 The structure of trench capacitor type dynamic random access memory (DRAM) is shown. Detailed Implementation

[0038] The embodiments will now be described in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the presented embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments described below are only for the purpose of explaining aspects by reference to the accompanying drawings. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of” modify the entire list of elements when following a list of elements, without modifying individual elements in the list.

[0039] In the following description, when a constituent element is positioned "above" or "on" another constituent element, the constituent element may be directly on or on the other constituent element in a non-contact manner. Expressions used in the singular form in this specification also include their plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprising" and / or "including" as used herein indicate the presence of a stated feature or component, but do not exclude the presence or addition of one or more other features or components. For ease of description, spatial relational terms such as "above," "below," "on," etc., may be used herein to describe the relationship of one element or feature to another(s) elements or features as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, spatial relational terms are intended to also cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relational descriptions used herein are interpreted accordingly. Furthermore, when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more other intervening elements may be present.

[0040] The use of the terms “a” and “the” and similar pronouns in the context of describing this disclosure shall be interpreted to cover both the singular and plural. Furthermore, the steps of all methods described herein may be performed in any suitable order unless otherwise indicated herein or otherwise obviously contradicted by the context. This disclosure is not limited to the order in which the steps are described. Any and all examples or language (e.g., “such as”) provided herein are intended only to better illustrate this disclosure and do not impose limitations on its scope unless otherwise stated.

[0041] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical values ​​include manufacturing tolerances (e.g., ±10%) surrounding the stated values. Furthermore, when the terms “generally” and “substantially” are used in conjunction with geometry, it is intended that a high degree of precision in the geometry is not required, but rather a tolerance for the shape is within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified with “about” or “substantially”, it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) surrounding the stated numerical values ​​or shapes.

[0042] Figure 1 This is a cross-sectional view of an electronic device 100 according to an example embodiment. Figure 1 The illustrated electronic device 100 (which is a semiconductor-based device) may have a gate stack structure including a dielectric layer 140 and a gate electrode 150. The dielectric layer 140 may include, for example, a ferroelectric material. The electronic device 100 may include, for example, logic devices and / or memory devices.

[0043] Reference Figure 1 The electronic device 100 may include a substrate 110, and may further include a seed layer 130, a dielectric layer 140, and a gate electrode 150 sequentially stacked on the substrate 110. A channel layer 115 may be provided on the upper surface of the substrate 110 at a position corresponding to the gate electrode 150, and a source (S) 121 and a drain (D) 122 may be provided on the side of the channel layer 115, respectively.

[0044] Source 121 may be electrically connected to one side of channel layer 115, and drain 122 may be electrically connected to the other side of channel layer 115. Source 121 and drain 122 may be formed by implanting impurities in different regions of substrate 110, and the region of substrate 110 between source 121 and drain 122 may be defined as channel layer 115. Alternatively, source 121 and drain 122 may comprise conductive material deposited on different sides of channel layer 115.

[0045] Substrate 110 may be a semiconductor substrate, and may include, for example, a Si substrate, but may include materials other than Si. For example, substrate 110 may include Ge, SiGe, and / or group III-V semiconductors. In this case, channel layer 115 may include Si, Ge, SiGe, and / or group III-V semiconductors. In this case, channel layer 115 may be in the substrate, for example, as a portion of the substrate defined by source 121 and drain 121. The semiconductor substrate may be crystalline or polycrystalline. The material of substrate 110 is not limited to the above materials and may be varied. Alternatively, as described below, channel layer 115 may be formed as a material layer separate from substrate 110, and not as part of substrate 110.

[0046] The seed layer 130 and the dielectric layer 140 may be stacked sequentially on the upper surface of the channel layer 115 of the substrate 110. The seed layer 130 may be provided with a crystal orientation 130a aligned in a certain direction, and the dielectric layer 140 may be provided with a crystal orientation 140a aligned in the same direction as the crystal orientation of the seed layer 130.

[0047] Figure 2 yes Figure 1 Enlarged cross-sectional view of part of the seed layer 130 and dielectric layer 140.

[0048] Reference Figure 2 The seed layer 130 may include a plurality of grains 131 defined by grain boundaries 131a. In this case, the grains 131 forming the seed layer 130 may have an orientation in a certain direction. Figure 1 The crystal orientation is 130a. In Figure 2 In the figure, reference numeral 130b indicates the crystal plane of the grain 131 that forms the seed crystal layer 130, and generally, the crystal plane 130b can be formed perpendicular to the crystal direction 130a.

[0049] For example, the grains 131 forming the seed layer 130 can have <111> Crystal orientation. However, this is only an example; the grains 131 forming the seed layer 130 may have other orientations besides crystal orientation. <111> Other crystal orientations besides the crystal orientation itself. The term "..." <111> "" represents the Miller index, which indicates crystal orientation in crystallography, and can represent <111> Directional families. For example... <111> Crystal orientations can indicate

[111] , [-111], [1-11], [11-1], [-1-11], [-11-1], [1-1-1], and [-1-1-1]. For example, due to symmetry operations in the crystal, <111> Directional families can be equivalent.

[0050] The seed layer 130 may include, for example, oxides, nitrides, chalcogenides, and / or two-dimensional insulating materials. However, this disclosure is not limited thereto.

[0051] The oxide may include oxides of at least one of, for example, Y, Si, Al, Hf, Zr, La, Mo, W, Ru, and Nb. The oxide may also include a dopant. The dopant may be an oxide. In this case, the dopant may include at least one of, for example, Si, Al, Zr, Y, La, Gd, Sr, and Hf. The nitride may include, for example, InN.

[0052] Chalcogenides may include, for example, MoTe, WTe, HfS, and / or ZrS. Two-dimensional insulating materials may include, for example, hexagonal boron nitride (h-BN).

[0053] The seed layer 130 may have lattice parameters between those of the substrate 110 and the dielectric layer 140; and / or the seed layer 130 may be thin enough to prevent and / or mitigate lattice strain caused by lattice mismatch between the material of the seed layer 130 and the material of the substrate 110. Therefore, the seed layer 130 may also promote adhesion between the substrate 110 and the dielectric layer 140 by acting as an interlayer, thus preventing the dielectric layer 140 from peeling off from the substrate 110 due to lattice mismatch.

[0054] As described below, the seed layer 130 can be formed by depositing an amorphous dielectric material layer on the upper surface of the channel layer 115 of the substrate 110 via deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD), and then crystallizing the deposited amorphous dielectric material layer. Alternatively, the seed layer 130 can be formed by a transfer method. The seed layer 130 can be formed to a thickness of, for example, about 0.5 nm to 3 nm.

[0055] As described above, a dielectric layer 140 is provided on the upper surface of a seed layer 130 having an adjusted crystal orientation. The dielectric layer 140 may include a plurality of grains 141 defined by grain boundaries 141a. In this case, the grains 141 forming the dielectric layer 140 may have a crystal orientation 140a aligned in the same direction as the crystal orientation 130a of the seed layer 130. Figure 2 In the figure, reference numeral 140b indicates the crystal plane of the grain 141 forming the dielectric layer 140, and the crystal plane 140b may be perpendicular to the crystal direction 140a. The grain 141 forming the dielectric layer 140 may have the same crystal plane 140b as the crystal plane 130b of the seed layer 130.

[0056] As described below, the dielectric layer 140 can be formed by depositing an amorphous dielectric material layer on the upper surface of a seed layer 130 having an adjusted crystal orientation 130a, and then crystallizing the deposited amorphous dielectric material layer. The seed layer 130 can help promote the nucleation of seed crystals in the dielectric layer 140 during the annealing of the dielectric layer 140. The seed crystal can be oriented in the same crystal orientation as the seed layer 130. The dielectric layer 140 can be formed from an enlarged nucleated seed crystal and / or from a new nucleated seed crystal formed at the interface between the seed layer 130 and the amorphous dielectric material layer. Therefore, as the amorphous dielectric material layer crystallizes through the annealing process, grains 141 having a crystal orientation 140a aligned in the same direction as the crystal orientation of the seed layer 130 grow, thus forming a dielectric layer 140 having an adjusted crystal orientation 140a.

[0057] For example, when the grains 131 forming the seed layer 130 have <111> During crystal orientation, the grains 141 forming the dielectric layer 140 can have the same crystal orientation as the grains 131 of the seed layer 130. <111> Crystal orientation.

[0058] The dielectric layer 140 may include a ferroelectric material. Ferroelectric materials possess spontaneous dipoles (electric dipoles). That is, ferroelectric materials can spontaneously polarize due to the charge distribution within the unit cells of a non-centrosymmetric crystalline material structure. Even in the absence of an external electric field, the ferroelectric material exhibits remanent polarization due to its dipoles. Furthermore, the polarization direction can be flipped in domains by an external electric field. Depending on the external electric field, the ferroelectric material may or may not possess hysteresis characteristics.

[0059] The dielectric layer 140 may include an oxide, such as an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr. However, this is merely an example. Furthermore, the dielectric layer 140 may also include a dopant, as desired. In this case, the dopant may include, for example, at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf. When the dielectric layer 140 includes a dopant, the dopant may be incorporated at a uniform (e.g., the same) concentration or at different concentrations depending on the region. Furthermore, the different regions of the dielectric layer 140 may be doped with different dopants.

[0060] As described below, the dielectric layer 140 can be formed by depositing an amorphous dielectric film on the upper surface of the seed layer 130 via deposition methods such as CVD, ALD, and PVD, and then crystallizing the deposited amorphous dielectric film by annealing. The dielectric layer 140 can have a thickness greater than or equal to that of the seed layer 130. The dielectric layer 140 can have a thickness, for example, from about 0.5 nm to 20 nm.

[0061] The gate electrode 150 may be located on the upper surface of the dielectric layer 140. In this case, the gate electrode 150 may be disposed facing the channel layer 115 of the substrate 110. The gate electrode 150 may comprise a conductive material, such as a metal, a doped semiconductor, and / or a conductive carbon-based compound (such as graphene and / or a conductive polymer).

[0062] In the electronic device 100 according to this embodiment, since the dielectric layer 140 is formed as a ferroelectric material, the subthreshold swing (SS) of the electronic device 100 can be reduced.

[0063] Figure 3 This is a graph illustrating the effect of improving the SS characteristics of logic transistors according to the implementation method. Figure 3In this context, "A" represents the operating voltage Vg and current Id characteristics of a silicon-based logic transistor according to the related art, and "B" represents the operating voltage Vg and current Id characteristics of a logic transistor according to an example embodiment.

[0064] Reference Figure 3 In silicon-based transistors according to related technologies, the voltage spectral density (SS) is known to be limited to about 60 mV / dec. However, in logic transistors according to exemplary embodiments, by using a ferroelectric layer, voltage amplification occurs when domains in the ferroelectric material flip due to the negative capacitance effect, allowing SS to be reduced to about 60 mV / dec or less.

[0065] In the electronic device 100 according to this embodiment, since the ferroelectric material included in the dielectric layer 140 includes grains 141 having an aligned crystal orientation 140a, the polarization characteristics of the dielectric layer 140 and the performance of the electronic device 100 can be improved.

[0066] In electronic devices including ferroelectric materials according to related technologies, the ferroelectric grains are arranged in random directions. However, in the electronic device 100 according to this embodiment, since the ferroelectric material included in the dielectric layer 140 includes grains 141 having an aligned crystal orientation 140a, the remanent polarization can be larger compared to electronic devices according to related technologies. Therefore, the polarization characteristics of the dielectric layer 140 can be improved.

[0067] Furthermore, in the electronic device 100 according to this exemplary embodiment, since the polarization direction is aligned and thus the depolarization field increases, and due to the increased negative capacitance effect, the SS can be further reduced. Therefore, the performance of the electronic device 100 can be further improved. For example, the minimum operating threshold voltage of the electronic device 100 can be about 0.8V or less; however, this disclosure is not limited thereto.

[0068] Figure 4 This is a cross-sectional view of an electronic device 200 according to another embodiment. Except for the amorphous dielectric layer 260 provided between the seed layer 130 and the channel layer 115, Figure 4 The electronic device 200 shown is Figure 1 The electronic components are 100 times the same.

[0069] Reference Figure 4An amorphous dielectric layer 260 may be provided between the channel layer 115 and the seed layer 130 of the substrate 110. The amorphous dielectric layer 260 may include oxides of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr, but this disclosure is not limited thereto. Alternatively, instead of the amorphous dielectric layer 260 described above, a crystalline dielectric layer (not shown) having a crystal orientation different from that of the seed layer 130 may be provided between the channel layer 115 and the seed layer 130 of the substrate 110. In the case of either the amorphous dielectric layer 260 or the crystalline dielectric layer (not shown), this layer may, for example, serve as an intermediate layer between the substrate 110 and the seed layer 130. As described above, the intermediate layer can help prevent and / or mitigate peeling of layers above and below the intermediate layer. Any intermediate layer (e.g., amorphous dielectric layer 260 or crystalline dielectric layer (not shown)) can also help the formation of the seed layer 130 having crystal orientation 130a by acting as a barrier between the seed layer 130 and the substrate 110 during the annealing of the seed layer 130, thus preventing and / or mitigating lattice interference of the substrate or affecting crystal formation in the seed layer 130.

[0070] Figure 5 This is a cross-sectional view of an electronic device 300 according to another embodiment. The following description mainly discusses the differences from the embodiment described above.

[0071] Reference Figure 5 The electronic device 300 may include a substrate 310 and a channel layer 315, a seed layer 130, a dielectric layer 140 and a gate electrode 150 sequentially deposited on the substrate 310. A source electrode 321 and a drain electrode 322 may be provided on both sides of the channel layer 315.

[0072] Although substrate 310 may include semiconductor materials such as Si, Ge, and / or III-V semiconductors, this disclosure is not limited thereto. A channel layer 315 may be provided on the upper surface of substrate 310. Channel layer 315 may be provided as a material layer separate from substrate 310 (e.g., not part of substrate 310). Channel layer 315 may include at least one of, for example, oxide semiconductors, nitride semiconductors, oxide-oxygen nitride semiconductors, two-dimensional semiconductor materials, quantum dots (QDs), and organic and / or carbon-based semiconductors. In this case, oxide semiconductors may include, for example, InGaZnO; two-dimensional semiconductor materials may include, for example, transition metal dichalcogenides (TMDs), molybdenum disulfide (MoS2), and / or graphene; quantum dots may include colloidal quantum dots and / or nanocrystalline structures; and organic and / or carbon-based semiconductors may include, for example, carbon nanotubes (CNTs) and / or other π-bonded molecules. However, this is merely an example, and this disclosure is not limited thereto.

[0073] Source electrode 321 and drain electrode 322 may be provided on both sides of channel layer 315. Source electrode 321 may be connected to one side of channel layer 315, and drain electrode 322 may be connected to the other side of channel layer 315. Source electrode 321 and drain electrode 322 may be formed of conductive materials, such as metals, metal compounds, and / or conductive carbon-based materials (such as conductive polymers and / or π-bonded carbon materials (such as graphene and / or armchair-type carbon nanotubes)).

[0074] Since the seed layer 130, the dielectric layer 140, and the gate electrode 150 are sequentially deposited on the channel layer 315 as described above, their detailed description is omitted. Alternatively, although not in Figure 5 As shown, however, an amorphous dielectric layer may be further provided between the channel layer 315 and the seed layer 130, or a crystalline dielectric layer having a different crystal orientation than the seed layer 130 may be further provided.

[0075] Figure 6 This is a cross-sectional view of an electronic device 400 according to another embodiment. Figure 6 The electronic device 400 shown can be, for example, a capacitor.

[0076] Reference Figure 6 The electronic device 400 may include a first electrode 410 and a second electrode 420 spaced apart from each other, a seed layer 430 provided between the first electrode 410 and the second electrode 420, and a dielectric layer 440 provided between the seed layer 430 and the second electrode 420. In this case, the dielectric layer 440 may include a ferroelectric material.

[0077] Each of the first electrode 410 and the second electrode 420 may include a conductive material, such as a metal. In this case, the electronic device 400 may be a capacitor having a metal-ferroelectric-metal (MFM) structure. Furthermore, the first electrode 410 may include a semiconductor, and the second electrode 420 may include a conductive metal. In this case, the electronic device 400 may be a capacitor having a metal-ferroelectric-semiconductor (MFS) structure.

[0078] A seed layer 430 is provided on the upper surface of the first electrode 410, and a dielectric layer 440 is provided on the upper surface of the seed layer 430. In this case, the seed layer 430 may have a crystal orientation 430a aligned in a certain direction, and the dielectric layer 440 may have a crystal orientation 440a aligned in the same direction as the crystal orientation of the seed layer 430. The first electrode 410 and the second electrode 420 may have crystal orientations different from the crystal orientations of the seed layer 430 and the dielectric layer 440.

[0079] The seed layer 430 may include grains (not shown) having a crystal orientation 430a aligned in a certain direction. The dielectric layer 440 may include grains (not shown) having a crystal orientation 440a aligned in the same direction as the crystal orientation 430a of the grains in the seed layer 430.

[0080] For example, the grains forming the seed layer 430 and the grains forming the dielectric layer 440 can both have <111> Crystal orientation. However, this is only an example; the grains forming the seed layer 430 and the grains forming the dielectric layer 440 may have other orientations besides crystal orientation. <111> Other crystal orientations besides the crystal orientation.

[0081] The seed layer 430 may include an insulating material, such as an oxide, nitride, chalcogenide, and / or a two-dimensional insulating material. However, this disclosure is not limited thereto. The seed layer 430 may have a thickness of, for example, from about 0.5 nm to 3 nm.

[0082] The dielectric layer 440 may comprise an insulating material, such as an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr. However, this is merely an example. Furthermore, the dielectric layer 440 may also comprise a dopant, if desired. In this case, the dopant may comprise, for example, at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf. The dopant and the oxide may comprise the same or different elements. The dielectric layer 440 may have a thickness, for example, from about 0.5 nm to 20 nm.

[0083] In the electronic device 400 according to this embodiment, since the ferroelectric material included in the dielectric layer 440 includes grains having an aligned crystal orientation 440a, the remanent polarization and capacitance of the electronic device 400 can be large compared to electronic devices according to related technologies.

[0084] Figure 10 The structure of trench capacitor type dynamic random access memory (DRAM) is shown.

[0085] Reference Figure 10 On the semiconductor substrate 720, a device isolation region can be defined by a field oxide film 721, and a gate electrode 723, a source region 722, and a drain region 722' can be formed in the device isolation region. An oxide film can be formed as an interlayer insulating film 724. Regions that do not form trenches can be covered by a trench buffer layer, and a portion of the source region 722 can be left open to form a contact portion.

[0086] The trench extends through the interlayer insulating film 724 into the semiconductor substrate 720, and a sidewall oxide film 725 can be formed on the inner surface of the trench. The sidewall oxide film 725 can compensate for damage in the semiconductor substrate caused by etching used to form the trench and can serve as a dielectric film between the semiconductor substrate 720 and the storage electrode 726. A portion of the sidewall of the source region 722 can be exposed by the trench.

[0087] A PN junction (not shown) can be formed in the sidewall portion of the source region by impurity implantation. A trench can be formed in the source region 722. The sidewalls of the trench can directly contact the source region 722, and the PN junction can be formed by additionally implanting impurities into the source region.

[0088] The storage electrode 726 can be formed on a portion of the interlayer insulating film 724, the exposed source region 722, and the surface of the sidewall oxide film 725 in the trench. The storage electrode 726 can be formed to contact the source region 722 which contacts the upper sidewall of the trench. Next, an insulating film 727, serving as a capacitor dielectric film, can be formed along the upper surface of the storage electrode 726, and a polysilicon layer serving as a plate electrode 728 can be formed thereon, thereby completing the trench capacitor type DRAM. For example, the insulating film 727 can be an embodiment that provides a seed layer and a dielectric layer between the first electrode and the second electrode, such that the storage electrode 726 is the first electrode and the plate electrode 728 is the second electrode.

[0089] Figure 7 This is a cross-sectional view of an electronic device 500 according to another embodiment. Except for the amorphous dielectric layer 560 provided between the first electrode 410 and the seed layer 430, Figure 7 The electronic device 500 shown is Figure 6 The electronic components are the same as those in 400. Figure 7 The electronic device 500 can be a capacitor with a metal-ferroelectric-insulator-metal (MFIM) structure or a capacitor with a metal-ferroelectric-insulator-semiconductor (MFIS) structure.

[0090] Reference Figure 7 An amorphous dielectric layer 560 may be provided between the first electrode 410 and the seed layer 430. In this case, although the amorphous dielectric layer 560 may include oxides of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr, this disclosure is not limited thereto. Alternatively, instead of the amorphous dielectric layer 560, a crystalline dielectric layer (not shown) having a crystal orientation different from that of the seed layer 430 may be provided between the first electrode 410 and the seed layer 430.

[0091] In the following description, refer to Figure 8A and Figure 8BThe performance of a general electronic device is compared with the performance of an electronic device according to the embodiment. Figure 8A and Figure 8B In this text, "A" represents a general electronic device, and "B" represents an electronic device according to the example embodiment. In this case, both the general electronic device and the electronic device according to the embodiment use a capacitor with an MFIS structure.

[0092] A typical electronic device has a structure in which silicon oxide, an HfZrO ferroelectric layer, and a Mo layer are sequentially deposited on a p-type silicon substrate. In this case, the HfZrO ferroelectric layer comprises grains with random crystal orientation and has a thickness of approximately 7 nm. An electronic device according to an example embodiment has a structure in which silicon oxide, an HfZrO seed layer, an HfZrO ferroelectric layer, and a Mo layer are sequentially deposited on a p-type silicon substrate. In this case, the HfZrO seed layer comprises grains with random crystal orientation and a thickness of approximately 7 nm. <111> The grains are oriented in a specific crystal direction and have a thickness of approximately 2 nm. The HfZrO ferroelectric layer includes grains with... <111> The grains are oriented in a specific crystal direction and have a thickness of approximately 5 nm.

[0093] Figure 8A This is a graph comparing the capacitance of a general electronic device with the capacitance of an electronic device according to an example embodiment. (Refer to...) Figure 8A As can be seen, in the electronic device according to the embodiment, the dielectric constant value k is increased compared to that of a general electronic device, and therefore the capacitance is increased.

[0094] Figure 8B This is a graph comparing the residual polarization of a general electronic device with that of an electronic device according to an example embodiment. (Refer to...) Figure 8B As can be seen, in the electronic device according to the embodiment, the residual polarization Pr is increased compared with that of a general electronic device, thus the polarization characteristics are improved.

[0095] Figures 9A to 9D This is a cross-sectional view used to describe a method of manufacturing an electronic device according to an example embodiment.

[0096] Reference Figure 9A A substrate 610 is prepared in which a channel layer 615, a source 621, and a drain 622 are provided. The source 621 and the drain 622 can be formed by implanting / doping impurities in different regions of the substrate 610, and the region of the substrate 610 between the source 621 and the drain 622 can be defined as the channel layer 615.

[0097] Substrate 610 may include, for example, Si, Ge, SiGe, and / or group III-V semiconductors. In this case, like substrate 610, channel layer 615 may include Si, Ge, SiGe, and / or group III-V semiconductors. The material of substrate 610 is not limited to those described above and can be varied. Furthermore, the formation timing of source 621 and drain 622 can be varied. For example, substrate 610 may be fabricated to include source 621 and drain 622, or source 621 and drain 622 may be formed at times as described later. Figure 9D The gate electrode 650 is then formed in the substrate 610.

[0098] alternative sites, and Figure 9A Unlike other materials, the channel layer 615 can be formed on the upper surface of the substrate 610 as a material layer separate from the substrate 610 (e.g., not part of the substrate 610). In this case, the material of the channel layer 615 can be configured in various ways. For example, the channel layer 615 can include at least one of oxide semiconductors, nitride semiconductors, oxide-oxygen nitride semiconductors, two-dimensional materials, quantum dots, and organic and / or carbon-based semiconductors. Oxide semiconductors can include, for example, InGaZnO, two-dimensional materials can include, for example, MoS2, TMD, and / or graphene, quantum dots can include colloidal quantum dots and / or nanocrystal structures, and organic and / or carbon-based semiconductors can include, for example, carbon nanotubes (CNTs) and / or other π-bonded molecules. However, this is merely an example, and this disclosure is not limited thereto.

[0099] Reference Figure 9B A seed layer 630 is formed on the upper surface of the channel layer 615 of the substrate 610. The seed layer 630 includes grains having an aligned crystal orientation 630a. Although the seed layer 630 may include, for example, oxides, nitrides, chalcogenides and / or two-dimensional insulating materials, this disclosure is not limited thereto.

[0100] The oxide may include, for example, an oxide of at least one of Y, Si, Al, Hf, Zr, La, Mo, W, Ru, and Nb. The oxide may also include a dopant. In this case, the dopant may include, for example, at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf. Nitrides may include, for example, InN. Chalcogenides may include, for example, MoTe, WTe, HfS, and / or ZrS. Two-dimensional insulating materials may include, for example, h-BN.

[0101] The seed layer 630 can be formed by depositing a first amorphous dielectric material layer (not shown) on the upper surface of the channel layer 615 of the substrate 610 and then crystallizing the deposited first amorphous dielectric material layer. The first amorphous dielectric material layer can be deposited by deposition methods such as CVD, ALD, and PVD. The seed layer 630 can be formed by crystallizing the first amorphous dielectric material layer via an annealing process. In the crystallization process of the first amorphous dielectric material layer, the seed layer 630 can be formed as grains having a crystal orientation 630a aligned in a certain direction grow. The seed layer 630 can include a dopant. The dopant can be implanted into the formed seed layer 630 and / or deposited during the formation of the first amorphous dielectric material layer. The dopant can include, for example, interstitial dopants between lattice vertices, substitutes in the lattice, and / or at the boundaries between grains.

[0102] The formation of the seed layer 630 can depend on the material of the seed layer 630, the type and concentration of the dopant, and / or the annealing temperature. The annealing temperature of the first amorphous dielectric material layer can be, for example, from about 300°C to about 1000°C, however, this disclosure is not limited thereto. The seed layer 630 can have a thickness of from about 0.5 nm to about 3.0 nm. However, this is only an exemplary embodiment, and this disclosure is not limited thereto.

[0103] Seed layer 630 may include, for example, having <111> Grains with specific crystal orientations. However, this is merely an example; the seed layer 630 may include grains with, but not limited to, specific orientations. <111> Grains with orientations other than the crystal orientation.

[0104] The seed layer 630 can be formed by a transfer method instead of the deposition method described above. In this case, the seed layer 630 can be formed by transferring a dielectric thin film comprising grains having crystal orientations aligned in a certain direction to the upper surface of the channel layer 615 of the substrate 610.

[0105] Alternatively, although not shown in the figures, an amorphous dielectric layer may be formed on the upper surface of the channel layer 615 of the substrate 610 before the seed layer 630 is formed, or a crystalline dielectric layer having a crystal orientation different from that of the seed layer 630 may be formed. For example, the amorphous dielectric layer or the crystalline dielectric layer may be formed on the upper surface of the channel layer 615 by deposition methods such as CVD, ALD, and PVD, or by transfer methods.

[0106] Reference Figure 9CA dielectric layer 640 comprising grains having an aligned crystal orientation 640a is formed on the upper surface of the seed layer 630. In this case, the dielectric layer 640 comprises grains having a crystal orientation 640a aligned in the same direction as the crystal orientation 630a of the seed layer 630. For example, when the grains forming the seed layer 630 have <111> When oriented, the grains forming the dielectric layer 640 can have the same crystal orientation as the seed layer 630. <111> Crystal orientation.

[0107] The dielectric layer 640 may include a ferroelectric material. Although the dielectric layer 640 may include an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd and Sr, this is only an example.

[0108] The dielectric layer 640 can be formed by depositing a second amorphous dielectric material layer (not shown) on the upper surface of the seed layer 630 and then crystallizing the second amorphous dielectric material layer. The second amorphous dielectric material layer can be deposited on the upper surface of the seed layer 630 by deposition methods such as CVD, ALD, and PVD. The second amorphous dielectric material layer can be crystallized by an annealing process to form the dielectric layer 640. In the crystallization process of the second amorphous dielectric material layer, the dielectric layer 640 can be formed as grains having a crystal orientation 640a aligned in the same direction as the crystal orientation 630a of the seed layer 630 grow.

[0109] Furthermore, the dielectric layer 640 may also include a dopant, as needed. In this case, the dopant may include at least one of, for example, Si, Al, Zr, Y, La, Gd, Sr, and Hf. When the dielectric layer 640 includes a dopant, the dopant may be doped at the same concentration throughout the layer and / or at different concentrations depending on the region. Different dopant materials may be doped according to the different regions of the dielectric layer 640. The dopant may be implanted into the formed dielectric layer 640 and / or deposited during the formation of the second amorphous dielectric material layer. The dopant may, for example, be included as an interstitial dopant between lattice vertices, as a substitute in the lattice, and / or at the boundaries between grains.

[0110] The formation of dielectric layer 640 from a second amorphous dielectric material layer can depend on the material of dielectric layer 640, the type and concentration of dopants, and / or the annealing temperature. Although the annealing temperature of the second amorphous dielectric material layer can, for example, be lower than the annealing temperature of the first amorphous dielectric material layer described above, this disclosure is not limited thereto. Dielectric layer 640 can have a thickness of about 0.5 nm to 20 nm. However, this is merely an example.

[0111] Reference Figure 9DWhen the gate electrode 650 is formed on the upper surface of the dielectric layer 640, the electronic device 600 according to the exemplary embodiment is completed. The gate electrode 650 can be formed by depositing a conductive material via, for example, CVD, PVD, and / or ALD. The deposited conductive material can then be annealed. The gate electrode 650 can also be formed by a transfer method.

[0112] In the above description, when annealing processes are performed separately, a seed layer 630, a dielectric layer 640, and a gate electrode 650 are formed. However, alternatively, after a first amorphous dielectric material layer and a second amorphous dielectric material layer are sequentially deposited on the upper surface of the channel layer 615 of the substrate 610, the seed layer 630 and the dielectric layer 640 are formed by the same annealing process. The annealing processes for forming the seed layer 630 and the dielectric layer 640 can be the same or different processes, and can be performed simultaneously or at different times. For example, the first annealing process for forming the seed layer 630 can be performed at a higher temperature than the second annealing process for forming the dielectric layer 640. Alternatively, one annealing process can be used to form both the seed layer 630 and the dielectric layer 640. Then, after depositing a conductive material on the upper surface of the dielectric layer 640, another annealing process can be used to form the gate electrode 650. Furthermore, after the first amorphous dielectric material layer, the second amorphous dielectric material layer, and the conductive material are sequentially deposited on the upper surface of the channel layer 615 of the substrate 610, the seed layer 630, the dielectric layer 640, and the gate electrode 650 can be formed by the same annealing process.

[0113] According to the above embodiments, since the dielectric layer is formed as a ferroelectric material, the subthreshold swing of the electronic device can be reduced. Furthermore, since the ferroelectric material included in the dielectric layer comprises grains with aligned crystal orientations, the remanent polarization can be increased, thereby improving the polarization characteristics of the ferroelectric thin film. Moreover, since the polarization direction is aligned, the depolarization field increases, and due to the increased negative capacitance effect, the subthreshold swing can be further reduced. Therefore, the performance of the electronic device can be further improved. Although embodiments have been described above, these are merely examples, and various modifications can be made by those skilled in the art.

[0114] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The descriptions of features and / or aspects within each embodiment should generally be considered applicable to other similar features and / or aspects in other embodiments. Although one and / or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0115] This application claims the benefit of Korean Patent Application No. 10-2019-0173466, filed on December 23, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An electronic device, comprising: Substrate; A seed layer on the substrate, the seed layer comprising grains having an aligned crystal orientation; A dielectric layer on the seed crystal layer, the dielectric layer comprising grains having a crystal orientation aligned in the same direction as the crystal orientation of the seed crystal layer; as well as Electrodes on the dielectric layer, The crystalline dielectric layer is provided between the seed layer and the substrate and has a crystal orientation different from the orientation of the seed layer.

2. The electronic device according to claim 1, further comprising: Source pole; Drain; as well as The channel layer is located on the upper surface of the substrate, or on the upper surface, between the source and the drain, and at a position corresponding to the electrode. The electrode mentioned therein is a gate electrode.

3. The electronic device according to claim 2, wherein the channel layer comprises at least one of Si, Ge, III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional semiconductor materials, quantum dots, and organic semiconductors.

4. The electronic device according to claim 1, wherein the seed layer comprises at least one selected from oxides, nitrides, chalcogenides, and two-dimensional insulating materials.

5. The electronic device according to claim 4, wherein the oxide comprises an oxide of at least one of Y, Si, Al, Hf, Zr, La, Mo, W, Ru and Nb.

6. The electronic device of claim 5, wherein the oxide further comprises a dopant.

7. The electronic device according to claim 1, wherein the seed layer has a thickness of 0.5 nm to 3 nm.

8. The electronic device according to claim 1, wherein the dielectric layer comprises a ferroelectric material.

9. The electronic device according to claim 1, wherein the dielectric layer comprises an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd and Sr.

10. The electronic device of claim 9, wherein the dielectric layer further comprises a dopant.

11. The electronic device according to claim 1, wherein the dielectric layer has a thickness of 0.5 nm to 20 nm.

12. The electronic device according to claim 1, wherein the crystal orientation of the grains of the seed layer and the crystal orientation of the grains of the dielectric layer have <111> orientation.

13. The electronic device according to claim 1, wherein: The electrode is the first electrode, and The substrate is the second electrode.

14. The electronic device of claim 13, wherein the electronic device is a capacitor.

15. The electronic device of claim 14, wherein the dielectric layer has residual polarization.

16. A method for manufacturing an electronic device, the method comprising: Prepare the substrate; A seed layer is formed on the substrate, the seed layer comprising grains having an aligned crystal orientation; A dielectric layer is formed on the seed crystal layer, the dielectric layer comprising grains having a crystal orientation aligned in the same direction as the crystal orientation of the seed crystal layer; as well as Electrodes are formed on the dielectric layer. The method further includes forming a crystalline dielectric layer located between the seed layer and the substrate and having a crystal orientation different from that of the seed layer.

17. The method of claim 16, wherein forming the seed layer comprises: An amorphous dielectric material layer is deposited on the substrate, and This causes the deposited amorphous dielectric material layer to crystallize.

18. The method of claim 16, wherein forming the seed layer comprises transferring grains having an aligned crystal orientation onto the substrate.

19. The method of claim 16, wherein forming the dielectric layer comprises: An amorphous dielectric material layer is deposited on the seed crystal layer, and The amorphous dielectric material layer is crystallized.

20. The method of claim 16, wherein the dielectric layer comprises a ferroelectric material.

21. The method of claim 16, wherein the dielectric layer comprises an oxide of at least one of Hf, Si, Al, Zr, Y, La, Gd, and Sr.

22. The method of claim 21, wherein the dielectric layer further comprises a dopant.

23. The method of claim 16, further comprising forming a trench layer on the substrate.

24. A storage device comprising: transistor; as well as The electronic device according to claim 14 is electrically connected to the source region of the transistor.

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