Deep trench isolation and substrate connection on soi

Abstract

An apparatus includes a first trench formed in a semiconductor layer. The first trench has a first width and a first depth. A second trench is formed in the semiconductor layer. The second trench has a second width and a second depth. The first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate. The buried dielectric layer contacts a first bottom surface of the first trench. An inner liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the inner liner dielectric. A second layer is formed on the first layer and extends to the substrate through an opening formed on the first bottom surface.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor-on-insulator (SOI) device, and more specifically, to a deep trench isolation and substrate interconnect on an SOI and a method of fabricating the same. Background Technology

[0002] Deep trench structures in SOI devices have been used to provide high-voltage isolation and for electrical contact with the SOI substrate. In some cases, the same trench has been used for both high-voltage isolation and substrate contact. Deep trenches rely on sidewall dielectrics to provide high-voltage isolation between adjacent circuit blocks.

[0003] Increasing the thickness of the dielectric will improve voltage isolation, but at the cost of narrower conductive plugs or wider trenches. Reducing the width of the plugs will unnecessarily increase the resistance of the substrate connection. Alternatively, increasing the width of the trenches will increase the die size area and the level of defects due to dislocation faults introduced during trench formation. Summary of the Invention

[0004] As should be understood, the disclosed embodiments include at least the following. In one embodiment, a device includes a first trench formed in a semiconductor layer, the first trench including a first width and a first depth. A second trench is formed in the semiconductor layer, the second trench including a second width and a second depth, wherein the first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate, and a buried oxide layer contacts a first bottom surface of the first trench. An inner liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the inner liner dielectric. A second layer is formed on the first layer and extends through an opening formed on the first bottom surface to the substrate.

[0005] Alternative embodiments of the device include one or any combination of the following features: The first depth of the first trench is equal to the second depth of the second trench, the liner dielectric is formed on a second bottom surface of the second trench and a second sidewall of the second trench, and the first layer is formed on the liner dielectric in the second trench. The second sidewall of the second trench contacts a shallow trench isolation disposed on a top semiconductor surface of the semiconductor layer. The first depth of the first trench is equal to the second depth of the second trench, the liner dielectric is formed on a second bottom surface of the second trench and a first portion of the second sidewall of the second trench, the first layer is formed on the liner dielectric, and the second layer is formed on a second portion of the second sidewall. The second layer contacts a side portion of the first layer. The second depth of the second trench is less than the first depth of the first trench, the second layer is formed on a second bottom surface of the second trench and a second sidewall of the second trench, wherein the second bottom surface is separated from the buried dielectric layer by the semiconductor layer. The second sidewall of the second trench is separated from the shallow trench isolation by the semiconductor layer.

[0006] In another embodiment, a method of fabricating deep trench isolation and substrate connection on a semiconductor-on-insulator includes forming a first trench in a semiconductor layer, the first trench including a first width and a first depth, wherein a shallow trench isolation is formed on a top semiconductor surface of the semiconductor layer, a buried oxide layer is formed between a bottom semiconductor surface of the semiconductor layer and a substrate, and the buried dielectric layer contacts a first bottom surface of the first trench. A second trench is formed in the semiconductor layer, the second trench including a second width and a second depth, wherein the first width is wider than the second width. An inner liner dielectric is deposited in the first trench and the second trench. A first layer is deposited on the inner liner dielectric, wherein the first layer fills the second trench. A portion of the inner liner dielectric and the buried dielectric layer is etched from the first bottom surface of the first trench to form an opening on the first bottom surface. A second layer is deposited on the first layer to form contact with the substrate through the opening.

[0007] Alternative embodiments of the method for fabricating deep trench isolation and substrate interconnection on a semiconductor-on-insulator include one or any combination of the following features: Anisotropically etching the first layer to expose a top liner surface of the liner dielectric on a first bottom surface of the first trench, wherein the liner dielectric on a second bottom surface of the second trench is not etched. Simultaneously etching the first trench and the second trench. Removing the surface layer of the second layer to expose the first layer in the first trench and the second trench. The first depth of the first trench is equal to the second depth of the second trench. The first trench and the second trench are each formed by etching through the shallow trench isolation. Patterning a mask to expose the second trench, wherein the first depth of the first trench is equal to the second depth of the second trench; etching the first layer such that the first layer in the second trench is recessed to the depth of a buried conductive layer formed in the semiconductor layer; removing the mask; and depositing a third layer in the second trench to form a conductive contact with the buried conductive layer. A patterned mask is used to expose the second trench, wherein the second depth of the second trench is less than the first depth of the first trench, and the second bottom surface of the second trench is separated from the buried dielectric layer by the semiconductor layer; the first layer is etched to remove the first layer in the second trench; the mask is removed; and a third layer is deposited in the second trench to form a conductive contact with the buried conductive layer formed in the semiconductor layer. The second layer and the third layer are each polycrystalline silicon layers doped with conductive dopants.

[0008] In another embodiment, a method of fabricating deep trench isolation and substrate connection on a semiconductor-on-insulator includes forming a first trench in a semiconductor layer, the first trench including a first width and a first depth, a buried dielectric layer formed between a bottom semiconductor surface of the semiconductor layer and a substrate, and the buried dielectric layer contacting a first bottom surface of the first trench. A second trench is formed in the semiconductor layer, the second trench including a second width and a second depth, wherein the first width is wider than the second width and the second depth is less than the first depth. An inner liner dielectric is deposited in the first trench and the second trench. An undoped first layer is deposited on the inner liner dielectric, wherein the undoped first layer fills the second trench. A portion of the inner liner dielectric and the buried dielectric layer is etched from the first bottom surface of the first trench to form an opening on the first bottom surface. A second layer is deposited on the undoped first layer to form contact with the substrate through the opening.

[0009] Alternative embodiments of the method for fabricating deep trench isolation and substrate interconnection on a semiconductor-on-insulator include one or any combination of the following features: Patterning a mask to expose the second trench; Etching the undoped first layer to remove the undoped first layer in the second trench; Removing the mask; Depositing a third layer in the second trench to form a conductive contact with a buried layer formed in the semiconductor layer; Shallow trench isolation formed on the top semiconductor surface of the semiconductor layer, wherein the first trench is formed by etching through the shallow trench isolation, and the second trench is formed by etching through a silicon region excluding the shallow trench isolation; The second and third layers are each polycrystalline silicon layers doped with conductive dopants. Attached Figure Description

[0010] The invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity, and these elements are not necessarily drawn to scale.

[0011] Figures 1 to 7 This is a cross-sectional view of the sequential manufacturing stages of an SOI device including deep trench isolation and substrate interconnection according to a first exemplary embodiment of the present disclosure.

[0012] Figures 8 to 13 This is a cross-sectional view of the sequential manufacturing stages of an SOI device including deep trench isolation and substrate interconnection according to a second exemplary embodiment of the present disclosure.

[0013] Figures 14 to 20 This is a cross-sectional view of the sequential manufacturing stages of an SOI device including deep trench isolation and substrate interconnection according to a third exemplary embodiment of the present disclosure.

[0014] Figure 21 This is a flowchart representation of a method for fabricating deep trench isolation and substrate interconnection on SOI according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0015] The embodiments described herein achieve independently optimized low-resistance contact with the substrate or other buried layer while simultaneously achieving high-voltage isolation. Forming two independent trenches with different widths minimizes the impact on manufacturing process complexity. Wide trenches are formed to allow for low-resistance contact, while narrow trenches are formed for high-voltage isolation, and in some embodiments, for contact with the buried layer or trap.

[0016] First embodiment:

[0017] Figure 1Example embodiment 10 illustrates the initial manufacturing steps with two additional trenches of different widths. In one embodiment, a first (wide) trench 12 is formed in an epitaxial layer 14. In other example embodiments, the epitaxial layer 14 is a semiconductor layer formed without epitaxial growth. The first trench 12 provides contact with the SOI substrate while providing high-voltage isolation. It should be understood that throughout this disclosure, references to SOI can be replaced with silicon on insulator to form alternative embodiments of those embodiments including semiconductor on insulator. A second (narrow) trench 16 is formed in the epitaxial layer 14. The second trench 16 achieves high-voltage isolation in some embodiments and contact with a buried layer or well in other embodiments. In some embodiments, the first trench 12 and the second trench 16 are formed simultaneously, while in other embodiments, the two trenches are formed sequentially. In embodiments of SOI that do not require substrate contact, only the second trench 16 is formed.

[0018] The first trench 12 has a first width 22, a first depth 24, a first bottom surface 26, and a first sidewall 28. The second trench 16 has a second width 32, a second depth 34, a second bottom surface 36, and a second sidewall 38. A shallow trench isolation (STI) layer 40 is formed on a top epitaxial surface 42. A nitride layer 44 is formed on top of the STI 40. A high-density plasma (HDP) hard mask is formed on top of the nitride layer 44. The HDP hard mask is a silicon oxide film formed in a high-density plasma. It should be understood that references to HDP throughout this disclosure can be replaced with silicon oxide (or silicon dioxide) films formed by chemical vapor deposition (CVD) to form alternative embodiments. The nitride layer 44 and the HDP hard mask are used to facilitate the formation of trenches 12 and 16.

[0019] A buried oxide (BOX) layer 50 is located between the bottom epitaxial surface 52 and the substrate 54. In Example Embodiment 10, the first trench 12 and the second trench 16 are each formed by timed etching such that the first bottom surface 26 of the first trench 12 and the second bottom surface 36 of the second trench 16 both contact the BOX layer 50. Therefore, within manufacturing tolerances, the first depth 24 is equal to the second depth 34. In the various embodiments described herein, for ease of illustration, the epitaxial layer 14 is shown above the BOX layer 50. More specifically, in the various embodiments, the silicon closest to the BOX layer 50 is formed from a pulled crystal, and said silicon is filled with epitaxial silicon.

[0020] Figure 2 Showing has Figure 1 Example embodiment 60 of subsequent manufacturing steps, wherein an inner liner oxide 62 is formed in both the first trench 12 and the second trench 16. The inner liner oxide 62 provides electrical isolation for trenches 12 and 16. Subsequently, as Figure 3As shown in Example 64, an undoped polysilicon film (or layer) 66 is deposited. The thickness of the polysilicon film is chosen such that the second narrow trench 16 is completely filled, while a liner is provided only over the first wider trench 12. It should be understood that throughout this disclosure, references to undoped polysilicon can be replaced with undoped amorphous silicon, lightly doped silicon, or lightly doped amorphous silicon to form alternative embodiments. In Example 64, the polysilicon layer 66 is undoped. In another embodiment, the polysilicon layer 66 is doped.

[0021] Turn now Figure 4 Example embodiment 70 illustrates an undoped polysilicon layer 66 etched from a wafer surface using an anisotropic reactive ion etching (RIE) process. Figure 4 As shown, an undoped polysilicon layer 66 is also etched from the substrate of the first trench 12 at the first bottom surface 26. The undoped polysilicon layer 66 is partially recessed at the top of the second trench 16. Figure 5 Example embodiment 80 is shown, wherein an opening 82 is formed between the first trench 12 and the substrate 54. The opening 82 is formed by partially etching the inner oxide 62 and the BOX 50 from the first bottom surface 26 of the first trench 12 using anisotropic RIE etching. The undoped polysilicon layer 66 in the second trench 16 is not etched by this step. Figure 6 Example embodiment 84 is shown, in which a doped polysilicon film 86 is deposited to fill the first trench 12, thereby forming a conductive contact with the substrate 54 through an opening 82. Figure 7 Example embodiment 88 illustrates the removal of a surface layer, an inner oxide liner 62, and an HDP hard mask 46 of doped polysilicon 86, the removal stopping at a nitride layer 44 that acts as a CMP polishing stop layer. In one embodiment, chemical mechanical polishing (CMP) is used to remove the surface layer. In another embodiment, plasma etching is used to remove the surface layer. In one embodiment, a subsequent step is performed on example embodiment 88 to remove the nitride layer 44 using etching, thereby retaining a low-resistance substrate contact in a first trench 12 and a high-voltage insulator in a second trench 16. Advantageously, at least two trenches of different widths are formed using the same mask set, one trench contacting the layer beneath the BOX layer 50, while the other formed trench does not penetrate the BOX layer 50. In some example embodiments, various trenches of different widths are etched simultaneously.

[0022] Second embodiment:

[0023] Traditionally, forming a contact with a buried conductive layer in a semiconductor device requires high-energy implantation. High-energy implantation necessitates a limited dose level of the implanted material, thereby unnecessarily increasing the contact resistance with the buried conductive layer. In the following embodiments, a high-energy implantation resist mask is replaced with an etch mask to establish a connection between low-resistivity doped polysilicon and the buried layer or well. The advantages of low-resistivity substrate contact and high-voltage isolation are maintained. It should be understood that in other embodiments, one or more of the advantages of low-resistivity substrate connection, high-voltage isolation, and buried layer (or well) connection are achieved. In some embodiments, the width of the trench used to contact the buried layer (or well) differs from the width of the first trench 12 or the second trench 16.

[0024] In some embodiments, the second trench 16 is formed by etching through the STI layer 40. In other embodiments, the second trench 16 is formed by etching only through the silicon (or epitaxial) layer. However, when the trench is etched only through the silicon, the second trench 16 may not be etched down to the BOX layer 50, depending on the width of the second trench 16.

[0025] Figure 8 Example embodiment 100 illustrates the use of... Figure 6 Modifications to the subsequent process of Example 84, and Figures 1 to 5 The aforementioned steps are shown in the diagram. Specifically, the surface layer of polysilicon 86 is removed by CMP or RIE etching, while the inner oxide 62 and HDP hard mask 46 are retained on the nitride layer 44. Figure 8 The image shows the contact between the buried conductive layer 102 and the sidewall of the second trench 16. This is to form... Figure 8 Example 100, modified Figures 1 to 6 The processing steps shown include burying a conductive layer 102. In some embodiments, the buried conductive layer 102 contacts one or more sidewall surfaces of the second trench 16, surrounds the second trench 16, or is replaced by a trap.

[0026] Figure 9 Example embodiment 104 is shown, in which an additional layer of doped polysilicon is added to an existing polysilicon layer 86. In another embodiment, Figure 6 The doped polycrystalline silicon layer 86 becomes thinner and skips Figure 7 The process steps are shown in the figure. Then, a second HDP hard mask 106 is added to the polysilicon layer 86 and the second HDP hard mask 106 is opened over the second trench 16 using a patterned resist layer (not shown). Figure 10 Example embodiment 110 is shown, in which RIE etching is used to etch through the doped polysilicon 86 and to recess the undoped polysilicon layer 66 within the second trench 16 to a depth at or below the buried conductive layer 102. Figure 11Example embodiment 112 is shown, wherein isotropic etching is used to remove the liner oxide in the portion of the second trench 16 above the remaining polysilicon 66. The resulting structure of example embodiment 112 includes a first portion 114 of the second sidewall 38 covered by the liner oxide 62, and a second portion 116 of the second sidewall 38.

[0027] Figure 12 Example embodiment 120 is shown, in which a doped polysilicon layer 122 is deposited over a doped polysilicon layer 86 to fill the second trench 16 and contact the buried conductive layer 102. In some embodiments, the doped polysilicon layers 86 and 122 have the same dopant type and dopant content. In another embodiment, the doped polysilicon layer 122 has different dopant characteristics compared to the doped polysilicon layer 86 to design a specific contact resistance with the buried conductive layer 102. Figure 13 Example embodiment 124 is shown, in which the surface layers, inner oxide 62, and HDP hard mask 46 of doped polysilicon 86 and 122 are removed by CMP or plasma etching. In one embodiment, the side portion 126 of the undoped polysilicon layer 66 contacts the doped polysilicon layer 122. Figure 13 Example embodiment 124 achieves low-resistance contact with the substrate 54 in the first trench and low-resistance (or designed resistance) contact with the buried conductive layer 102 in the second trench 16.

[0028] In one embodiment, a subsequent step is performed on Example 88 to remove the nitride layer 44 by etching, thereby retaining a low-resistance substrate contact in the first trench 12 and a contact with the buried conductive layer 102 in the second trench 16.

[0029] Third embodiment:

[0030] Similar to Figures 8 to 13 The second and third embodiments described herein enable deeper contact to the second trench 16 (e.g., closer to the bottom of the trench). In some embodiments, lower resistance contact with the buried conductive layer 102 is achieved due to the increased contact area between the doped polysilicon 122 and the buried conductive layer 102. It should be understood that in other embodiments, one or more of the advantages of low-resistance substrate connection, high-voltage isolation, and buried layer (or well) connection are achieved. In some embodiments, the width of the trench for contacting the buried layer (or well) is different from the width of the first trench 12 or the second trench 16.

[0031] Figure 14 Example 130 and Figure 1The difference in Example Embodiment 10 is that the STI layer 132 does not contact the second trench 16. Example Embodiment 130 also includes a buried conductive layer 102 and a second trench 16, which is shallower than the first trench 12. A second width 32 of the second trench 16 is chosen to ensure, using plasma etching hysteresis, that the second trench 16 is not etched down to the BOX layer 50. Etching the second trench 16 through silicon rather than through the STI 132 reduces the etch depth of the second trench 16, thus making the second depth 34 of the second trench 16 less than the first depth 24 of the first trench 12. The following is as follows: Figures 2 to 6 A similar process flow is shown.

[0032] Figure 15 Showing something similar Figure 6 Example 140 of Example 84. In Example 140, the thickness of the doped polysilicon layer 86 is sufficient to seal the top of the first trench 12. Figure 16 Example embodiment 142 is shown, in which a second HDP hard mask 46 and a patterned resist layer 144 are deposited over a doped polysilicon layer 86. The patterning of the resist layer 144 is used to open the second HDP hard mask 46 over a second trench 16. Figure 17 Example embodiment 150 is shown, in which the resist layer 144 is removed, and then the doped polysilicon layer 86 is opened over the second trench 16 using plasma etching, and all undoped polysilicon 66 is removed from the second trench 16. Figure 18 Example embodiment 152 is shown, in which wet etching is used to remove the liner oxide 62 in the second HDP hard mask 106 and the second trench 16.

[0033] Figure 19 Example embodiment 160 is shown, in which a doped polysilicon layer 122 is deposited over a doped polysilicon layer 86 to fill a second trench 16 and contact a buried conductive layer 102 (or well). In some embodiments, the doped polysilicon layers 86 and 122 have the same dopant type and dopant content. In another embodiment, the doped polysilicon layer 122 has different dopant properties compared to the doped polysilicon layer 86 to design a specific contact resistance with the buried conductive layer 102. Figure 20 Example embodiment 162 is shown, in which the surface layers, inner oxide 62, and HDP hard mask 46 of doped polysilicon 86 and 122 are removed by CMP, RIE, or a combination of CMP and RIE. Figure 20Example embodiment 162 achieves low-resistance contact with the substrate 54 in the first trench and low-resistance (or designed resistance) contact with the buried conductive layer 102 in the second trench 16. Advantageously, trenches of different depths are formed with the same mask. In some example embodiments, the openings are formed through the BOX layer 50 using the same mask set as other openings that do not penetrate the BOX layer 50. In some example embodiments, various trenches with different widths and / or depths are etched simultaneously.

[0034] Figure 21 ,refer to Figures 1 to 7 This illustrates a method 170 for fabricating deep trench isolation and substrate interconnection on SOI according to an exemplary embodiment of the present disclosure. At 172, a first trench 12 is formed in an epitaxial layer 14. At 174, a second trench 16 is formed in the epitaxial layer 14. The first trench 12 is wider than the second trench 16. At 176, an inner liner oxide 62 is deposited in each trench. At 178, a first polysilicon layer 66 is deposited on the inner liner oxide 62. The second trench 16 is filled with the first polysilicon layer 66. At 180, a portion of the inner liner oxide 62 and BOX 50 in the first trench 12 is etched to form an opening 82 to a substrate 54. At 182, a second polysilicon layer 86 is deposited on the first polysilicon layer 66 to form a contact with the substrate 54.

[0035] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of the invention. It is not intended that any advantage, benefit, or solution to the problem described herein with reference to specific embodiments be construed as a critical, necessary, or essential feature or element of any or all claims.

[0036] Unless otherwise stated, terms such as “first” and “second” are used to distinguish, arbitrarily, the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority of such elements.

Claims

1. A semiconductor-on-insulator (SOI) device, characterized in that, include: A first trench, the first trench being formed in a semiconductor layer, the first trench including a first width and a first depth; A second trench is formed in the semiconductor layer, the second trench having a second width and a second depth, wherein the first width is wider than the second width; A buried dielectric layer is disposed between the bottom semiconductor surface of the semiconductor layer and the substrate, and the buried dielectric layer contacts the first bottom surface of the first trench; The inner dielectric liner is formed on the first bottom surface and the first sidewall of the first trench, and on the second bottom surface and the first portion of the second sidewall of the second trench; A first layer is formed on the inner liner dielectric; A second layer is formed on the first layer and extends into the substrate through an opening formed on the first bottom surface; as well as A third layer is formed on the second portion of the sidewall, filling the second trench to the second portion of the second sidewall, and the third layer contacts the buried conductive layer that contacts the second portion of the second sidewall.

2. The SOI device according to claim 1, characterized in that, The first depth of the first trench is equal to the second depth of the second trench.

3. The SOI device according to claim 1, characterized in that, The third layer has the same dopant type and dopant content as the second layer.

4. The SOI device according to claim 1, characterized in that, The second depth of the second trench is less than the first depth of the first trench, wherein the second bottom surface is separated from the buried dielectric layer by the semiconductor layer.

5. A method for fabricating deep trench isolation and substrate interconnection on a semiconductor-on-insulator, characterized in that, include: A first trench is formed in a semiconductor layer, the first trench having a first width and a first depth, a buried dielectric layer is formed between the bottom semiconductor surface of the semiconductor layer and the substrate, and the buried dielectric layer contacts the first bottom surface of the first trench; A second trench is formed in the semiconductor layer, the second trench having a second width and a second depth, wherein the first width is wider than the second width; Deposit an inner lining dielectric in the first trench and the second trench; A first layer is deposited on the inner liner dielectric, wherein the first layer fills the second trench; Etch a portion of the inner liner dielectric and the buried dielectric layer from the first bottom surface of the first trench to form an opening on the first bottom surface; A second layer is deposited on the first layer to form contact with the substrate through the opening; as well as Patterned mask to expose the second trench, The first layer and the inner liner dielectric in the second trench are etched to recess the first layer and the inner liner dielectric in the second trench to the depth of the buried conductive layer formed in the semiconductor layer. Remove the mask, and A third layer is deposited in the second trench to form a conductive contact with the buried conductive layer.

6. The method according to claim 5, characterized in that, The additional step includes anisotropically etching the first layer to expose the top liner surface of the liner dielectric on the first bottom surface of the first trench, wherein the liner dielectric on the second bottom surface of the second trench is not etched.

7. The method according to claim 5, characterized in that: The first depth of the first trench is equal to the second depth of the second trench.

8. The method according to claim 5, characterized in that: The second depth of the second trench is less than the first depth of the first trench, and the second bottom surface of the second trench is separated from the buried dielectric layer by the semiconductor layer.

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