Image sensor, semiconductor device and method for forming the same

Abstract

The present invention discloses a complementary metal oxide semiconductor image sensor with a global shutter and a method for manufacturing a complementary metal oxide semiconductor image sensor. In one embodiment, a semiconductor device includes: a light sensing region; a charge storage region; a light shielding structure; and at least one through-hole contact; wherein the charge storage region is spatially configured to be adjacent to the light sensing region in a lateral direction, wherein the light shielding structure is configured to be above the charge storage region in a vertical direction to prevent incident light from leaking from the light sensing region to the signal processing region, wherein the light shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light shielding structure is formed synchronously with the at least one through-hole contact.

Description

Technical Field

[0001] Embodiments of the present invention relate to image sensors, semiconductor devices, and methods of forming the same. Background Art

[0002] Global shutter (GS) complementary metal oxide semiconductor (CMOS) image sensors have been widely used in various applications due to numerous advantages, including synchronized pixel exposure and readout functions that enable higher quality imaging, especially at high speed, high frame rate, and high resolution. One of the implementations of GS CMOS image sensors is to use a memory-in-pixel scheme, in which each pixel of the GS CMOS image sensor (in addition to the photodiode and readout circuit) contains an additional memory node for temporarily storing the photogenerated charge generated by the photodiode. Using this scheme, all pixels in the CMOS image sensor begin to be exposed at the same time. At the end of exposure, the photogenerated charge is globally transferred from the photodiode to the corresponding memory node and read out from the corresponding memory node by conventional row-by-row scanning. The pixel-level memory node receives the photogenerated charge from the corresponding photodiode and allows the photogenerated charge to accumulate, thereby eliminating the need for a rolling shutter pulse.

[0003] Parasitic light or light leakage to the memory nodes or bulk substrate caused by mechanisms such as diffraction and scattering can also generate photogenerated charge, which then contaminates the stored charge in the memory nodes and produces artifacts. For high image quality, it is necessary to minimize the contamination of the photogenerated charge from the photodiode and stored in the memory nodes by parasitic light before readout. Current technology uses metal light shielding designed for memory nodes, which provides limited improvement and may cause plasma damage to the memory nodes during the manufacturing process. Therefore, it is necessary to develop a method to reduce parasitic light to the memory nodes in GS CMOS image sensors. Summary of the invention

[0004] In one embodiment, a semiconductor device includes: a light sensing region; a signal processing region; and a light shielding structure, wherein the signal processing region is spatially configured to be adjacent to the light sensing region in a lateral direction, wherein the light shielding structure is configured to be above the signal processing region in a vertical direction so as to prevent incident light from leaking from the light sensing region to the signal processing region, and wherein the light shielding structure is configured in an interlayer dielectric (ILD) layer and is formed synchronously with a plurality of through-hole contacts.

[0005] In another embodiment, a complementary metal oxide semiconductor (CMOS) image sensor includes a plurality of pixels configured in a pixel array, wherein each of the plurality of pixels includes a light sensing region and a signal processing region, wherein the signal processing region is spatially configured to be adjacent to the light sensing region in a lateral direction, wherein the signal processing region is configured to be below a light shielding structure in a vertical direction so as to prevent incident light from leaking from the light sensing region to the signal processing region, wherein the light shielding structure is configured in an interlayer dielectric (ILD) layer and is formed synchronously with a plurality of through-hole contacts.

[0006] In another embodiment, a method for forming a semiconductor device includes: depositing an interlayer dielectric (ILD) layer on a substrate, wherein the substrate includes a plurality of pixels configured in a pixel array, and wherein each of the plurality of pixels includes a light sensing region and a signal processing region; patterning the ILD layer to synchronously form a first plurality of fully etched through-holes and a first plurality of shallow etched regions; and depositing a metal layer on the ILD layer to synchronously form a plurality of through-hole contacts of a plurality of light shielding structures in each of the plurality of pixels in the first plurality of fully etched through-holes and the first plurality of shallow etched regions, wherein each of the plurality of light shielding structures is configured to be vertically aligned with the signal processing region in the pixel so as to prevent incident light from leaking from the light sensing region to the signal processing region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the size and geometry of the various features may be arbitrarily increased or reduced for clarity of illustration.

[0008] Figure 1 An exemplary block diagram of a global shutter (GS) complementary metal oxide semiconductor (CMOS) image sensor (CIS) according to some embodiments of the present disclosure is shown.

[0009] Figure 2A and Figure 2B An exemplary circuit diagram of a pixel array including a plurality of pixels according to some embodiments of the present disclosure is shown.

[0010] Figure 3A An exemplary top view of a pixel in a pixel array in a global shutter complementary metal oxide semiconductor (CMOS) image sensor (CIS) according to some embodiments of the present disclosure is shown.

[0011] Figure 3BAn exemplary cross-sectional view of a pixel in a pixel array in a global shutter complementary metal oxide semiconductor (CMOS) image sensor (CIS) according to some embodiments of the present disclosure is shown.

[0012] Figure 4 A flow chart illustrating an exemplary method for forming a metal light shield over a memory node of a pixel in a global shutter complementary metal oxide semiconductor (CMOS) image sensor (CIS), according to some embodiments of the present disclosure.

[0013] Figures 5A to 5G A cross-sectional view of a pixel in a global shutter complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a metal light shield over a memory node of the pixel during various manufacturing stages according to some embodiments of the present disclosure is shown.

[0014] Fig. 6A An exemplary cross-sectional view illustrating a portion of a pixel in a pixel array of a CIS according to some embodiments of the present disclosure.

[0015] FIG. 6B to FIG. 6C The method for patterning according to some embodiments of the present disclosure is shown Fig. 6A An exemplary top view of a portion of a photomask showing a light shielding structure in an interlayer dielectric (ILD) layer is shown in FIG.

[0016] Fig. 7A An exemplary cross-sectional view illustrating a portion of a pixel in a pixel array of a CIS according to some embodiments of the present disclosure.

[0017] Figure 7B The method for patterning according to some embodiments of the present disclosure is shown Fig. 7A An exemplary top view of a portion of a photomask showing a light shielding structure in an inter-layer dielectric (ILD) layer is shown in FIG.

[0018] Fig. 8A An exemplary cross-sectional view illustrating a portion of a pixel in a pixel array of a CIS according to some embodiments of the present disclosure.

[0019] Figure 8B The method for patterning according to some embodiments of the present disclosure is shown Fig. 8A An exemplary top view of a portion of a photomask showing a light shielding structure in an inter-layer dielectric (ILD) layer is shown in FIG.

[0020] Fig. 9 An exemplary cross-sectional view illustrating a portion of a pixel in a pixel array of a CIS according to some embodiments of the present disclosure.

[0021] Description of Figure Numbers

[0022] 100: complementary metal oxide semiconductor image sensor;

[0023] 102, 200: pixel array;

[0024] 104: vertical shift register;

[0025] 106: horizontal shift register;

[0026] 108: Noise canceller;

[0027] 110: timing generator;

[0028] 112: Automatic gain control logic;

[0029] 114: digital / analog converter;

[0030] 116: Automatic gain control;

[0031] 118: analog / digital converter;

[0032] 120: voltage regulator;

[0033] 201-1, 201-2, 201-3, 201-4, 201-5, 201-6, 201-7, 201-8, 201-9, 210: active pixels;

[0034] 203, 203-1, 203-2, 203-3: positive power supply voltage power;

[0035] 205, 205-1, 205-2, 205-3: zero voltage reference;

[0036] 207, 207-1, 207-2, 207-3: readout lines;

[0037] 209-1, 209-2, 209-3: voltage control lines;

[0038] 212: Photodiode;

[0039] 214-1: transistor M1;

[0040] 214-2: transistor M2;

[0041] 214-3: transistor M3;

[0042] 214-4: transistor M4;

[0043] 214-5: transistor M5;

[0044] 214-6: transistor M6;

[0045] 216: Capacitor;

[0046] 218: node;

[0047] 220, 220-1, 220-2, 220-3: G_RST;

[0048] 222, 222-1, 222-2, 222-3: TX;

[0049] 226, 226-1, 226-2, 226-3: RST;

[0050] 228, 228-1, 228-2, 228-3: OP;

[0051] 230, 230-1, 230-2, 230-3: R_SEL;

[0052] 301: pixel boundary;

[0053] 302: active area;

[0054] 304: insulation area;

[0055] 306, 504-1: light sensing area;

[0056] 308, 504-2: charge storage area;

[0057] 310-1, 508: transfer gate;

[0058] 310-2, 606: storage node;

[0059] 312, 526: through-hole contacts;

[0060] 314: ground contact;

[0061] 316, 316-1, 316-2: functional gate;

[0062] 318: contact point;

[0063] 322, 502: substrate;

[0064] 324: deep n-type implant region;

[0065] 326, 510: interlayer dielectric layer;

[0066] 336: light shielding structure;

[0067] 400: Methods;

[0068] 402, 404, 406, 408, 410: Operation;

[0069] 300, 500, 700, 800: pixels;

[0070] 504: conductive area;

[0071] 506: interface layer;

[0072] 511, 602, 702, 802, 904: thickness;

[0073] 512: photoresist layer;

[0074] 514: pattern array;

[0075] 515, 610, 710, 810: photomask;

[0076] 516: Opening;

[0077] 517, 518: shallow etching area;

[0078] 519: perforated opening;

[0079] 520: Perforation;

[0080] 522: light shielding structure;

[0081] 524: wrinkles;

[0082] 612, 712, 722, 812, 822, 832: aperture;

[0083] 704, 806: height;

[0084] 714, 724, 814, 824, 834: critical dimensions;

[0085] 716, 726, 816, 826, 836: pitch size;

[0086] 804: step height;

[0087] 902: bowl-shaped bottom surface;

[0088] a, b, c: rows;

[0089] A, B, C: columns;

[0090] A-A': section. DETAILED DESCRIPTION

[0091] The following disclosure describes various exemplary embodiments for implementing the different features of the subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these components and arrangements are only examples and are not intended to be limiting. For example, it should be understood that when an element is referred to as being "connected to" another element or "coupled to" another element, it may be directly connected to another element or coupled to another element, or there may be one or more intervening elements.

[0092] The present disclosure presents various embodiments of a metal light shield for a signal processing area of ​​a pixel in a global shutter complementary metal oxide semiconductor (CMOS) image sensor to reduce light leakage to the processing area in order to remove artifacts and improve the signal-to-noise ratio.

[0093] Figure 1 An exemplary block diagram of a complementary metal oxide semiconductor (CMOS) image sensor (CIS) 100 is shown according to some embodiments of the present disclosure. It should be noted that CIS 100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional functional blocks may be provided in Figure 1 The CIS100 or coupled to Figure 1 The CIS 100 is described below, and some other functional blocks may only be briefly described herein.

[0094] exist Figure 1 In the illustrated embodiment of the present invention, CIS 100 includes a pixel array 102, a vertical shift register (VSR) 104, a horizontal shift register (HSR) 106, a noise canceller 108, a timing generator 110, an automatic gain control (AGC) logic 112, a digital-to-analog (D / A) converter 114, an AGC 116, an analog-to-digital (A / D) converter 118, and a voltage regulator 120. Pixel array 102 includes a plurality of active pixels arranged in a column-row configuration, such as Figure 2A and Figure 2B 100 is further discussed in detail in . In some embodiments, CIS 100 is a CIS with a global shutter. Specifically, each of the plurality of active pixels in pixel array 102 includes a CMOS photodiode, a memory node, and a plurality of transistors. In some embodiments, pixel array 102 may further include a plurality of dummy pixels arranged at the boundaries of the active pixels, the plurality of dummy pixels acting as optical dummy pieces to ensure that the active pixels at the boundaries have the same performance as the remaining active pixels.

[0095] In some embodiments, the memory node in each of the plurality of active pixels comprises a floating diffusion capacitor. In some other embodiments, the memory node further comprises a diode. In some embodiments, the plurality of transistors in each of the plurality of active pixels are used to at least one of: transfer photogenerated charge to a memory node of a corresponding CMOS photodiode; reset the photodiode for receiving a new exposure; reset the memory node of the corresponding CMOS photodiode for receiving photogenerated charge from a new exposure; and enable the active pixel for signal output.

[0096] In some embodiments, the vertical shift register (VSR) 104 is configured to perform at least one of the following functions, including: receiving a row address of the pixel array 102 from the timing generator 110; and driving a control line of the pixel array 102. In some embodiments, the horizontal shift register (HSR) 106 is used to perform the following: read out the output signal column by column. The VSR 104 and the HSR 106 are each coupled to the pixel array 102. In the illustrated embodiment, the HSR 106 is coupled to the pixel array 102 through the noise canceller 108, wherein the noise canceller 108 is a circuit used to remove noise from the output signal.

[0097] In some embodiments, the timing generator 110 generates a clock signal used to synchronize the output signal from the pixel array 102. An automatic gain control (AGC) 116 is a system used to tune the amplitude of the output signal. In the illustrated embodiment, the AGC 116 is coupled to an AGC logic 112, which provides control of the AGC 116. In some embodiments, the AGC 116 is further coupled to a D / A converter 114, which converts a digital signal to an analog signal. The AGC 116 may be further coupled to the pixel array 102, the VSR 104, the HSR 106, and the noise canceller 108. In the illustrated embodiment, the AGC 116 is coupled to an A / D converter 118, which converts an analog signal to a digital signal. In some embodiments, a voltage regulator 120 is coupled to the pixel array 102, the VSR 104, the HSR 106, and the noise canceller 108 to provide voltage control and maintain a constant voltage level of the coupled components.

[0098] Figure 2AAn exemplary circuit diagram of a pixel array 200 of a CMOS image sensor (CIS) 100 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the pixel array 200 of the CIS 100 includes a plurality of active pixels 201-1, 201-2, 201-3, 201-4, 201-5, 201-6, 201-7, 201-8, and 201-9. Although only 9 active pixels are shown, any desired number of active pixels may be included in the pixel array 200 and still be within the scope of the present disclosure. As described above, active pixel 201-1, active pixel 201-2, active pixel 201-3, active pixel 201-4, active pixel 201-5, active pixel 201-6, active pixel 201-7, active pixel 201-8, and active pixel 201-9 are arranged in a column-row configuration. More specifically, in some embodiments, pixel array 102 includes voltage control lines from vertical shift register (VSR) 104 and readout lines 207-1, 207-2, and 207-3. In some embodiments, pixel array 200 also includes positive power supply voltage power (VDD) 203-1, 203-2, and 203-3 and zero voltage reference (GND) 205-1, 205-2, and 205-3. Thus, the pixel array 200 may include a first plurality of columns (e.g., arranged vertically), a second plurality of rows (e.g., arranged horizontally), wherein each column includes a corresponding pair of VDD 203, GND 205, and a readout line 207, and each row includes a corresponding VDD 203, GND 205, and voltage control lines, namely, G_RST 220, TX 222, RST 226, OP 228, and R_SEL 230. In the illustrated embodiment, the active pixels 201-1 to 201-9 in the pixel array 200 may also each directly provide a corresponding data output through a corresponding readout line 207.

[0099] For example, if Figure 2A As shown in the illustrated embodiment, the pixel array 102 includes columns "A", columns "B" and columns "C" and rows "a", "b" and "c", wherein column A includes a corresponding readout line 207-1; column B includes a corresponding readout line 209-2; column C includes a corresponding readout line 207-3; row a includes a corresponding VDD 203-1, GND 205-1, and a voltage control line 209-1; row b includes a corresponding VDD 203-2, GND 205-2, and a voltage control line 209-2; and row c includes a corresponding VDD 203-3, GND 205-3, and a voltage control line 209-3.

[0100] In the illustrated embodiment, each row includes 5 control lines, namely G_RST 220, RST 226, OP 228, TX222, and R_SEL 230. In some embodiments, as discussed in detail below, the 5 control lines are used to provide control signals to the gates of the five transistors in each of the pixels of the row. Specifically, row a includes corresponding G_RST 220-1, RST226-1, OP 228-1, TX 222-1, and R_SEL 230-1; row b includes corresponding G_RST 220-2, RST 226-2, OP228-2, TX 222-2, and R_SEL 230-2; and row c includes corresponding G_RST 220-3, RST 226-3, OP 228-3, TX222-3, and R_SEL 230-3.

[0101] As described above, each active unit of the pixel array 102 (e.g., active pixel 201-1, active pixel 201-2, active pixel 201-3, active pixel 201-4, active pixel 201-5, active pixel 201-6, active pixel 201-7, active pixel 201-8, active pixel 201-9, etc.) may include a plurality of transistors, which will be described below. Figure 2B It should also be noted that Figure 2A This is an example for illustration purposes only and is not intended to be limiting.The types of signal lines in the pixel array 102 of the present disclosure may be arranged in different ways depending on the circuit wiring design and type of bit cells used in the array.

[0102] Figure 2B An exemplary circuit diagram of an active pixel 210 in a pixel array 200 of a CIS 100 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the active pixel 210 includes a photodiode 212, six transistors: a transistor M1 214-1, a transistor M2 214-2, a transistor M3 214-3, a transistor M4 214-4, a transistor M5 214-5, and a transistor M6 214-6. In some embodiments, each of the six transistors in the active pixel 200 includes a p-type metal-oxide-semiconductor (PMOS) transistor. Although Figure 2BThe illustrated embodiment shows that transistors M1 to transistor M6 are PMOS transistors, but any of a variety of transistors or devices suitable for use in a memory device may be implemented as at least one of transistors M1 to transistor M6, such as an NMOS bipolar junction transistor (BJT), a high-electron mobility transistor (HEMT), etc.

[0103] Active pixel 210 may further include capacitor 216. In some embodiments, transistor M1 214-1 and transistor M3 214-3 are reset transistors. In some embodiments, transistor M1 214-1 is a global reset gate and transistor M3 214-3 is a reset gate.

[0104] In some embodiments, source terminals of transistor M1 214-1, transistor M3 214-3, and transistor M5 214-5 are coupled to VDD 203. A drain terminal of transistor M1 214-1 is further coupled to photodiode 212, wherein one of the terminals of photodiode 212 is coupled to GND 205. A drain terminal of transistor M1 214-1 is further coupled to a source terminal of transistor M2 214-2. Drain terminals of transistor M2 214-2 and transistor M4 214-4 are coupled together to GND through capacitor 216. A drain terminal of transistor M3 214-3 and a source terminal of transistor M4 214-4 are coupled together at node 218. A drain terminal of transistor M5 214-5 and a source terminal of transistor M6 214-6 are coupled together. In some embodiments, a gate terminal of transistor M5 214-5 is coupled to node 218. The drain terminal of transistor M6 214-6 is coupled to the readout line 207. The gate terminals of transistor M1 214-1, transistor M2 214-2, transistor M3 214-3, transistor M4 214-4, and transistor M6 214-6 are coupled to a first control line (G_RST) 220, a second control line (TX) 222, a third control line (RST) 226, a fourth control line (OP) 228, and a fifth control line (R_SEL) 230, respectively.

[0105] When sensing, the voltage on G_RST switches from low to high to turn on transistor M1 214-1 to reset photodiode 212. Photodiode 212 then receives the light signal and photon-induced charge carriers generated within photodiode 212. The voltage on TX then switches from low to high to turn on transistor M2 214-2, while the voltage on OP remains low to turn off transistor M4 214-4. The photon-induced charge carriers are then directed to capacitor 216 (i.e., the storage node of the active pixel) through transistor M2 214-2. As described below in FIG. 3A to FIG. 3B As discussed in detail in , capacitor 216 is covered with a light shielding structure to prevent light induced noise.

[0106] When reading the background signal, the voltage on OP remains low to keep transistor M4 214-4 closed, and the voltage on RST switches from low to high to turn on transistor M3 214-3, which pulls the voltage level at node 218 from low to high. The voltage on node 218 can then turn on transistor M5 214-5. The voltage on R_SEL then switches from low to high to read the background signal to the readout line 207.

[0107] When reading out the stored photoinduced charge carriers to the readout line 207 , the voltage on RST is then switched from high to low; the voltage on OP is switched from low to high; and the voltage on R_SEL remains high to read out the signal stored on the storage node to the readout line 207 .

[0108] Figure 3A An exemplary top view of a portion of a pixel 300 in a pixel array 200 of a CIS 100 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the pixel 300 in the pixel array 102 of the CIS 100 includes an active area 302 and an insulating area 304 within a pixel boundary 301. In some embodiments, the insulating area 304 includes a deep trench isolation (DTI) structure or a shallow trench isolation (STI) structure that separates adjacent active pixels to reduce noise and crosstalk. In some embodiments, the size of the active pixel is 1.4×1.4 square microns to 5.5×5.5 square microns. In some embodiments, the ratio between the first area of ​​the active area 302 and the second area of ​​the insulating area 304 is in the range of 0.5 to 0.8.

[0109] In some embodiments, the active area 302 of the active pixel 201 includes at least a light sensing region 306 and a charge storage region 308. In the illustrated embodiment, the charge storage region 308 is configured to be adjacent to the light sensing region and overlap with the light sensing region 306. The overlapping area of ​​the light sensing region 306 and the charge storage region 308 is determined by the area of ​​a transfer gate, which is used to transfer photogenerated charges from the light sensing region 306 to the charge storage region 308. In some embodiments, the ratio between the area of ​​the light sensing region 306 and the area of ​​the charge storage region 308 is in the range of 1.5 to 2.5. In some other embodiments, the ratio between the area of ​​the light sensing region 306 and the area of ​​the charge storage region 308 is 1.5 to 2.5.

[0110] In some embodiments, the light sensing region 306 includes a photodiode (not shown). In some embodiments, the photodiode is a CMOS photodiode. In some other embodiments, the light sensing region 306 may further include at least one light guide structure for guiding incident light to the photodiode, wherein at least one light guide structure includes a high refractive index material. In some embodiments, the refractive index and size of at least one light guide structure are designed and selected according to the size and wavelength range of the photodiode. In some other embodiments, the light sensing region 306 may further include a filter for color imaging, a microlens, and an anti-reflection (AR) coating for improved light collection. In some embodiments, the CMOS photodiode in the light sensing region 306 detects light guided from the surface of the object. In some embodiments, the CMOS photodiode uses a semiconductor pn junction or a pin junction to convert light into a current signal. In some embodiments, the CMOS photodiode is a buried photodiode or a pinned photodiode, wherein the pinned photodiode includes a deep n-type implant in a p-type substrate and a heavily doped p-type layer in the deep n-type implant region to pin the surface, which can provide advantages such as low noise, high quantum efficiency, and low dark current. It should be noted that the CMOS photodiode in the light sensing region 306 also includes electrical contacts, which are not shown in the pixel 300 for the sake of clarity.

[0111] In some embodiments, the charge storage region 308 includes a transfer gate 310-1, a memory node 310-2, and a light shielding structure 336. In some embodiments, the transfer gate 310-1 is electrically coupled through a via contact 312. In some embodiments, the light shielding structure 336 in the charge storage region 308 of the pixel 300 provides light isolation to reduce charge contamination generated by parasitic light and improve global shutter efficiency. In some embodiments, as described in detail below, the light shielding structure 336 includes tungsten (W) metal and is configured above the charge storage region 308 to prevent incident light from reaching the transfer gate 310-1 or the memory node 310-2. In some embodiments, in order to prevent electrostatic charging from occurring on the light shielding structure 336 supported by an interlayer dielectric (ILD) layer (hereinafter referred to as Figure 3B ), the light shielding structure 336 is grounded via the ground contact 314.

[0112] In some embodiments, the charge storage region 308 further includes a plurality of transistors. For example, in the illustrated embodiment, the charge storage region 308 includes two functional gates 316-1 / 316-2, which are used to transfer the photogenerated carriers stored in the storage node to an external circuit and / or device. The functional gates 316-1 / 316-2 are coupled to corresponding contacts 318. In some embodiments, the storage node 310-2 is a floating diffusion node. In some embodiments, the storage node 310-2 further includes a diode having a heavily doped p-region and an n-region for low dark current.

[0113] In some embodiments, the pixel 300 may further include a plurality of transistors, including: a reset (RST) metal-oxide-semiconductor field-effect transistor (MOSFET) for resetting the sensing node to convert the charge into a voltage according to its intrinsic capacitance; a source follower (SF) MOSFET for performing amplification within the pixel; and a row select switch (RS) MOSFET for connecting the pixel to the column sample-and-hold stage. In some embodiments, when the CMOS photodiode is a pinned photodiode, a transfer gate (TG) MOSFET is required during integration into the sensing node. Figure 3A The embodiments shown in are examples and are not intended to be limiting. It should be noted that active pixels may include any number of transistors and any type of photodiode in any wiring design and remain within the scope of the present invention.

[0114] It should be noted that the via contact 312, ground contact 314, functional gate 316, and corresponding electrical contact 318 of transfer gate 310-1 in pixel 300 are for illustrative purposes and are not intended to be limiting. Any wiring design of active region 302, insulating region 304, charge storage region 308, light sensing region 306, light shielding structure 336, and multiple transistors / contacts is within the scope of the present invention.

[0115] Figure 3B An exemplary cross-sectional view of a portion of a pixel 300 in a pixel array 200 of a CIS 100 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the exemplary cross-sectional view is a view vertically cut through Figure 3A 3. In some embodiments, the pixel array 200 is fabricated on a substrate 322. In some embodiments, the substrate 322 comprises a lightly doped p-type silicon wafer. In some embodiments, the pixel 300 comprises a light sensing region 306 and a charge storage region 308. In some embodiments, the light sensing region 306 comprises a CMOS diode having a deep n-type implant region 324 and a pinned surface p-type region 324a. In some embodiments, the charge storage region 308 comprises a transfer gate 310-1, a storage node 310-2, and a light shielding structure 336, wherein the light shielding structure 336 is configured to be above the charge storage region 308 so as to prevent incident light from reaching the storage gate 310-1 or the storage node 310-2.

[0116] In some embodiments, a light shielding structure 336 is fabricated in the transfer gate 310-1 and separated from the transfer gate 310-1 by an interlayer dielectric (ILD) layer 326. In the illustrated embodiment, the top surfaces of the light shielding structure 336 and the ILD layer 326 are coplanar. In some embodiments, the bottom surface of the light shielding structure 336 includes corrugations, wherein the depth, geometry, and location of the corrugations are determined by an interference lithography and subsequent dry etching process (as described below in Figures 5A to 5G and FIG. 6A to FIG. 6C In some embodiments, the light shielding structure 336 is connected to the through-hole contact 312 of the transfer gate 310-1, the functional gate 316 ( Figure 3A ) through-hole contact 318, through-hole contact of CMOS photodiode (not shown) and ground contact 314 are simultaneously manufactured. Therefore, the light shielding structure 336 does not need a separate manufacturing step to be manufactured in the present disclosure, and does not cause plasma damage to the transfer gate 310-1.

[0117] Figure 44 is a flowchart showing a method 400 for forming a pixel array 200 in a CIS 100 according to some embodiments of the present disclosure. It should be noted that the method 400 is only an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 400 may be used in the embodiment of the present disclosure. Figure 4 Additional operations are provided before, during, and after the method 400, and some other operations may only be briefly described herein. In some embodiments, the operations of the method 400 may be respectively as follows: Figures 5A to 5G 1 is associated with a cross-sectional view of a portion of a pixel in a pixel array 200 in a CIS 100 at various stages of fabrication illustrated in FIG. 1 , which will be discussed in further detail below.

[0118] Reference Figure 4 , method 400 begins at operation 402, wherein a substrate according to some embodiments is provided. In some embodiments, the substrate includes at least one light sensing region and at least one charge storage region. In some embodiments, manufacturing at least one charge storage region further includes depositing, patterning, and etching a polysilicon layer, an interface layer, and a spacer layer to form at least one transfer gate structure above at least one corresponding storage node. In some embodiments, the interface layer is a silicon oxide layer and the spacer layer includes oxynitride. Method 400 continues with operation 404, wherein an interlayer dielectric (ILD) layer is formed on the surface of the substrate and the at least one transfer gate structure. In some embodiments, the ILD layer includes silicon oxide and is polished using a chemical mechanical polishing process. Method 400 continues with operation 406, wherein a photoresist layer is patterned according to some embodiments. In some embodiments, the photoresist layer is patterned to simultaneously define a plurality of via contacts, a plurality of ground contacts, and a light shielding structure. In some embodiments, the patterned photoresist layer includes a region where the photoresist layer is completely removed for electrical contacts (e.g., a plurality of via contacts and a ground contact) and a region where the photoresist layer is partially removed for a light shielding structure. Method 400 continues with operation 408, wherein the ILD layer is patterned using a patterned photoresist layer according to some embodiments. In some embodiments, the ILD layer is etched using the patterned photoresist layer as a hard mask. In some embodiments, the patterned ILD layer includes a region having a perforated opening for a through-hole contact and a partially thinned region for a light shielding structure. In some embodiments, the partially thinned region is aligned with at least one charge storage region in the substrate. Method 400 continues with operation 410, wherein the light shielding structure and a plurality of through-hole contacts are formed synchronously. In some embodiments, a metal layer is deposited and the patterned photoresist is removed according to some embodiments. In some embodiments, the metal layer includes tungsten (W) metal. In some embodiments, the W layer also fills the perforated openings in the ILD layer to form a plurality of through-hole contacts and / or ground contacts, and fills the partially thinned region to form a light shielding structure above at least one charge storage region.

[0119] As mentioned above, Figures 5A to 5G Shown in cross-section Figure 4 A portion of a pixel 500 in a pixel array 200 in a CIS 100 at various manufacturing stages of the method 400 is shown. In addition, in order to better understand the concepts of the present disclosure, the following is simplified. Figures 5A to 5G The concept of the present disclosure is a method for manufacturing a light shielding structure for a GC CMOS image sensor. Although the figure shows a pixel 500, it should be understood that the pixel 500 may include a plurality of other devices, such as signal lines, transistors, capacitors, light guides, through-hole contacts, ground contacts, STI structures, etc. (e.g. Figure 3A For the sake of clarity, Figures 5A to 5G The other components are not fully shown in the figure.

[0120] Figure 5A is a method for performing the above steps in various manufacturing stages according to some embodiments of the present disclosure. Figure 4 A cross-sectional view of a portion of a pixel 500 in a pixel array 200 in a CIS 100 including a substrate 502 at a manufacturing stage of operation 402 of . The substrate 502 includes at least two conductive regions 504. In some embodiments, the at least two conductive regions 504 are configured to sense incident light and store photogenerated charge. In some embodiments, the first conductive region 504-1 is a light sensing region. In some embodiments, the light sensing region 504-1 includes a photodiode, wherein the photodiode in the light sensing region 504-1 includes a complementary metal oxide semiconductor (CMOS) photodiode. In some embodiments, the CMOS photodiode detects incident light directed from the surface of an object. In some embodiments, the CMOS photodiode uses a semiconductor pn junction or a pin junction to convert light into a current signal, which is then directed to a second conductive region 504-2, wherein the second conductive region 504-2 is a charge storage region.

[0121] In some embodiments, substrate 502 is a silicon substrate. Alternatively, substrate 502 may include semiconductor materials of other elements, such as germanium. Substrate 502 may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. Substrate 502 may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, substrate 502 includes an epitaxial layer. For example, substrate 502 may have an epitaxial layer of an overlying bulk semiconductor. In addition, substrate 502 may include a semiconductor-on-insulator (SOI) structure. For example, substrate 502 may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0122] In some embodiments, the conductive region 504 includes a region in the substrate 502 implemented by processes such as ion implantation and / or diffusion. The conductive region 504 includes an n-well, a p-well, a lightly doped region (LDD), a heavily doped source and drain (S / D) contact, and various channel doping features configured to form various integrated circuit (IC) devices. In some embodiments, the memory node 606 includes a capacitor. The substrate 502 may further include other functional features formed in and on the substrate, which are not shown for clarity purposes. The substrate 502 further includes lateral isolation features, such as shallow trench isolation (STI), configured to form separate various devices in the substrate 502. The various devices in the substrate 502 further include silicides, which are disposed on the S / D, gate, and other device features to reduce contact resistance and improve process compatibility when coupling between devices through local interconnections.

[0123] Alternatively, the conductive region 504 may further include a silicide feature, which is typically disposed on the source, drain, or gate electrode using a sintering process initiated by at least one of a process including thermal heating, laser irradiation, or ion beam mixing. The silicide feature may be formed on a polysilicon gate (commonly referred to as a polycide gate) or on a source / drain (commonly referred to as salicide) by a self-aligned silicide technique. In another embodiment, the conductive region 504 may include an electrode of a capacitor or one end of a resistor.

[0124] In some embodiments, the interface layer 506 includes silicon oxide. In some embodiments, the interface layer 506 includes a material that is at least one of silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low-k material may include fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), Black (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, bis-benzocyclobutenes (BCB), SiLK (Dow Chemical, Midland, Mich.), polyimide, and / or other low-k dielectric materials to be developed in the future. In some embodiments, the interface layer 506 is deposited using plasma enhanced chemical vapor deposition (PECVD) using silane gas as a precursor gas. In some other embodiments, the interface layer 506 is deposited using one of the following: a physical vapor deposition (PVD) process, a thermal oxidation process, and an atomic layer deposition (ALD) process.

[0125] In some embodiments, the transfer gate 508 is formed by a photolithography process. The patterned photoresist layer is used as a mask in the etching of the conformal polysilicon (polySi) layer to form the storage gate 508, which is configured above the charge storage region 504-2 in the substrate 502. Therefore, in some embodiments, the patterned photoresist layer is formed after a conventional patterning (e.g., photolithography) process to align the transfer gate 508 with the conductive region 504 in the substrate 502. In some embodiments, the polysilicon layer is etched by a dry etching process and / or a wet etching process using the patterned first photoresist layer as a hard mask.

[0126] In some embodiments, the transfer gate 508 further includes a spacer layer, the spacer layer including a material that is at least one of: silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low-k material may include fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), Black (Applied Materials, Inc., Santa Clara, California), xerogels, aerogels, amorphous fluorinated carbons, parylene, bisbenzocyclobutene (BCB), SiLK (The Dow Chemical Company, Midland, Michigan), polyimide, and / or other low-k dielectric materials developed in the future. In some embodiments, the spacer layer is deposited using plasma enhanced chemical vapor deposition (PECVD) using silane gas as a precursor gas. In some other embodiments, the spacer layer is deposited using a physical deposition process such as sputtering and evaporation. In some embodiments, the spacer layer is deposited using an atomic layer deposition (ALD) process. In some embodiments, the spacer layer has a thickness equal to or greater than 100 nanometers. In some embodiments, the spacer layer is patterned so as to cover only a portion of the interface layer 506 and cover the surrounding transfer gate 508, such as Figure 5A shown in.

[0127] Figure 5B is a method for performing the above steps in various manufacturing stages according to some embodiments of the present disclosure. Figure 4 4. A cross-sectional view of a portion of a pixel 300 in a pixel array 200 in a CIS 100 including an interlayer dielectric (ILD) 510 at one manufacturing stage of operation 404 of FIG. The ILD layer 510 includes a material that is at least one of silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low-k material may include fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), Black (Applied Materials, Inc., Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), SiLK (Dow Chemical Company, Midland, Michigan), polyimide and / or other low-k dielectric materials to be developed in the future. In some embodiments, the surface of the ILD layer 510 is further planarized by a Chemical-Mechanical Polishing (CMP) process. In some embodiments, the ILD layer 510 after the CMP process has a thickness 511 of several hundred nanometers. In some embodiments, the thickness 511 of the ILD layer 510 is in the range of 550 nanometers to 600 nanometers.

[0128] Figure 5C is a method for performing the above steps in various manufacturing stages according to some embodiments of the present disclosure. Figure 4 4 is a cross-sectional view of a portion of a pixel 300 in a pixel array 200 in a CIS 100 including a photoresist layer 512 and a photomask 515 at a manufacturing stage of operation 406 of . In some embodiments, the initial photoresist layer 512 has a thickness in a range of 450 nanometers to 520 nanometers. In some embodiments, the photomask 515 includes a pattern array 514 aligned with the charge storage region 504-2 for forming a light shielding structure in the ILD layer 510. In some embodiments, the photomask 515 further includes an opening 516 aligned with the charge storage region 504-2 for forming a through-hole contact of the transfer gate 508. In some embodiments, the pattern array 514 in the photomask 515 includes an array of apertures in an opaque coating (e.g., chrome metal) that allows incident light to pass through so as to expose the photoresist layer 512. In some embodiments, the critical size of the apertures in the pattern array 514 is less than the critical size of the apertures in the opening 516. In some other embodiments, the distance between the apertures in pattern array 514 is less than the distance between opening 516 and the apertures in the pattern array adjacent to opening 516. This configuration of photomask 515 allows the via contacts and light shielding areas in photoresist layer 512 to be patterned simultaneously using one photolithography step, which reduces manufacturing costs and improves manufacturing yields. In some embodiments, the design of the aperture array in pattern array 514 can be adjusted to achieve various light shielding structures, which will be FIG. 6A to FIG. 8B This is discussed in detail.

[0129] Figure 5D is a method for performing the above steps in various manufacturing stages according to some embodiments of the present disclosure. Figure 44 is a cross-sectional view of a portion of a pixel 300 in a pixel array 200 in a CIS 100 including a patterned photoresist layer 512 at a manufacturing stage of operation 406 of FIG. In some embodiments, the patterned photoresist layer 512 includes a shallow etched region 517 and a perforated opening 519 corresponding to a pattern array 514 and an opening 516 in a photomask 515, respectively. In some embodiments, the shallow etched region 517 is generated in the photoresist layer 512 synchronously with the perforated opening 519. The surface of the ILD layer 510 is exposed in the perforated opening 519, while the surface of the ILD layer 510 is covered by the photoresist layer 512 in the shallow etched region 517. By designing and adjusting the critical dimensions and pitch size of the pattern array 514 in the photomask 515, taking into account the wavelength and power of the UV light used for exposure and the dielectric properties of the photoresist layer 512, the geometry of the partially exposed shallow etched area 517 below the pattern array 514 can be controlled, wherein the geometry includes at least one of: the thickness of the partially exposed photoresist layer, the distance between the wrinkles, and the height of the wrinkles.

[0130] In some embodiments, the exposed photoresist layer 512 is then developed. In some embodiments, the exposed portion of the photoresist layer 512 may be removed using one or more chemical cleaning processes using acetone, 1-Methyl-2-pyrrolidon (NMP), dimethyl sulfoxide (DMSO), or other suitable removal chemicals. In some embodiments, the chemicals used may need to be heated to a temperature above room temperature to effectively dissolve the patterned photoresist layer 512. The choice of remover is determined by the type and chemical structure of the exposed photoresist layer 512, ILD layer 510, and substrate 502 to ensure chemical compatibility of these layers with the chemical cleaning process. In some embodiments, this cleaning process is followed by a rinse process using isopropyl alcohol or the like, followed by a rinse using deionized water.

[0131] In some embodiments, the patterning process of the photoresist layer 512 includes: using an ultraviolet (UV) light source having a wavelength of 248 nanometers, operating at a power in the range of 650 watts to 750 watts, to expose the photoresist layer 512 for 0.5 seconds to 1.2 seconds. The exposed photoresist layer 512 is then developed for 6 seconds to 11 seconds. In the illustrated embodiment, the patterning process of the photoresist layer 512 can simultaneously produce perforated openings 519 in the photoresist layer 512, and shallow etched areas 517, wherein the perforated openings 519 are used to electrically contact the transfer gate 508, and in the shallow etched areas 517, the photoresist layer 512 is partially removed and partially thinned due to the geometry of the pattern array 514 in the photomask 515.

[0132] Figure 5E is a method for performing the above steps in various manufacturing stages according to some embodiments of the present disclosure. Figure 4 4 is a cross-sectional view of a portion of a pixel 300 in a pixel array 200 in a CIS 100 including a patterned ILD layer 510 at one manufacturing stage of operation 408 of FIG. The ILD layer 510 is etched using a dry etching process and using the patterned photoresist layer 512 as a hard mask. In some embodiments, during the dry etching process, the exposed ILD layer 510 below the perforation opening 519 is completely removed to form a perforation 520 that exposes the top surface of the transfer gate 508 for contact purposes. During the dry etching process, the ILD layer 510 below the shallow etched region 517 is also partially thinned to produce a shallow etched region 518 after removing the residual photoresist layer 512 during the same dry etching process. In some embodiments, the wrinkles at the bottom of the shallow etched region 517 present in the photoresist layer 512 are also transferred to the bottom of the shallow etched region 518 of the partially etched ILD layer 510.

[0133] Fig. 5F is a method for performing the above steps in various manufacturing stages according to some embodiments of the present disclosure. Figure 4 4 is a cross-sectional view of a portion of a pixel 500 in a pixel array 200 in a CIS 100 including a light shielding structure 522 (i.e., a metal layer) at a manufacturing stage of operation 410 of FIG. In some embodiments, the light shielding structure 522 includes tungsten (W) metal. In some embodiments, the light shielding structure 522 fills the perforation 520 and the shallow etched area 518 in the ILD layer 510. The light shielding structure 522 is further deposited on the surface of the patterned photoresist layer 512. In some embodiments, the light shielding structure 522 is deposited using a PVD process such as sputtering and electron beam evaporation.

[0134] Figure 5G is a method for performing the above steps in various manufacturing stages according to some embodiments of the present disclosure. Figure 4 A cross-sectional view of a portion of a pixel 300 in a pixel array 200 in a CIS 100 including a light shielding structure 522 and a via contact in an ILD layer 510 at one manufacturing stage of operation 410. In some embodiments, acetone, 1-methyl-2-pyrrolidone (NMP), or dimethyl sulfoxide (DMSO) is used, and then the light shielding structure 522 in direct contact with the patterned photoresist layer 512 is stripped to remove the photoresist layer 512 covered by the metal coating. In some embodiments, the surface of the IDL layer 510 is further polished by a CMP process, after which the surface of the light shielding structure 522, the via contact 526, and the surface of the ILD layer 510 are coplanar. In addition, the via contact 526 is electrically isolated from the light shielding structure 522, as shown in FIG. Figure 3A and Figure 3B Although Figures 5A to 5G Although not shown, it should be noted that via contacts and active device and ground contacts for functional gates in pixel 300 may be fabricated by method 500 and are within the scope of the present invention.

[0135] Fig. 6A An exemplary cross-sectional view of a portion of a pixel 300 in a pixel array 200 of a CIS 100 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the pixel 300 includes a light sensing region 504-1, a charge storage region 504-2, and a transfer gate 508. The pixel 300 further includes an ILD layer 510 and a light shielding structure 522 in the ILD layer 510. It should be noted that, for clarity, the via contacts of the transfer gate 508 and other via contacts and ground contacts of other active components (including transistors, functional gates, etc.) are not depicted.

[0136] In some embodiments, the light shielding structure 522 is aligned with the charge storage region 504-2 and the transfer gate 508 in the substrate 502 to prevent light leakage from these regions. In some embodiments, the light shielding structure 522 is coplanar with the ILD layer 510. In some embodiments, the thickness 602 of the light shielding structure 522 is equal to or greater than 150 nanometers. In some embodiments, the light shielding structure 522 includes a plurality of corrugations 524 at the bottom of the light shielding structure 522.

[0137] FIG. 6B to FIG. 6C The method for patterning according to some embodiments of the present disclosure is shown Fig. 6A 6 is an exemplary top view of a portion of a photomask 610 depicting a light shielding structure 522 in an interlayer dielectric (ILD) layer. In the illustrated embodiment, the photomask 610 includes an array of apertures 612 in an opaque coating (e.g., chrome metal) that allows incident light to pass through the apertures 612 so as to be visible. Figures 5A to 5G The critical dimension of the array of apertures 612 (e.g., the diameter of the apertures 612 or the width of the apertures 612) is less than or equal to 160 nanometers, and the pitch size of the array is less than or equal to 260 nanometers. When incident light passes through the photomask 610 with small and closely arranged apertures 612, the light waves spread out, that is, light diffraction occurs, thereby partially exposing the photoresist layer that is not directly under the apertures 612. The diffracted light waves from adjacent apertures 612 can further cause interference in the photoresist layer in the area covered by the opaque coating and between the adjacent apertures 612.

[0138] Fig. 7AAn exemplary cross-sectional view of a portion of a pixel 700 in the pixel array 200 of the CIS 100 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the pixel 700 includes a light sensing region 504-1, a charge storage region 504-2, and a transfer gate 508. The pixel 700 further includes an ILD layer 510 and a light shielding structure 522 in the ILD layer 510. It should be noted that for clarity, the via contact of the transfer gate 508 and other via contacts and ground contacts of other active components (including transistors, functional gates, etc.) are not depicted.

[0139] In some embodiments, the light shielding structure 522 is aligned with the charge storage region 504-2 and the transfer gate 508 in the substrate 502 to prevent light leakage from these regions. In some embodiments, the light shielding structure 522 is coplanar with the ILD layer 510. In some embodiments, the thickness 702 of the light shielding structure 522 is equal to or greater than 150 nanometers. In some embodiments, the light shielding structure 522 includes a corrugation 524 at the bottom of the light shielding structure 522. In some embodiments, the corrugation 524 has an inter-corrugation distance of 0 nanometers to 180 nanometers. In some embodiments, the light shielding structure 522 further includes a wall at the edge, which has a height 704 greater than the thickness 702 of the light shielding structure.

[0140] Figure 7B The method for patterning according to some embodiments of the present disclosure is shown Fig. 7A FIG. 1 is an exemplary top view of a portion of a photomask 710 depicting a light shielding structure 522 in an interlayer dielectric (ILD) layer 510. In the illustrated embodiment, the photomask 710 includes an array of apertures 712 / 722 in an opaque coating (e.g., chrome metal) that allow incident light to pass through the apertures 712 / 722 to be viewed as Figures 5A to 5G The exposure photoresist layer is discussed in . The critical dimension of the array of apertures 712 / 722 (e.g., the diameter of the hole or the width of the gap) is less than or equal to 160 nanometers, and the pitch size of the array is less than or equal to 260 nanometers. When the incident light passes through the photomask 610 with smaller and closely arranged apertures 712 / 722, the light waves are spread out, that is, light diffraction occurs, which partially exposes the photoresist layer that is not directly below the apertures 712 / 722. The diffracted light waves from adjacent apertures 712 / 722 can further cause interference in the photoresist layer in the area covered by the opaque coating and between adjacent apertures 612. In the illustrated embodiment, in order to form a wall structure at the edge of the light shielding structure 522, the critical dimension 714 and the pitch size 716 of the aperture 712 are respectively larger than the critical dimension 724 and the pitch size 726 of the aperture 722, so that the photoresist layer below the aperture 712 has better exposure than the photoresist layer below the aperture 722, and the photoresist can be removed more completely during the development process than the photoresist below the aperture 722.

[0141] Fig. 8A An exemplary cross-sectional view of a portion of a pixel 800 in the pixel array 200 of the CIS 100 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the pixel 800 includes a light sensing region 504-1, a charge storage region 504-2, and a transfer gate 508. The pixel 800 further includes an ILD layer 510 and a light shielding structure 522 in the ILD layer 510. It should be noted that for clarity, the via contact of the transfer gate 508 and other via contacts and ground contacts of other active components (including transistors, functional gates, etc.) are not depicted.

[0142] In some embodiments, the light shielding structure 522 is aligned with the charge storage region 504-2 and the transfer gate 508 in the substrate 502 to prevent light leakage from these regions. In some embodiments, the light shielding structure 522 is coplanar with the ILD layer 510. In some embodiments, the thickness 802 of the light shielding structure 522 is equal to or greater than 150 nanometers. In some embodiments, the light shielding structure 522 includes a corrugation 524 at the bottom of the light shielding structure 522. In some embodiments, the corrugation 524 has an inter-corrugation distance in the range of 0 nanometers to 180 nanometers. In some embodiments, the light shielding structure 522 further includes a wall at the edge, which has a height 806 greater than the thickness 802 of the light shielding structure. In the illustrated embodiment, the wall at the edge of the light shielding structure 522 further includes a step having a step height 804, the step height 804 being greater than the thickness 802 of the light shielding structure 522 and less than the height 806 of the wall.

[0143] Figure 8B The method for patterning according to some embodiments of the present disclosure is shown Fig. 8A 8 is an exemplary top view of a portion of a photomask 810 depicting a light shielding structure 522 in an interlayer dielectric (ILD) layer 510. In the illustrated embodiment, the photomask 810 includes an array of apertures 812 / 822 / 824 in an opaque coating (e.g., chrome metal) that allow incident light to pass through the apertures 812 / 822 / 824 to be viewed as Figures 5A to 5GThe exposure photoresist layer discussed in . The critical dimension of the array of apertures 812 / 822 / 824 (e.g., the diameter of the hole or the width of the gap) is less than or equal to 160 nanometers, and the pitch size of the array is less than or equal to 260 nanometers. When the incident light passes through the photomask 810 with smaller and closely arranged apertures 812 / 822 / 824, the light wave is spread out, that is, light diffraction occurs, which partially exposes the photoresist layer that is not directly below the aperture 812 / 822 / 824. The diffracted light waves from adjacent apertures 812 / 822 / 824 can further produce interference in the photoresist layer in the region covered by the opaque coating and between adjacent apertures 812 / 822 / 824. In the illustrated embodiment, to form the wall at the edge of the light shielding structure 522, the critical dimension 814 and the pitch size 816 of the aperture 812 are respectively larger than the critical dimension 824 and the pitch size 826 of the aperture 822, thereby allowing the photoresist layer below the aperture 812 to have better exposure than the photoresist layer below the aperture 822. Similarly, to form the step at the edge of the light shielding structure 522, the critical dimension 824 and the pitch size 826 of the aperture 822 are respectively larger than the critical dimension 834 and the pitch size 836 of the aperture 832, thereby allowing the photoresist layer below the aperture 822 to have better exposure than the photoresist layer below the aperture 832.

[0144] Fig. 9 An exemplary cross-sectional view of a portion of a pixel 300 in a pixel array 200 of a CIS 100 according to some embodiments of the present disclosure is shown. In the illustrated embodiment, the pixel 300 includes a light sensing region 504-1, a charge storage region 504-2, and a transfer gate 508. The pixel 300 further includes an ILD layer 510 and a light shielding structure 522 in the ILD layer 510. It should be noted that, for clarity, the via contacts of the transfer gate 508 and other via contacts and ground contacts of other active components (including transistors, functional gates, etc.) are not depicted.

[0145] In some embodiments, the light shielding structure 522 is aligned with the charge storage region 504-2 and the transfer gate 508 in the substrate 502 to prevent light leakage from these regions. In some embodiments, the light shielding structure 522 is coplanar with the ILD layer 510. In some embodiments, the light shielding structure 522 has a bowl-shaped bottom surface 902, wherein the bowl-shaped bottom surface includes corrugations 524. In some embodiments, the light shielding structure 522 has a thickness 904 equal to or greater than 150 nanometers measured between the highest point of the bottom surface and the top surface.

[0146] In one embodiment, a semiconductor device includes: a light sensing region; a signal processing region; and a light shielding structure, wherein the signal processing region is spatially configured to be adjacent to the light sensing region in a lateral direction, wherein the light shielding structure is configured to be above the signal processing region in a vertical direction so as to prevent incident light from leaking from the light sensing region to the signal processing region, and wherein the light shielding structure is configured in an interlayer dielectric (ILD) layer and is formed synchronously with a plurality of via contacts. In some embodiments, the light shielding structure includes a first surface and a second surface, wherein the first surface is coplanar with the interlayer dielectric layer, and wherein the second surface includes a plurality of wrinkles. In some embodiments, the light shielding structure includes tungsten metal and is electrically grounded through at least one grounding contact. In some embodiments, the first thickness of the light shielding structure is at least 150 nanometers, and wherein the second thickness of the interlayer dielectric layer is at least 330 nanometers. In some embodiments, the charge storage region includes at least one of the following: at least one transfer gate and a charge storage node. In some embodiments, the light sensing region includes a complementary metal oxide semiconductor photodiode. In some embodiments, the at least one via contact is configured to provide electrical contact to the charge storage region and to be electrically isolated from the light shielding structure, wherein the at least one via contact comprises tungsten metal.

[0147] In another embodiment, a complementary metal oxide semiconductor (CMOS) image sensor includes a plurality of pixels configured in a pixel array, wherein each of the plurality of pixels includes a light sensing region and a signal processing region, wherein the signal processing region is spatially configured to be adjacent to the light sensing region in a lateral direction, wherein the signal processing region is configured to be below a light shielding structure in a vertical direction so as to prevent incident light from leaking from the light sensing region to the signal processing region, wherein the light shielding structure is configured in an interlayer dielectric (ILD) layer and is formed synchronously with a plurality of via contacts. In some embodiments, each of the plurality of light shielding structures includes a first surface and a second surface, wherein the first surface is coplanar with the interlayer dielectric layer, and wherein the second surface includes a corrugation. In some embodiments, the light shielding structure in each of the plurality of pixels includes tungsten metal and is electrically grounded through at least one ground contact. In some embodiments, the first thickness of the light shielding structure is at least 150 nanometers, and wherein the second thickness of the interlayer dielectric layer is at least 330 nanometers. In some embodiments, the charge storage region includes at least one of the following: at least one transfer gate and a charge storage node. In some embodiments, the at least one via contact is configured to provide electrical contact to the charge storage region and to be electrically isolated from the light shielding structure, wherein the at least one via contact comprises tungsten metal. In some embodiments, the complementary metal oxide semiconductor image sensor further comprises: a vertical shift register coupled to the pixel array to perform at least one of the following functions: receiving a row address of the pixel array, and driving a control line of the pixel array; a horizontal shift register coupled to the pixel array to perform the following operations: reading an output signal from the pixel array; a timing generator coupled to the pixel array, the vertical shift register, and the horizontal shift register to generate a clock signal for synchronization purposes; and a voltage regulator coupled to the pixel array, the vertical shift register, and the horizontal shift register to provide voltage control and maintain voltage levels.

[0148] However, in another embodiment, a method for forming a semiconductor device includes: depositing an interlayer dielectric (ILD) layer on a substrate, wherein the substrate includes a plurality of pixels configured in a pixel array, and wherein each of the plurality of pixels includes a light sensing region and a signal processing region; patterning the ILD layer to synchronously form a first plurality of fully etched through holes and a first plurality of shallowly etched regions; and depositing a metal layer on the ILD layer to synchronously form a plurality of through-hole contacts of a plurality of light shielding structures in each of the plurality of pixels in the first plurality of fully etched through holes and the first plurality of shallowly etched regions, wherein each of the plurality of light shielding structures is configured to align with the signal processing region in the pixel in a vertical direction so as to prevent incident light from leaking from the light sensing region to the signal processing region. In some embodiments, each of the plurality of light shielding structures includes tungsten metal and is electrically grounded through the at least one grounding contact. In some embodiments, the first thickness of each of the plurality of light shielding structures is at least 150 nanometers, and wherein the second thickness of the interlayer dielectric layer is at least 330 nanometers. In some embodiments, the charge storage region includes at least one of the following: at least one transfer gate and a charge storage node. In some embodiments, each of the plurality of light shielding structures includes a first surface and a second surface, wherein the first surface is coplanar with the interlayer dielectric layer, and wherein the second surface includes a plurality of wrinkles. In some embodiments, the patterning further includes: patterning the photoresist layer to synchronously form a second plurality of perforated openings and a second plurality of shallow etched areas in the photoresist layer; and etching the interlayer dielectric layer using the patterned photoresist layer as a hard mask to synchronously form the first plurality of perforated openings and the first plurality of shallow etched areas in the interlayer dielectric layer, wherein the second plurality of shallow etched areas in the photoresist layer are formed using an aperture array having a critical dimension equal to or less than 160 nanometers and a pitch size equal to or less than 260 nanometers.

[0149] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: Light sensing area; Charge storage area; a transfer gate formed above the charge storage region; Light shielding structure; as well as at least one through-hole contact; wherein the charge storage region is spatially configured to be adjacent to the light sensing region in a lateral direction, wherein the light shielding structure is configured to be above the charge storage region in a vertical direction so as to prevent incident light from leaking from the light sensing region to the charge storage region, wherein the light shielding structure is configured in an interlayer dielectric layer, wherein the light shielding structure includes a first surface and a second surface, wherein the first surface is coplanar with the interlayer dielectric layer, and the second surface includes a plurality of wrinkles, wherein a relatively lower portion of each of the wrinkles is higher than a top portion of the transfer gate, and wherein the light shielding structure is formed synchronously with the at least one through-hole contact. 2 . The semiconductor device according to claim 1 , wherein the light shielding structure comprises a first thickness measured between highest points of the first surface and the second surface, wherein the first thickness is equal to or greater than 150 nanometers. 3 . The semiconductor device according to claim 1 , wherein the light shielding structure comprises tungsten metal and is electrically grounded through at least one ground contact. 4 . The semiconductor device according to claim 1 , wherein the second thickness of the interlayer dielectric layer is at least 330 nanometers. 5 . The semiconductor device according to claim 1 , wherein the charge storage region comprises a charge storage node. 6 . The semiconductor device according to claim 1 , wherein the light sensing region comprises a complementary metal oxide semiconductor photodiode.

7. The semiconductor device of claim 1, wherein the at least one via contact is configured to provide electrical contact to the charge storage region and to be electrically isolated from the light shielding structure, wherein the at least one via contact comprises tungsten metal.

8. A complementary metal oxide semiconductor image sensor, comprising: A plurality of pixels are arranged in a pixel array. wherein each of the plurality of pixels comprises: Light sensing area; a charge storage region formed to be adjacent to the light sensing region in a lateral direction; a transfer gate formed above the charge storage region; a light shielding structure formed to be above the charge storage region in a vertical direction so as to prevent incident light from leaking from the light sensing region to the charge storage region, wherein the light shielding structure is disposed in an interlayer dielectric layer, wherein the light shielding structure includes a first surface and a second surface, wherein the first surface is coplanar with the interlayer dielectric layer, and the second surface includes a plurality of corrugations, wherein a relatively lower portion of each of the corrugations is higher than a top portion of the transfer gate; and At least one via contact extends through the interlayer dielectric layer to contact a top surface of the transfer gate. 9 . The complementary metal oxide semiconductor image sensor of claim 8 , wherein the light shielding structure comprises a first thickness measured between highest points of the first surface and the second surface, wherein the first thickness is equal to or greater than 150 nanometers.

10. The complementary metal oxide semiconductor image sensor of claim 8, wherein the light shielding structure in each of the plurality of pixels comprises tungsten metal and is electrically grounded through at least one ground contact. 11 . The complementary metal oxide semiconductor image sensor of claim 8 , wherein the second thickness of the interlayer dielectric layer is at least 330 nanometers.

12. The CMOS image sensor of claim 8, wherein the charge storage region comprises a charge storage node.

13. The complementary metal oxide semiconductor image sensor of claim 8, wherein the at least one via contact is configured to provide electrical contact to the charge storage region and to be electrically isolated from the light shielding structure, wherein the at least one via contact comprises tungsten metal.

14. The complementary metal oxide semiconductor image sensor according to claim 8, further comprising: a vertical shift register coupled to the pixel array to perform at least one of the following functions: receiving a row address of the pixel array, and driving a control line of the pixel array; a horizontal shift register coupled to the pixel array to perform the following operations: reading an output signal from the pixel array; a timing generator coupled to the pixel array, the vertical shift register, and the horizontal shift register to generate a clock signal for synchronization purposes; as well as A voltage regulator is coupled to the pixel array, the vertical shift register, and the horizontal shift register to provide voltage control and maintain voltage levels.

15. A method for forming a semiconductor device, comprising: depositing an interlayer dielectric layer on a substrate, wherein the substrate comprises a plurality of pixels arranged in a pixel array, and wherein each of the plurality of pixels comprises a light sensing region, a charge storage region, and a transfer gate, wherein the transfer gate is formed above the charge storage region; patterning the interlayer dielectric layer to simultaneously form a first plurality of through-hole openings and a first plurality of shallow etched regions in the interlayer dielectric layer; as well as depositing a metal layer on the interlayer dielectric layer to simultaneously form a plurality of via contacts and at least one ground contact in the first plurality of through-hole openings and a plurality of light shielding structures in the first plurality of shallow etched areas, wherein the charge storage region is spatially configured to be adjacent to the light sensing region in a lateral direction, wherein the plurality of light shielding structures are configured to be above the charge storage region in a vertical direction so as to prevent incident light from leaking from the light sensing region to the charge storage region, wherein each of the plurality of light shielding structures comprises a first surface and a second surface, wherein the first surface is coplanar with the interlayer dielectric layer, and wherein the second surface comprises a plurality of wrinkles, wherein a relatively lower portion of each of the wrinkles is higher than a top portion of the transfer gate. 16 . The method for forming a semiconductor device according to claim 15 , wherein each of the plurality of light shielding structures comprises tungsten metal and is electrically grounded through the at least one ground contact.

17. A method for forming a semiconductor device according to claim 15, wherein a first thickness of each of the plurality of light shielding structures measured between the highest points of the first surface and the second surface is at least 150 nanometers, and wherein a second thickness of the interlayer dielectric layer is at least 330 nanometers.

18. The method for forming a semiconductor device according to claim 15, wherein the charge storage region comprises a charge storage node.

19. The method for forming a semiconductor device according to claim 17, wherein the patterning further comprises: patterning the photoresist layer to simultaneously form a second plurality of perforation openings and a second plurality of shallow etched regions in the photoresist layer; as well as etching the interlayer dielectric layer using the patterned photoresist layer as a hard mask to simultaneously form the first plurality of through-hole openings and the first plurality of shallow etched regions in the interlayer dielectric layer, The second plurality of shallow etched regions in the photoresist layer are formed using an aperture array having a critical dimension equal to or less than 160 nanometers and a pitch size equal to or less than 260 nanometers.

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