Selective nitrided gate oxide for rts noise and white pixel reduction

Abstract

This application relates to selective gate oxide nitride (GNOV) for reducing RTS noise and white pixels. The invention provides a pixel cell comprising a nitrogen-implanted region at a semiconductor material-gate oxide interface in a region above a photodiode. The pixel cell further excludes nitrogen implantation in the channel regions of a plurality of pixel transistors. Therefore, Si-N bonds are formed at the semiconductor material-gate oxide interface in the region above the photodiode, thus protecting the channel region from nitrogen implantation at the semiconductor material-gate oxide interface. A method for forming the pixel cell is also described.

Description

Technical Field

[0001] This disclosure generally relates to image sensors, and more particularly, but not exclusively, to pixel cells having selective nitride gate oxide regions. Background Technology

[0002] CMOS image sensors (CIS) are ubiquitous. They are widely used in digital cameras, mobile phones, security cameras, and in medical, automotive, and other applications. A typical image sensor operates in response to image light reflected from an external scene incident on the sensor. An image sensor comprises an array of pixels with photosensitive elements (such as photodiodes) that absorb a portion of the incident image light and generate an image charge in the process. The image charge of each pixel can be measured as the output voltage of each photosensitive element, which varies depending on the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light used to produce a digital image (i.e., image data) representing the external scene.

[0003] The technology used to manufacture image sensors continues to advance at a rapid pace. The demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices. Combined with the need for image sensors with high dynamic range and low light sensitivity, the design of pixel units with high conversion gain and high signal-to-noise ratio has become increasingly challenging. Summary of the Invention

[0004] In one aspect, this application provides a method for fabricating a pixel unit, comprising: providing a semiconductor material layer; forming a photodiode, a floating diffuser, and a plurality of doped regions of a plurality of pixel transistors of a pixel in the semiconductor material layer; forming a gate oxide layer on the semiconductor material layer; forming a plurality of gate electrodes of the plurality of pixel transistors of the pixel on the gate oxide layer; selectively masking the channel regions of the plurality of pixel transistors of the pixel with a photoresist to expose a region above the photodiode; implanting nitrogen at a semiconductor material-gate oxide adjacent interface in the region above the photodiode; and removing the photoresist to provide the channel regions of the plurality of pixel transistors of the pixel without nitrogen implantation.

[0005] On the other hand, this application provides a pixel unit comprising: a photodiode, a floating diffuser, and multiple doped regions of multiple pixel transistors of the pixel, disposed in a semiconductor material layer; a gate oxide layer disposed on the semiconductor material layer, the gate oxide layer including a nitrogen implantation region at the semiconductor material-gate oxide adjacency interface in the region above the photodiode; and multiple gate electrodes of the multiple pixel transistors of the pixel, disposed on the gate oxide layer, wherein the semiconductor material-gate oxide adjacency interface is not implanted with nitrogen in the channel region of the multiple pixel transistors.

[0006] In another aspect, this application provides an imaging system comprising: a pixel unit array, wherein each of the pixel units includes: a photodiode, a floating diffuser, and a plurality of doped regions of a plurality of pixel transistors disposed in a semiconductor material layer; a gate oxide layer disposed on the semiconductor material layer; and a plurality of gate electrodes of the plurality of pixel transistors of the pixel disposed on the gate oxide layer; wherein the pixel unit includes a nitrogen-implanted region at a semiconductor material-gate oxide adjacent interface in a region above the photodiode, and wherein the pixel unit does not have nitrogen implanted in the channel regions of the plurality of pixel transistors; a control circuit coupled to the pixel unit array to control the operation of the pixel unit array; and a readout circuit coupled to the pixel unit array to read out image data from the pixel unit array. Attached Figure Description

[0007] Non-limiting and non-exhaustive embodiments of this disclosure are described with reference to the following figures, wherein similar reference numerals throughout the various views refer to similar portions unless otherwise specified.

[0008] Figure 1A This is a schematic diagram illustrating an example of a pixel unit having two photodiodes according to the teachings of this disclosure.

[0009] Figure 1B It is a cross-sectional view illustrating a portion of a pixel unit according to the teachings of this disclosure.

[0010] Figure 1C It is a cross-sectional view illustrating a portion of a pixel unit according to the teachings of this disclosure.

[0011] Figure 2 This is a flowchart illustrating an example of the process of creating a pixel unit according to the teachings of this disclosure.

[0012] Figure 3A It is a plan view illustrating an example of a portion of a pixel unit during an exemplary process step according to the teachings of this disclosure.

[0013] Figure 3B It is a cross-sectional view illustrating an example of a portion of a pixel unit during an exemplary process step according to the teachings of this disclosure.

[0014] Figure 3C It is a cross-sectional view illustrating an example of a portion of a pixel unit during an exemplary process step according to the teachings of this disclosure.

[0015] Figure 3D It is a cross-sectional view illustrating a portion of a pixel unit according to the teachings of this disclosure.

[0016] Figure 4 This is a schematic diagram illustrating an example of an imaging system comprising a pixel array having pixel units, according to the teachings of this disclosure.

[0017] Throughout the various views in the accompanying drawings, corresponding reference characters indicate the corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements to aid in understanding the various embodiments of the invention. Furthermore, common but well-understood elements that are useful or necessary in commercially viable embodiments are generally not depicted in order to contribute to a less obstructive view of these various embodiments of the invention. Detailed Implementation

[0018] Apparatus and methods relating to pixel units having nitrogen-implanted regions at a semiconductor material-gate oxide interface in a region located above a photodiode are disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of these specific details or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0019] Throughout this specification, the reference to "an example" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that example is included in at least one embodiment of the invention. Therefore, the phrases "in an example" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same example. Furthermore, particular features, structures, or characteristics may be combined in one or more examples in any suitable manner.

[0020] As illustrated in the figures, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “down,” “above,” “upper,” and the like may be used herein to describe the relationship of one element or feature to another element(s). It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms are intended to encompass different orientations of the device being used or operated. For example, if the device in the figures were flipped, then an element described as “below,” “under,” or “down” of other elements or features would be oriented as “above” of other elements or features. Thus, the exemplary terms “below” or “down” may encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.

[0021] Several technical terms are used throughout this specification. These terms have their common meaning in the field of their origin, unless otherwise expressly defined herein or the context in which they are used will clearly indicate a different meaning. It should be noted that component names and symbols may be used interchangeably throughout this document (e.g., Si for silicon); however, they have the same meaning.

[0022] In this disclosure, the term "semiconductor substrate" or "substrate" refers to any type of substrate for forming semiconductor devices thereon, including single-crystal substrates, semiconductor-on-insulator (SOI) substrates, doped silicon bulk substrates, and epitaxial-on-semiconductor (EPI) substrates and the like. Furthermore, although various embodiments will be described primarily with respect to materials and processes compatible with silicon-based semiconductor materials (e.g., silicon and alloys of silicon with germanium and / or carbon), the technology is not limited in this respect. More precisely, various embodiments can be implemented using any type of semiconductor material.

[0023] During pixel fabrication, silicon (Si) dangling bonds and / or weak bonds (e.g., silicon-hydrogen (Si-H) bonds) are believed to exist in photodiodes. These chemical structural defects can act as generation-recombination (GR) centers and increase current leakage into the photodiode, thereby causing dark current and resulting in white pixel (WP) defects. Decoupling plasma nitriding (DPN) treatment of the semiconductor surface forms silicon-nitrogen (Si-N) bonds, which reduces WP defects by decreasing the number of GR centers. After DPN treatment, a final SiO2 growth step is performed directly on the Si surface of the pixel to provide the gate oxide layer. However, the nitrogen added to the Si interface via DPN also reduces RTS noise in the transistor due to the nitrogen trapping and detrapping of charge carrier electrons (electrons) present in the gate oxide layer and the polysilicon gate interface. - ).

[0024] As will be discussed, an example of the teachings according to the invention relates to a pixel cell comprising a nitrogen-implanted region at the semiconductor-gate oxide interface in a region above a photodiode. The pixel cell further excludes nitrogen implantation at the semiconductor-gate oxide interface in the channel regions of the plurality of pixel transistors. Thus, Si-N bonds are formed at the semiconductor-gate oxide interface in the region above the photodiode, protecting or shielding the channel regions from nitrogen implantation at the semiconductor-gate oxide interface. By reacting Si dangling bonds to form Si-N bonds and replacing weaker bonds (e.g., Si-H bonds) with Si-N bonds at the semiconductor-gate oxide interface in the region above the photodiode, the number of GR centers is reduced, which in turn reduces the number of current leakage and WP defects. Furthermore, because the pixel cell excludes nitrogen implantation at the semiconductor-gate oxide interface in the channel regions of the plurality of pixel transistors, carrier trapping and detrapping-induced random telegraph signal (RTS) noise is reduced and / or prevented.

[0025] Figure 1A This is a schematic diagram illustrating an example of a pixel unit according to the teachings of this disclosure. For example... Figure 1A As illustrated in the depicted examples, pixel unit 100 may include multiple photodiodes (e.g., two photodiodes as shown), including photodiode PD1 102A and photodiode PD2 102B. In other examples, it should be understood that pixel unit 100 may include a smaller number of photodiodes (e.g., one photodiode in one example) or a larger number of photodiodes (e.g., four photodiodes in another example). Figure 1A In the illustrated example, photodiodes PD1 102A and PD2 102B are configured to generate image charge in response to incident light. Figure 1B This is a cross-sectional view illustrating an example of a portion of a pixel unit according to the teachings of this disclosure. For example... Figure 1BAs shown, pixel unit 100 has a semiconductor layer having a photodiode disposed therein, and a gate oxide layer formed on a semiconductor substrate above the semiconductor layer. A nitrogen-implanted semiconductor material-gate oxide adjacency interface is located in the region above the photodiode (e.g., photodiode PD1 102A). Therefore, Si-N bonds are formed at the semiconductor material-gate oxide interface in the region above photodiode PD1 102A, where Si dangling bonds react with nitrogen to form Si-N bonds, and weaker bonds (e.g., Si-H bonds) are replaced by Si-N bonds at the semiconductor material-gate oxide adjacency interface in the region above photodiode 102A. In some embodiments, nitrogen is implanted through the gate oxide layer and distributed on a very shallow silicon (Si) surface above photodiode 102A.

[0026] Return to reference Figure 1A A plurality of transfer transistors, including transfer transistors 106A and 106B, are each coupled between a floating diffusion section FD 108 and corresponding photodiodes PD1 102A and PD2 102B. In an example, the floating diffusion section FD 108 is a single floating diffusion section shared between photodiodes PD1 102A and PD2 102B and transfer transistors 106A and 106B. In operation, each of the transfer transistors 106A and 106B is coupled to transfer image charge generated in each corresponding photodiode PD1 102A and PD2 102B in response to corresponding transfer control signals TX1 and TX2 received at the corresponding transfer gates of the transfer transistors 106A and 106B to the shared floating diffusion section FD 108. In some embodiments, it should be understood that transfer transistors 106A and 106B may be referred to as transfer gates.

[0027] The source follower transistor SF 112 has a gate terminal coupled to a shared floating diffuser FD 108. In this example, the drain terminal of the source follower transistor SF 112 is coupled to a supply voltage (e.g., VDD). Thus, the source follower transistor SF 112 is coupled to generate image data at its source terminal in response to photogenerated image charge stored in the floating diffuser FD 108.

[0028] A row select transistor 114 is coupled between the source terminal of the source follower transistor SF 112 and the output bit line 144, as shown. Thus, the row select transistor 114 is coupled to selectively output image data at the source terminal of the source follower transistor SF 112 in response to the row select control signal RS.

[0029] Pixel unit 100 also includes a reset transistor 110 coupled between a supply voltage (e.g., VRST) and a floating diffuser FD 108. For example, the drain terminal of reset transistor 110 is coupled to the supply voltage VRST, and the source terminal of reset transistor 110 is coupled to the floating diffuser FD 108. The source terminal of reset transistor 110 is further coupled to the floating diffuser FD 108, photodiodes PD1 102A and PD2 102B via corresponding transfer transistors 106A and 106B. Thus, reset transistor 110 is coupled to reset pixel unit 100 in response to a reset control signal RST. For example, the reset transistor may be configured to reset the charge in the floating diffuser FD 108 and photodiodes PD1 102A and PD2 102B. In one example, the supply voltage VRST may be the same as the supply voltage VDD and is supplied from a voltage power source.

[0030] Figure 1C This is a cross-sectional view illustrating a portion of a pixel unit according to the teachings of this disclosure. Reference Figure 1C The pixel unit 100 does not have nitrogen implanted at the semiconductor material-gate oxide adjacent interface located in the channel region of the multiple pixel transistors.

[0031] In some embodiments, the channel region of pixel unit 100 may be included in a plurality of pixel transistors. For example, the plurality of pixel transistors may include a reset transistor, a source follower transistor, and a row select transistor. In some embodiments, the plurality of pixel transistors include a transfer transistor, a reset transistor, a source follower transistor, and a row select transistor. In some embodiments, the plurality of pixel transistors include a transfer transistor, a floating diffuser, a reset transistor, a source follower transistor, a dual floating transistor, and a row select transistor.

[0032] Therefore, in some embodiments, a pixel unit includes: a photodiode disposed in a semiconductor material layer formed on a semiconductor substrate, a floating diffusion portion, multiple doped regions of multiple pixel transistors of the pixel; a gate oxide layer disposed above the semiconductor material layer; and multiple gate electrodes of the multiple pixel transistors of the pixel disposed above the gate oxide layer. A nitrogen-implanted region exists at the semiconductor material-gate oxide proximity interface in the region above the photodiode, and the semiconductor material-gate oxide proximity interface does not have nitrogen implanted in the channel regions of the multiple pixel transistors. The nitrogen-implanted region at the semiconductor material-gate oxide proximity interface in the region above the photodiode can generate Si-N bonds, reducing defects at the semiconductor material-gate oxide proximity interface and preventing charge carrier trapping and detrapping at the semiconductor material-gate oxide proximity interface, thereby reducing both dark current noise associated with defects at the semiconductor material-gate oxide proximity interface above the photodiode and trapping and detrapping-induced random telegraph signal (RTS) noise.

[0033] Figure 2 This is a flowchart illustrating an example of the process of creating a pixel unit according to the teachings of this disclosure. (See reference) Figure 2 The pixel unit manufacturing process 200 includes: providing a semiconductor material layer (step 210); forming a photodiode, a floating diffuser, and multiple doped regions of a plurality of pixel transistors of the pixel in the semiconductor material layer (step 220); and then forming a gate oxide layer on the semiconductor material layer (step 230). In some instances, the gate oxide layer may comprise silicon dioxide (SiO2), which can be manufactured using wet oxidation of a semiconductor material (e.g., silicon) or using an in-situ vapor generation (ISSG) oxidation process of the semiconductor material. In some embodiments, the semiconductor material layer may be formed on a bulk semiconductor substrate, for example, by an epitaxial growth process. In some embodiments, depending on the transistor processing technology and performance requirements, such as random telegraph signal (RTS) noise requirements, the thickness of the gate oxide layer may be [specified value]. arrive The changes between them.

[0034] Then, multiple gate electrodes of the multiple pixel transistors of the pixel are formed on the gate oxide layer (step 240). A photoresist is formed on a semiconductor material layer (e.g., on the top surface of the semiconductor material layer), which is patterned to selectively mask the channel regions of the multiple pixel transistors of the pixel, exposing the region above the photodiode (step 250). Figure 3A This is a plan view illustrating an example of a portion of a pixel unit after photoresist patterning, according to the teachings of this disclosure. Figure 3AAs shown, the pixel has a photoresist applied across a channel region, which includes, for example, a reset transistor, a source follower transistor, and a row select transistor.

[0035] Refer again Figure 2 After nitrogen is implanted at the semiconductor material-gate oxide adjacent interface in the region above the photodiode where photoresist has been applied (step 270), a shallow nitrogen region is formed between the gate oxide layer and the semiconductor material. Figure 3B This is a cross-sectional view illustrating an example of a portion of a pixel unit according to the teachings of this disclosure. For example... Figure 3B As shown, nitrogen implantation occurs in the exposed region of the semiconductor material-gate oxide interface, but is blocked in the channel region containing the pixel transistors that are masked by photoresist.

[0036] Refer again Figure 2 After nitrogen implantation, the photoresist is removed to provide non-nitrogen-implanted channel regions for the multiple pixel transistors of the pixel (step 280). In some embodiments, the photoresist is removed from the semiconductor material layer, for example by a stripping and cleaning process, such as an SC1 stripping and cleaning process or a sulfuric acid and hydrogen peroxide mixture (SPM) photoresist stripping and cleaning process (step 290).

[0037] In some embodiments, the photoresist is made of a material that is substantially impermeable to nitrogen implantation (e.g., 95% or less impermeable, 97% or less impermeable, 99% or less impermeable, or 100% impermeable). For example, the photoresist may comprise an epoxy polymer or a mixture of diazonaphthoquinone and a phenolic resin.

[0038] In some embodiments, implanting nitrogen at the semiconductor material-gate oxide adjacent interface in the region above the photodiode comprises subjecting the semiconductor material-gate oxide adjacent interface to plasma immersion ion implantation (PIII).

[0039] Nitrogen implantation can occur on a very shallow silicon surface of the semiconductor material in an unmasked region near the semiconductor material-gate oxide interface. In one embodiment, nitrogen implantation is performed on a very shallow silicon surface of the semiconductor material in an unmasked or exposed region of the gate oxide layer above an individual photodiode. Nitrogen implantation quenches Si dangling bonds by forming Si-N bonds and / or replaces Si-H bonds with Si-N bonds (e.g., by forming SiO₂) at the semiconductor material-gate oxide interface. x N y ).

[0040] Refer again Figure 2The process may further include implanting a pinning layer on the photodiode (step 260). In some embodiments, the pinning layer may be implanted on the photodiode after nitrogen is implanted at the semiconductor material-gate oxide adjacent interface in the region above the photodiode. In some embodiments, the pinning layer may be implanted on the photodiode before nitrogen is implanted at the semiconductor material-gate oxide adjacent interface in the region above the photodiode. Figure 3C This is a cross-sectional view illustrating an example of a portion of a pixel unit according to the teachings of this disclosure. For example... Figure 3C As shown, the pixel unit includes a nitrogen-implanted semiconductor material-gate oxide proximity interface disposed on a pinned layer, which in turn is disposed on a photodiode. The channel region of the pixel transistor in the pixel unit does not have nitrogen implanted at the semiconductor material-gate oxide proximity interface.

[0041] In some embodiments, nitrogen may also be implanted into the sidewalls and bottom of a shallow trench isolation (STI) structure disposed between the photodiode (PD) and the pixel transistor region, thereby providing isolation between the photodiode (PD) and the pixel transistor (e.g., a reset transistor, a source follower transistor, and the like) to further reduce dangling bonds at the trench sidewalls and bottom surface that could lead to trapping sites, and thus further reduce dark current noise. For example, during the formation of the STI structure, after oxidizing the sidewalls and bottom of the STI structure and forming a pad oxide layer on the sidewalls and bottom of the STI structure, and before backfilling (e.g., oxide filling) the trench structure of the STI structure with a dielectric, a shallow implant of nitrogen may be implanted under the pad oxide layer by plasma implantation at various tilt angles (e.g., implantation at 5 to 45 degrees) so that the shallow implant of nitrogen completely covers the sidewall and bottom surfaces of the STI structure. Figure 3D It is a cross-sectional view illustrating a portion of a pixel unit according to the teachings of this disclosure. Figure 3D An exemplary pixel cell structure with a nitrogen-implanted semiconductor-gate oxide proximity interface is illustrated, the interface being disposed above the sidewall / bottom surface of an STI structure between a pinned layer and the regions of a photodiode and a pixel transistor (e.g., a source follower transistor, a reset transistor, a row select transistor). In an embodiment, at least a portion of the gate of the pixel transistor may be formed above the STI structure. Reiterating, the shallow trench structure with sidewall and bottom surfaces disposed near the photodiode is nitrogen-implanted. The channel regions of the pixel transistors in the pixel cell are not nitrogen-implanted at the semiconductor-gate oxide proximity interface.

[0042] Examples of pixel cells disclosed herein offer numerous advantages. For example, pixel cells can be fabricated using existing methods. Compared to pixel cells that have not undergone nitrogen implantation at the semiconductor-gate oxide proximity interface in the region above the photodiode, and / or compared to pixel cells that have nitrogen implantation both at the semiconductor-gate oxide proximity interface in the region above the photodiode and above the transistor channel region, the pixel cells may have reduced white pixels and reduced random telegraph signal noise. For example, compared to pixels that have not undergone nitrogen implantation at the semiconductor-gate oxide proximity interface in the region above the photodiode, the pixel may have a white pixel reduction of from 140 ppm to 60 ppm. Compared to pixels that have not undergone nitrogen implantation at the semiconductor-gate oxide proximity interface in the region above the photodiode, the pixel may have a white pixel reduction of up to 50% or more. In some embodiments, compared to pixels that have not undergone nitrogen implantation at the semiconductor-gate oxide proximity interface in the region above the photodiode, the pixel has a dark current reduction of from 2.4 electrons / s to 2.0 electrons / s. In some embodiments, the pixel exhibits a dark current reduction of up to approximately 20% compared to pixels that have not undergone nitrogen implantation at the semiconductor material-gate oxide proximity interface in the region above the photodiode. In some embodiments, the pixel exhibits a random telegraph signal (RTS) noise reduction of from approximately 150 ppm to approximately 70 ppm compared to pixels that have undergone nitrogen implantation in the channel regions of multiple pixel transistors (e.g., both at the semiconductor material-gate oxide proximity interface in the region above the photodiode and above the transistor channel region).

[0043] Figure 4 This is a block diagram illustrating one example of an imaging system 300. The imaging system 300 includes a pixel array 310, control circuitry 320, readout circuitry 330, and functional logic 340. In one example, the pixel array 310 is a two-dimensional (2D) array of photodiodes or image sensor pixels 315 (e.g., pixels P1, P2…, Pn). As illustrated, the photodiodes are arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of people, places, objects, etc., which can then be used to present 2D images of people, places, objects, etc. However, in other examples, it should be understood that the photodiodes need not be arranged in rows and columns, and other configurations may be used.

[0044] In one example, after the image sensor photodiode / pixel 315 in pixel array 310 has acquired its image data or image charge, the image data is read out by readout circuit 330 via bit line 350 and then transmitted to functional logic 340. In various examples, readout circuit 330 may include amplifier circuitry, analog-to-digital (ADC) conversion circuitry, or others. Functional logic 340 can easily store or even manipulate image data by applying post-processing image effects such as cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others. In one example, readout circuit 330 may read out one line of image data at a time along the readout column line (shown), or may use various other techniques (not shown) to read out image data, such as simultaneous serial readout of all pixels or fully parallel readout.

[0045] In one example, control circuitry 320 is coupled to pixel array 310 to control the operation of multiple photodiodes within pixel array 310. For example, control circuitry 320 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal, used to simultaneously enable all pixels within pixel array 310 to capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal, causing each row, column, or group of pixels to be sequentially enabled during consecutive acquisition windows. In yet another example, image acquisition is synchronized with a lighting effect (e.g., flash).

[0046] refer to Figure 4 In the depicted example, the imaging system 300 may include: a pixel array 310 comprising a plurality of pixel units 315 as described herein; control circuitry 320 coupled to the pixel array 310 to control the operation of the pixel units 315; and readout circuitry 330 coupled to the pixel array 310 to read image data from the pixel units 315. The imaging system may further include functional logic 340 coupled to the readout circuitry to store image data from the pixel array.

[0047] In one example, each pixel unit 315 of the pixel array 310 in the imaging system 300 may include: a photodiode disposed in a semiconductor material layer, a floating diffusion portion, multiple doped regions of multiple pixel transistors of the pixel; a gate oxide layer disposed above the semiconductor material layer; and multiple gate electrodes of the multiple pixel transistors of the pixel disposed above the gate oxide layer, as described above. A nitrogen-implanted region exists at the semiconductor material-gate oxide adjacent interface in the region above the photodiode, and the semiconductor material-gate oxide adjacent interface does not have nitrogen implanted in the channel regions of the multiple pixel transistors. In some embodiments, the nitrogen-implanted region at the semiconductor material-gate oxide adjacent interface in the region above the photodiode contains Si-N bonds. For example, compared to a semiconductor material-gate oxide adjacent interface that has not been nitrogen-implanted, the nitrogen-implanted region at the semiconductor material-gate oxide adjacent interface in the region above the photodiode may contain fewer Si dangling bonds and Si-H bonds.

[0048] In one example, each pixel unit 315 of the pixel array 310 in the imaging system 300 may further include a transfer gate disposed on a semiconductor material between a photodiode and a floating diffuser. The transfer gate is coupled to selectively transfer image charge from the photodiode to the floating diffuser.

[0049] In some embodiments, in a given pixel unit 315, the photodiode is a first photodiode among a plurality of photodiodes adapted to generate image charge in response to incident light, and the transfer gate is a first transfer gate among a plurality of transfer gates. The pixel unit 315 may further include a second photodiode among a plurality of photodiodes and a second transfer gate among a plurality of transfer gates, as shown in FIG1 and described above.

[0050] As discussed above, in some embodiments, the plurality of pixel transistors includes a reset transistor, a source follower transistor, and a row select transistor. In some embodiments, the plurality of pixel transistors includes a transfer transistor, a reset transistor, a source follower transistor, and a row select transistor. In some embodiments, the channel region of the plurality of pixel transistors is included in the region above the transfer resistor, the floating diffuser, the reset transistor, the source follower transistor, and the row select transistor.

[0051] As discussed above, the nitrogen-implanted region at the semiconductor-gate oxide adjacency interface in the region above the photodiode includes Si-N bonds. For example, compared to a semiconductor-gate oxide adjacency interface without nitrogen implantation, the nitrogen-implanted region at the semiconductor-gate oxide adjacency interface in the region above the photodiode may have fewer Si dangling bonds and Si-H bonds.

[0052] Compared to pixel cells that have not undergone nitrogen implantation at the semiconductor-gate oxide proximity interface in the region above the photodiode, and / or compared to pixel cells that have nitrogen implantation both at the semiconductor-gate oxide proximity interface in the region above the photodiode and above the transistor channel region, each pixel cell may have reduced white pixels and reduced random telegraph signal noise. For example, compared to pixels that have not undergone nitrogen implantation at the semiconductor-gate oxide proximity interface in the region above the photodiode, each pixel cell may have a white pixel reduction of from 140 ppm to 60 ppm. Compared to pixels that have not undergone nitrogen implantation at the semiconductor-gate oxide proximity interface in the region above the photodiode, each pixel cell may have a white pixel reduction of up to 50% or more. Compared to pixels that have not undergone nitrogen implantation at the semiconductor-gate oxide proximity interface in the region above the photodiode, each pixel cell may have a dark current reduction of from 2.4 electrons / s to 2.0 electrons / s. Each pixel cell can have up to approximately 20% dark current reduction compared to pixels that have not undergone nitrogen implantation at the semiconductor material-gate oxide proximity interface in the region above the photodiode. In some embodiments, each pixel cell has a random telegraph signal (RTS) noise reduction of from approximately 150 ppm to approximately 70 ppm compared to pixels that have nitrogen implanted in the channel regions of multiple pixel transistors (e.g., both at the semiconductor material-gate oxide proximity interface in the region above the photodiode and above the transistor channel region).

[0053] In one example, the imaging system 300 may be included in a digital camera, mobile phone, laptop computer, automobile, or the like. Additionally, the imaging system 300 may be coupled to other hardware components such as a processor (general purpose or otherwise), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), illumination / flash memory, electrical inputs (keyboard, touchscreen, trackpad, mouse, microphone, etc.), and / or a display. These other hardware components may send instructions to the imaging system 300, retrieve image data from the imaging system 300, or manipulate the image data supplied by the imaging system 300.

[0054] The above description of the examples illustrating this invention includes the content described in the abstract and is not intended to be exhaustive or limiting to the precise forms disclosed. While specific embodiments and examples of the invention have been described herein for illustrative purposes, various equivalent modifications can be made without departing from the broader spirit and scope of the invention. In fact, it should be understood that specific examples of voltage, current, frequency, power range values, time, etc., are provided for illustrative purposes, and other values ​​may be used in other embodiments and examples according to the teachings of this invention.

[0055] Based on the above detailed description, these modifications can be made to the embodiments of the present invention. The terminology used in the appended claims should not be construed as limiting the invention to the specific embodiments disclosed in this specification and claims. Rather, the scope will be fully defined by the appended claims, which will be understood according to the established principles of interpretation of the claims. Therefore, this specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A method for manufacturing a pixel unit, comprising: Provides a semiconductor material layer; Multiple doped regions of a plurality of pixel transistors, including photodiodes, floating diffusers, and pixels, are formed in the semiconductor material layer. A gate oxide layer is formed on the semiconductor material layer; Multiple gate electrodes of the plurality of pixel transistors of the pixel are formed on the gate oxide layer; The channel regions of the plurality of pixel transistors of the pixel are selectively masked with a photoresist, exposing the region above the photodiode; Nitrogen is implanted at the semiconductor material-gate oxide adjacent interface in the region above the photodiode and at the sidewall and bottom surfaces of a shallow trench isolation structure disposed near the photodiode, wherein the shallow trench isolation structure extends to a depth below the pinning layer and wherein the shallow trench isolation structure separates the gate electrode from the photodiode. and Remove the photoresist to provide the non-nitrogen-implanted channel region of the plurality of pixel transistors of the pixel.

2. The method of claim 1, wherein removing the photoresist comprises stripping and cleaning the semiconductor material layer to remove the photoresist by oxygen plasma.

3. The method of claim 1, further comprising implanting the nitrogen at the semiconductor material-gate oxide adjacent interface in the region above the photodiode, and then implanting the pinning layer on the photodiode.

4. The method of claim 1, further comprising implanting the pinning layer on the photodiode before implanting the nitrogen at the semiconductor material-gate oxide adjacent interface in the region above the photodiode.

5. The method according to claim 1, wherein the photoresist is impermeable to nitrogen implantation.

6. The method of claim 1, wherein implanting nitrogen at the semiconductor material-gate oxide adjacent interface in the region above the photodiode comprises subjecting the semiconductor material-gate oxide adjacent interface in the region above the photodiode to plasma immersion ion implantation of PIII.

7. The method of claim 1, wherein the nitrogen implantation occurs on the shallow silicon surface of the semiconductor material in an unmasked region of the gate oxide layer above the photodiode.

8. The method of claim 1, wherein the nitrogen implantation quenches Si dangling bonds, replaces Si-H bonds with Si-N bonds, or a combination thereof, at the semiconductor material-gate oxide adjacent interface.

9. The method of claim 1, wherein the plurality of pixel transistors includes a reset transistor, a source follower transistor, and a row select transistor.

10. A pixel unit comprising: Multiple doped regions of a photodiode, a floating diffuser, and multiple pixel transistors of a pixel are disposed in a semiconductor material layer; A gate oxide layer disposed on the semiconductor material layer, the gate oxide layer including a nitrogen-implanted region at the semiconductor material-gate oxide adjacent interface in the region above the photodiode; and The plurality of gate electrodes of the plurality of pixel transistors of the pixel disposed on the gate oxide layer, and A shallow trench isolation (STI) structure is disposed near the photodiode, the shallow trench isolation structure having a sidewall surface and a bottom surface at least partially disposed beneath the gate oxide layer, wherein the sidewall surface and the bottom surface are implanted with nitrogen, wherein the shallow trench isolation structure extends to a depth beneath the pinning layer, and wherein the shallow trench isolation structure separates the gate electrode from the photodiode. The semiconductor material-gate oxide adjacent interface is free of nitrogen implantation in the channel region of the plurality of pixel transistors.

11. The pixel unit of claim 10, wherein the nitrogen-implanted region at the semiconductor material-gate oxide adjacent interface in the region above the photodiode comprises Si-N bonds.

12. The pixel unit of claim 10, wherein the nitrogen-implanted region at the semiconductor material-gate oxide adjacent interface in the region above the photodiode comprises fewer Si dangling bonds and Si-H bonds compared to a semiconductor material-gate oxide adjacent interface that has not yet been implanted with nitrogen.

13. The pixel unit of claim 10, wherein the gate oxide layer has a thickness of 30 Å to 75 Å.

14. The pixel unit of claim 10, further comprising a shallow trench structure disposed near the photodiode, the shallow trench structure having a nitrogen-embedded sidewall surface and a bottom surface.

15. The pixel unit of claim 10, wherein the pixel comprises a reduction of white pixels from 140 ppm to 60 ppm compared to pixels that have not yet undergone nitrogen implantation at the semiconductor material-gate oxide adjacent interface in the region above the photodiode.

16. The pixel unit of claim 10, wherein the pixel comprises at least 50% reduction in white pixels compared to pixels that have not yet undergone nitrogen implantation at the semiconductor material-gate oxide adjacent interface in the region above the photodiode.

17. The pixel unit of claim 10, wherein the pixel comprises a reduction in dark current from 2.4 electrons / s to 2.0 electrons / s compared to a pixel that has not yet undergone nitrogen implantation at the semiconductor material-gate oxide adjacent interface in the region above the photodiode.

18. The pixel unit of claim 10, wherein the pixel comprises at least a 20% reduction in dark current compared to a pixel that has not yet undergone nitrogen implantation at the semiconductor material-gate oxide adjacent interface in the region above the photodiode.

19. The pixel unit of claim 10, wherein the pixel includes a random telegraph signal (RTS) noise reduction of from 150 ppm to 70 ppm compared to a pixel comprising nitrogen in the channel region of the plurality of pixel transistors.

20. The pixel unit of claim 10, wherein the plurality of pixel transistors includes a reset transistor, a source follower transistor, and a row select transistor.

21. An imaging system comprising: Pixel unit array, wherein each of the pixel units comprises: Photodiodes, floating diffusers, and multiple doped regions of multiple pixel transistors are disposed in a semiconductor material layer; A gate oxide layer disposed on the semiconductor material layer; and The plurality of gate electrodes of the plurality of pixel transistors of the pixel disposed on the gate oxide layer; The pixel unit includes a nitrogen-implanted region at the semiconductor material-gate oxide adjacent interface in the region above the photodiode, and The pixel unit wherein no nitrogen is implanted in the channel region of the plurality of pixel transistors; and A shallow trench isolation (STI) structure is disposed near the photodiode, the shallow trench isolation structure having a sidewall surface and a bottom surface at least partially disposed beneath the gate oxide layer, wherein the sidewall surface and the bottom surface are implanted with nitrogen, wherein the shallow trench isolation structure extends to a depth beneath the pinning layer, and wherein the shallow trench isolation structure separates the gate electrode from the photodiode. Control circuitry coupled to the pixel array to control the operation of the pixel array; and A readout circuit is coupled to the pixel unit array to read image data from the pixel unit array.

22. The imaging system of claim 21, further comprising functional logic coupled to the readout circuit for storing image data from the pixel unit array.

23. The imaging system of claim 21, wherein the plurality of pixel transistors includes a reset transistor, a source follower transistor, and a row select transistor.

24. The imaging system of claim 21, wherein the nitrogen-implanted region at the semiconductor material-gate oxide adjacent interface in the region above the photodiode comprises Si-N bonds.

25. The imaging system of claim 21, wherein the nitrogen-implanted region at the semiconductor material-gate oxide adjacent interface above the photodiode comprises fewer Si dangling bonds and Si-H bonds compared to the unimplanted semiconductor material-gate oxide adjacent interface.

26. The imaging system of claim 21, wherein the gate oxide layer has a thickness of 30 Å to 75 Å.

27. The imaging system of claim 21, wherein each of the pixel units comprises a reduction of white pixels from 140 ppm to 60 ppm compared to pixels that have not yet undergone nitrogen implantation at the semiconductor material-gate oxide adjacent interface in the region above the photodiode.

28. The imaging system of claim 21, wherein each of the pixel units comprises up to 50% reduction in white pixels compared to pixels that have not yet undergone nitrogen implantation at the semiconductor material-gate oxide adjacent interface in the region above the photodiode.

29. The imaging system of claim 21, wherein each of the pixel units comprises a dark current reduction of from 2.4 electrons / second to 2.0 electrons / second compared to pixels that have not yet undergone nitrogen implantation at the semiconductor material-gate oxide adjacent interface in the region above the photodiode.

30. The imaging system of claim 21, wherein each of the pixel units comprises a dark current reduction of up to 20% compared to pixels that have not yet undergone nitrogen implantation at the semiconductor material-gate oxide adjacent interface in the region above the photodiode.

31. The imaging system of claim 21, wherein each of the pixel units comprises a reduced random telegraph signal (RTS) noise of 150 ppm to 70 ppm compared to pixels comprising nitrogen in the channel region of the plurality of pixel transistors.

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