Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the semiconductor device includes: a substrate including a core device region and an input / output device (I / O) device region; a plurality of core devices in the core device, each of the plurality of core devices including a first active region extending along a first direction; and a plurality of first input / output device (I / O) transistors in the input / output device region, each of the plurality of first input / output device (I / O) transistors including a second active region extending along the first direction. The first active region includes a first width along a second direction perpendicular to the first direction, and the second active region includes a second width along the second direction. The second width is greater than the first width.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices for high voltage applications and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Over the course of integrated circuit development, functional density has generally increased (i.e., the number of interconnected devices per chip area) while decreasing geometry size (i.e., the smallest component (or line) that can be manufactured using a manufacturing process). This process of miniaturization generally provides benefits by increasing production efficiency and reducing associated costs. However, such miniaturization is also accompanied by increased complexity in the design and manufacture of devices incorporating these integrated circuits, and in order to achieve these advances, similar developments in device manufacturing are needed.

[0003] The miniaturization of semiconductor devices has also reduced the thickness of the gate dielectric layer, which leads to a reduced gate voltage to avoid device failure. However, the supply voltage from the external circuit has not kept up with the pace of miniaturization of semiconductor devices. Although the thickness of the gate dielectric layer has been reduced by several times, the supply voltage has only been reduced from about 5 volts to about 3.3 volts. This unequal miniaturization trend has led to an increasing electric field in the gate dielectric layer near the drain. The increased electric field in turn leads to hot carrier injection (HCI, or hot carrier effect (HCE)), which describes a phenomenon in which charge carriers (electrons or holes) gain high kinetic energy due to the presence of high electric fields. The hot carrier effect is undesirable because it degrades device performance and causes leakage. The hot carrier effect is particularly relevant to input / output (I / O) devices because they interface with external circuits that operate at the supply voltage. Known techniques such as increasing channel length and increasing gate dielectric thickness have been implemented to mitigate the effects caused by the hot carrier effect. However, these known techniques may not satisfactorily address device degradation or leakage caused by hot carrier effects. Summary of the invention

[0004] Some embodiments of the present disclosure provide a semiconductor device comprising: a substrate, a plurality of core devices, and a plurality of first input / output (I / O) transistors. The substrate includes a core device region and an input / output (I / O) device region. The plurality of core devices are in the core device region, and each of the plurality of core devices includes a first active region extending along a first direction. The plurality of first input / output (I / O) transistors are in the input / output device region, and each of the plurality of first input / output transistors includes a second active region extending along the first direction. The first active region includes a first width along a second direction perpendicular to the first direction, and the second active region includes a second width along the second direction, wherein the second width is greater than the first width.

[0005] Other embodiments of the present disclosure provide a semiconductor device comprising: a substrate, a plurality of core devices, a plurality of first input / output (I / O) transistors, and a plurality of second input / output transistors. The plurality of core devices are above the substrate, and each of the plurality of core devices includes a first active region extending along a first direction. The plurality of first input / output (I / O) transistors are above the substrate, and each of the plurality of input / output transistors includes a second active region extending along the first direction. The plurality of second input / output transistors are above the substrate, and each of the plurality of second input / output transistors includes a third active region extending along the first direction. The first active region includes a first width along a second direction perpendicular to the first direction, the second active region includes a second width along the second direction, and the third active region includes a third width along the second direction. The first width is equal to the second width, and the third width is greater than the first width.

[0006] Still other embodiments of the present disclosure provide a method for manufacturing a semiconductor device, comprising: providing a substrate comprising a first region and a second region; depositing a hard mask layer over the substrate; selectively forming a plurality of spacer features over the hard mask layer in the first region; selectively forming a material feature over the hard mask layer in the second region; etching the hard mask layer using the plurality of spacer features and the material features as an etching mask to form a patterned hard mask layer; and etching the substrate using the patterned hard mask layer as an etching mask, wherein each of the plurality of spacer features and the material features extends longitudinally along a first direction, wherein each of the plurality of spacer features has a first width along a second direction perpendicular to the first direction, wherein the material feature has a second width along the second direction, wherein the second width is greater than the first width. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description and the attached Figure 1The various aspects of the present disclosure will be best understood by reading together. It is emphasized that, according to standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to various aspects of the present disclosure;

[0009] Figures 2 to 16 According to various aspects of the present disclosure, for example, Figure 1 partial schematic cross-sectional views of a workpiece at various manufacturing stages associated with the method;

[0010] Fig.17 and Fig.18 is a partial schematic cross-sectional view of a semiconductor device according to various aspects of the present disclosure.

[0011]

Explanation of symbols

[0012] 100: Method

[0013] 102: Blocks

[0014] 104: Blocks

[0015] 106: Blocks

[0016] 108: Blocks

[0017] 110: Block

[0018] 112: Block

[0019] 114: Blocks

[0020] 116: Blocks

[0021] 200:Semiconductor device (workpiece)

[0022] 202:Substrate

[0023] 203: Pad oxide layer

[0024] 204: Hard Mask Layer

[0025] 206: First floor

[0026] 208: Second floor

[0027] 209: Sacrificial layer

[0028] 210: Mandrel Features

[0029] 211: Spacer layer

[0030] 212: Spacer Features

[0031] 214: Bottom anti-reflective coating

[0032] 216: Photoresist layer

[0033] 217: Material Characteristics

[0034] 220: Isolation Structure

[0035] 222: Gate structure

[0036] 224: first gate section

[0037] 226: second gate segment

[0038] 228: Third gate segment

[0039] 230: Fourth gate segment

[0040] 232: Virtual gate dielectric layer

[0041] 234: Fifth gate segment

[0042] 240: first fin (first semiconductor fin, first active region)

[0043] 240-1: First fin

[0044] 240-2: First fin

[0045] 240-3: First fin

[0046] 240-4: First fin

[0047] 240-5: First fin

[0048] 240-6: First fin

[0049] 250: second fin (second semiconductor fin, second active region, mesa)

[0050] 252: Third fin

[0051] 1000: First Area

[0052] 1000A: First sub-area

[0053] 1000B: Second sub-area

[0054] 2000: Second Region

[0055] 3000: Third Area

[0056] W1: First width

[0057] W2: Second width

[0058] W3: Third width DETAILED DESCRIPTION

[0059] It is understood that the disclosure that follows provides many different implementations or embodiments for implementing different features of various implementations. Specific embodiments of components and configurations are described below to simplify the disclosure. Of course, these are merely embodiments and are not intended to be limiting. For example, in the subsequent description, forming a first feature above or on a second feature may include an implementation in which the first and second features are formed in direct contact, and may also include forming additional features that may be inserted between the first and second features, so that the first and second features may not be in direct contact. In addition, the disclosure may repeat numbers and / or letters in various embodiments. Such repetition is for the sake of simplicity and clarity, and the repetition itself does not mean the relationship between the various embodiments and / or configurations discussed.

[0060] In the disclosure that follows, a feature is formed on, connected to, and / or coupled to another feature, which may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features are formed and inserted between the features so that the features may not be in direct contact. In addition, to facilitate description of the relationship between one feature and another, spatially relative terms such as "lower," "higher," "horizontal," "vertical," "above," "above," "below," "below," "up," "down," "top," "bottom," and the like, and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," and the like) are used. Spatially relative terms are intended to encompass different orientations of a device including multiple features.

[0061] In addition, when describing a number or a range of numbers with "about," "approximately," and the like, such terms are intended to encompass a plurality of numbers within a reasonable range including the described number, such as within + / -10% of the number, or other values ​​understood by those skilled in the art. For example, the term "about 5 nm (nanometers)" encompasses a size range from 4.5 nm to 5.5 nm.

[0062] The present disclosure relates to a structure for high voltage applications and a method for forming the same. Specifically, the present disclosure relates to an input / output (I / O) transistor whose interface is between a core device in a core device region and an external circuit. In some embodiments, an input / output transistor according to the present disclosure includes a semiconductor fin that is wider than a semiconductor fin in a core device region. In some implementations, the wider semiconductor fin may be referred to as a mesa. In some alternative embodiments, an input / output transistor according to the present disclosure includes a combination of a first semiconductor fin and a second semiconductor fin, the first semiconductor fin being similar in size to the semiconductor fin in the core device region, and the second semiconductor fin being wider than the first semiconductor fin. The wider semiconductor fin allows the input / output transistor of the present disclosure to operate at a voltage equal to or greater than 3.3V. A method for forming an input / output transistor of the present disclosure is also provided.

[0063] The scaling down of semiconductor devices has its fair share of challenges in many areas. One of the challenges comes from a phenomenon known as hot carrier injection (HCI) or hot carrier effect (HCE). Multi-gate devices such as fin field effect transistors (FinFETs) include a gate structure surrounding the active region to provide improved channel control and resistance to short channel effect (SCE) compared to known planar devices. The improved channel control of the FinFET may cause impact ionization and increased lateral electric fields near the drain due to the hot carrier effect, resulting in gate dielectric damage and device failure. The hot carrier effect is more pronounced when the input / output (I / O) device operates at a supply voltage from an external circuit, which is much higher than the operating voltage for the core device (such as a logic device or a memory device). Known, extended gates and thicker gate dielectrics have been implemented for input / output FinFETs to compensate for damage and device failure due to the hot carrier effect. However, while some of these known techniques may work, they may not produce reliable input / output FinFET devices with good service life. Some other known techniques involve the use of additional circuits to reduce the supply voltage to avoid hot carrier effects at the input / output FinFET devices. However, adding additional circuits means additional costs and may not always be ideal.

[0064] The present disclosure provides a method for forming a semiconductor device including an input / output fin field effect transistor device having a good service life when operated under a supply voltage from an external circuit. In some implementations, a hard mask layer is deposited over a substrate having a first region and a second region. Then, a double patterning or multi-patterning technique is used to form a plurality of spacer features over the hard mask layer in the first region, and a lithography technique is used to form a plurality of material features over the hard mask layer in the second region. Each of the plurality of material features is wider than each of the plurality of spacer features. The material features and the spacer features are then used as an etching mask to pattern the hard mask layer. Then, the patterned hard mask layer is used to pattern the substrate to form a plurality of first active regions in the first region and a plurality of second active regions in the second region. A plurality of narrower first active regions may be used to form a plurality of core devices and a plurality of input / output fin field effect transistor devices, and a plurality of wider second active regions may be used to form an input / output fin field effect transistor device suitable for operating under a supply voltage, such as about 3.3V or higher.

[0065] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1 is a flow chart of a method 100 for manufacturing a semiconductor device according to various aspects of the present disclosure. In some implementations, the semiconductor device includes a multi-gate transistor in which the gate structure wraps around multiple sides of the active region in its channel region. Embodiments of the multi-gate transistor include fin field effect transistors. Method 100 is merely one embodiment and is not intended to limit the present disclosure to that explicitly described in method 100. Additional steps may be provided before, during, and after method 100, and some of the steps described may be moved, replaced, or deleted for additional implementations of method 100. For simplicity, not all steps are described in detail herein. Method 100 will be described below in conjunction with Figures 2 to 16 2 is a partial cross-sectional view of a workpiece 200 shown in FIG. Because a semiconductor device will be formed from the workpiece 200 , the workpiece 200 may be referred to as a semiconductor device 200 as the context requires.

[0066] The semiconductor device 200 may be included in a microprocessor, a memory, and / or other integrated circuit (IC) devices. In some implementations, the semiconductor device 200 may be part of an integrated circuit chip, a system on a chip (SoC), or a portion thereof, which includes various passive and active microelectronic devices, such as: resistors, capacitors, inductors, diodes, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused metal oxide (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. Figures 2 to 16 The illustration of the semiconductor device 200 in FIG. 2 has been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features may be added to the semiconductor device 200 , and in other implementations of the semiconductor device 200 , some of the features described below may be replaced, modified, or deleted.

[0067] See also Figure 1 and Figure 2 , method 100 includes block 102, wherein a workpiece 200 is received, the workpiece 200 including a substrate 202. For the avoidance of doubt, workpiece 200 is used herein to refer to a workpiece on which method 100 is performed. Figure 2When only substrate 202 is shown, the same is true in the case where more layers and features will be formed on substrate 202 in subsequent operations. Substrate 202 has a first region 1000 and a second region 2000. In the depicted embodiment, substrate 202 is a bulk substrate including silicon. Alternatively, in some implementations, substrate 202 includes a bulk substrate (including, for example, silicon) and one or more material layers disposed above the bulk substrate. For example, the one or more material layers may include a semiconductor layer stack having various semiconductor layers (e.g., a heterostructure) disposed above the bulk substrate, wherein the semiconductor layer stack is subsequently patterned to form a plurality of fins. The semiconductor layer may include any suitable semiconductor material, such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or a combination thereof. Depending on the design requirements of semiconductor device 200, the semiconductor layer may include the same or different materials, etching rates, composition atomic percentages, composition weight percentages, thicknesses, and / or configurations. In some implementations, the semiconductor layer stack includes alternating semiconductor layers, such as semiconductor layers composed of a first material and semiconductor layers composed of a second material. For example, the semiconductor layer stack alternates silicon layers and silicon germanium layers (e.g., Si / SiGe / Si from bottom to top). In some implementations, the semiconductor layer stack includes semiconductor layers of the same material but with alternating composition atomic percentages, such as semiconductor layers with a first atomic percentage composition and semiconductor layers with a second atomic percentage composition. For example, the semiconductor layer stack includes silicon germanium layers with alternating silicon and / or germanium atomic percentages (e.g., Si / SiGe / Si from bottom to top). a Ge b / Si c Ge d / Si a Ge b, where a and c are different atomic percentages of silicon, and b and d are different atomic percentages of germanium. Alternatively or additionally, bulk substrate 202 and / or one or more material layers include another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and / or cadmium telluride; an alloy semiconductor, such as SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; other III-V materials; other II-V materials; or a combination thereof. Alternatively, substrate 202 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0068] In some embodiments, the first region 1000 is a core device region, on which logic devices and memory devices may be formed, and the second region 2000 is an input / output device (I / O) region, on which input / output devices may be formed. In some alternative embodiments, the first region 1000 is a mixed region that includes logic devices, memory devices, and input / output devices, and the second region 2000 includes only input / output devices.

[0069] Still viewing Figure 1 and Figure 3 , the method 100 includes block 104, where a hard mask layer 204 is deposited over the substrate 202. The hard mask layer 204 may be a single layer or multiple layers. Figure 3 In some embodiments shown in FIG. 1 , the hard mask layer 204 is a multi-layer structure including a first layer 206 and a second layer 208 over the first layer 206. In some implementations, the first layer 206 may be formed of silicon nitride, silicon oxynitride, silicon carbon nitride, or other suitable dielectric materials, and the second layer 208 may be formed of silicon oxide or other suitable dielectric materials. To provide control over the etching process through the hard mask layer 204, the materials used for the first layer 206 and the second layer 208 are selected so that they have different etch selectivities with respect to the etching process. The first layer 206 may have a thickness between about 1000 and about 1000. About and the second layer 208 may have a thickness between about About In one embodiment, the first layer 206 is formed of silicon nitride and has a thickness between about Peace and the second layer 208 is formed of silicon oxide and has a thickness between about Peace In some embodiments, the hard mask layer 204 may be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition techniques. Figure 3 In some implementations shown in FIG. 2 , a pad oxide layer 203 is formed over the substrate 202 prior to the deposition of the hard mask layer 204 to improve the adhesion of the hard mask layer 204. The pad oxide layer 203 may be formed by thermal oxidation, atomic layer deposition, chemical vapor deposition, or other suitable methods. In some cases, the pad oxide layer 203 has a thickness between about 100 Å and about 100 Å. Peace The thickness between.

[0070] See also Figure 1 and Figures 4 to 7 , the method 100 includes block 106, wherein a plurality of spacer features 212 are formed over the hard mask layer 204 in the first region 1000. According to the present disclosure, the plurality of spacer features 212 may be temporary features formed in a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned patterning (SADP) process, a spacer as dielectric patterning (SIDP) process, other double patterning processes, or combinations thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (STAP) process, other triple patterning processes, or combinations thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or combinations thereof. Generally, a multi-patterning process combines a lithography process with a self-aligned process, allowing for the construction of patterns having, for example, a pitch smaller than that obtainable using a single direct lithography process.

[0071] A non-limiting embodiment for forming the plurality of spacer features 212 is typically Figures 4 to 7 See Figure 4 , a sacrificial layer 209 is deposited over the hard mask layer 204. In one embodiment, the sacrificial layer 209 may be a silicon nitride or polysilicon layer deposited using chemical vapor deposition, low pressure chemical vapor deposition (LPCVD), atomic layer deposition, or a suitable method, and may be formed to be between about Peace The thickness between Peace Then, the sacrificial layer 209 is patterned by a lithography process to form Figure 5 . A photoresist layer (not shown) is deposited over the sacrificial layer 209 using spin coating, and the photoresist layer is then baked in a pre-exposure bake process. The photoresist layer may be a single layer or multiple layers, such as three layers. The pre-baked photoresist layer is then exposed to radiation, which is reflected from or transmitted through a photomask having a pattern. The exposed photoresist layer is then baked in a post-exposure bake process and developed in a development process. The radiation source may be an excimer electro-radiation source, an ultraviolet (UV) source, a deep ultraviolet (DUV) source, or an extreme ultraviolet (EUV) source. Because the photoresist layer is selected to be sensitive to radiation, during the development process, the exposed (or unexposed) portion of the photoresist layer undergoes a chemical change to become soluble in a developer solution. The resulting patterned photoresist layer has a pattern corresponding to the pattern of the mask. The patterned photoresist layer can then be used as an etching mask during an etching process to remove portions of the sacrificial layer 209 underneath. The etching process may include a dry etching process (e.g., a reactive ion etching (RID) process), a wet etching process, other suitable etching processes, or a combination thereof. After the etching process, the patterned photoresist layer may be removed by ashing or a suitable method. Alternatively, the exposure process may implement maskless lithography, electron beam direct writing, ion beam direct writing, and / or nano-printing technology. After removing the patterned photoresist layer, a hard mask layer 204 in the first region 1000 is formed. Figure 5 A plurality of mandrel features 210 are shown in FIG.

[0072] View now Figure 6 , a spacer layer 211 is then blanket deposited over the workpiece 200, including over the plurality of mandrel features 210 in the first region 1000. Figure 6 As shown in , the spacer layer 211 is deposited along the top surface and sidewalls of the plurality of spindle features 210. In some embodiments, the spacer layer 211 may be formed of a material having an etch selectivity different from the etch selectivity of the spindle features 210, such that the plurality of spindle features 210 may be selectively removed in a subsequent process. For example, the spacer layer 211 may be formed of silicon nitride, silicon oxynitride, silicon carbon nitride, silicon carbide, or other suitable material. The spacer layer 211 is then etched back to expose the top surface of the spindle features 210. In some implementations, the etch back of the spacer layer 211 leaves multiple vertical portions of the spacer layer 211 extending along the sidewalls of the spindle features 210, while removing multiple horizontal portions of the spacer layer 211 covering the top surface of the hard mask layer 204. As shown in Figure 7 As shown in , the exposure of the mandrel features 210 allows the mandrel features 210 to be selectively removed, thereby forming a plurality of spacer features 212 over the hard mask layer 204 in the first region 1000 .

[0073] Reference Figure 1 and Figure 8 , the method 100 includes block 108, where a bottom anti-reflective coating (BARC) 214 is blanket deposited over the substrate 202. In some embodiments, the bottom anti-reflective coating 214 may include silicon oxynitride, a polymer, or a suitable material. The bottom anti-reflective coating 214 may be deposited using spin coating, chemical vapor deposition, or other suitable methods.

[0074] See also Figure 1 , Figure 8 ,and Fig. 9 , method 100 includes block 110, wherein the bottom anti-reflective coating 214 is patterned to form material features 217 in the second region 2000. To pattern the bottom anti-reflective coating 214, a photoresist layer may be deposited over the bottom anti-reflective coating 214 using spin coating, and then the photoresist layer is baked in a pre-exposure bake process. The photoresist layer may be a single layer or multiple layers, for example, three layers. The pre-baked photoresist layer is then exposed to radiation that is reflected from a photomask having a pattern or transmitted through a photomask having a pattern. The exposed photoresist layer is then baked in a post-exposure bake process and developed in a development process. The radiation source may be an excimer electro-radiation source, an ultraviolet (UV) source, a deep ultraviolet (DUV) source, or an extreme ultraviolet (EUV) source. Because the photoresist layer is selected to be sensitive to radiation, during the development process, the exposed (or unexposed) portion of the photoresist layer undergoes a chemical change to become soluble in a developer solution. As in Figure 8 The patterned photoresist layer 216 is formed as shown in FIG. 2 with a pattern corresponding to the pattern of the mask. The patterned photoresist layer 216 can then be used as an etch mask during an etching process to remove portions of the bottom anti-reflective coating 214 below to form material features 217 above the hard mask layer 204 in the second region 2000, as shown in FIG. Fig. 9 The etching process may include a dry etching process (eg, a reactive ion etching (RIE) process), a wet etching process, other suitable etching processes, or a combination thereof.

[0075] See also Figure 1 , Fig.10 ,and Fig.11 , the method 100 includes a block 112, wherein the hard mask layer 204 is patterned using the plurality of spacer features 212 and the patterned bottom anti-reflective coating 214 as an etch mask. In some embodiments, the operation at block 112 may include more than one etching operation. In one embodiment, in a first etching process suitable for etching the second layer 208, Fig.10The second layer 208 in the embodiment is first etched using the plurality of spacer features 212 and the patterned bottom anti-reflective coating 214 as an etch mask. Then, as in Fig.11 As shown in , in a subsequent second etching process suitable for etching the first layer 206, the first layer 206 is etched using the plurality of spacer features 212 and the patterned bottom anti-reflective coating 214 as an etching mask. Finally, a third etching process may be performed to etch through the pad oxide layer 203 to expose the substrate 202 underneath. Fig.11 In some implementations shown in , because the plurality of spacer features 212 and the first layer 206 may be formed of substantially similar materials, the second etching process may simultaneously etch both the plurality of spacer features 212 and the first layer 206. Fig.11 In the embodiment of the present invention, the thickness of each of the plurality of spacer features 212 may be reduced while the second etching process passes through the first layer 206. A third etching process may then be performed subsequent to the second etching process to etch through the pad oxide layer 203. In some cases, the first etching process and the third etching process may include similar chemistries. At the end of the operations of block 112, the hard mask layer 204 is patterned to have mask features corresponding to the plurality of spacer features 212 in the first region 1000 and mask features corresponding to the patterned bottom anti-reflective coating layer 214 in the second region 2000.

[0076] See also Figure 1 , Fig.12 ,and Fig.13 , the method 100 includes a block 114, in which the substrate 202 is patterned using the patterned hard mask layer 204 as an etch mask. In some embodiments, the substrate 202 may be anisotropically etched through the patterned hard mask layer 204. As the etching process proceeds downward into the substrate 202, the plurality of spacer features 212 above the patterned hard mask layer 204 may be removed, such as in Fig.13 At block 114, the hard mask layer is patterned to include the first fin 240 (or first semiconductor fin 240) in the first region 1000 and the second fin 250 (or second semiconductor fin 250) in the second region 2000. Fig.13, but each of the first fin 240 and the second fin 250 extends longitudinally along the Y direction. In some implementations, each of the first fins 240 includes a first width W1 along the X direction, and each of the second fins 250 includes a second width W2 along the X direction. The second width W2 is greater than the first width W1. In some implementations, the ratio (W2 / W1) of the second width W2 relative to the first width W1 is between about 2 and about 600. That is, the second width W2 is at least twice the first width W1. In one embodiment, the first width W1 is between about 5nm and about 10nm, and the second width W2 is between about 20nm and about 6000nm. Because the first fin 240 and the second fin 250 serve as the semiconductor body of the device on the semiconductor device 200, the first fin 240 may be referred to as the first active region 240 and the second fin 250 may be similarly referred to as the second active region 250. Since their width along the X-direction is greater than the width of the first fins 240 , the second fins 250 may be referred to as mesas 250 .

[0077] See also Figure 1 , Fig.14 , Fig.15 ,and Fig.16 , the method 100 includes block 116, wherein further processes are performed. Such further processes may include forming the isolation structure 220 along the first and second fins 240 and 250, forming a dummy gate dielectric layer over the first fin 240 and the second fin 250, forming a dummy gate stack over the channel region of the first fin 240 and the second fin 250, forming one or more gate spacers over the sidewalls of the dummy gate stack, depositing an interlayer dielectric (ILD) layer over the workpiece, forming source / drain recesses in the source / drain region, forming source / drain features in the source / drain recesses, removing the dummy gate stack, forming the first fin 240 and the second fin 250, and forming a gate structure 222 over the channel region of the first fin 240 and the second fin 250 longitudinally along the X direction (in Fig.14 In some embodiments, the gate structure 222 may include an interface layer, a gate dielectric layer above the interface layer, one or more work function layers above the gate dielectric layer, and a metal filling layer above the work function layer. Depending on the design of the semiconductor device 200, the gate structure 222 may be divided into Fig.15 and Fig.16 The multiple gate segments shown in .

[0078] Now refer to Fig.15 In some embodiments, Fig.14The gate structure 222 shown in FIG. 1 may undergo a metal gate cutting process to be divided into a first gate region 224, a second gate region 226, a third gate region 228, and a fourth gate region 230. Fig.15 As shown in , the first gate segment 224 spans over and surrounds the first fins 240-1 and 240-2, the second gate segment 226 spans over and surrounds the first fins 240-3 and 240-4, the third gate segment 228 spans over and surrounds the first fins 240-5 and 240-6, and the fourth gate segment 230 spans over and surrounds the second fin 250. In these embodiments, each of the first, second, and third gate segments 224, 226, and 228 controls a core device in the first region 1000, and the fourth gate segment 230 controls an input / output (I / O) device in the second region 2000. Although only one input / output device in the second region 2000 is shown, the semiconductor device 200 may include multiple similar input / output devices in the second region 2000. Fig.15 In the embodiments shown in , the first region 1000 is a core device region and the second region 2000 is an input / output device region. In some implementations, the core device in the first region 1000 may have an operating voltage between 0.5V and about 0.9V, for example 0.8V. Since the increased width of the second fin 250 mitigates the hot carrier effect, the input / output device in the second region 2000 may operate at a voltage between about 2.5V and about 8V (for example, between about 3.3V and about 8V) with a good service life. Here, a good service life may be defined as no failures in a 10-year simulation cycle. In addition, the input / output device in the second region 2000 serves as an input / output device for the core device in the first region 1000. Note that although in Fig.15 , they are merely examples, and the present disclosure fully contemplates other single fin or other multi-fin devices. In addition, although four gate segments are shown, the present disclosure fully contemplates multiple embodiments with more or less gate segments. In some cases, the ratio of the operating voltage of the core device in the first region 1000 to the operating voltage of the input / output device in the second region 2000 may be between about 3 and about 10, including between about 4 and about 10.

[0079] View now Fig.16In some alternative embodiments, the first region 1000 may be divided into a first sub-region 1000A and a second sub-region 1000B. Each of the first and second gate segments 224 and 226 controls a core device in the first sub-region 1000A. The third gate segment 228 controls a first input / output device in the second sub-region 1000B. The fourth gate segment 230 controls a second input / output device in the second region 2000. In these alternative embodiments, the dummy gate dielectric layer over the second sub-region 1000B is not removed from the first fins 240-5 and 240-6 or is not completely removed from the first fins 240-5 and 240-6, while the dummy gate dielectric layer over the first sub-region 1000A and the second region 2000 is completely removed. The non-removal or incomplete removal of the dummy gate dielectric layer in the second sub-region 1000B results in a remaining dummy gate dielectric layer 232 in the second sub-region 1000B, thereby increasing the operating voltage of the first input / output device in the second sub-region 1000B. Because the composition of the remaining dummy gate dielectric layer 232 is similar to the composition of the interface layer commonly formed in the first region 1000 and the second region 2000, the presence of the remaining dummy gate dielectric layer 232 has the effect of increasing the thickness of the interface layer in the first input / output device in the second sub-region 1000B.

[0080] Still viewing Fig.16 , the semiconductor device 200 according to these alternative embodiments provides two different input / output device regions: a second sub-region 1000B and a second region 2000. The first input / output device in the second sub-region 1000B has an additional remaining virtual gate dielectric layer 232 (or an effectively thicker interface layer), and the second input / output device in the second region 2000 has a wider active region. In some cases, the first input / output device may have an operating voltage between about 1.8V and about 2.75V, and the second input / output device may have an operating voltage between about 2.5V and about 8V, including between about 3.3V and about 8V. The semiconductor device 200 according to these alternative embodiments may be compatible with external circuits operating at an operating voltage of the first input / output device (between about 1.8V and about 2.75V) or an operating voltage of the second input / output device (between about 2.5V and about 8V, including between about 3.3V and about 8V). Due to the Figure 1 The method 100 in the embodiment representatively illustrates a formation process, wherein the second sub-region 1000B is disposed between the first sub-region 1000A and the second region 2000 .

[0081] The present disclosure contemplates a number of further implementations that satisfy various other design requirements. Fig.17 and Fig.18 Several examples of such further embodiments are shown in FIG. Fig.16 Compared with the semiconductor device 200 shown in Fig.17 The semiconductor device 200 in the embodiment includes a plurality of third fins 252 in the third region 3000 instead of the second fins 250 in the second region 2000. The fifth gate segment 234 is disposed above the plurality of third fins 252 to control the input / output device in the third region 3000. Each of the plurality of third fins 252 has a third width W3 that is greater than the first width W1. The ratio of the third width W3 to the first width W1 may be between about 2 and about 600. In some implementations, Fig.17 The third width W3 of the third fin 252 in Fig.16 . In these implementations, the ratio of the second width W2 to the third width W3 may be between about 2 and about 5. In these implementations, the third fin 252 may be referred to as a wide fin or a hybrid fin, and the second fin may be referred to as a mesa. In some embodiments, the input / output devices in both the second region 2000 and the third region 3000 have an operating voltage between about 2.5V and about 8V. In some other embodiments, the operating voltage of the input / output device in the third region 3000 is less than the operating voltage of the input / output device in the second region 2000.

[0082] exist Fig.18 The semiconductor device 200 shown in FIG. Fig.16 and Fig.17 A combination of the embodiments described in Fig.18 The semiconductor device 200 in the embodiment includes three regions: a first region 1000, a second region 2000, and a third region 3000. The different types of active regions in the first, second, and third regions 1000, 2000, and 3000 have been described above and will not be repeated here. Fig.18 The semiconductor device 200 in the embodiment includes three types of input / output devices. The first type of input / output devices are those provided in the second sub-region 1000B; the second type of input / output devices are those provided in the second region 2000; and the third type of input / output devices are those provided in the third region 3000.

[0083] The semiconductor device of the present disclosure provides benefits. The example semiconductor device includes a first region and a second region. The first region includes a core device formed in a first fin, and the second region includes an input / output (I / O) device formed in a second fin. Each of the first fins has a first width W1, and each of the second fins has a second width W2. The second width W2 is greater than the first width W1. In an embodiment of the present disclosure, the ratio of the second width W2 to the first width W1 may be between about 2 and about 600. The larger second width W2 reduces the hot carrier effect and allows the input / output fin field effect transistor in the second region to operate at a supply voltage between about 2.5V and about 8V, with a good service life. The example semiconductor device is therefore compatible with an external circuit having a supply voltage between about 2.5V and 8V (e.g., 3.3V). Other variations are also possible. For example, the input / output device may be formed in the first fin in the first region, so that the semiconductor device may also be compatible with external circuits at different supply voltages.

[0084] The present disclosure provides many different embodiments. In one embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate including a core device region and an input / output (I / O) device region; a plurality of core devices in the core device region, each of which includes a first active region extending along a first direction; and a plurality of first input / output (I / O) transistors in the input / output device region. Each of the plurality of first input / output transistors includes a second active region extending along the first direction. The first active region includes a first width along a second direction perpendicular to the first direction, and the second active region includes a second width along the second direction. The second width is greater than the first width.

[0085] In some embodiments, the ratio of the second width to the first width is between about 2 and about 600. In some embodiments, the plurality of core devices operate at a first voltage and the plurality of input / output transistors operate at a second voltage. The ratio of the second voltage to the first voltage is between about 3 and about 10. In some cases, the first voltage is about 0.8V and the second voltage is between 2.5V and about 8V. In some embodiments, the semiconductor device further comprises a first gate structure disposed above the first active region and a second gate structure disposed above the second active region. The first gate structure comprises a first interface layer disposed on the first active region. The second gate structure comprises a second interface layer disposed on the second active region. The thickness of the first interface layer is substantially similar to the thickness of the second interface layer. In some embodiments, the semiconductor device further comprises a plurality of second input / output (I / O) transistors. Each of the plurality of second input / output transistors comprises a third active region along the first direction. The third active region comprises a third width along the second direction, and the third width is substantially equal to the first width. In some embodiments, the semiconductor device further comprises a first gate structure disposed above the first active region, a second gate structure disposed above the second active region, and a third gate structure disposed above the third active region. The first gate structure includes a first interface layer disposed on the first active region. The second gate structure includes a second interface layer disposed on the second active region. The third gate structure includes a third interface layer disposed on the third active region. The thickness of the first interface layer is substantially similar to the thickness of the second interface layer. The thickness of the third interface layer is greater than the thickness of the first interface layer. In some cases, a plurality of core devices operate at a first voltage, a plurality of first input / output transistors operate at a second voltage, and a plurality of second input / output transistors operate at a third voltage. The second voltage is greater than the third voltage, and the third voltage is greater than the first voltage. In some cases, the first voltage is between about 0.5V and about 0.9V, the second voltage is between about 2.5V and about 8V, and the third voltage is between about 1.8V and about 2.75V. In some embodiments, a plurality of second input / output transistors are disposed between the plurality of first input / output transistors and the plurality of core devices.

[0086] In another embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate, a plurality of core devices, each of which includes a first active region extending along a first direction, a plurality of first input / output (I / O) transistors, each of which includes a second active region extending along the first direction, and a plurality of second input / output transistors, each of which includes a third active region extending along the first direction. The first active region includes a first width along a second direction perpendicular to the first direction, the second active region includes a second width along the second direction, and the third active region includes a third width along the second direction. The first width is equal to the second width, and the third width is greater than the first width.

[0087] In some embodiments, a plurality of first input / output transistors are disposed between a plurality of core devices and a plurality of second input / output transistors. In some implementations, the semiconductor further comprises: a first gate structure disposed over the first active region and extending along a second direction; a second gate structure disposed over the second active region and extending along the second direction; and a third gate structure disposed over the third active region and extending along the second direction. The first gate structure comprises a first interface layer disposed over the first active region, and the second gate structure comprises a second interface layer disposed over the second active region. The third gate structure comprises a third interface layer disposed over the third active region, and the thickness of the first interface layer is substantially similar to the thickness of the third interface layer. The thickness of the second interface layer is greater than the thickness of the first interface layer. In some embodiments, a plurality of core devices operate at a first voltage, a plurality of first input / output transistors operate at a second voltage, a plurality of second input / output transistors operate at a third voltage, and the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage. In some cases, the first voltage is between about 0.5V and about 0.9V, the second voltage is between about 1.8V and about 2.75V, and the third voltage is between about 2.5V and about 8V.

[0088] In yet another embodiment, a method is provided. The method includes: providing a substrate including a first region and a second region; depositing a hard mask layer over the substrate; selectively forming a plurality of spacer features over the hard mask layer in the first region; selectively forming a material feature over the hard mask layer in the second region; etching the hard mask layer using the plurality of spacer features and the material feature as an etch mask to form a patterned hard mask layer; and etching the substrate using the patterned hard mask layer as an etch mask. Each of the plurality of spacer features and the material feature extends longitudinally along a first direction. Each of the plurality of spacer features has a first width along a second direction perpendicular to the first direction. The material feature has a second width along the second direction. The second width is greater than the first width.

[0089] In some embodiments, the first region includes a core device region and the second region includes an input / output (I / O) device region. In some embodiments, the selective formation of a plurality of spacer features includes depositing a sacrificial layer over a hard mask layer, patterning the sacrificial layer to form a plurality of mandrel features, depositing a spacer layer over the mandrel features, etching back the spacer layer to expose a plurality of top surfaces of the plurality of mandrel features, and selectively removing the plurality of mandrel features. In some embodiments, the formation of a material feature includes depositing a bottom anti-reflective coating (BARC) over the plurality of spacer features and the hard mask layer, and patterning the bottom anti-reflective coating to form the material feature. In some embodiments, a ratio of the second width to the first width is between about 2 and about 600.

[0090] Several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for the design and modification of other processes and structures to achieve the same purpose as the embodiments described herein, or to achieve the same advantages. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a substrate including a core device region and an input / output device region; A plurality of core devices, wherein in the core device region, each of the plurality of core devices comprises a first active region extending along a first direction, and the first active region comprises two semiconductor fins extending in parallel along the first direction and spaced apart along a second direction perpendicular to the first direction; a plurality of first input / output transistors, each of which includes a second active region extending along the first direction in the input / output device region; a first gate structure surrounding the two semiconductor fins in the first active region and extending longitudinally along the second direction; a second gate structure surrounding the second active region and extending longitudinally along the second direction; as well as a plurality of second input / output transistors, the plurality of second input / output transistors comprising a third active region extending along the first direction; wherein each of the two semiconductor fins of the first active region comprises a first width along the second direction, and the second active region comprises a second width along the second direction, wherein the second width is greater than the first width, The first gate structure includes a first gate dimension along the first direction, The second gate structure includes a second gate dimension along the first direction, wherein the first gate size and the second gate size are the same, and the first gate structure and the second gate structure are aligned with each other and spaced apart in the second direction, and the first gate structure and the second gate structure are cut from a single gate structure extending along the second direction, wherein the third active region comprises a third width along the second direction, The third width is equal to the first width.

2. The semiconductor device according to claim 1, wherein: A ratio of the second width to the first width is between 2 and 600.

3. The semiconductor device according to claim 1, wherein: wherein the first active region and the second active region extend continuously from the substrate; wherein the plurality of core devices operate at a first voltage, wherein the plurality of first input / output transistors operate at a second voltage, A ratio of the second voltage to the first voltage is between 3 and 10.

4. The semiconductor device according to claim 3, wherein: wherein a height of the first active region measured from a top of the substrate is equal to a height of the second active region measured from a top of the substrate, The first voltage is 0.8V, and the second voltage is between 2.5V and 8V.

5. The semiconductor device according to claim 1, wherein: Also includes: The first gate structure includes a first interface layer disposed on the first active region, The second gate structure includes a second interface layer disposed on the second active region, The thickness of the first interface layer is equal to the thickness of the second interface layer.

6. The semiconductor device according to claim 1, wherein: Also includes: a third gate structure surrounding the third active region, wherein the first gate structure is directly disposed on the first active region, wherein the second gate structure is directly disposed on the second active region, The third gate structure and the third active region are separated by a remaining virtual gate dielectric layer.

7. The semiconductor device according to claim 1, wherein: wherein a height of the first active region measured from a top of the substrate is equal to a height of the second active region measured from a top of the substrate, wherein the plurality of core devices operate at a first voltage, wherein the plurality of first input / output transistors operate at a second voltage, wherein the plurality of second input / output transistors operate at a third voltage, The second voltage is greater than the third voltage, and the third voltage is greater than the first voltage.

8. The semiconductor device according to claim 7, wherein: wherein the first active region and the second active region extend continuously from the substrate, The first voltage is between 0.5V and 0.9V, the second voltage is between 2.5V and 8V, and the third voltage is between 1.8V and 2.75V.

9. The semiconductor device according to claim 1, wherein: The plurality of second input / output transistors are disposed between the plurality of first input / output transistors and the plurality of core devices.

10. A semiconductor device, characterized in that: Include: a substrate; a plurality of core devices over the substrate, each of the plurality of core devices comprising a first active region extending along a first direction; a plurality of first input / output transistors over the substrate, each of the plurality of input / output transistors comprising a second active region extending along the first direction, wherein the plurality of first input / output transistors are fin field effect transistors; a plurality of second input / output transistors above the substrate, each of the plurality of second input / output transistors comprising a third active region extending along the first direction, A plurality of first gate structures surrounding the first active region along a second direction perpendicular to the first direction; as well as A plurality of second gate structures surround the second active region along the second direction, wherein the first active region comprises a first width along a direction perpendicular to the second direction, the second active region comprises a second width along the second direction, and the third active region comprises a third width along the second direction, wherein the first width is equal to the second width, The third width is greater than the first width.

11. The semiconductor device according to claim 10, wherein: The plurality of first input / output transistors are disposed between the plurality of core devices and the plurality of second input / output transistors.

12. The semiconductor device according to claim 10, wherein: Also includes: a third gate structure, which is disposed above the third active region and extends along the second direction, wherein the second gate structure and the second active region are separated by a remaining dummy gate dielectric layer, wherein the first gate structure is in contact with the first active region, The third gate structure is in contact with the third active region.

13. The semiconductor device according to claim 10, wherein: wherein the first active region, the second active region and the third active region are in direct contact with the substrate, wherein the plurality of core devices operate at a first voltage, wherein the plurality of first input / output transistors operate at a second voltage, wherein the plurality of second input / output transistors operate at a third voltage, The third voltage is greater than the second voltage and the second voltage is greater than the first voltage.

14. The semiconductor device according to claim 13, wherein: wherein a height of the first active region measured from a top of the substrate is equal to a height of the second active region measured from a top of the substrate, The first voltage is between 0.5V and 0.9V, the second voltage is between 1.8V and 2.75V, and the third voltage is between 2.5V and 8V.

15. A method for manufacturing a semiconductor device, characterized in that: Include: Providing a substrate, comprising a first active region, a second active region and a third active region along a first direction, wherein the third active region is disposed between the first active region and the second active region; depositing a hard mask layer over the substrate; selectively forming a plurality of spacer features over the hard mask layer of the first active region and the third active region; selectively forming a material feature over the hard mask layer in the second active region; etching the hard mask layer using the plurality of spacer features and the material feature as an etch mask to form a patterned hard mask layer; and etching the substrate using the patterned hard mask layer as an etching mask, wherein each of the plurality of spacer features and the material feature extends longitudinally along a first direction, wherein each of the plurality of spacer features in the first active region has a first width along a second direction perpendicular to the first direction, wherein the material feature has a second width along the second direction, and each of the plurality of spacer features in the third active region has a third width along the second direction, The second width is greater than the first width, and the third width is equal to the first width; Also includes: forming a plurality of fin structures in the first active region, a plurality of fin structures in the third active region, and a platform structure in the second active region; forming a gate structure layer covering the first gate structure, a second gate structure, and a third gate structure; and A first gate structure, a second gate structure, and a third gate structure are formed by a metal gate cutting process, which are aligned with each other and spaced apart in the second direction, wherein the first gate structure surrounds the plurality of fin structures in the first active region, the second gate structure surrounds the platform structure in the second active region, and the third gate structure surrounds the plurality of fin structures in the third active region; A plurality of core devices are formed in the first active region, a plurality of first input / output transistors are formed in the second active region, and a plurality of second input / output transistors are formed in the third active region.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The first active region includes a core device area, and the second active region includes an input / output device area.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: wherein selectively forming the plurality of spacer features comprises: depositing a sacrificial layer over the hard mask layer; patterning the sacrificial layer to form a plurality of mandrel features; depositing a spacer layer over the mandrel features; etching back the spacer layer to expose top surfaces of the mandrel features; as well as The plurality of mandrel features are selectively removed.

18. The method for manufacturing a semiconductor device according to claim 15, wherein: Wherein forming the material feature comprises: depositing a bottom anti-reflective coating over the plurality of spacer features and the hard mask layer; and The bottom anti-reflective coating is patterned to form the material features.

19. The method for manufacturing a semiconductor device according to claim 15, wherein: A ratio of the second width to the first width is between 2 and 600.

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