Display device

Abstract

A display device is disclosed. The display device may include: a pixel circuit layer including a plurality of transistors; a first partition wall and a second partition wall located on the pixel circuit layer and both protruding in a thickness direction; a first electrode and a second electrode formed on the same layer and located on the first partition wall and the second partition wall, respectively; a light emitting element located between the first electrode and the second electrode; and a first organic pattern located directly on the light emitting element.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0178428, filed on Dec. 30, 2019, which is hereby incorporated by reference herein in its entirety. Technical Field

[0002] Various embodiments of the present disclosure relate to a display device and a method for manufacturing the same. Background Art

[0003] As multimedia develops, the importance of display devices is increasing. Therefore, various types of display devices such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs) are being used.

[0004] The device for displaying an image of the display device includes a display panel such as an organic light emitting display panel or a liquid crystal display panel. The light emitting display panel may include a light emitting element. Examples of light emitting diodes (LEDs) may include organic light emitting diodes using organic materials as fluorescent materials and inorganic light emitting diodes using inorganic materials as fluorescent materials.

[0005] Inorganic light emitting diodes using inorganic semiconductors as fluorescent materials are durable even in high temperature environments and have higher blue light efficiency than organic light emitting diodes. In addition, a transfer method using a dielectrophoresis (DEP) method has been developed to overcome the limitations of existing manufacturing processes for inorganic light emitting diode elements. Therefore, research on inorganic light emitting diodes having superior durability and efficiency compared to organic light emitting diodes is ongoing. Summary of the invention

[0006] Various embodiments of the present disclosure are directed to a method of reducing the number of masks used when manufacturing a display device including nano-scale to micro-scale light emitting elements.

[0007] Furthermore, various embodiments of the present disclosure are directed to a display device having a substantially flat upper surface.

[0008] The present disclosure is not limited to the objects of the above-mentioned embodiments, and other objects not mentioned will be clearly understood by those skilled in the art through the following description.

[0009] An embodiment of the present disclosure may provide a display device comprising: a pixel circuit layer comprising a plurality of transistors; a first partition wall and a second partition wall located on the pixel circuit layer and both protruding in a thickness direction; a first electrode and a second electrode formed on the same layer (e.g., at the same level) and respectively located on the first partition wall and the second partition wall; a light-emitting element located between the first electrode and the second electrode; and a first organic pattern directly on the light-emitting element.

[0010] In an embodiment, the display device may further include: a second organic pattern directly on the first electrode; and a third organic pattern directly on the second electrode.

[0011] The first organic pattern, the second organic pattern, and the third organic pattern may be located on the same layer (eg, at the same level).

[0012] The display device may further include: a first contact electrode in contact with the first end of the light emitting element and the first electrode; and a second contact electrode in contact with the second end of the light emitting element and the second electrode.

[0013] The display device may further include: a second organic pattern directly located on the first electrode; and a third organic pattern directly located on the second electrode, wherein the first contact electrode may be located between the first organic pattern and the second organic pattern, and wherein the second contact electrode may be located between the first organic pattern and the third organic pattern.

[0014] The first contact electrode may be positioned along an edge of a groove defined by the first and second organic patterns, and the second contact electrode may be positioned along an edge of a groove defined by the first and third organic patterns.

[0015] The display device may further include: a fourth organic pattern directly on the first contact electrode; and a fifth organic pattern directly on the second contact electrode.

[0016] The fourth organic pattern and the fifth organic pattern may be located on the same layer (eg, at the same level).

[0017] Respective upper portions of the first, second, third, fourth, and fifth organic patterns may have the same (eg, substantially the same) height.

[0018] The display device may further include an insulating layer on a portion of each of the first electrode and the second electrode, wherein the insulating layer may expose another portion of each of the first electrode and the second electrode.

[0019] The insulating layer may be located between the first electrode and the second electrode, and the light emitting element may be located on a region of the insulating layer between the first electrode and the second electrode.

[0020] The display device may further include a bank on the insulating layer, and the bank has a height higher than heights of the first partition wall and the second partition wall.

[0021] The display device may further include a second organic pattern and a third organic pattern between the bank and the first organic pattern, and the first organic pattern, the second organic pattern, and the third organic pattern may be located on the same layer (eg, at the same level).

[0022] An embodiment of the present disclosure may provide a method for manufacturing a display device, the display device comprising: a pixel circuit layer comprising a plurality of transistors; a first partition wall and a second partition wall located on the pixel circuit layer and both protruding in a thickness direction; and a first electrode and a second electrode located on the first partition wall and the second partition wall, respectively, the method comprising: aligning a light-emitting element between the first electrode and the second electrode; forming a first organic layer comprising a first organic pattern directly on the light-emitting element; and forming contact electrodes, the contact electrodes comprising a first contact electrode in contact with a first end portion of the light-emitting element and the first electrode, and a second contact electrode in contact with a second end portion of the light-emitting element and the second electrode.

[0023] The step of forming a first organic layer may include: forming a first organic material layer covering the first electrode, the second electrode and the light-emitting element; and forming a first photoresist material and exposing a portion of the first organic material layer by applying a first photoresist material to the first organic material layer and irradiating UV or laser onto a portion of the first photoresist material.

[0024] After forming a first photoresist material and exposing it to light, the first organic material layer may be divided into a first organic pattern, a second organic pattern, and a third organic pattern.

[0025] The first organic pattern may be directly on the first electrode, the second organic pattern may be directly on the second electrode, and the third organic pattern may be directly on the light emitting element.

[0026] The forming of the contact electrode may include: forming a contact electrode material layer on each of the first organic pattern, the second organic pattern, and the third organic pattern; and coating the second organic material layer on a portion of the contact electrode material layer and etching.

[0027] After forming the contact electrode, the contact electrode material layer may be divided into a first contact electrode and a second contact electrode.

[0028] The etching may be a wet etching.

[0029] Additional details of other embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings, together with the specification, illustrate embodiments of the presently disclosed subject matter, and, together with the description, serve to explain principles of the embodiments of the presently disclosed subject matter.

[0031] Figure 1 and Figure 2 are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0032] Figure 3 and Figure 4 are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0033] Figure 5 and Figure 6 are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0034] Figure 7 is a conceptual diagram illustrating a display panel according to an embodiment of the present disclosure.

[0035] Figure 8 It is shown Figure 7 A circuit diagram of an example of a sub-pixel included in a display panel.

[0036] Figures 9 to 12 It is shown that it can be applied to Figure 8 A circuit diagram of an example of a unit pixel included in a sub-pixel.

[0037] Fig.13 It is shown Figure 7 A plan layout diagram showing the arrangement of some components in a sub-pixel included in a display panel.

[0038] Fig.14 The display panel is along Fig.13 A cross-sectional view taken along line II'.

[0039] Fig.15 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0040] Figures 16 to 26 It is shown in Fig.15 Cross-sectional views of the various processes described in the flow chart.

[0041] Fig. 27 is a cross-sectional view showing a display panel according to an embodiment of the present disclosure.

[0042] Fig.28 and Fig.29 It is shown Fig. 27 Cross-sectional views of some processes of a method for manufacturing a display device.

[0043] Figure 30 to Figure 33 is a circuit diagram illustrating another example of a unit pixel included in a sub-pixel applicable to a display panel according to an embodiment of the present disclosure.

[0044] Fig.34 is a plan layout diagram showing the arrangement of some components in one sub-pixel included in a display panel according to another embodiment of the present disclosure.

[0045] Fig.35The display panel is along Fig. 27 A cross-sectional view taken along line II-II'. DETAILED DESCRIPTION

[0046] With reference to the embodiments described in more detail below and the accompanying drawings, the features of the present disclosure and the methods for realizing the same will be apparent. However, the subject matter of the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art, and the scope of the present disclosure will be limited only by the appended claims and their equivalents.

[0047] It will be understood that when an element or layer is referred to as being “on” another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer, or one or more intervening elements or layers may be present. Like reference numerals refer to like elements throughout.

[0048] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the spirit and scope of the present disclosure, the first element discussed below may be referred to as the second element. In the present disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0049] Here, the elements formed on the same layer may be elements containing the same (eg, substantially the same) material and formed substantially at the same time. In addition, elements formed on different layers may be formed at different times, and the elements may contain the same or different materials.

[0050] Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals are used to represent the same or similar elements.

[0051] Figure 1 and Figure 2 1 is a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure. Figure 1 and Figure 2 , a rod-type light emitting element LD having a cylindrical shape is shown in FIG. 1 , but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0052] Reference Figure 1 and Figure 2, the light emitting element LD may include a first conductive electrode layer 11, a second conductive electrode layer 13, and an active layer 12 disposed between the first conductive electrode layer 11 and the second conductive electrode layer 13. For example, the light emitting element LD may be a stacked body formed by continuously stacking the first conductive electrode layer 11, the active layer 12, and the second conductive electrode layer 13 in one direction.

[0053] In an embodiment, the light emitting element LD may be in the form of a rod extending in one direction. The light emitting element LD may have a first end and a second end in one direction.

[0054] In an embodiment, one of the first conductive electrode layer 11 and the second conductive electrode layer 13 may be on a first end of the light emitting element LD, and the other of the first conductive electrode layer 11 and the second conductive electrode layer 13 may be located on a second end of the light emitting element LD.

[0055] In the embodiment, the light emitting element LD may be a rod-type light emitting diode manufactured in the form of a rod. Here, the term "rod-like shape" includes a rod-like shape and a strip-like shape (such as a cylindrical shape and a prismatic shape) that are longer in the longitudinal direction than in the width direction (for example, to have an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0056] In an embodiment, the light emitting element LD may have a small size corresponding to the nanometer or micrometer level, for example, a diameter D and / or a length L corresponding to the nanometer or micrometer range. For example, the light emitting element LD may have a length L and / or a diameter D of 1 nanometer (nm) to 5 micrometers (μm), such as 1nm to 100nm, 100nm to 5μm, or 100nm to 800nm. However, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various suitable ways according to the design conditions of various suitable devices (for example, a display device using a light emitting device using the light emitting element LD as a light source).

[0057] The first conductive electrode layer 11 may include at least one n-type semiconductor material. For example, the first conductive electrode layer 11 may include an n-type semiconductor material including one selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, and / or Sn. However, the material forming the first conductive electrode layer 11 is not limited thereto, and the first conductive electrode layer 11 may be formed of various other suitable materials.

[0058] The active layer 12 may be located on the first conductive electrode layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer doped with a conductive dopant may be located on and / or below the active layer 12. For example, the cladding layer may include an AlGaN layer and / or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using materials such as AlGaN and / or AlInGaN, and various other suitable materials may be used to form the active layer 12.

[0059] If a threshold voltage or more is applied to opposite ends of the light emitting element LD, the light emitting element LD can emit light by combining (e.g., recombination) electron-hole pairs in the active layer 12. Since light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as various suitable light emitting devices and light sources of pixels of display devices.

[0060] The second conductive electrode layer 13 may be located on the active layer 12 and include a semiconductor material of a type different from that of the semiconductor material of the first conductive electrode layer 11. For example, the second conductive electrode layer 13 may include at least one p-type semiconductor material. For example, the second conductive electrode layer 13 may include a p-type semiconductor material including at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the material forming the second conductive electrode layer 13 is not limited thereto, and the second conductive electrode layer 13 may be formed of various other suitable materials.

[0061] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be located on the surface of the light emitting element LD to surround at least the periphery (e.g., the outer circumferential surface) of the active layer 12. In addition, the insulating film INF may further surround the region of each of the first conductive electrode layer 11 and the second conductive electrode layer 13. The insulating film INF may allow the opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive electrode layer 11 and the second conductive electrode layer 13 located on the corresponding opposite ends of the light emitting element LD relative to the longitudinal direction, for example, two surfaces (e.g., the top surface and the bottom surface) of the cylinder may be exposed instead of covering them.

[0062] In an embodiment, the insulating film INF may include a silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) and titanium dioxide (TiO2 ), but it is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various suitable insulating materials generally available in the art.

[0063] In an embodiment, in addition to the first conductive electrode layer 11, the active layer 12, the second conductive electrode layer 13 and / or the insulating film INF, the light emitting element LD may further include other additional components. For example, the light emitting element LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor material layer and / or at least one electrode layer on one end of the first conductive electrode layer 11, the active layer 12 and / or the second conductive electrode layer 13.

[0064] Figure 3 and Figure 4 are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure. Figure 5 and Figure 6 are a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0065] Reference Figure 3 and Figure 4 The light emitting element LD may further include at least one electrode layer 14 on one end portion of the second conductive electrode layer 13 .

[0066] Reference Figure 5 and Figure 6 The light emitting element LD may further include at least one electrode layer 15 on one end portion of the first conductive electrode layer 11 .

[0067] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but it is not limited thereto. In addition, each of the electrode layers 14 and 15 may include a metal and / or a conductive metal oxide. For example, each of the electrode layers 14 and 15 may be formed by a transparent electrode material such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides and / or alloys thereof, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and / or indium tin zinc oxide (ITZO), alone or in combination. The electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside of the light emitting element LD after passing through the electrode layers 14 and 15.

[0068] In an embodiment, the insulating film INF may at least partially surround the outer surfaces of the electrode layers 14 and 15, or may not surround them. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different polarities, for example, at least one region of each of the electrode layers 14 and 15 may be exposed. However, this is not limited to this, and the insulating film INF may not be provided.

[0069] If the insulating film INF is provided on the surface of the light emitting element LD (for example, provided on the surface of the active layer 12), a short circuit between the active layer 12 and at least one electrode (for example, at least one of the contact electrodes bonded to the opposite ends of the light emitting element LD, etc.) can be prevented or its possibility or degree can be reduced. As a result, the electrical stability of the light emitting element LD can be ensured.

[0070] In addition, the insulating film INF can be formed on the surface of the light emitting element LD, thereby minimizing or reducing surface defects of the light emitting element LD and improving the life and efficiency of the light emitting element LD. In addition, the insulating film INF is formed on the light emitting element LD, thereby preventing an undesirable short circuit between the light emitting elements LD or reducing the possibility or degree of an undesirable short circuit between the light emitting elements LD even if a plurality of light emitting elements LD are arranged in close proximity to each other.

[0071] In an embodiment, the light emitting element LD may be manufactured by a surface treatment process (e.g., coating). For example, when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) to be supplied to each light emitting region (e.g., the light emitting region of each pixel), the light emitting element LD may be uniformly dispersed in the solution without being unevenly aggregated in the solution. Here, the light emitting region is a region where light is emitted by the light emitting element LD. The light emitting region may be distinguished from a non-light emitting region where no light is emitted.

[0072] In some embodiments, the insulating film INF itself may be formed by a hydrophobic film using a hydrophobic material, or a hydrophobic film of a hydrophobic material may be further formed on the insulating film INF. In an embodiment, the hydrophobic material may be a material containing fluorine to exhibit hydrophobicity. In an embodiment, the hydrophobic material may be applied to the light emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercially available fluorine-containing material (such as Teflon TM and / or Cytop TM) and / or a corresponding material.

[0073] The light-emitting device including the above-mentioned light-emitting element LD can be used in various suitable devices including display devices using light sources. For example, at least one ultra-small light-emitting element LD (for example, multiple ultra-small light-emitting elements LD each having a size range from nanometers to micrometers) can be located in each pixel area of ​​the display panel to form a light source (or light source unit) of the corresponding pixel using the ultra-small light-emitting element LD. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in various suitable devices using light sources such as lighting devices.

[0074] Figure 7 is a conceptual diagram showing a display panel according to an embodiment of the present disclosure. According to an embodiment, Figure 7 Shows that you can use Figures 1 to 6 A display panel with a light emitting element LD as a light source.

[0075] The display panel may be used as a display panel for a large display device such as a television or a monitor, and a small or medium-sized display device such as a mobile phone, a tablet computer, a vehicle navigation device, a game console, and / or a smart watch.

[0076] In an embodiment, the display panel may have a rectangular shape that is longer in the second direction DR2 than in the first direction DR1. The thickness direction of the display panel is indicated by the third direction DR3. However, since the directions indicated by the first direction to the third directions DR1, DR2, and DR3 are relative concepts, each direction may be converted into another direction. Hereinafter, the first direction to the third direction DR1, DR2, and DR3 are reference numerals indicating the directions indicated by the three directions DR1, DR2, and DR3, respectively. The display panel may have various suitable shapes, without being limited to the shapes shown in the drawings.

[0077] The display panel may include a base layer (or substrate) SUB1 and pixels PXL on the base layer SUB1. In more detail, the display panel and the base layer SUB1 may include a display area DA displaying an image and a non-display area NDA formed with a set or predetermined area except the display area DA.

[0078] The display area DA and the non-display area NDA may be defined in the substrate SUB1. In an embodiment, the display area DA may be located in the central portion of the display panel, and the non-display area NDA may be located in the peripheral portion of the display panel to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0079] The base layer SUB1 may form a base member of the display panel. For example, the base layer SUB1 may form a base member of a lower panel (eg, a lower plate of the display panel).

[0080] In an embodiment, the base layer SUB1 may be a rigid or flexible substrate, and its material or properties are not particularly limited. For example, the base layer SUB1 may be a rigid substrate made of glass or tempered glass, or a flexible substrate formed of a thin film made of plastic or metal. In addition, the base layer SUB1 may be a transparent substrate, but it is not limited thereto. For example, the base layer SUB1 may be a translucent substrate, an opaque substrate, or a reflective substrate.

[0081] The area on the substrate layer SUB1 is defined as a display area DA in which the pixels PXL are positioned, and the other area on the substrate layer SUB1 is defined as a non-display area NDA. For example, the substrate layer SUB1 may include a display area DA including a plurality of light emitting areas in which the pixels PXL are formed, and a non-display area NDA positioned around the display area DA. Various suitable lines and / or internal circuits of the pixels PXL coupled to the display area DA may be located in the non-display area NDA.

[0082] Each of the pixels PXL may include at least one light emitting element LD driven by a data signal and a corresponding scan signal (eg, according to Figures 1 to 6 For example, the pixel PXL may include a plurality of rod-type light emitting diodes coupled in parallel to each other, each of which has a small size ranging from nanometer to micrometer. The plurality of rod-type light emitting diodes may form the light source of the pixel PXL.

[0083] In addition, the pixel PXL may include a plurality of sub-pixels. For example, the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. In an embodiment, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may respectively emit light of different colors. For example, the first sub-pixel SPX1 may be a red sub-pixel to emit red light, the second sub-pixel SPX2 may be a green sub-pixel to emit green light, and the third sub-pixel SPX3 may be a blue sub-pixel to emit blue light. However, the color, type, and / or number of sub-pixels forming the pixel PXL are not particularly limited. For example, the color of light emitted from each of the sub-pixels SPX1, SPX2, and SPX3 may be changed in various suitable ways. Although in Figure 7 , an embodiment in which the sub-pixels SPX1, SPX2, and SPX3 are arranged in a stripe shape in the display area DA is shown, but the present disclosure is not limited thereto. For example, the pixels PXL may be arranged in various suitable pixel array forms commonly used in the art.

[0084] In an embodiment, each of the sub-pixels SPX1, SPX2, and SPX3 may include a plurality of unit pixels SSPX1, SSPX2, and SSPX3 (see Figure 8 ).

[0085] In some embodiments, a plurality of pads may be located in the non-display area NDA. The wires in the display panel may be electrically coupled to a driver IC located outside the display panel through the pads.

[0086] Figure 8 It is shown that the Figure 7 A circuit diagram of an example of a sub-pixel in a display panel. Figure 8 Shown included in Figure 7 The first to third sub-pixels SPX1, SPX2 and SPX3 in the display panel.

[0087] Because the first to third subpixels SPX1, SPX2 and SPX3 are substantially identical to one another except that they are respectively coupled to corresponding data lines Dj, Dj+1 and Dj+2, the first to third subpixels SPX1, SPX2 and SPX3 will be described based on the first subpixel SPX1.

[0088] The first to third subpixels SPX1, SPX2, and SPX3 may be located in regions divided by scan lines Si-1 and Si (i is a natural number) and data lines Dj, Dj+1, and Dj+2 (j is a natural number), respectively. For example, the first subpixel SPX1 may be located in a region defined by the i-1th scan line Si-1 and the i-th scan line Si and the jth data line Dj and the j+1th data line Dj+1. However, the arrangement of the first to third subpixels SPX1, SPX2, and SPX3 is not limited thereto.

[0089] The first sub-pixel SPX1 may be coupled to the scan line Si and the data line Dj, and may also be coupled to the first power line and the second power line. Here, the first power VDD may be applied to the first power line, and the second power VSS may be applied to the second power line. Each of the first power line and the second power line may be a common line coupled to a plurality of sub-pixels. The first power VDD and the second power VSS may have different potentials so that the first sub-pixel SPX1 emits light. The first power VDD may have a voltage level higher than that of the second power VSS.

[0090] In an embodiment, the first subpixel SPX1 may include at least one unit pixel SSPX1 to SSPXk (k is a natural number).

[0091] Each of the unit pixels SSPX1 to SSPXk may be coupled to a scan line Si and a data line Dj, and may also be coupled to a first power line and a second power line. Each of the unit pixels SSPX1 to SSPXk may emit light having a brightness corresponding to a data signal transmitted through the data line Dj in response to a scan signal transmitted through the scan line Si. The unit pixels SSPX1 to SSPXk may include substantially the same pixel structure or pixel circuit.

[0092] In other words, the first sub-pixel SPX1 may include unit pixels SSPX1 to SSPXk which independently emit light in response to one scan signal and one data signal.

[0093] In an embodiment, each of the unit pixels SSPX1 to SSPXk (or sub-pixels SPX1 to SPX3) may be an active pixel. However, the type, structure and / or driving scheme of the unit pixels that can be applied to the display panel of the present disclosure are not particularly limited. For example, the unit pixel may be configured as a pixel of a display panel having various suitable passive structures or active structures commonly used in the art.

[0094] Figures 9 to 12 It is shown that it can be applied to Figure 8 A circuit diagram of an example of a unit pixel included in a sub-pixel.

[0095] Each of the drawings will be described with reference to one unit pixel. Figure 8 The description of the first unit pixel SSPX1 to the kth unit pixel SSPXk shown in FIG. 1 can be applied to Figures 9 to 12 , so it will not be described here repeatedly. For example, Figure 8 The first to k-th unit pixels SSPX1 to SSPXk shown in FIG. 1 have substantially the same or similar structures. Figures 9 to 12 The first unit pixel SSPX1 shown in FIG. 1 is illustrative and may be equally or similarly applied to Figure 8 Any one of the first unit pixel SSPX1 to the kth unit pixel SSPXk.

[0096] First, refer to Fig. 9 , the unit pixel SSPX1 may include a light source unit LSU that emits light having brightness corresponding to the data signal. The unit pixel SSPX1 may selectively further include a pixel circuit PXC to drive the light source unit LSU.

[0097] In an embodiment, the light source unit LSU may include a plurality of light emitting elements LD electrically coupled to each other between a first power source VDD and a second power source VSS. In an embodiment, the light emitting elements LD may be coupled to each other in parallel, but are not limited thereto. For example, the plurality of light emitting elements LD may be coupled to each other in parallel between the first power source VDD and the second power source VSS.

[0098] The first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD emits light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage or more of the light emitting element LD at least during the light emitting period of the unit pixel SSPX1 (or the first sub-pixel SPX1).

[0099] Although in Fig. 9 , an embodiment in which the light-emitting elements LD are connected in parallel in the same (e.g., substantially the same) direction (e.g., in the forward direction) between the first power supply VDD and the second power supply VSS is shown, but the present disclosure is not limited thereto. For example, some of the light-emitting elements LD may be connected to each other in the forward direction between the first power supply VDD and the second power supply VSS, thereby forming a corresponding effective light source, and other light-emitting elements LD may be connected to each other in the reverse direction. As another example, the unit pixel SSPX1 may include only a single light-emitting element LD (e.g., a single effective light source connected in the forward direction between the first power supply VDD and the second power supply VSS).

[0100] According to an embodiment, a first end of each of the light emitting elements LD may be commonly coupled to an associated pixel circuit PXC through a first electrode, and may be commonly coupled to a first power supply VDD through the pixel circuit PXC and a first power supply line. A second end of each of the light emitting elements LD may be commonly coupled to a second power supply VSS through a second electrode and a second power supply line.

[0101] The light source unit LSU may emit light having a brightness corresponding to the driving current supplied thereto through the corresponding pixel circuit PXC. Thus, it is possible to Figure 7 ) displays a set or predetermined image.

[0102] The pixel circuit PXC can be coupled to the scan line Si and the data line Dj of the corresponding sub-pixel (e.g., the first sub-pixel SPX1). For example, if the first sub-pixel SPX1 is located on the i-th row and j-th column of the display area DA, the pixel circuit PXC of the unit pixels SSPX1 to SSPXk can be coupled to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0103] The pixel circuit PXC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0104] The first transistor (or driving transistor) T1 may be coupled between the first power source VDD and the light source unit LSU. A gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0105] The second transistor (or switching transistor) T2 may be coupled between the data line Dj and the first node N1. A gate electrode of the second transistor T2 may be coupled to the scan line Si.

[0106] In response to a scan signal of a gate-on voltage (eg, a low voltage) supplied from the scan line Si, the second transistor T2 may be turned on to electrically couple the first node N1 to the data line Dj.

[0107] During a frame period, a data signal corresponding to a frame is supplied to the data line Dj. The data signal may be transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal may be charged to the storage capacitor Cst.

[0108] A first electrode of the storage capacitor Cst may be coupled to the first power source VDD, and a second electrode thereof may be coupled to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal supplied to the first node N1 during each frame period and maintain the charged voltage until a data signal of a subsequent frame is supplied.

[0109] Although in Fig. 9 The transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, any one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0110] For example, Fig.10 As shown in , both the first transistor T1 and the second transistor T2 may be formed of N-type transistors. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the data line Dj in each frame period in the unit pixel SSPX1_1 may be a high-level voltage. Similarly, the voltage of the data signal for turning on the first transistor T1 may be a voltage which is equal to Fig. 9 The waveform voltage of the embodiment is opposite to the waveform voltage. For example, in Fig.10 In the embodiment, as the grayscale value to be expressed increases, a data signal with a higher voltage level may be supplied.

[0111] In addition to the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signals and data signals) being changed according to the change of transistor types, Fig.10 The unit pixel SSPX1_1 shown in FIG. 1 is similar in structure and operation to the Fig. 9 The unit pixel SSPX1 is basically similar. Therefore, it will not be repeated here. Fig.10 Repeated description of unit pixel SSPX1_1.

[0112] The structure of the pixel circuit PXC is not limited to Fig. 9 and Fig.10 In other words, the pixel circuit PXC may be formed by any suitable pixel circuit commonly used in the art, and the pixel circuit may have various suitable structures and / or be operated by various suitable driving schemes. For example, the pixel circuit PXC may be formed by any suitable pixel circuit commonly used in the art, and the pixel circuit may have various suitable structures and / or be operated by various suitable driving schemes. Fig.11 0 and 1. The embodiments shown in FIG. 2 are configured in the same manner (eg, substantially the same manner) as the embodiments shown in FIG.

[0113] Reference Fig.11 , the pixel circuit PXC in the unit pixel SSPX1_2 can be coupled not only to the corresponding scan line Si but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the sub-pixel SPX on the i-th row of the display area DA (or the unit pixel SSPX included therein) can be further coupled to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit PXC can be coupled not only to the first power supply VDD and the second power supply VSS, but also to other power supplies. For example, the pixel circuit PXC can also be coupled to the initialization power supply Vint.

[0114] According to an embodiment, the pixel circuit PXC may include seven transistors T1 to T7. The pixel circuit PXC may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0115] The first transistor T1 may be coupled between the first power source VDD and the light source unit LSU. The first electrode (e.g., source electrode) of the first transistor T1 may be coupled to the first power source VDD through the fifth transistor T5, and the second electrode (e.g., drain electrode) of the first transistor T1 may be coupled to the first electrode of the light source unit LSU (e.g., the first electrode of the corresponding sub-pixel SPX) via the sixth transistor T6. The gate electrode of the first transistor T1 may be coupled to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0116] The second transistor T2 may be coupled between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 may be coupled to the corresponding scan line Si. When a scan signal of a gate-on voltage is supplied from the scan line Si, the second transistor T2 may be turned on to electrically couple the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the data line Dj may be transmitted to the first transistor T1.

[0117] The third transistor T3 may be coupled between the second electrode (e.g., drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be coupled to the corresponding scan line Si. When a scan signal of a gate-on voltage is supplied from the scan line Si, the third transistor T3 may be turned on to couple the first transistor T1 in a diode form.

[0118] The fourth transistor T4 may be coupled between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 may be coupled to a previous scan line, for example, the i-1th scan line Si-1. When a scan signal of a gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. Here, the voltage of the initialization power supply Vint may be the minimum or lower voltage of the data signal or less.

[0119] The fifth transistor T5 may be coupled between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be coupled to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal of a gate-off voltage (for example, a high voltage) is supplied to the emission control line Ei, and may be turned on in other cases.

[0120] The sixth transistor T6 may be coupled between the first transistor T1 and the first electrode of the light source unit LSU. The gate electrode of the sixth transistor T6 may be coupled to a corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal of a gate-off voltage is supplied to the emission control line Ei, and may be turned on in other cases.

[0121] The seventh transistor T7 may be coupled between the first electrode of the light source unit LSU and the initialization power supply Vint (or a third power supply line transmitting the initialization power). The gate electrode of the seventh transistor T7 may be coupled to any one of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal of a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU. In this case, during the initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the first electrode of the light source unit LSU may be initialized.

[0122] The control signal for controlling the operation of the seventh transistor T7 may be variously changed. For example, the gate electrode of the seventh transistor T7 may be coupled to a scan line corresponding to a horizontal line, that is, the i-th scan line Si. In this case, when a scan signal of a gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU.

[0123] The storage capacitor Cst may be coupled between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1. The second node N2 may also be coupled to the first power source VDD.

[0124] Although in Fig.11 , the transistors (e.g., the first transistor T1 to the seventh transistor T7) included in the pixel circuit PXC in the unit pixel SSPX1_2 have been shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an N-type transistor.

[0125] According to an embodiment, the pixel circuit PXC may be further coupled to another line other than the data line Dj.

[0126] Reference Fig.12 , the pixel circuit PXC in the unit pixel SSPX1_3 may be coupled to the sensing line SENj. The pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst. Because the first and second transistors T1 and T2 and the storage capacitor Cst are substantially identical or similar to the reference Fig.10 The first and second transistors T1 and T2 and the storage capacitor Cst are described above, so a repeated description thereof will not be repeated here.

[0127] The third transistor T3 may be coupled between the sensing line SENj and the second node N2. Gate electrodes of the second transistor T2 and the third transistor T3 may be coupled to the first scan line S1 and another second scan line S2 (eg, the jth scan line Sj and another j+1th scan line Sj+1), respectively.

[0128] The light source unit LSU may be coupled between the second node N2 and a second power line (eg, a power line to which the second power VSS is applied).

[0129] The third transistor T3 may be turned on in response to a scan signal of a gate-on voltage transmitted from the second scan line S2 to electrically couple the sensing line SENj to the second node N2 .

[0130] For example, when the third transistor T3 is turned on with a driving current corresponding to a reference voltage flowing in the first transistor T1, the driving current flowing through the first transistor T1 can be provided to an external sensing device through the third transistor T3 and the sensing line SENj, and a signal corresponding to a characteristic (e.g., Vth) of the first transistor T1 based on the driving current can be output to the outside through the sensing line SENj.

[0131] In addition, the structure of the unit pixel SSPX1 that can be applied to the present disclosure is not limited to Figures 9 to 12 , and the unit pixel SSPX1 may have various suitable structures. For example, the pixel circuit PXC included in the unit pixel SSPX1 may be formed by any suitable pixel circuit commonly used in the art, and the pixel circuit may have various suitable structures and / or be operated by various suitable driving schemes. The unit pixel SSPX1 may be formed in a passive light emitting display panel or the like. In this case, the pixel circuit PXC may be omitted, and each of the first electrode and the second electrode of the light source unit LSU may be directly coupled to the scan line Si, the data line Dj, the power line and / or the control line.

[0132] Fig.13 It is shown in Figure 7 A plan layout diagram showing the arrangement of some components in a sub-pixel included in a display panel. Fig.13 The light source unit LSU (see FIG. 1 ) included in the unit pixels SSPX1 to SSPX3 is shown. Figures 9 to 12 ) (or a light emitting element layer). Since the first to third unit pixels SSPX1 to SSPX3 are substantially identical to one another, the light source unit LSU will be described based on the first unit pixel SSPX1.

[0133] Reference Fig.13, the first subpixel SPX1 may include a first electrode ETL1 and second electrodes ETL21 , ETL22 , and ETL23 spaced apart from each other, and at least one light emitting element LD coupled between the first electrode ETL1 and the second electrodes ETL21 , ETL22 , and ETL23 .

[0134] According to an embodiment, the light emitting element LD included in the same unit pixel SSPX1 to SSPX3 may emit light of the same (e.g., substantially the same) color. According to an embodiment, the first unit pixel SSPX1 to the third unit pixel SSPX3 may define a light emitting area emitting light of different colors. For example, the first unit pixel SSPX1 may include a light emitting element LD emitting red light, the second unit pixel SSPX2 may include a light emitting element LD emitting green light, and the third unit pixel SSPX3 may include a light emitting element LD emitting blue light. According to an embodiment, all of the first unit pixel SSPX1 to the third unit pixel SSPX3 may include a light emitting element LD emitting blue light. In this case, in order to form a full-color pixel PXL, a light conversion layer and / or a color filter that converts the color of light emitted from the corresponding unit pixel may be located on at least some of the first unit pixel SSPX1 to the third unit pixel SSPX3.

[0135] According to an embodiment, the first electrode ETL1 may be an electrode shared by the first to third unit pixels SSPX1 to SSPX3 In this case, the first to third unit pixels SSPX1 to SSPX3 may be arranged along the first direction DR1.

[0136] The second electrodes ETL21, ETL22, and ETL23 may be spaced apart from one side of the first electrode ETL1 in the second direction DR2. The second electrodes ETL21, ETL22, and ETL23 in the first to third unit pixels SSPX1 to SSPX3 may be arranged along the first direction DR1.

[0137] The first electrode ETL1 and the second electrodes ETL21 , ETL22 , and ETL23 may be arranged side by side (in parallel, for example, substantially parallel to each other) to be spaced apart by a set or predetermined interval.

[0138] According to an embodiment, the first electrode ETL1 may be a cathode electrode electrically coupled to the second power source VSS. The second electrodes ETL21, ETL22, and ETL23 may be anode electrodes electrically coupled to the first power source VDD. Each of the second electrodes ETL21, ETL22, and ETL23 may include a contact hole CH. The light emitting element LD electrically coupled to the first electrode ETL1 and the second electrodes ETL21, ETL22, and ETL23 at the first end and the second end is positioned so that each of the second electrodes ETL21, ETL22, and ETL23 and the first electrode ETL1 may be electrically coupled to each other.

[0139] According to an embodiment, a light-emitting area for a unit pixel (e.g., SSPX1) may be defined. The light-emitting area may be distinguished by a non-light-emitting area. In some embodiments, a pixel defining layer (or embankment, light-shielding pattern) for preventing or reducing the transmission of light emitted from the light-emitting element LD to another area may be located in the non-light-emitting area to overlap with it. Here, unless otherwise defined, the term "overlapping" refers to two components overlapping each other in the thickness direction of the display panel (in the drawings, perpendicular to (e.g., substantially perpendicular to) the surface of the substrate layer SUB1 (e.g., the third direction DR3)).

[0140] Fig.14 is along Fig.13 A cross-sectional view of the display panel taken along line II'.

[0141] Reference Fig.14 , the display panel may include a base layer SUB1 positioned at a lower position. Since the base layer SUB1 has been described above, a repeated description thereof will not be repeated here.

[0142] The first buffer layer 111 is located on the base layer SUB1. The first buffer layer 111 plays a role in making the surface of the base layer SUB1 smooth and preventing or reducing the penetration of water or external air. The first buffer layer 111 may be an inorganic layer. The first buffer layer 111 may be a single-layer structure or a multi-layer structure.

[0143] A plurality of transistors Tdr and Tsw are located on the first buffer layer 111. Here, each of the transistors Tdr and Tsw may be a thin film transistor. The two transistors Tdr and Tsw shown in the figure correspond to a driving transistor and a switching transistor, respectively.

[0144] Each of the transistors Tdr and Tsw may include semiconductor patterns ACT1, ACT2, gate electrodes GE1, GE2, source electrodes SDE2, SDE4, and drain electrodes SDE1, SDE3. For example, the first transistor Tdr as a driving transistor may include a first semiconductor pattern ACT1, a first gate electrode GE1, a first source electrode SDE2, and a first drain electrode SDE1. The second transistor Tsw as a switching transistor may include a second semiconductor pattern ACT2, a second gate electrode GE2, a second source electrode SDE4, and a second drain electrode SDE3.

[0145] In some embodiments, the semiconductor layer is located on the first buffer layer 111. The semiconductor layer may include a first semiconductor pattern ACT1 and a second semiconductor pattern ACT2. The semiconductor layer may further include a third semiconductor pattern ACT3.

[0146] The semiconductor layer may include amorphous silicon, polycrystalline silicon, low temperature polycrystalline silicon and an organic semiconductor. In an embodiment, the semiconductor layer may be an oxide semiconductor. In some embodiments, the semiconductor layer may include a channel region and a source region and a drain region located on both sides of the channel region and doped with impurities.

[0147] The first gate insulating layer 112 is located on the semiconductor layer. The first gate insulating layer 112 may be an inorganic layer. The first gate insulating layer 112 may be a single-layer structure or a multi-layer structure.

[0148] The first conductive layer is located on the first gate insulating layer 112. The first conductive layer may include the first gate electrode GE1 and the second gate electrode GE2 described above. The first conductive layer may also include a first low power pattern VSSL1. The first conductive layer may be formed of a metal material having conductivity. For example, the first conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti). The first conductive layer may be a single-layer structure or a multi-layer structure.

[0149] The first low power pattern VSSL1 may be electrically coupled to the second power line. The first low power pattern VSSL1 may be located in the display area DA, and may overlap the third semiconductor pattern ACT3.

[0150] The second gate insulating layer 113 is located on the first conductive layer. The second gate insulating layer 113 may be an inorganic layer. The second gate insulating layer 113 may be a single-layer structure or a multi-layer structure.

[0151] The second conductive layer is located on the second gate insulating layer 113. The second conductive layer may include a third gate electrode GE3. The third gate electrode GE3 may be a gate electrode of another transistor, but the present disclosure is not limited thereto. The second conductive layer may be formed of a conductive metal material. For example, the second conductive layer may include molybdenum (Mo), aluminum (Al), copper (Cu) and / or titanium (Ti). The second conductive layer may be a single-layer structure or a multi-layer structure.

[0152] The interlayer insulating layer 114 is located on the second conductive layer. The interlayer insulating layer 114 may be an organic layer or an inorganic layer. The interlayer insulating layer 114 may have a single layer structure or a multilayer structure.

[0153] The third conductive layer is located on the interlayer insulating layer 114. The third conductive layer may include the above-mentioned source electrodes SDE2 and SDE4 and drain electrodes SDE1 and SDE3. The third conductive layer may also include a second low power pattern VSSL2. The third conductive layer may be formed of a metal material having electrical conductivity (e.g., electrical conductivity). For example, the source electrodes SDE2 and SDE4, the drain electrodes SDE1 and SDE3, and the second low power pattern VSSL2 may include aluminum (Al), copper (Cu), titanium (Ti), and / or molybdenum (Mo).

[0154] The second low power pattern VSSL2 may be electrically coupled to the second power line. The second low power pattern VSSL2 may contact the first low power pattern VSSL1 through a contact hole formed through the second gate insulating layer 113 and the interlayer insulating layer 114. The second low power pattern VSSL2 may be located in the display area DA and may overlap the first low power pattern VSSL1 and the third semiconductor pattern ACT3.

[0155] The source electrodes SDE2 and SDE4 and the drain electrodes SDE1 and SDE3 are not limited to the names. Fig.14 The source electrodes SDE2 and SDE4 shown in FIG. 1 can perform the function of drain electrodes, Fig.14 The drain electrodes SDE1 and SDE3 shown in FIG. 4 may perform the function of source electrodes.

[0156] The source electrodes SDE2 and SDE4 and the drain electrodes SDE1 and SDE3 may be electrically coupled to the source and drain regions of each of the corresponding semiconductor patterns ACT1 and ACT2 through contact holes formed through the interlayer insulating layer 114 , the second gate insulating layer 113 , and the first gate insulating layer 112 .

[0157] In some embodiments, the display panel may further include a storage capacitor on the base layer SUB1.

[0158] The first protective layer 121 is located on the third conductive layer. Here, the first protective layer 121 is located to cover the circuit including the transistors Tdr and Tsw. The first protective layer 121 may be located in at least a portion of the non-display area NDA. The first protective layer 121 may be a passivation layer or a planarization layer. The passivation layer may include SiO 2 and / or SiN x The first protective layer 121 may include a passivation layer and a planarization layer. In this case, the passivation layer may be located on the third conductive layer and the interlayer insulating layer 114, and the planarization layer may be located on the passivation layer. The upper surface of the first protective layer 121 may be planarized.

[0159] The fourth conductive layer may be located on the first protective layer 121. The fourth conductive layer may include several conductive patterns such as power lines, signal lines, and connection electrodes. In the drawings, the fourth conductive layer includes the first connection pattern CE1 in the display area DA. The fourth conductive layer may be formed of a metal material having electrical conductivity (e.g., electrical conductivity). For example, the fourth conductive layer may include aluminum (Al), copper (Cu), titanium (Ti), and / or molybdenum (Mo).

[0160] The first connection pattern CE1 may contact any one of the source electrode SDE2 and the drain electrode SDE1 of the first transistor Tdr through one contact hole formed through the first protective layer 121 .

[0161] The second protective layer 122 is located on the fourth conductive layer. The second protective layer 122 may be a passivation layer or a planarization layer. The passivation layer may include SiO 2 and / or SiN x The second protective layer 122 may include a passivation layer and / or a planarization layer.

[0162] In some embodiments, the second protective layer 122 may include openings to expose upper portions of some members of the fourth conductive layer included in the fourth conductive layer. For example, the second protective layer 122 may include openings to expose at least a portion of the first connection pattern CE1.

[0163] Here, the base layer SUB1 to the second protective layer 122 are referred to as a pixel circuit layer.

[0164] The display panel may include first and second partition walls PW1 and PW21, first and second electrodes ETL1 and ETL21, an insulating layer 131, a bank BNK, a light emitting element LD, a first organic layer 141, first and second contact electrodes CNE1 and CNE21, a second organic layer 142, and a thin film encapsulation layer 151 sequentially located on the second protective layer 122 in the display area DA.

[0165] Although it is shown in the drawings that the above-mentioned elements are directly and sequentially located on the second protective layer 122 , some elements may be omitted or other elements may be further located between the elements.

[0166] The first partition wall PW1 and the second partition wall PW21 may be located on the pixel circuit layer (e.g., the second protective layer 122). The first partition wall PW1 and the second partition wall PW21 may protrude from the pixel circuit layer in the thickness direction (e.g., the third direction DR3). In an embodiment, the first partition wall PW1 and the second partition wall PW21 may have the same (e.g., substantially the same) height, but the present disclosure is not limited thereto. For example, the protruding height of each of the first partition wall PW1 and the second partition wall PW21 may be in the range of about 1.0 μm to about 1.5 μm.

[0167] In an embodiment, the first partition wall PW1 may be located between the pixel circuit layer and the first electrode ETL1. The second partition wall PW21 may be located between the pixel circuit layer and the second electrodes ETL21, ETL22, and ETL23 (wherein, Fig.13 The diagram shows the second electrodes ETL22 and ETL23).

[0168] In an embodiment, each of the first partition wall PW1 and the second partition wall PW21 may have various suitable shapes. For example, as shown in the drawings, each of the first partition wall PW1 and the second partition wall PW21 may have a trapezoidal cross-sectional shape whose width decreases from the bottom to the top thereof. In this case, each of the first partition wall PW1 and the second partition wall PW21 may have an inclined surface on at least one side.

[0169] As another example, each of the first partition wall PW1 and the second partition wall PW21 may have a semicircular or semi-elliptical cross-section whose width decreases from the bottom to the top thereof. In this case, each of the first partition wall PW1 and the second partition wall PW21 may have a curved surface on at least one side. In other words, the shape of each of the first partition wall PW1 and the second partition wall PW21 may be changed in various suitable ways without being particularly limited. In an embodiment, at least one of the first partition wall PW1 and the second partition wall PW21 may be omitted or the position may be changed.

[0170] Each of the first partition wall PW1 and the second partition wall PW21 may include an insulating material, and the insulating material includes an inorganic material or an organic material. For example, the first partition wall PW1 and the second partition wall PW21 may include at least one inorganic layer, and the at least one inorganic layer includes various suitable inorganic insulating materials commonly used in the art, such as SiN x and / or SiOx In some embodiments, the first partition wall PW1 and the second partition wall PW21 may include at least one organic layer and / or a photoresist layer including various suitable organic insulating materials, or may be combined to form a single-layer insulator or a multi-layer insulator including organic / inorganic materials. In other words, the materials of the first partition wall PW1 and the second partition wall PW21 may be variously changed.

[0171] In an embodiment, each of the first partition wall PW1 and the second partition wall PW21 may be used as a reflective member. For example, the first partition wall PW1 and the second partition wall PW21 together with the first electrode ETL1 and the second electrode ETL21 disposed on the first partition wall PW1 and the second partition wall PW21 may be used as a reflective member to guide light emitted from each light emitting element LD in a desired direction, thereby enhancing the light efficiency of the pixel PXL.

[0172] The first electrode ETL1 and the second electrode ETL21 may be respectively located on the first partition wall PW1 and the second partition wall PW21. The first electrode ETL1 and the second electrode ETL21 may be spaced apart from each other. The first electrode ETL1 and the second electrode ETL21 may be formed on the same layer (eg, at the same level).

[0173] In an embodiment, the first electrode ETL1 and the second electrode ETL21 on the upper portions of the first partition wall PW1 and the second partition wall PW21, respectively, may have shapes corresponding to the corresponding shapes of the first partition wall PW1 and the second partition wall PW21. For example, the first electrode ETL1 and the second electrode ETL21 may each protrude in the thickness direction of the display panel while having an inclined surface or a curved surface corresponding to the first partition wall PW1 and the second partition wall PW21, respectively.

[0174] Each of the first electrode ETL1 and the second electrode ETL21 may include at least one conductive material. For example, each of the first electrode ETL1 and the second electrode ETL21 may include at least one of a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti and / or an alloy thereof, a conductive oxide such as ITO, IZO, ZnO and / or ITZO, and a conductive polymer such as PEDOT; however, not limited thereto.

[0175] In addition, each of the first electrode ETL1 and the second electrode ETL21 may have a single-layer structure or a multi-layer structure. For example, each of the first electrode ETL1 and the second electrode ETL21 may include at least one reflective electrode layer. Each of the first electrode ETL1 and the second electrode ETL21 may selectively further include at least one of at least one transparent electrode layer on the upper and / or lower portion of the reflective electrode layer and at least one conductive cover layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0176] According to an embodiment, the reflective electrode layer of each of the first electrode ETL1 and the second electrode ETL21 may be formed of an electrode material having a uniform (e.g., substantially uniform) reflectivity. For example, the reflective electrode layer may include at least one of a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and an alloy thereof; however, the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various suitable reflective electrode materials. When each of the first electrode ETL1 and the second electrode ETL21 includes a reflective electrode layer, light emitted from both ends (i.e., the first end and the second end) of each of the light emitting elements LD may further advance in the direction of displaying an image (e.g., the third direction DR3, the positive direction). For example, if the first electrode ETL1 and the second electrode ETL21 are positioned to face the first and second ends of the light emitting element LD while having an inclined surface or a curved surface corresponding to the shape of the first and second partition walls PW1 and PW21, light emitted from the first and second ends of each of the light emitting elements LD may be reflected by the first and second electrodes ETL1 and ETL21, and may then further travel in the positive direction of the display panel (e.g., the third direction DR3 which is the upper direction of the base layer SUB1). As a result, the efficiency of light emitted from the light emitting element LD may be improved.

[0177] In addition, the transparent electrode layer of each of the first electrode ETL1 and the second electrode ETL21 may be formed of various suitable transparent electrode materials. For example, the transparent electrode layer may include ITO, IZO and / or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ETL1 and the second electrode ETL21 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, if the first electrode ETL1 and the second electrode ETL21 are each composed of a multilayer structure of two or more layers, the voltage drop caused by the signal delay (RC delay) can be minimized or reduced. Therefore, a suitable or desired voltage can be effectively transmitted to the light emitting element LD.

[0178] In addition, if each of the first electrode ETL1 and the second electrode ETL21 includes a conductive covering layer covering the reflective electrode layer and / or the transparent electrode layer, damage to the reflective electrode layer of the first electrode ETL1 and the second electrode ETL21 due to defects caused during the manufacturing process of the pixel PXL can be prevented or reduced. However, the conductive covering layer may be selectively included in the first electrode ETL1 and the second electrode ETL21, and may be omitted according to the embodiment. In addition, the conductive covering layer may be considered as a component of each of the first electrode ETL1 and the second electrode ETL21, or as a separate component on the first electrode ETL1 and the second electrode ETL21.

[0179] In the embodiment, the second electrodes ETL21, ETL22 and ETL23 (wherein the second electrodes ETL22 and ETL23 are Fig.13 At least some areas of the second protective layer 122 (shown in FIG. 1 ) may overlap the first connection pattern CE1. The second electrodes ETL21, ETL22, and ETL23 may contact the first connection pattern CE1 through the contact holes CH formed through the second protective layer 122.

[0180] The insulating layer 131 may be located in one region of each of the first electrode ETL1 and the second electrode ETL21 in the display area DA. For example, the insulating layer 131 may be formed to cover one region of each of the first electrode ETL1 and the second electrode ETL21, and may include an opening to expose another region of each of the first electrode ETL1 and the second electrode ETL21.

[0181] In some embodiments, the insulating layer 131 may be disposed between the first and second electrodes ETL1 and ETL21 and the light emitting element LD, and may expose at least one region of each of the first and second electrodes ETL1 and ETL21. After forming the first and second electrodes ETL1 and ETL21, the insulating layer 131 is formed to cover the first and second electrodes ETL1 and ETL21, thereby being able to prevent or reduce damage to the first and second electrodes ETL1 and ETL21 or to prevent or reduce precipitation of metal in subsequent processes. In addition, the insulating layer 131 may stably support each light emitting element LD. In an embodiment, the insulating layer 131 may be omitted.

[0182] The light emitting element LD may be supplied and aligned (or aligned, arranged) between the first electrode ETL1 and the second electrode ETL21 in the region where the insulating layer 131 is positioned. For example, the light emitting element LD may be supplied by an inkjet method or the like, and the light emitting element LD may be aligned between the first electrode ETL1 and the second electrode ETL21 by a set or predetermined alignment (or alignment, arrangement) voltage (or alignment (or alignment, arrangement) signal) applied to the first electrode ETL1 and the second electrode ETL21.

[0183] In an embodiment, the thickness of the insulating layer 131 may be about to about within the range.

[0184] The bank BNK may be located on the insulating layer 131. For example, the bank BNK may be formed between other sub-pixels to surround the sub-pixel ( Figure 8 The height of the bank BNK may be higher than that of the partition walls PW1 and PW21.

[0185] In some embodiments, the bank BNK may not be between the unit pixels SSPX1 to SSPXk in the same sub-pixels SPX1 to SPX3 , but the present disclosure is not limited thereto.

[0186] The first organic layer 141 may be positioned on the insulating layer 131 , the first and second electrodes ETL1 and ETL21 , and the light emitting element LD.

[0187] In an embodiment, the first organic layer 141 may include an organic material. For example, the organic material may include a material such as polyimide resin, acrylic resin, silicon compound, and / or polyacrylic resin.

[0188] In an embodiment, the first organic layer 141 may include a first organic pattern 1411 in direct contact with the second electrode ETL21, a second organic pattern 1412 in direct contact with the first electrode ETL1, and a third organic pattern 1413 in direct contact with the light emitting element LD. The third organic pattern 1413 may be located between the first organic pattern 1411 and the second organic pattern 1412, and each of the first organic pattern 1411 and the second organic pattern 1412 may be located between the bank BNK and the third organic pattern 1413.

[0189] The third organic pattern 1413 may be directly located on the light emitting element LD aligned between the first electrode ETL1 and the second electrode ETL21, and may expose the first end and the second end of the light emitting element LD. For example, the third organic pattern 1413 may be only partially located on one region of each of the light emitting elements LD without covering the first end and the second end of the light emitting element LD. The third organic pattern 1413 may be formed in a separate pattern on each light emitting region; however, the present disclosure is not limited thereto. In addition, as Fig.14 As shown in , if there is a space between the insulating layer 131 and each of the light emitting elements LD before forming the third organic pattern 1413, the space can be filled with the third organic pattern 1413. As a result, the light emitting element LD can be supported more stably. In other embodiments, the space between the insulating layer 131 and each of the light emitting elements LD can be omitted.

[0190] In an embodiment, the first organic pattern 1411 and the third organic pattern 1413 may be spaced apart from each other, and the second organic pattern 1412 and the third organic pattern 1413 may be spaced apart from each other. A space defined between the first organic pattern 1411 and the third organic pattern 1413 may expose at least a portion of the second electrode ETL21 and a first end portion of the light emitting element LD, and a space defined between the second organic pattern 1412 and the third organic pattern 1413 may expose at least a portion of the first electrode ETL1 and a second end portion of the light emitting element LD.

[0191] The upper surface of the first organic layer 141 may be substantially flat. In other words, the first to third organic patterns 1411, 1412, and 1413 may generally have the same (e.g., substantially the same) height. In an embodiment, the bank BNK and the first to third organic patterns 1411, 1412, and 1413 may generally have the same (e.g., substantially the same) height. Therefore, the display panel may have a substantially flat surface on the bank BNK and the first to third organic patterns 1411, 1412, and 1413.

[0192] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE21 may be located on the same layer (e.g., located at the same level). The first contact electrode CNE1 and the second contact electrode CNE21 may be formed along the edge of the space defined by the first to third organic patterns 1411, 1412, and 1413. For example, the first contact electrode CNE1 may be formed along the edge of the space between the second organic pattern 1412 and the third organic pattern 1413. In addition, the second contact electrode CNE21 may be positioned along the edge of the space between the first organic pattern 1411 and the third organic pattern 1413. Therefore, each of the first contact electrode CNE1 and the second contact electrode CNE21 may define a groove on an upper portion thereof.

[0193] The first contact electrode CNE1 may be located on the first electrode ETL1 to contact the first electrode ETL1. For example, the first contact electrode CNE1 may be located to contact the first electrode ETL1 on an area of ​​the first electrode ETL1 that is not covered by the insulating layer 131 and the second organic pattern 1412. In addition, the first contact electrode CNE1 may be located on ends of at least two light emitting elements LD adjacent to the first electrode ETL1 to contact the ends of the at least two light emitting elements LD. In other words, the first contact electrode CNE1 may be located to cover the first end or the second end of each of the light emitting elements LD and at least one area of ​​the first electrode ETL1 corresponding thereto. Thus, the first end or the second end of each of the light emitting elements LD may be electrically coupled to each of the first electrodes ETL1.

[0194] The second contact electrode CNE21 may be located on the second electrode ETL21 to contact the second electrode ETL21. For example, the second contact electrode CNE21 may be located to contact the second electrode ETL21 on an area of ​​the second electrode ETL21 that is not covered by the insulating layer 131 and the first organic pattern 1411. In addition, the second contact electrode CNE21 may be located on the ends of at least two light emitting elements LD adjacent to the second electrode ETL21 to contact the ends of the at least two light emitting elements LD. In other words, the second contact electrode CNE21 may be located to cover the first end or the second end of each of the light emitting elements LD and at least one area of ​​the second electrode ETL21 corresponding thereto. Thus, the first end or the second end of each of the light emitting elements LD may be electrically coupled to each second electrode ETL21.

[0195] In embodiments, each of the first and second contact electrodes CNE1 and CNE21 may be formed of a transparent conductive material such as ITO, IZO, and / or ITZO to allow transmission of light emitted from the light emitting element LD.

[0196] In embodiments, the second organic layer 142 may be located on the first and second contact electrodes CNE1 and CNE21 to cover the first and second contact electrodes CNE1 and CNE21 .

[0197] The second organic layer 142 may include a fourth organic pattern 1421 directly on the second contact electrode CNE21 and a fifth organic pattern 1422 directly on the first contact electrode CNE1. The fourth organic pattern 1421 and the fifth organic pattern 1422 may fill the grooves on the second contact electrode CNE21 and the first contact electrode CNE1, respectively. In an embodiment, the bank BNK, the first to third organic patterns 1411, 1412, and 1413, the first and second contact electrodes CNE1 and CNE21, and the fourth and fifth organic patterns 1421 and 1422 may have the same (e.g., substantially the same) height. Therefore, the display panel may have an almost flat surface on the bank BNK, the first to third organic patterns 1411, 1412, and 1413, the first and second contact electrodes CNE1 and CNE21, and the fourth and fifth organic patterns 1421 and 1422.

[0198] In embodiments, the second organic layer 142 may include an organic material, such as a polyimide resin, an acrylic resin, a silicon compound, and / or a polyacrylic resin.

[0199] The display panel may have a thin film encapsulation layer 151 on the bank BNK, the first to third organic patterns 1411, 1412, and 1413, the first and second contact electrodes CNE1 and CNE21, and the fourth and fifth organic patterns 1421 and 1422 to cover them. The thin film encapsulation layer 151 may include another insulating layer. In an embodiment, the thin film encapsulation layer 151 may be a passivation layer. In an embodiment, the thin film encapsulation layer 151 may be omitted.

[0200] Next, refer to Figures 15 to 26 Hereinafter, since each effective operation of the manufacturing process of the display panel is a part of the manufacturing method of the display device, the manufacturing method of the display panel will be referred to as the manufacturing method of the display device.

[0201] Fig.15 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. Figures 16 to 26 It is shown in Fig.15 Cross-sectional views of the various processes described in the flow chart.

[0202] Reference Fig.15According to the embodiment, the manufacturing method of the display device may include an insulating layer forming step S110, a dam forming step S120, a light emitting element aligning (or aligning, arranging) step S130, a first organic layer forming step S140, a contact electrode forming step S150 and a thin film encapsulation layer forming step S160.

[0203] Although it is described herein that corresponding valid operations are sequentially performed according to the flowchart, it should be obvious to those skilled in the art that, unless the spirit of the present disclosure is changed, some valid operations shown as being performed sequentially may be performed concurrently (e.g., simultaneously), the order of the valid operations may be changed, some valid operations may be omitted, or another valid operation may be further included between the corresponding valid operations. In addition, Fig.15 The manufacturing method of the display device shown in corresponds to some effective operations of manufacturing a display panel. Figures 16 to 26 A process of manufacturing the insulating layer 131 to the thin film encapsulation layer 151 during the manufacturing process of the display panel is shown.

[0204] First, refer to Fig.16 , an insulating layer forming step S110 may be performed. The insulating layer forming step S110 corresponds to forming the insulating layer 131 .

[0205] A first insulating material layer 131 a is disposed throughout the entire surface of the display panel to cover the partition walls PW1 and PW21 and the first and second electrodes ETL1 and ETL21 , and a photoresist material is applied to the first insulating material layer 131 a .

[0206] The first insulating material layer 131a and the photoresist material can be applied by a slit coating method, a spin coating method and / or a gravure printing method. The photoresist material can be a positive photoresist material or a negative photoresist material. The photoresist material shown in the present embodiment includes a positive photoresist material, but the present disclosure is not limited thereto. Here, the first insulating material layer 131a includes the material included in the insulating layer 131.

[0207] Subsequently, a first mask 201 may be positioned on the first insulating material layer 131a and the photoresist material. The first mask 201 may include a transmissive portion 201a and a non-transmissive portion 201b. The non-transmissive portion 201b corresponds to a region where the insulating layer 131 is to be formed, and the transmissive portion 201a corresponds to a region other than the region where the insulating layer 131 is to be formed (e.g., a region where the first insulating material layer 131a is to be removed).

[0208] Subsequently, after performing an exposure process, a development process, and an etching process, the Fig.17 The insulating layer 131 is completed as shown in FIG.

[0209] Next, refer to Fig.17 , a bank forming step S120 may be performed. The bank forming step S120 corresponds to forming a bank BNK.

[0210] A bank material layer BNKa is disposed over the entire surface of the display panel to cover the partition walls PW1 and PW21, the first and second electrodes ETL1 and ETL21, and the insulating layer 131, and a photoresist material is applied to the bank material layer BNKa. Here, the bank material layer BNKa includes a material included in the bank BNK.

[0211] Subsequently, a second mask 202 may be positioned on the bank material layer BNKa and the photoresist material. The second mask 202 may include a transmissive portion 202a and a non-transmissive portion 202b. The non-transmissive portion 202b corresponds to an area where the bank BNK is to be formed, and the transmissive portion 202a corresponds to an area other than the area where the bank BNK is formed.

[0212] Subsequently, after performing an exposure process, a development process, and an etching process, the Fig.18 The completed embankment is shown in BNK.

[0213] Next, refer to Fig.18 , a light emitting element alignment step S130 may be performed. The light emitting element alignment step S130 corresponds to aligning the light emitting element LD.

[0214] A solution 300 including at least one light emitting element LD may be disposed in a region in which the first electrode ETL1 and the second electrode ETL21 are formed. As a non-limiting example of a method of placing the light emitting element LD on each of the first electrode ETL1 and the second electrode ETL21, an inkjet printing method and / or a fine drop process (or fine drop process) of 50 pL or less corresponding thereto may be used.

[0215] For example, a solution 300 including a light emitting element LD may be dropped in a state where a DC voltage or an AC voltage is applied to the first and second electrodes ETL1 and ETL21. The light emitting element LD may be self-aligned (or self-aligned, self-positioned, self-arranged) between the first and second electrodes ETL1 and ETL21.

[0216] For example, the self-alignment of the light emitting element LD may be induced by applying a DC voltage or an AC voltage to the first electrode ETL1 and the second electrode ETL21. In some embodiments, if a voltage is applied to the first electrode ETL1 and the second electrode ETL21, bipolarity is induced in the light emitting element LD by an electric field generated between the first electrode ETL1 and the second electrode ETL21. Fig.19 As shown in , the light emitting element LD is self-aligned between the first electrode ETL1 and the second electrode ETL21.

[0217] In some embodiments, Figures 16 to 18 In contrast to the effective operation of the embodiment, after the light emitting element LD is supplied on the first insulating material layer 131a and aligned on the first insulating material layer 131a, the first insulating material layer 131a may be partially opened to expose the first electrode ETL1 and the second electrode ETL21. For example, the above operations may be performed in an order different from that described herein.

[0218] Reference Figures 19 to 23 , a first organic layer forming step S140 may be performed. The first organic layer forming step S140 corresponds to forming a first organic layer 141 .

[0219] The first organic layer forming step S140 may include a plurality of sub-operations. For example, the first organic layer forming step S140 may include a first organic material layer forming step S141, a first photoresist material forming step S142, an exposure step S143, an etching step S144 and / or a developing step S145. The first organic material layer forming step S141, the first photoresist material forming step S142, the exposure step S143, the etching step S144 and the developing step S145 correspond to Figures 19 to 23 .

[0220] First, if Fig.19 As shown in FIG. 1 , in the first organic material layer forming step S141 , a first organic material layer 141 a may be provided over the entire surface of the display panel to cover the insulating layer 131 , the first and second electrodes ETL1 and ETL21 , and the light emitting element LD. Here, the first organic material layer 141 a includes the material included in the first organic layer 141 .

[0221] In embodiments, the first organic material layer 141a may be applied to a portion between the banks BNK. However, not limited thereto, in embodiments, the first organic material layer 141a may be applied to cover the banks BNK, the insulating layer 131, the first and second electrodes ETL1 and ETL21, and the light emitting element LD.

[0222] Then, if Fig. 20 As shown in the figure, in the first photoresist material forming step S142 and the exposure step S143, the first photoresist material PR1 is applied to the first organic material layer 141a. For example, the first photoresist material PR1 can be applied by a slit coating method, a spin coating method and / or a gravure printing method. The first photoresist material PR1 can be a positive photoresist material, but the present disclosure is not limited thereto.

[0223] Then, if Fig.21 As shown in , the third mask 203 may be located on the first organic material layer 141a and the first photoresist material PR1. The third mask 203 may include a transmissive portion 203a and a non-transmissive portion 203b. The non-transmissive portion 203b corresponds to a region where the first to third organic patterns 1411, 1412, and 1413 are to be formed, and the transmissive portion 203a corresponds to a region other than the region where the first to third organic patterns 1411, 1412, and 1413 are formed (e.g., a region where the first organic material layer 141a is to be removed). The region other than the region where the first to third organic patterns 1411, 1412, and 1413 are formed may be a region where the first contact electrode CNE1 and the second contact electrode CNE21 are formed.

[0224] Light (e.g., UV light or laser) may be emitted toward the display panel on the third mask 203. The accompanying drawings show the emitted light. The light may pass through the transmission portion 203a of the third mask 203, and may not pass through the non-transmission portion 203b. The light may pass through the transmission portion 203a, and then may be irradiated onto the corresponding area on the first photoresist material PR1.

[0225] Then, if Fig. 22 and Fig.23 As shown in FIG. 1 , in the etching step S144 and the developing step S145, the first organic material layer 141a may be divided into first to third organic patterns 1411, 1412, and 1413 by an etchant. In addition, the first photoresist material PR1 may be removed by developing or stripping.

[0226] After performing the etching step S144 and the developing step S145, the first to third organic patterns 1411, 1412 and 1413 can be formed, the second electrode ETL21, the insulating layer 131 and the first end of the light emitting element LD can be exposed between the first organic pattern 1411 and the third organic pattern 1413, and the first electrode ETL1, the insulating layer 131 and the second end of the light emitting element LD can be exposed between the second organic pattern 1412 and the third organic pattern 1413.

[0227] Reference Fig.24 and Fig.25 , a contact electrode forming step S150 may be performed. The contact electrode forming step S150 corresponds to forming contact electrodes CNE1, CNE21, CNE22, and CNE23. The contact electrode forming step S150 may include a plurality of sub-operations. For example, the contact electrode forming step S150 may include a contact electrode material layer forming step S151 and a second organic material layer forming and etching step S152.

[0228] First, if Fig.24 As shown in FIG. 1 , in the contact electrode material layer forming step S151, a contact electrode material layer CNEa may be provided over the entire surface of the display panel to cover the end of the light emitting element LD, the first to third organic patterns 1411, 1412, and 1413, the first electrode ETL1, the second electrode ETL21, and the insulating layer 131. Here, the contact electrode material layer CNEa includes the material included in the first contact electrode CNE1 and the second contact electrode CNE21.

[0229] The contact electrode material layer CNEa may be formed on upper portions of the first to third organic patterns 1411, 1412, and 1413 and edges between the first to third organic patterns 1411, 1412, and 1413. The contact electrode material layer CNEa may define a groove on an upper portion thereof and between the first to third organic patterns 1411, 1412, and 1413. In addition, the contact electrode material layer CNEa may be formed to contact an end portion of the light emitting element LD, the first electrode ETL1, and the second electrode ETL21.

[0230] Then, if Fig.25 As shown in the second organic material layer forming and etching step S152, a second organic material layer 142a may be formed between the first to third organic patterns 1411, 1412, and 1413. The second organic material layer 142a may be formed by coating the above-mentioned grooves. Subsequently, an etching process may be performed. For example, the etching process may be a wet etching process. Through the etching process, the contact electrode material layer CNEa may be removed from the region overlapping with the upper portion of the first to third organic patterns 1411, 1412, and 1413, and the contact electrode material layer CNEa may remain in the region overlapping with the second organic material layer 142a. Fig.26 As shown in FIG. 1 , the remaining contact electrode material layer CNEa may become the first contact electrode CNE1 and the second contact electrode CNE21. In addition, the second organic material layer 142a may become the fourth organic pattern 1421 in a region overlapping the second contact electrode CNE21, and may become the fifth organic pattern 1422 in a region overlapping the first contact electrode CNE1.

[0231] When the contact electrode material layer CNEa is formed into the first and second contact electrodes CNE1 and CNE21 through the contact electrode material layer forming step S151 and the second organic material layer forming and etching step S152 , the first and second contact electrodes CNE1 and CNE21 may be formed without separate masks.

[0232] Then, if Fig.26 As shown in FIG. 1 , a display device may be manufactured through a thin film encapsulation layer forming step S160 of forming a thin film encapsulation layer 151 on the first to third organic patterns 1411 , 1412 , and 1413 , the first contact electrode CNE1 , and the second contact electrode CNE21 .

[0233] Next, the display device according to the embodiment will be described. Figures 1 to 26 The components shown in FIG. 1 are described repeatedly and the same or similar reference numerals are used.

[0234] Fig. 27 is a cross-sectional view showing a display panel according to an embodiment of the present disclosure. Fig.28 and Fig.29 It is shown Fig. 27 Cross-sectional views of some processes of a method for manufacturing a display device. Fig. 27 Shows the pair with Fig.13 The portion intercepted by line II' corresponds to the modification of the portion.

[0235] Fig. 27 Examples and Fig.14 The embodiment of FIG. 1 is different in that the fourth organic pattern 1421 and the fifth organic pattern 1422 are omitted.

[0236] Reference Fig.28 and Fig.29 , the contact electrode forming step S150 may include a contact electrode material layer forming step S151 and a second photoresist material forming and etching step S152_1. For example, in the contact electrode forming step S150, a second photoresist material PR2 may be applied between the first to third organic patterns 1411, 1412, and 1413 on the contact electrode material layer CNEa, and then the second photoresist material PR2 may be etched.

[0237] After the second photoresist material forming and etching step S152_1, the contact electrode material layer CNEa may be removed from the region overlapping the upper portion of the first to third organic patterns 1411, 1412, and 1413, and the second photoresist material PR2 may also be removed. In this case, the contact electrode material layer CNEa may remain in the region overlapping the second photoresist material PR2. The remaining contact electrode material layer CNEa may be divided into the first contact electrode CNE1 and the second contact electrode CNE21.

[0238] Figure 30 to Figure 33 is a circuit diagram showing another example applicable to a unit pixel included in a sub-pixel of a display panel according to an embodiment of the present disclosure. Fig.30 The unit pixel SSPX1_4 is shown, Fig.31 The unit pixel SSPX1_5 is shown, Fig.32 shows a unit pixel SSPX1_6, and Fig.33 A unit pixel SSPX1_7 is shown. Figure 30 to Figure 33 Corresponding to Figures 9 to 12 modification.

[0239] Reference Figure 30 to Figure 33 In some embodiments, a plurality of light emitting elements LD may be connected in series or in parallel.

[0240] Fig.34 is a plan layout diagram showing the arrangement of some components in one sub-pixel included in a display panel according to another embodiment of the present disclosure. Fig.35 The display panel is along Fig.34 A cross-sectional view taken along line II-II'. Fig.34 and Fig.35 The display panel shown in FIG. 1 corresponds to the application of Figure 30 to Figure 33 Since the first to third unit pixels SSPX1 to SSPX3 are substantially identical to one another, the first unit pixel SSPX1 will be mainly described.

[0241] Reference Fig.34 and Fig.35 According to the display panel of this embodiment, Fig.13 and Fig.14 The display panel of EMBODIMENT 1 is different in that island-shaped electrodes ETL31 , ETL32 , ETL33 , ETL41 , ETL42 , and ETL43 are included between the first electrode ETL1 and the second electrodes ETL21 , ETL22 , and ETL23 .

[0242] Each of the first to fourth electrodes ETL1, ETL21, ETL31, and ETL41 in the first unit pixel SSPX1 may extend in the first direction DR1, and may be spaced apart from each other by a set or predetermined interval in the second direction DR2 to be arranged side by side (in parallel, for example, substantially in parallel with each other). In an embodiment, the length of the first electrode ETL1 extending in the first direction DR1 may be longer than the length of the second to fourth electrodes ETL21, ETL31, and ETL41 extending in the first direction DR1. The third electrode ETL31 and the fourth electrode ETL41 may be located between the first electrode ETL1 and the second electrode ETL21. The third electrode ETL31 and the fourth electrode ETL41 may be island electrodes floating relative to the first electrode ETL1 and the second electrode ETL21. Therefore, each of the third electrode ETL31 and the fourth electrode ETL41 may be referred to as an island electrode.

[0243] According to an embodiment, the first electrode ETL1 may be an electrode shared by the first to third unit pixels SSPX1 to SSPX3. In this case, the first to third unit pixels SSPX1 to SSPX3 may be arranged along the first direction DR1. Each of the first to fourth electrodes ETL1, ETL22, ETL32, and ETL42 in the second unit pixel SSPX2 may extend in the first direction DR1, and may be spaced apart from each other by a set or predetermined interval in the second direction DR2 to be arranged side by side (in parallel, for example, substantially parallel to each other). Similarly, each of the first to fourth electrodes ETL1, ETL23, ETL33, and ETL43 in the third unit pixel SSPX3 may extend in the first direction DR1, and may be spaced apart from each other by a set or predetermined interval in the second direction DR2 to be arranged side by side (in parallel, for example, substantially parallel to each other).

[0244] The light emitting element LD may be located between the first electrode ETL1 and the second electrode ETL21 , between the second electrode ETL21 and the third electrode ETL31 , and between the third electrode ETL31 and the fourth electrode ETL41 .

[0245] exist Fig.35 In the embodiment, the fourth conductive layer on the first protection layer 121 includes first to fifth conductive patterns CE1 to CE5.

[0246] The second conductive pattern CE2 can be coupled to any one of the source electrode SDE31 and the drain electrode SDE41 of the first transistor Tdr through one contact hole formed through the first protective layer 121, and the fifth conductive pattern CE5 can be coupled to the remaining one of the source electrode SDE31 and the drain electrode SDE41 of the first transistor Tdr through another contact hole formed through the first protective layer 121.

[0247] First to fourth partition walls PW1, PW21, PW31 and PW41, first to fourth electrodes ETL1, ETL21, ETL31 and ETL41, an insulating layer 131, a light emitting element LD, a first organic layer 141, first to fourth contact electrodes CNE1, CNE21, CNE31 and CNE41, a second organic layer 142 and a thin film encapsulation layer 151 may be sequentially located on the second protective layer 122.

[0248] The first to fourth partition walls PW1, PW21, PW31, and PW41 may be located on the pixel circuit layer (eg, the second protective layer 122). The first to fourth partition walls PW1, PW21, PW31, and PW41 may protrude from the pixel circuit layer in a thickness direction (eg, a third direction DR3).

[0249] The first to fourth electrodes ETL1, ETL21, ETL31, and ETL41 may be located on the first to fourth partition walls PW1, PW21, PW31, and PW41, respectively. The first to fourth electrodes ETL1, ETL21, ETL31, and ETL41 may be spaced apart from each other.

[0250] In an embodiment, at least a portion of the first electrode ETL1 may overlap with the first conductive pattern CE1, at least a portion of the second electrode ETL21 may overlap with the fourth conductive pattern CE4 and the fifth conductive pattern CE5, at least a portion of the third electrode ETL31 may overlap with the second conductive pattern CE2, and at least a portion of the fourth electrode ETL41 may overlap with the third conductive pattern CE3.

[0251] The first electrode ETL1 may be electrically coupled to the first conductive pattern CE1 through the first contact hole CNT11, and the second electrode ETL21 may be electrically coupled to the fifth conductive pattern CE5 through the second contact hole CNT21. The second protective layer 122 may further include a third contact hole CNT22 and a fourth contact hole CNT23. The fifth conductive pattern CE5 may correspond to Fig.14 The third electrode ETL31 may be insulated from the second conductive pattern CE2, the fourth electrode ETL41 may be insulated from the third conductive pattern CE3, and the second electrode ETL21 may be insulated from the fourth conductive pattern CE4.

[0252] The first to fourth contact electrodes CNE1, CNE21, CNE31, and CNE41 may be located on the first and second ends of the light emitting element LD and the first to fourth electrodes ETL1, ETL21, ETL31, and ETL41. In an embodiment, the first to fourth contact electrodes CNE1, CNE21, CNE31, and CNE41 may be located on the first and second ends of the light emitting element LD and the first to fourth electrodes ETL1, ETL21, ETL31, and ETL41. Fig.35 In this case, the first to fourth contact electrodes CNE1, CNE21, CNE31, and CNE41 may be formed in the same (eg, substantially the same) process using the same (eg, substantially the same) electrode material.

[0253] The first contact electrode CNE1 may be located on the first electrode ETL1 to contact the first electrode ETL1. For example, the first contact electrode CNE1 may be located to contact (e.g., physically contact) the first electrode ETL1 on an area of ​​the first electrode ETL1 that is not covered by the insulating layer 131. In addition, the first contact electrode CNE1 may be located on the first end to contact at least one light emitting element LD adjacent to the first electrode ETL1, for example, to contact the first ends of the plurality of light emitting elements LD. In other words, the first contact electrode CNE1 may be located to cover the first end of each of the light emitting elements LD and at least one area of ​​the first electrode ETL1 corresponding thereto. Thus, the first end of each of the light emitting elements LD may be electrically coupled to the first electrode ETL1.

[0254] Similarly, the third contact electrode CNE31 may be located on the third electrode ETL31 to contact the third electrode ETL31. For example, the third contact electrode CNE31 may be located to contact the third electrode ETL31 on an area of ​​the third electrode ETL31 that is not covered by the insulating layer 131. In addition, the third contact electrode CNE31 may be located on the ends of at least two light emitting elements LD adjacent to the third electrode ETL31 to contact the ends of the at least two light emitting elements LD. In other words, the third contact electrode CNE31 may be located to cover the first end or the second end of each of the light emitting elements LD and at least one area of ​​the third electrode ETL31 corresponding thereto. Thus, the first end or the second end of each of the light emitting elements LD may be electrically coupled to the third electrode ETL31.

[0255] Similarly, the fourth contact electrode CNE41 may be located on the fourth electrode ETL41 to contact the fourth electrode ETL41. For example, the fourth contact electrode CNE41 may be located to contact the fourth electrode ETL41 on an area of ​​the fourth electrode ETL41 that is not covered by the insulating layer 131. In addition, the fourth contact electrode CNE41 may be located on the ends of at least two light emitting elements LD adjacent to the fourth electrode ETL41 to contact the ends of the at least two light emitting elements LD. In other words, the fourth contact electrode CNE41 may be located to cover the first end or the second end of each of the light emitting elements LD and at least one area of ​​the fourth electrode ETL41 corresponding thereto. Thus, the first end or the second end of each of the light emitting elements LD may be electrically coupled to the fourth electrode ETL41.

[0256] Similarly, the second contact electrode CNE21 may be located on the second electrode ETL21 to contact the second electrode ETL21. For example, the second contact electrode CNE21 may be located to contact the second electrode ETL21 on one region of the second electrode ETL21 that is not covered by the insulating layer 131. In addition, the second contact electrode CNE21 may be located on the second end portion to contact the second end portion of at least one light emitting element LD that is adjacent to the second electrode ETL21. In other words, the second contact electrode CNE21 may be located to cover the second end portion of each of the light emitting elements LD and at least one region of the second electrode ETL21 corresponding thereto. Thus, the second end portion of each of the light emitting elements LD may be electrically coupled to the second electrode ETL21.

[0257] In some embodiments, one end of one light emitting element LD may contact the first contact electrode CNE1, and the other end may contact the third contact electrode CNE31. One end of another light emitting element LD may contact the third contact electrode CNE31, and the other end may contact the fourth contact electrode CNE41. One end of yet another light emitting element LD may contact the fourth contact electrode CNE41, and the other end may contact the second contact electrode CNE21.

[0258] In an embodiment of the present disclosure, a method for manufacturing a display device can minimize or reduce the number of masks used.

[0259] Furthermore, since the upper surface of the display device is substantially flat, additional elements can be easily stacked.

[0260] The effects of the present disclosure are not limited to the foregoing, and other various effects are included in the scope of the present disclosure.

[0261] Although the embodiments of the present disclosure have been disclosed, it will be appreciated by those skilled in the art that the present disclosure may be implemented in other specific forms and their equivalents without departing from the scope and spirit of the disclosure as disclosed in the appended claims. Therefore, it should be understood that the exemplary embodiments are for illustrative purposes only and do not limit the boundaries of the present disclosure.

Claims

1. A display device, comprising: A pixel circuit layer including a plurality of transistors; A first partition wall and a second partition wall are located on the pixel circuit layer and both protrude in the thickness direction; A first electrode and a second electrode are located on the same layer and are located on the first partition wall and the second partition wall respectively; a light emitting element, located between the first electrode and the second electrode; A first organic pattern directly located on the light emitting element; a second organic pattern directly located on the first electrode; as well as a third organic pattern, directly located on the second electrode, The first organic pattern, the second organic pattern and the third organic pattern are located on the same layer.

2. The display device according to claim 1, further comprising: a first contact electrode in contact with the first end of the light emitting element and the first electrode; as well as The second contact electrode contacts the second end of the light emitting element and the second electrode.

3. The display device according to claim 2, wherein: The first contact electrode is located between the first organic pattern and the second organic pattern, and Wherein, the second contact electrode is located between the first organic pattern and the third organic pattern.

4. The display device according to claim 3, in, The first contact electrode is positioned along an edge of a groove defined by the first organic pattern and the second organic pattern, and The second contact electrode is positioned along an edge of a groove defined by the first organic pattern and the third organic pattern.

5. The display device according to claim 3, further comprising: a fourth organic pattern directly located on the first contact electrode; as well as The fifth organic pattern is directly located on the second contact electrode.

6. The display device according to claim 5, wherein: The fourth organic pattern and the fifth organic pattern are located on the same layer.

7. The display device according to claim 1, further comprising: an insulating layer located on a portion of each of the first electrode and the second electrode, The insulating layer exposes another portion of each of the first electrode and the second electrode.

8. The display device according to claim 7, in, The insulating layer is located between the first electrode and the second electrode, and The light emitting element is located on a region of the insulating layer between the first electrode and the second electrode.

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