Display panel

Abstract

A display panel includes a first substrate, a pixel disposed on the first substrate and configured to define a display area, a second substrate facing the first substrate, an insulating layer on the first substrate and including an edge closer to the display area than an edge of the first substrate, a conductive layer on the insulating layer, and a sealing member between the first substrate and the second substrate and surrounding the display area.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0179807, filed on December 31, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display panel in which damage caused by static electricity can be reduced. Background Technology

[0003] Typically, a display device is manufactured by forming organic light-emitting diodes (OLEDs) on a lower substrate and bonding the lower substrate to an upper substrate so that the OLEDs are arranged inside the display device. Organic light-emitting display devices can be used as displays for relatively small products such as mobile phones, or as displays for large products such as televisions.

[0004] In the case of an organic light-emitting display device, a sealing member can be used to bond the lower substrate and the upper substrate together, and can be arranged in the peripheral area. In addition to the sealing member, wiring for displaying images, device circuitry, thin inorganic layers, etc., can also be arranged in the peripheral area. Summary of the Invention

[0005] When static electricity is applied to a display panel, problems such as damage to layers (or layers) included in the display panel or peeling of sealing components can occur. This disclosure provides solutions to problems including those described above, and discloses a display panel in which the possibility of damage due to static electricity or the like is reduced. However, this is merely an example, and the scope of the disclosure is not limited thereto.

[0006] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosed embodiments.

[0007] According to one or more embodiments, the display panel includes: a first substrate; pixels disposed on the first substrate and configured to define a display area; a second substrate facing the first substrate; an insulating layer located on the first substrate and including an edge of the display area closer to the edge of the first substrate than the edge of the display area; a conductive layer located on the insulating layer; and a sealing member located between the first substrate and the second substrate and surrounding the display area.

[0008] The sealing component can directly contact the first substrate.

[0009] The sealing member may include an outer surface and an inner surface, wherein, in a plan view, the edge of the insulating layer is located between the outer surface and the inner surface of the sealing member.

[0010] At least a portion of the conductive layer may be stacked with the sealing member.

[0011] The conductive layer can directly contact the sealing component.

[0012] Each pixel in a pixel may include: a pixel electrode; an emitter layer located on the pixel electrode; and a counter electrode located on the emitter layer and electrically connected to the conductive layer.

[0013] The sealing component may include SiO2.

[0014] Insulating layers may include inorganic insulating layers.

[0015] The conductive layer can cover the side surface of the insulating layer corresponding to the edge of the insulating layer.

[0016] The edge of the conductive layer can extend toward the edge of the first substrate beyond the edge of the insulating layer.

[0017] The insulating layer may include sublayers that form step differences.

[0018] The display panel may also include a thin-film transistor electrically connected to one of the pixels and including a semiconductor layer and a gate electrode, wherein the insulating layer includes a first sublayer located on the semiconductor layer and a second sublayer located on the gate electrode.

[0019] According to one or more embodiments, a display panel includes: a first substrate; pixels disposed on the first substrate, defining a display area, and each pixel including a pixel electrode, an emitter layer, and a counter electrode; a second substrate facing the first substrate; an insulating layer located on the first substrate; a conductive layer located on the insulating layer and electrically connected to the counter electrode; and a sealing member located between the first substrate and the second substrate, surrounding the display area, and including an inner surface facing the display area and an outer surface opposite to the inner surface, wherein, in a plan view, the edges of the insulating layer and the conductive layer are located between the inner surface and the outer surface of the sealing member.

[0020] The sealing component can directly contact the first substrate.

[0021] The sealing component may include SiO2.

[0022] Insulating layers may include inorganic insulating layers.

[0023] The conductive layer can cover the side surface of the insulating layer corresponding to the edge of the insulating layer.

[0024] The edge of the conductive layer can extend toward the edge of the first substrate beyond the edge of the insulating layer.

[0025] The insulating layer may include sublayers that form step differences.

[0026] The display panel may also include a thin-film transistor electrically connected to one of the pixels and including a semiconductor layer and a gate electrode, wherein the insulating layer includes a first sublayer located on the semiconductor layer and a second sublayer located on the gate electrode.

[0027] Apart from the details described above, other aspects, features, and advantages will be set forth through the detailed description, claims, and drawings. Attached Figure Description

[0028] The above and other aspects of the disclosed embodiments will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a schematic plan view of a display panel according to some embodiments, and shows the arrangement of sealing members included in the display panel;

[0030] Figure 2 It is an equivalent circuit diagram of pixels included in a display panel according to some embodiments;

[0031] Figure 3 This is a schematic plan view of a display panel according to some embodiments, and shows the arrangement of conductive layers included in the display panel;

[0032] Figure 4 This is a schematic plan view of a display panel according to some embodiments, and shows the arrangement of sealing members and conductive layers included in the display panel;

[0033] Figure 5 yes Figure 4 A magnified planar view of part of V; and

[0034] Figure 6A and Figure 6B It is along Figure 5 The sectional view of the display panel is taken by line VI-VI'. Detailed Implementation

[0035] Aspects of some embodiments of this disclosure and methods of implementing them can be more readily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete and will fully convey aspects of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques not essential for those skilled in the art to fully understand aspects of this disclosure are not described.

[0036] Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the accompanying drawings and written description, and therefore their description will not be repeated. Furthermore, for clarity, parts unrelated to the description of the embodiments may be omitted. In the drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity. Additionally, the use of crosshairs and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless stated otherwise, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, scale, commonalities between the elements shown, and / or any other characteristics, properties, etc.

[0037] Various embodiments are described herein with reference to cross-sectional views that serve as schematic illustrations of examples and / or intermediate structures. Thus, variations in the illustrated shapes will be expected, for example, due to manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes specifically shown in the regions, but will include deviations in shape caused, for example, by manufacturing processes.

[0038] For example, an injection region shown as rectangular will typically have a circular (or rounded) or curved feature at its edges and / or a gradient of injection concentration, rather than a binary change from an injection region to a non-injection region. Similarly, an embedded region formed by injection will result in some injection in the area between the embedded region and the surface through which the injection occurs. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device, nor are they intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing entirely from the spirit or scope of this disclosure.

[0039] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be clear that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0040] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as a second element, component, region, layer, or portion.

[0041] For ease of explanation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature and another (other) element or feature as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as “below,” “below,” or “below” another element or feature would then be positioned “above” said other element or feature. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “above” a second part, this means that the first part is arranged above or below the second part, not limited to being above it based on the direction of gravity.

[0042] Furthermore, in this specification, the phrase "in a plane" or "plan view" refers to a view of the target portion from the top, and the phrase "in a cross-section" refers to a view of the target portion from the side, formed by vertically cutting the target portion.

[0043] It will be understood that when a component, layer, region, or assembly is referred to as "formed on," "on (or located on)," "connected to," or "bonded to" another component, layer, region, or assembly, the component, layer, region, or assembly may be directly formed on, directly on, directly connected to, or directly bonded to the other component, layer, region, or assembly, or the component, layer, region, or assembly may be indirectly formed on, indirectly on, indirectly connected to, or indirectly bonded to the other component, layer, region, or assembly, such that one or more intermediate components, layers, regions, or assemblies may exist. For example, when a layer, region, or assembly is referred to as "electrically connected" or "electrically bonded" to another layer, region, or assembly, the layer, region, or assembly may be directly electrically connected or directly electrically bonded to the other layer, region, and / or assembly, or intermediate layers, regions, or assemblies may exist. However, "direct connection / direct combination" refers to a component being directly connected to or directly combined with another component without any intermediate components. Similarly, other expressions describing relationships between components can be interpreted as "between," "directly between," or "adjacent to" and "directly adjacent to." Furthermore, it will be understood that when an element or layer is referred to as "between" two elements or layers, that element or layer can be the only element or layer between the two elements or layers, or there may be one or more intermediate elements or layers.

[0044] For the purposes of this disclosure, expressions such as “at least one of…” modify the entire list of elements when following a list of elements, without modifying the individual elements in that list. For example, “at least one of X, Y, and Z”, “at least one of X, Y, or Z”, and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of two or more of X, Y, Z, or Z only, such as XYZ, XYY, YZ, and ZZ, or any variations thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B.

[0045] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that, when used in this specification, the terms “comprising,” “having,” “including,” and variations thereof indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0047] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to take into account the inherent biases in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” includes the stated value and indicates a deviation within an acceptable range from the specific value as determined by one of ordinary skill in the art considering the measurements discussed and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Furthermore, in describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0048] When one or more embodiments can be implemented differently, a particular process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0049] Furthermore, any numerical range disclosed and / or described herein is intended to include all subranges with the same numerical precision contained within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between the described minimum value 1.0 and the described maximum value 10.0 (and including both the described minimum value 1.0 and the described maximum value 10.0), i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits to which it falls, and any minimum numerical limit described in this specification is intended to include all higher numerical limits to which it falls. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges to which it expressly falls. All such ranges are intended to be intrinsically described in this specification such that amendments to expressly describe any such subranges will comply with the applicable requirements.

[0050] Electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of such devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of such devices can be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate.

[0051] Furthermore, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard memory devices such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0052] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly stated herein.

[0053] Figure 1 This is a schematic plan view of a display panel according to some embodiments, and shows the arrangement of sealing members included in the display panel.

[0054] Reference Figure 1 The display panel 10 may include a display area DA and a surrounding area SA. The display panel 10 can provide an image by using light emitted from emitting elements (or light-emitting elements) included in pixels PX arranged in the display area DA. That is, the display area DA can be defined by the pixels PX. The surrounding area SA is an area where no pixels PX are arranged and can surround the display area DA.

[0055] Each of the pixels PX arranged in the display area DA can include, for example, an organic light-emitting diode (OLED) (see...). Figure 2 The emitting element of an organic light-emitting diode (OLED). Each pixel PX can emit light, such as red, green, blue, and / or white light, from an OLED. In this specification, as described above, a pixel PX can be a sub-pixel that emits any one of red, green, blue, and white light.

[0056] In the following description, the display panel 10 according to some embodiments includes an organic light-emitting display panel, but the display panel 10 is not limited thereto. In other embodiments, the display panel 10 may be a display panel such as an inorganic light-emitting display panel or a quantum dot light-emitting display panel. For example, the emitting layer of the display elements of the display panel 10 may include organic materials, inorganic materials, or quantum dots, or both organic materials and quantum dots, or both inorganic materials and quantum dots.

[0057] The display panel 10 may include an edge 10E. In some embodiments, reference is made to… Figure 1 The display panel 10 may include a first edge 10E1 and a second edge 10E2 that are parallel to each other, and a third edge 10E3 and a fourth edge 10E4 that are parallel to each other and join the first edge 10E1 and the second edge 10E2 together. The first edge 10E1 and the second edge 10E2 may be relatively longer than the third edge 10E3 and the fourth edge 10E4. In other embodiments, the display panel 10 may include three, five or more edges 10E and corners positioned between adjacent edges 10E. Furthermore, with Figure 1 Unlike the illustration, in other embodiments, the corners may be rounded (or chamfered).

[0058] The display panel 10 may include a first substrate 100 and a second substrate 300 stacked on top of each other, and a sealing member 350 positioned between the first substrate 100 and the second substrate 300. The first substrate 100 and the second substrate 300 may face each other. Figure 1 The first substrate 100 and the second substrate 300 are shown stacked on top of each other.

[0059] The sealing member 350 can be arranged in the surrounding area SA and can extend along the edge of the display area DA to surround the display area DA.

[0060] The first substrate 100 may include pads (or "solder pads") disposed in the surrounding area SA. The pads may not be covered by the second substrate 300. The pads may be connected via wiring to lines passing through the display area DA (e.g., see below). Figure 3 (Description includes data lines, drive power lines, etc.). A driver IC including a data driver can be positioned on the pad PAD, or an end of a flexible printed circuit board on which a data driver is mounted can be positioned. The driver IC can be electrically connected to the pad PAD via an anisotropic conductive film positioned between the driver IC and the pad PAD. The flexible printed circuit board can be electrically connected to the pad PAD via various types of conductive components.

[0061] Figure 2 It is an equivalent circuit diagram of pixels included in a display panel according to some embodiments.

[0062] Reference Figure 2 A pixel PX includes a pixel circuit PC comprising thin-film transistors T1 to T7 and a storage capacitor Cap. The pixel PX may include an organic light-emitting diode (OLED) as an emitting element, which emits light through the pixel circuit PC by receiving a driving voltage or driving current Id.

[0063] The pixel circuit PC may include thin-film transistors T1 to T7 and a storage capacitor Cap. According to some embodiments, such as... Figure 2 As shown, thin-film transistors T1 to T7 may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, a driving control thin-film transistor T5, an emission control thin-film transistor T6, and a second initialization thin-film transistor T7.

[0064] The gate electrode of the driving thin-film transistor T1 is connected to the electrode of the storage capacitor Cap. One of the source and drain electrodes of the driving thin-film transistor T1 is connected to the driving power line PL via the driving control thin-film transistor T5. The other of the source and drain electrodes of the driving thin-film transistor T1 is electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The driving thin-film transistor T1 is configured to receive the data signal Dm according to the switching operation of the switching thin-film transistor T2, and is configured to supply the driving current Id to the OLED.

[0065] The gate electrode of the switching thin-film transistor T2 is connected to the first scan line SWL. One of the source and drain electrodes of the switching thin-film transistor T2 is connected to the data line DL. The other of the source and drain electrodes of the switching thin-film transistor T2 is connected to the driving thin-film transistor T1 and then connected to the driving power line PL via the driving control thin-film transistor T5. The switching thin-film transistor T2 is turned on in response to the scan signal GW transmitted via the first scan line SWL and is configured to perform a switching operation that transmits the data signal Dm transmitted to the data line DL to the driving thin-film transistor T1.

[0066] The gate electrode of the compensation thin-film transistor T3 is connected to the first scan line SWL. One of the source and drain electrodes of the compensation thin-film transistor T3 is connected to the driving thin-film transistor T1 and connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The other of the source and drain electrodes of the compensation thin-film transistor T3 is connected to the electrode of the storage capacitor Cap, connected to the first initialization thin-film transistor T4, and connected to the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to the scan signal GW transmitted through the first scan line SWL, and the driving thin-film transistor T1 is diode-connected by electrically connecting the gate electrode of the driving thin-film transistor T1 to one of the source and drain electrodes (e.g., the drain electrode) of the driving thin-film transistor T1.

[0067] The gate electrode of the first initialization thin-film transistor T4 is connected to the second scan line SIL. One of the source and drain electrodes of the first initialization thin-film transistor T4 is connected to the second initialization thin-film transistor T7 and to the initialization voltage line VL. The other of the source and drain electrodes of the first initialization thin-film transistor T4 is connected to the electrode of the storage capacitor Cap, to the compensation thin-film transistor T3, and to the driving thin-film transistor T1. The first initialization thin-film transistor T4 is turned on in response to the previous scan signal GI transmitted through the second scan line SIL and is configured to perform an initialization operation in which the initialization voltage Vint is passed to the gate electrode of the driving thin-film transistor T1 such that the voltage of the gate electrode of the driving thin-film transistor T1 is initialized.

[0068] The gate electrode of the drive control thin film transistor T5 is connected to the emitter control line EL, one of the source electrode and drain electrode of the drive control thin film transistor T5 is connected to the drive power line PL, and the other of the source electrode and drain electrode of the drive control thin film transistor T5 is connected to the drive thin film transistor T1 and to the switch thin film transistor T2.

[0069] The gate electrode of the emission control thin film transistor T6 is connected to the emission control line EL. One of the source electrode and the drain electrode of the emission control thin film transistor T6 is connected to the driving thin film transistor T1 and to the compensation thin film transistor T3. The other of the source electrode and the drain electrode of the emission control thin film transistor T6 is electrically connected to the second initialization thin film transistor T7 and to the pixel electrode of the organic light-emitting diode OLED.

[0070] The drive control thin-film transistor T5 and the emitter control thin-film transistor T6 are simultaneously or substantially simultaneously turned on in response to the emitter control signal En transmitted through the emitter control line EL, and the drive voltage ELVDD is transferred to the organic light-emitting diode (OLED). Therefore, the drive current Id flows in the OLED.

[0071] The gate electrode of the second initialization thin-film transistor T7 is connected to the second scan line SIL. One of the source and drain electrodes of the second initialization thin-film transistor T7 is connected to the emission control thin-film transistor T6 and to the pixel electrode of the organic light-emitting diode (OLED). The other of the source and drain electrodes of the second initialization thin-film transistor T7 is connected to the first initialization thin-film transistor T4 and to the initialization voltage line VL. The second initialization thin-film transistor T7 is turned on in response to the previous scan signal GI transmitted through the second scan line SIL, and initializes the pixel electrode of the OLED.

[0072] Figure 2 The illustration shows a first initialization thin-film transistor T4 and a second initialization thin-film transistor T7 connected to a second scan line SIL, but one or more embodiments are not limited thereto. In other embodiments, the first initialization thin-film transistor T4 may be connected to the second scan line SIL and driven in response to a previous scan signal GI, while the second initialization thin-film transistor T7 may be connected to a first scan line or a second scan line of a pixel in the row preceding or following the corresponding pixel PX.

[0073] One electrode of the storage capacitor Cap is connected to the driving power line PL, and the counter electrode of the organic light-emitting diode (OLED) is connected to the power line to which a common voltage ELVSS is applied. Therefore, the OLED can emit light according to the driving current Id transmitted from the driving thin-film transistor T1, thus enabling the display of an image.

[0074] Figure 2 The pixel circuit PC shown includes seven thin-film transistors T1 to T7 and a storage capacitor Cap, but one or more embodiments are not limited thereto. The number of thin-film transistors and the storage capacitor can vary depending on the design of the pixel circuit PC.

[0075] Figure 3 This is a schematic plan view of a display panel according to some embodiments, and shows the arrangement of conductive layers included in the display panel.

[0076] Each of the pixels PX arranged in the display area DA can be electrically connected to external circuitry arranged in the surrounding area SA. In the surrounding area SA, a first driver 130, a second driver 140, a first conductive layer 150, and a second conductive layer 160 can be arranged. Both the first driver 130 and the second driver 140 may include a scan driver and / or an emission control driver.

[0077] The first driver 130 can transmit the scan signal via the corresponding scan line SL. Figure 2 The GW and GI) are transmitted to each pixel PX. As described herein, the scan line SL may include a first scan line ( Figure 2 SWL) and second scan line ( Figure 2 The first driver 130 can transmit the transmission control signal (SIL) via the corresponding transmit control line EL. Figure 2 The En signal is transmitted to each pixel PX. The second driver 140 may be arranged in parallel with the first driver 130, and the display area DA is located between the second driver 140 and the first driver 130. In some embodiments, some pixels PX may be electrically connected to the first driver 130, and other pixels PX may be connected to the second driver 140. In other embodiments, the second driver 140 may be omitted.

[0078] Drive voltage ( Figure 2 The ELVDD can be provided to each pixel PX via the drive power line PL connected to the first conductive layer 150, with a common voltage ( Figure 2 The ELVSS (Electronic Vibration Spectrometer) can provide counter electrodes connected to the second conductive layer 160 to each pixel PX. The first conductive layer 150 may include a first sub-conductive layer 151 and a second sub-conductive layer 152, which extend parallel to each other in the x-direction, and the display area DA is located between the first sub-conductive layer 151 and the second sub-conductive layer 152. The second conductive layer 160 may have an annular shape with an opening on one side and may partially surround the display area DA.

[0079] The data drive circuit can be electrically connected to the data line DL. The data signal of the data drive circuit ( Figure 2 The Dm can be provided to each pixel PX via the data line DL.

[0080] Figure 4 This is a schematic plan view of a display panel according to some embodiments, and shows the arrangement of sealing members and conductive layers of the display panel.

[0081] Reference Figure 4 , refer to Figure 1 The described sealing member 350 can be compared with the reference Figure 3 The second conductive layer 160 described is partially stacked.

[0082] Figure 5 yes Figure 4 A magnified planar view of region V.

[0083] Reference Figure 5 The first substrate 100 of the display panel 10 may include a display area DA and a surrounding area SA. The second driver 140, the second conductive layer 160 and the sealing member 350 may be disposed on the first substrate 100 in the surrounding area SA and may extend along the first edge 100E1 of the first substrate 100.

[0084] The sealing member 350 may be disposed on the outermost side or the outermost side of the first base 100. The term "outer side" refers to the direction from the center of the first base 100 toward the first edge 100E1, and is consistent with... Figure 5 The x-direction corresponds to the outer side. The inner side refers to the opposite side of the outer side. The sealing member 350 may include an inner surface 350a facing the display area DA and an outer surface 350b facing away from the inner surface 350a. That is, the inner surface 350a of the sealing member 350 may face the inner side of the first substrate 100, and the outer surface 350b of the sealing member 350 may face the outer side of the first substrate 100. The outer surface 350b of the sealing member 350 may be separated from the first edge 100E1 of the first substrate 100 towards the display area DA. Optionally, the outer surface 350b of the sealing member 350 may form a continuous surface with the first edge 100E1 of the first substrate 100.

[0085] The second conductive layer 160 may be positioned on the first substrate 100 closer to the inside than the sealing member 350. The second conductive layer 160 may overlap with at least a portion of the sealing member 350. In plan view / plan view, the first edge 160E1 of the second conductive layer 160 may be positioned between the inner surface 350a and the outer surface 350b of the sealing member 350. In plan view, the second edge 160E2 of the second conductive layer 160 may be closer to the display area DA than the first edge 160E1, and the inner surface 350a of the sealing member 350 may be positioned between the first edge 160E1 and the second edge 160E2 of the second conductive layer 160.

[0086] The second driver 140 may be positioned on the first substrate 100 closer to the display area DA than the second conductive layer 160. The display area DA may be positioned on the first substrate 100 further outward than the second driver 140, and thus may be surrounded by the surrounding area SA.

[0087] Figure 6A and Figure 6B It is along Figure 5 The sectional view of the display panel is taken by line VI-VI'. Figure 6A This is a cross-sectional view of a display panel according to some embodiments, showing the display area and the surrounding area.

[0088] Reference Figure 6A The display area DA is located on the first substrate 100, and the display layer 200 is positioned thereon. The display layer 200 may include a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC. The pixel circuit PC may include a thin-film transistor (TFT) and a storage capacitor Cap.

[0089] The first substrate 100 may be a transparent insulating substrate including glass, quartz, etc., and may have a single-layer structure. The first substrate 100 may include SiO2. The second substrate 300 may be a transparent insulating substrate including the same material as the first substrate 100.

[0090] A buffer layer 201 is positioned on the first substrate 100. The buffer layer 201 can reduce or prevent the penetration of foreign substances, moisture, or outside air from the bottom of the first substrate 100 and can provide a flat surface on the first substrate 100. The buffer layer 201 may include materials such as silicon oxide (SiO2). x ), silicon nitride (SiN) x It can be an inorganic material, an organic material, or a composite of organic and inorganic materials, or silicon oxynitride (SiON), and can have a single-layer structure or a multilayer structure.

[0091] On the buffer layer 201, thin-film transistors (TFTs) with pixels PX can be positioned. The thin-film transistors (TFTs) may include a semiconductor layer A and a gate electrode G.

[0092] Semiconductor layer A may be on buffer layer 201 and may include polycrystalline silicon. In other embodiments, semiconductor layer A may include amorphous silicon. In other embodiments, semiconductor layer A may include an oxide selected from at least one of the following: indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn).

[0093] Semiconductor layer A may include a channel region C, and may include a source region S and a drain region D doped with impurities. The source region S and the drain region D may correspond to the source electrode and the drain electrode, respectively.

[0094] The gate electrode G can be positioned on the semiconductor layer A. The gate electrode G can include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and can have a single-layer structure or a multi-layer structure including the above materials. In some embodiments, the gate electrode G can be a metal layer including Mo.

[0095] The first gate insulating layer 203 can be positioned between the semiconductor layer A and the gate electrode G. The first gate insulating layer 203 may include materials such as SiO2. x SiN x Inorganic insulating materials such as SiON, alumina (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO) are used. The first gate insulating layer 203 may have a single-layer structure or a multi-layer structure including the above-mentioned inorganic insulating materials.

[0096] The storage capacitor Cap may include a first electrode CE1 and a second electrode CE2 stacked on top of each other.

[0097] The second electrode CE2 may include Al, platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), Cr, lithium (Li), calcium (Ca), Mo, titanium (Ti), tungsten (W), and / or Cu, and may have a single-layer or multi-layer structure comprising the above materials. In some embodiments, the second electrode CE2 may be a metal layer comprising Mo.

[0098] Figure 6AThe illustration shows a storage capacitor Cap stacked with a thin-film transistor (TFT), and the first electrode CE1 is also the gate electrode G of the TFT; however, other embodiments are not limited to this. In other embodiments, the storage capacitor Cap may not be stacked with the TFT, and the first electrode CE1 may be separate from the gate electrode G of the TFT.

[0099] The second gate insulating layer 205 can be positioned between the first electrode CE1 and the second electrode CE2. The second gate insulating layer 205 may include materials such as SiO2 and SiN. x Inorganic insulating materials such as SiON, Al2O3, TiO2, Ta2O5, HfO2 or ZnO, and may have a single-layer structure or a multi-layer structure including the above materials.

[0100] The interlayer insulating layer 207 can be positioned on the second electrode CE2 of the storage capacitor Cap. The interlayer insulating layer 207 may include materials such as SiO2 and SiN. x Inorganic insulating materials such as SiON, Al2O3, TiO2, Ta2O5, HfO2 or ZnO, and may have a single-layer structure or a multi-layer structure including the above materials.

[0101] Data lines DL and drive power lines PL can be positioned on the interlayer insulating layer 207. Both data lines DL and drive power lines PL may comprise conductive materials such as Mo, Al, Cu, or Ti, and may have a single-layer or multi-layer structure comprising the aforementioned materials. In some embodiments, data lines DL and drive power lines PL may have a Ti / Al / Ti structure in which a Ti layer, an Al layer, and another Ti layer are sequentially stacked.

[0102] The planarization insulating layer 209 can be positioned on the data line DL and the drive power line PL. The planarization insulating layer 209 can have a flat upper surface, such that the pixel electrode 210 positioned on the upper part of the planarization insulating layer 209 can be flat. The planarization insulating layer 209 can be one or more layers comprising organic or inorganic materials. The planarization insulating layer 209 can include organic insulating materials. The planarization insulating layer 209 can include general polymers such as benzocyclobutene (BCB), PI, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS), polymer derivatives having phenolic groups, acryloyl polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof. The planarization insulating layer 209 can include SiO2, SiN... xMaterials include SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO. After forming the planarization insulating layer 209, chemical mechanical polishing can be performed to provide a flat upper surface.

[0103] The pixel electrode 210 can be positioned on the planarization insulating layer 209. The pixel electrode 210 can contact the source electrode or the drain electrode through the contact hole penetrating the planarization insulating layer 209, and can be electrically connected to the thin-film transistor TFT of the pixel circuit PC.

[0104] Pixel electrode 210 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). In other embodiments, pixel electrode 210 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or composites thereof. In other embodiments, pixel electrode 210 may also include a layer comprising ITO, IZO, ZnO, or In₂O₃ on and / or beneath the aforementioned reflective layer. In some embodiments, pixel electrode 210 may have an ITO / Ag / ITO structure.

[0105] The pixel defining layer 211 may cover the edge of the pixel electrode 210. The pixel defining layer 211 may be stacked with the pixel electrode 210 and may include an opening defining the emission region of the pixel PX. The pixel defining layer 211 can reduce or prevent the possibility of arcing at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230 above the upper part of the pixel electrode 210. The pixel defining layer 211 may include organic insulating materials such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed by spin coating or the like.

[0106] Intermediate layer 220 is positioned on pixel defining layer 211 to correspond to pixel electrode 210. Intermediate layer 220 may comprise polymer material or low molecular weight material and may emit, for example, red, green or blue light.

[0107] Counter electrode 230 is positioned on intermediate layer 220. Counter electrode 230 may include a conductive material with low work function. For example, counter electrode 230 may include a transparent (semi-transparent) layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. Optionally, counter electrode 230 may also include a layer comprising ITO, IZO, ZnO, or In2O3 on top of a transparent (semi-transparent) layer comprising the above-described materials.

[0108] The pixel electrode 210, the intermediate layer 220 and the counter electrode 230 can form an organic light-emitting diode (OLED).

[0109] The capping layer CPL can be formed on the counter electrode 230. The capping layer CPL can include materials such as LiF or SiN. x Inorganic and / or organic insulating materials. In some embodiments, a cover layer CPL may not be formed.

[0110] Reference Figure 6A The second driver 140 may be located in the surrounding region SA adjacent to the display region DA. The second driver 140 may include a thin-film transistor containing a source electrode and a drain electrode.

[0111] In the surrounding area SA, a sealing member 350 is positioned between a first base 100 and a second base 300. A first surface of the first base 100 may face a first surface of the second base 300, and the sealing member 350 may be located between the first surface of the first base 100 and the first surface of the second base 300. The first base 100 includes a second surface opposite to the first surface and a first edge 100E1 that joins the first and second surfaces of the first base 100 together, the first edge 100E1 corresponding to a side surface of the first base 100. The first edge 100E1 of the first base 100 may correspond to a first edge 10E1 of the display panel 10. As described above, the second base 300 includes a second surface opposite to the first surface and a first edge 300E1 that joins the first and second surfaces of the second base 300 together, the first edge 300E1 corresponding to a side surface of the second base 300. The first edge 100E1 of the first base 100 and the first edge 300E1 of the second base 300 may define the above-mentioned reference. Figure 1 The first edge 10E1 of the described display panel 10.

[0112] The outer surface 350b of the sealing member 350 may not be on the same vertical line as the first edge 100E1 of the first base 100 and the first edge 300E1 of the second base 300. That is, the outer surface 350b of the sealing member 350 may be on a different plane than the plane on which the first edge 100E1 of the first base 100 and the first edge 300E1 of the second base 300 are positioned. Optionally, the outer surface 350b of the sealing member 350 is continuously connected to the first edge 100E1 of the first base 100 and the first edge 300E1 of the second base 300, and thus forms a single surface.

[0113] The sealing member 350 may include, for example, a glass frit. The glass frit is a component comprising a glass material that forms the raw material for glass and can be hardened after exposure to a laser beam. The glass frit may comprise, as a main component, about 15 wt% to about 40 wt% of V₂O₅, about 10 wt% to about 30 wt% of TeO₂, about 1 wt% to about 15 wt% of P₂O₅, about 1 wt% to about 15 wt% of BaO, about 1 wt% to about 20 wt% of ZnO, about 5 wt% to about 30 wt% of ZrO₂, and about 5 wt% to about 20 wt% of WO₃, and may include as additives a composition comprising at least one of Fe₂O₃, CuO, MnO, Al₂O₃, Na₂O, and Nb₂O₅. In other embodiments, the sealing member 350 may include SiO₂. In other embodiments, the sealing member 350 may include a material such as epoxy resin.

[0114] Within the surrounding region SA, the insulating layer IL may include an edge IL-E. The insulating layer IL may include at least one inorganic insulating layer. For example, the insulating layer IL may include a buffer layer 201, a first gate insulating layer 203, a second gate insulating layer 205, and / or an interlayer insulating layer 207.

[0115] The insulating layer IL may include a first surface (bottom surface) facing the first substrate 100 and a second surface (upper surface) facing away from the first surface, and the edge IL-E of the insulating layer IL may correspond to the side surface that bonds the first surface and the second surface of the insulating layer IL together.

[0116] The edge IL-E of the insulating layer IL may be closer to the display area DA than the first edge 100E1 of the first substrate 100. For example, in a plan view, the edge IL-E of the insulating layer IL may be positioned between the inner surface 350a and the outer surface 350b of the sealing member 350. In some embodiments, the sealing member 350 may have a width between about 200 μm and about 800 μm and a thickness between about 2 μm and about 10 μm.

[0117] Since the edge IL-E of the insulating layer IL is positioned between the inner surface 350a and the outer surface 350b of the sealing member 350 in the plan view, the insulating layer IL may not directly contact the outside or may not be exposed to the outside due to the sealing member 350. Moreover, the insulating layer IL may partially overlap with the sealing member 350, and the sealing member 350 may directly contact the first substrate 100 in the portion of the surrounding area SA where the insulating layer IL is not positioned.

[0118] As a comparative example, when the edge IL-E of the insulating layer IL is on the same plane as the outer surface 350b of the sealing member 350 or the first edge 100E1 of the first substrate 100, the side surface of the insulating layer IL is exposed to the outside, and the sealing member 350 directly contacts the insulating layer IL instead of the first substrate 100. When external static electricity is applied to the display panel having the above structure, the applied external static electricity directly affects the insulating layer IL. When static electricity is applied to the insulating layer IL, which has a relatively small thickness, heat is generated, and the insulating layer IL is damaged accordingly. When the insulating layer IL is damaged by external static electricity, the insulating layer IL peels off from the first substrate 100, and the sealing member 350 also separates from the first substrate 100 or the insulating layer IL. Therefore, the display panel will have defects.

[0119] However, according to one or more embodiments, because the edge IL-E of the insulating layer IL is closer to the display area DA than the outer surface 350b of the sealing member 350, damage to the insulating layer IL due to external static electricity can be prevented or reduced.

[0120] The sealing member 350 can contact the first substrate 100 instead of just the insulating layer IL, thus improving the structural strength of the display panel 10. For example, a portion of the sealing member 350 including its outer surface 350b can directly contact the upper surface of the first substrate 100. In some embodiments, the sealing member 350 can comprise the same material as the first substrate 100, and both the sealing member 350 and the first substrate 100 can jointly comprise SiO2. When the sealing member 350 directly contacts the first substrate 100 comprising the same material as the sealing member 350, adhesion between the sealing member 350 and the first substrate 100 can be increased. The upper surface of the sealing member 350 can directly contact the second substrate 300.

[0121] The conductive layer may be positioned below the sealing member 350, for example, between the first substrate 100 and the sealing member 350. Figure 6A A second conductive layer 160 is shown, partially superimposed on an insulating layer IL beneath it. A portion of the second conductive layer 160 may be positioned on the insulating layer IL.

[0122] The second conductive layer 160 can be a power line through which electricity is applied to the pixels PX arranged in the display area DA. For example... Figure 6AAs shown, the second conductive layer 160 may be on the same layer as the data line DL or drive power line PL (e.g., interlayer insulation layer 207), and may be electrically connected to the counter electrode 230, with a connecting electrode layer 260 located between the second conductive layer 160 and the counter electrode 230. The counter electrode 230 may extend through the dummy pixel DPX and contact the connecting electrode layer 260, which may extend toward the sealing member 350 and contact the second conductive layer 160. The second conductive layer 160 may be configured to... (The text abruptly ends here, so the translation stops as well.) Figure 2 The described common voltage ELVSS is transferred to the counter electrode 230.

[0123] The second conductive layer 160 may be a metal layer and may include the same material as the data line DL or the drive power line PL. Furthermore, the second conductive layer 160 may include the same material as the source or drain electrode of the thin-film transistor TFT and may ensure the mechanical strength of the display panel 10.

[0124] At least a portion of the second conductive layer 160 may be stacked with the sealing member 350. In a plan view, a first edge 160E1 of the second conductive layer 160 may be positioned between the inner surface 350a and the outer surface 350b of the sealing member 350. By arranging the second conductive layer 160 to stack with the sealing member 350, the area of ​​portions of the display panel 10 that do not provide an image (e.g., dead space) can be reduced.

[0125] Reference Figure 6A The second conductive layer 160 can cover the side surface of the insulating layer IL corresponding to the edge IL-E. Although external static electricity is applied to the display panel 10, the second conductive layer 160 covers the side surface of the insulating layer IL, thus preventing or reducing the possibility of damage to the insulating layer IL due to static electricity.

[0126] The first edge 160E1 of the second conductive layer 160 may extend beyond the edge IL-E of the insulating layer IL toward the first edge 100E1 of the first substrate 100. This is because the second conductive layer 160 can receive a certain voltage (e.g., Figure 2 The common voltage (ELVSS) can prevent or reduce damage to adjacent structures or layers (e.g., insulation layer IL) caused by static electricity.

[0127] In some embodiments, the distance by which the first edge 160E1 of the second conductive layer 160 extends beyond the edge IL-E of the insulating layer IL (i.e., the distance “de” between the first edge 160E1 of the second conductive layer 160 and the edge IL-E of the insulating layer IL (e.g., in a plan view)) can be about 10 μm, about 30 μm, about 80 μm, or about 130 μm. Furthermore, in some embodiments, the ratio of the distance de to the width of the sealing member 350 can be between about 0.0125 and about 0.65.

[0128] Figure 6B This is a cross-sectional view of a display panel according to other embodiments, showing the display area and surrounding area. (Except for...) Figure 6B Outside the edge IL-E of the insulating layer IL and the second conductive layer 160, the structure is consistent with the reference. Figure 6A The structures described are the same; therefore, the main description will be... Figure 6A and Figure 6B The differences between the structures.

[0129] Reference Figure 6B The sublayers forming the insulating layer IL (i.e., buffer layer 201, first gate insulating layer 203, second gate insulating layer 205, and interlayer insulating layer 207) may form one or more step differences. Such step differences may be formed according to the process sequence and the method of forming each sublayer of the insulating layer IL.

[0130] When a step difference is formed in the sublayers of the insulating layer IL, the edge of the sublayer closest to the outer surface 350b of the sealing member 350 among the edges of the sublayers of the insulating layer IL can be defined as the edge IL-E of the insulating layer IL. In some embodiments, reference is made to... Figure 6B The edge of the buffer layer 201 corresponds to the edge IL-E of the insulating layer IL.

[0131] The second conductive layer 160 can cover the side surface of the insulating layer IL corresponding to the edge IL-E of the insulating layer IL. That is, the second conductive layer 160 can cover all edges of the sublayers of the insulating layer IL. Although in Figure 6B Although not shown in the diagram, the second conductive layer 160 may extend toward the edge of the first substrate 100 beyond the edge IL-E of the insulating layer IL.

[0132] According to one or more embodiments, a display panel that is less susceptible to damage from electrostatic discharge and has improved structural strength can be realized. However, the scope of this disclosure is not limited to the effects described above. Although the construction of the first edge (100E1) and its surroundings of the first substrate (100) has been described repeatedly, the above description can be applied in the same or similar way to the construction of the second to fourth edges (100E2, 100E3, 100E4 (not shown)) and their surroundings of the first substrate (100).

[0133] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within the embodiments should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims and their functional equivalents included therein.

Claims

1. A display panel, the display panel comprising: First base; Pixels are arranged on the first substrate and configured to define a display area; A thin-film transistor is disposed between the first substrate and the pixel, electrically connected to one of the pixels, and includes a semiconductor layer and a gate electrode; The second substrate faces the first substrate; An insulating layer is located on the first substrate, including a buffer layer located between the first substrate and the semiconductor layer, and including an edge closer to the display area than the edge of the first substrate; A conductive layer is located on the insulating layer; as well as A sealing member, located between the first substrate and the second substrate and surrounding the display area, includes an inner surface facing the display area and an outer surface facing away from the inner surface. In the plan view, the edge of the insulating layer and the edge of the conductive layer are located between the inner surface and the outer surface of the sealing member, and Wherein, at the edge of the conductive layer that directly contacts the first substrate, the portion of the sealing member adjacent to the outer surface directly contacts the first substrate.

2. The display panel according to claim 1, wherein, At least a portion of the conductive layer is overlapped with the sealing member.

3. The display panel according to claim 2, wherein, A portion of the conductive layer is in direct contact with the sealing member.

4. The display panel according to claim 1, wherein, Each pixel in the pixel group includes: Pixel electrode; An emissive layer, located on the pixel electrode; and The electrode is located on the emitter layer and electrically connected to the conductive layer.

5. The display panel according to claim 1, wherein, The sealing component comprises SiO2.

6. The display panel according to claim 1, wherein, The insulating layer includes an inorganic insulating layer.

7. The display panel according to claim 1, wherein, The conductive layer covers the side surface of the insulating layer corresponding to the edge of the insulating layer.

8. The display panel according to claim 7, wherein, The edge of the conductive layer extends toward the edge of the first substrate beyond the edge of the insulating layer.

9. The display panel according to claim 1, wherein, The insulating layer includes sublayers that form step differences.

10. The display panel according to claim 1, wherein, The insulating layer further includes a first sublayer located on the semiconductor layer and a second sublayer located on the gate electrode.

11. A display panel, the display panel comprising: First base; Each pixel is arranged on the first substrate, defines a display area, and includes a pixel electrode, an emitter layer, and a counter electrode. A thin-film transistor is disposed between the first substrate and the pixel, electrically connected to one of the pixels, and includes a semiconductor layer and a gate electrode; The second substrate faces the first substrate; An insulating layer is located on the first substrate and includes a buffer layer located between the first substrate and the semiconductor layer; A conductive layer is located on the insulating layer and is electrically connected to the counter electrode; as well as A sealing member, located between the first substrate and the second substrate, surrounds the display area and includes an inner surface facing the display area and an outer surface opposite to the inner surface. In the plan view, the edges of the insulating layer and the conductive layer are located between the inner and outer surfaces of the sealing member. Wherein, at the edge of the conductive layer that directly contacts the first substrate, the portion of the sealing member adjacent to the outer surface directly contacts the first substrate.

12. The display panel according to claim 11, wherein, The sealing component comprises SiO2.

13. The display panel according to claim 11, wherein, The insulating layer includes an inorganic insulating layer.

14. The display panel according to claim 11, wherein, The conductive layer covers the side surface of the insulating layer corresponding to the edge of the insulating layer.

15. The display panel according to claim 11, wherein, The edge of the conductive layer extends toward the edge of the first substrate beyond the edge of the insulating layer.

16. The display panel according to claim 11, wherein, The insulating layer includes sublayers that form step differences.

17. The display panel according to claim 11, wherein, The insulating layer further includes a first sublayer located on the semiconductor layer and a second sublayer located on the gate electrode.

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