Display device

Abstract

A display device is provided. The display device includes a substrate including a first area, a display area surrounding the first area, and a peripheral area surrounding the display area and including a curved area; a display unit including a pixel; a driving circuit in the peripheral area; and a fan-out unit in the peripheral area and including a first wiring portion and a second wiring portion spaced apart from each other in the curved area. The first wiring portion includes a first wiring. Each of the first wirings includes a first portion extending in a first direction between the display unit and the curved area, and a second portion extending in a second direction. A width of the first portion is greater than a width of the second portion.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0179978, filed on December 31, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device, and to a display device in which emission uniformity of the emission region is improved. Background Technology

[0003] Among display devices, organic light-emitting diode (OLED) displays have the advantages of wide viewing angle, excellent contrast ratio and fast response speed, and are therefore attracting attention as the next generation of display devices.

[0004] Typically, in organic light-emitting display devices, thin-film transistors and organic light-emitting diodes (OLEDs) can be formed or disposed on a substrate, and the OLEDs can spontaneously emit light. Organic light-emitting display devices can be used as display units in miniaturized products such as mobile phones, and as display units in large products such as televisions.

[0005] Display devices, such as organic light-emitting display devices, may include display units located on or disposed on a substrate and fan-out areas including wiring that can extend to the exterior of the display units. By bending at least a portion of the display device, visibility at various angles can be improved or the area of ​​non-display areas can be reduced.

[0006] It will be understood that the background art in the technical section is partly intended to provide useful background information for understanding the technology. However, the background art in the technical section may also include ideas, concepts, or knowledge that were known or understood by a person skilled in the art prior to the corresponding valid filing date of the subject matter disclosed herein. Summary of the Invention

[0007] One or more embodiments include a display device in which emission uniformity of the emission area can be improved. However, it should be understood that the embodiments described herein should be considered in a descriptive sense only and not for the purpose of limiting disclosure.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosed embodiments.

[0009] According to one or more embodiments, a display device may include: a substrate, the substrate including a first region, a display region surrounding the first region, and a peripheral region surrounding the display region and including a curved region; a display unit disposed in the display region and including a plurality of pixels; a driving circuit disposed in the peripheral region; and a fan-out unit disposed in the peripheral region between the display unit and the driving circuit to transmit data signals applied from the driving circuit to the display unit. The fan-out unit may include a first wiring portion and a second wiring portion spaced apart from each other in the curved region. The first wiring portion may include a plurality of first wirings. Each of the plurality of first wirings may include: a first portion extending in a first direction between the display unit and the curved region; and a second portion extending in a second direction intersecting the first direction. The width of the first portion may be greater than the width of the second portion.

[0010] A predetermined number of the multiple first wirings can be electrically connected to the multiple data lines, and a predetermined number of the multiple data lines can be wired relative to the first region.

[0011] In the plurality of first wirings, the interval between the first portions may be equal to or greater than the interval between the second portions.

[0012] The width of the first part can be approximately 1.5 to approximately 2 times the width of the second part.

[0013] Each of the plurality of first wirings may further include a third portion disposed in the curved region, and the width of the third portion may be greater than the width of the first portion.

[0014] Each of the plurality of first wirings may include: a first conductive layer disposed between the display area and the curved area; a second conductive layer disposed in the curved area; and a third conductive layer disposed between the curved area and the driving circuit. The first conductive layer, the second conductive layer, and the third conductive layer may be electrically connected to each other.

[0015] The first conductive layer and the third conductive layer may contain the same material.

[0016] The second conductive layer may include a material different from the material of the first conductive layer and the material of the third conductive layer.

[0017] The first and third conductive layers may include molybdenum (Mo).

[0018] The second conductive layer may include aluminum (Al).

[0019] The second conductive layer can be electrically connected to the first and third conductive layers through contact holes that pass through an insulating layer located outside the curved area.

[0020] The display unit may include pixel circuitry and display elements electrically connected to the pixel circuitry. The pixel circuitry may include a thin-film transistor (TFT), which includes: a semiconductor layer; a gate electrode stacked with a portion of the semiconductor layer; and an electrode layer disposed above the gate electrode. The first conductive layer and the gate electrode may include the same material.

[0021] The second conductive layer and the electrode layer may contain the same material.

[0022] The first region may include transparent regions.

[0023] The first region may include non-display areas.

[0024] The first area can be set at the top center of the display area.

[0025] The first wiring section can be located in the center of the fan-out unit.

[0026] The first area can be set at the upper left side of the display area.

[0027] The first wiring section can be located on the left side relative to the center of the fan-out unit.

[0028] The first area can be set at the upper right side of the display area.

[0029] The first wiring section can be located on the right side relative to the center of the fan-out unit.

[0030] The display device may also include a component disposed on one side of the substrate corresponding to the first region.

[0031] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments, drawings, and claims. Attached Figure Description

[0032] The above and other aspects, features, and advantages of the embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 This is a perspective view of a portion or area of ​​the display device according to an embodiment;

[0034] Figure 2A and Figure 2B This is a plan view of a portion or area of ​​the display device according to an embodiment;

[0035] Figures 3A to 3D This is a schematic cross-sectional view of a display device according to an embodiment;

[0036] Figures 4A to 4C This is a schematic cross-sectional view of a display device according to an embodiment;

[0037] Figure 5 This is an equivalent circuit diagram of the pixels of the display device according to an embodiment;

[0038] Figure 6 This is a schematic cross-sectional view of pixels according to an embodiment;

[0039] Figure 7 This is a plan view of the wiring around the opening area according to an embodiment;

[0040] Figure 8A It is along Figure 7 A schematic cross-sectional view of the wiring cut off by lines VIIIa-VIIIa';

[0041] Figure 8B It is along Figure 7 A schematic cross-sectional view of the wiring cut off by lines VIIIb-VIIIb';

[0042] Figure 9 yes Figure 2A An enlarged plan view of region A;

[0043] Figure 10 yes Figure 9 Enlarged plan view of a portion or area;

[0044] Figure 11 and Figure 12 yes Figure 10 A schematic cross-sectional view of a portion or area;

[0045] Figure 13 It is a plan view of a portion or area of ​​the display device according to the embodiment; and

[0046] Figure 14 and Figure 15 It is a plan view of a portion or area of ​​the display device according to an embodiment. Detailed Implementation

[0047] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only with reference to the accompanying drawings to explain the described aspects.

[0048] Some parts that are not relevant to the description may be omitted in order to describe the disclosed embodiments, and throughout the specification, the same reference numerals refer to the same elements.

[0049] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0050] The terms “and” and “or” can be used in a connecting or separating sense and can be understood as equivalent to “and / or”. In the specification and claims, for the purpose of understanding and interpreting the phrase “at least one of…”, the phrase is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0051] Because the disclosure allows for various modifications and numerous embodiments, embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of the disclosure, as well as the methods of implementing it, will become apparent and more readily understood from the following description and accompanying drawings of the embodiments. However, the disclosure is not limited to the embodiments herein and can be implemented in various forms. In the following description, when referring to the accompanying drawings, the same reference numerals are assigned to the same elements or corresponding elements, and repeated descriptions thereof are omitted.

[0052] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the publicly stated teachings, the first element or component discussed below may be referred to as the second element or component. Similarly, the second element or component may also be referred to as the first element or component.

[0053] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are also intended to include the plural forms.

[0054] It will also be understood that when the terms “comprising,” “including,” “having,” and / or variations thereof are used in this specification, they or may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0055] When a layer, film, region, substrate, area, or element is referred to as being "on" another layer, film, region, substrate, area, or element, it can be directly on the other layer, film, region, substrate, area, or element, or an intermediate layer, intermediate film, intermediate region, intermediate substrate, intermediate area, or intermediate element can exist between them. Conversely, when a layer, film, region, substrate, area, or element is referred to as being "directly on" another layer, film, region, substrate, area, or element, an intermediate layer, intermediate film, intermediate region, intermediate substrate, intermediate area, or intermediate element may not exist between them. Furthermore, when a layer, film, region, substrate, area, or element is referred to as being "below" another layer, film, region, substrate, area, or element, it can be directly below the other layer, film, region, substrate, area, or element, or an intermediate layer, intermediate film, intermediate region, intermediate substrate, intermediate area, or intermediate element can exist between them. Conversely, when a layer, membrane, region, substrate, area, or element is referred to as being "directly below" another layer, membrane, region, substrate, area, or element, an intermediate layer, intermediate membrane, intermediate region, intermediate substrate, intermediate area, or intermediate element may not exist between them. Furthermore, "above" or "on" can include being positioned on or below a target and does not necessarily imply a direction based on gravity.

[0056] For ease of description, the spatial relative terms “below,” “under,” “down,” “above,” “up,” etc., as shown in the accompanying drawings, are used to describe the relationship between one element or component and another element or component. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, in the case of flipping the device shown in the drawings, a device positioned “below” or “under” another device may be placed “above” another device. Therefore, the descriptive term “below” can include both lower and upper positions. The device may also be positioned in other directions, and thus the spatial relative terms can be interpreted differently depending on the orientation.

[0057] In the accompanying drawings, the dimensions and thicknesses of the elements may be enlarged for better understanding, clarity, and ease of description. However, the disclosure is not limited to the dimensions and thicknesses shown. The thicknesses of layers, films, panels, regions, and other elements may be exaggerated in the accompanying drawings for clarity. The thicknesses of some layers and regions may be exaggerated in the accompanying drawings for better understanding and ease of description.

[0058] Furthermore, in the instruction manual, the phrase "in a plan view" means when viewing the target portion from above, and the phrase "in a schematic sectional view" means when viewing from the side as a schematic cross-section taken by vertically cutting the target portion.

[0059] Additionally, the term "overlay" or variations thereof means that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlay" can include stacking, overlapping, facing, or variations thereof, extending over, covering, or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The term "facing" and variations thereof means that the first element may be directly or indirectly opposite the second element. In cases where a third element is inserted between the first and second elements, the first and second elements, although still facing each other, can be understood as being indirectly opposite each other. When an element is described as "not overlaying" another element or variations thereof, this can include elements spaced apart from each other, offset from each other, or separated from each other, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art.

[0060] When embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0061] It will be understood that when a layer, region, or component is referred to as "connected" or "bonded" to another layer, region, or component, it can be "directly connected" or "directly bonded" to said other layer, region, or component and / or can be "indirectly connected" or "indirectly bonded" to said other layer, region, or component with other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as "electrically connected" to another layer, region, or component, it can be "directly electrically connected" to said other layer, region, or component and / or can be "indirectly electrically connected" to said other layer, region, or component with other layers, regions, or components interposed therebetween.

[0062] Additionally, when a component is referred to as being "in contact" with another component or a variation thereof, the component may be "in electrical contact" or "in physical contact" with the other component, or "indirect contact" or "in direct contact" with the other component.

[0063] As used herein, “about” or “approximately” includes the stated value and, taking into account the measurement under discussion and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system), means within an acceptable deviation of the specific value as determined by one of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0064] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0065] As used herein, the term "unit" refers to a structure or element as shown in the accompanying drawings and described in the specification. However, the disclosure is not limited thereto. The term "unit" is not limited to the units shown in the accompanying drawings.

[0066] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Furthermore, it will be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense, unless expressly defined herein.

[0067] The display device according to the embodiments may be a device for displaying one or more images, and may include a liquid crystal display, an electrophoretic display, an organic light-emitting display, an inorganic light-emitting display, a field emission display, a surface-conducting electron emission display, a plasma display, a cathode ray display, and a quantum dot light-emitting display. For example, the emitting layer disposed on the display element of the display device may include organic materials, may include inorganic materials, may include quantum dots, may include organic materials and quantum dots, or may include inorganic materials and quantum dots. However, the disclosure is not limited thereto.

[0068] In the following description, although the organic light-emitting display device may be described as an example of a display device according to an embodiment, the display device according to the embodiment is not limited thereto and may include various types of display devices.

[0069] Figure 1 This is a perspective view of a portion or area of ​​the display device 1 according to an embodiment, and Figure 2A and Figure 2B This is a plan view of a portion or area of ​​the display device 1 according to an embodiment.

[0070] Reference Figure 1 The substrate 100 of the display device 1 may include a display area DA and a peripheral area PA outside the display area DA. The peripheral area PA may include a curved area BA in which a portion is flexible. The remaining areas besides the curved area BA in the substrate 100 may be one or more areas having a generally flat surface. Figure 1 As shown, the curved region BA of the base 100 can be bent about the bending axis BAX extending in the x direction.

[0071] The substrate 100 may include a variety of flexible, bendable, or rollable materials. For example, the substrate 100 may include polymeric resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate.

[0072] The substrate 100 may have a multilayer structure comprising two layers containing a polymer resin and a barrier layer containing an inorganic material between the two layers. The inorganic material may include silicon oxide, silicon nitride, and silicon oxynitride. However, various modifications are possible. In embodiments where the substrate 100 is a non-bending display device, the substrate 100 may include a glass material.

[0073] In the substrate 100, the width of the peripheral region PA, including the curved region BA, can be smaller than the width of the portion where the display region DA can be positioned or disposed. The corner portion 100c of the edge of the substrate 100 can have a substantially circular shape. This shape can be adapted to the display region DA. Figure 2A and Figure 2B As shown, the corner portion of the display area DA may have a substantially circular shape along the shape of the corner portion 100c of the base 100.

[0074] A first region A1 and a second region A2 may be located or disposed within a display region DA, with the second region A2 surrounding the first region A1. In an embodiment, the first region A1 may include a transmissive region through which light can pass, and the second region A2 outside the first region A1 may include a non-display region in which pixels may not be arranged or disposed. In an embodiment, when light passes through the first region A1, its transmittance may be about 50% or higher, about 70% or higher, about 75% or higher, about 80% or higher, about 85% or higher, or about 90% or higher. The first region A1 may include an area on one side of the substrate 100 in which components may be arranged or disposed. The first region A1 may have, for example, Figures 3A to 3D and Figures 4A to 4C Various schematic cross-sectional structures are shown.

[0075] Reference Figure 2A and Figure 2B The display device 1 may include, for example, Figure 1The diagram shows a display area DA with pixels positioned or disposed thereon, and a peripheral area PA. The peripheral area PA is located outside or adjacent to the display area DA. The peripheral area PA may include a pad (also called a solder pad or solder pad) area PDA on one side of the display area DA. The pad area PDA is an area where various types of electronic components (such as integrated circuits (ICs) or printed circuit boards, for example) can be electrically attached.

[0076] Figure 2A and Figure 2B This can be understood as a plan view of substrate 100 in the manufacturing process. In the final display device or electronic device including the display device (such as a smartphone), a portion of substrate 100 can be as follows: Figure 1 The curve is bent to minimize the area of ​​the peripheral region PA that is recognized by the user. For example, as... Figure 1 and Figure 2A (or Figure 2B As shown in the diagram, the base 100 may include portions with different widths in the x-direction. For example, the base 100 may be bent about a bending axis BAX parallel to the x-direction in a portion having a narrow width.

[0077] In this configuration, at least a portion of the pad area PDA can be superimposed on the display area DA. The bending direction can be set such that the pad area PDA does not indicate the display area DA and can be located or positioned behind the display area DA. Therefore, the user can perceive that the display area DA occupies a large portion of the display device 1.

[0078] The edges of the display area DA can have a shape generally similar to the edges of a rectangle or square. As an example, the display area DA may include a first edge E1, a second edge E2, a third edge E3, and a fourth edge E4, where the first edge E1 and the second edge E2 may face each other, and the third edge E3 and the fourth edge E4 may face each other and may be located or positioned between the first edge E1 and the second edge E2. The pad area PDA may be adjacent to the fourth edge E4 among the first edges E1 to the fourth edge E4. In this case, the first connecting portion P1 connecting the first edge E1 to the fourth edge E4 may have a generally circular shape. The display area DA may also have a generally circular shape at the second connecting portion P2 connecting the second edge E2 to the fourth edge E4. The display area DA may have a generally circular shape at its other edges.

[0079] Display unit 10 can be arranged or disposed in display area DA, and display unit 10 can include pixels. Fan-out unit 20, to which conductive lines can extend, can be arranged or disposed in pad area PDA. One side of fan-out unit 20 can be electrically connected to display unit 10, and the other side of fan-out unit 20 can be electrically connected to drive circuit unit 30. Drive circuit unit 30 can include various types of electronic devices, such as integrated circuits (ICs). It will be understood that fan-out unit 20 can also be referred to as a fan-out structure.

[0080] The first region A1 and the second region A2 can be located or set within the display region DA, and the second region A2 can surround the first region A1. For example... Figure 2A As shown, the first region A1 may be located or positioned at or near the top center of the display region DA. In an embodiment, as... Figure 2B As shown, the first region A1 can be located or set on one side (e.g., the upper right) of the display region DA. Although in Figure 2A and Figure 2B The diagram shows that a first region A1 can be set and the first region A1 is shown as a circle, but in the embodiment, two or more first regions A1 can be set, and the second region A2 can have a substantially elliptical shape around the first region A1.

[0081] Figures 3A to 3D It is along Figure 2A A schematic cross-sectional view of the display device 1 according to the embodiment, taken by line III-III'.

[0082] Reference Figure 3A The display device 1 may include a display panel 1-P and a component 1-C. The display panel 1-P includes display elements, and the component 1-C corresponds to the first region A1.

[0083] The display panel 1-P may include a substrate 100, a packaging substrate 300, and a display element layer 200. The packaging substrate 300 is a packaging member that can face the substrate 100. The display element layer 200 is disposed or disposed between the substrate 100 and the packaging substrate 300. A sealing material 350 (e.g., a sealant) may be disposed or disposed between the substrate 100 and the packaging substrate 300, and the sealing material 350 covers or overlaps with the sides of the display element layer 200. Although in Figure 3A The diagram shows that the sealing material 350 can be arranged or disposed on two opposite sides of the first region A1, but it is understood that when viewed in a direction perpendicular to the main surface of the substrate 100, the first region A1 can be completely surrounded by the sealing material 350.

[0084] The substrate 100 may have a multilayer structure including a layer containing a polymer resin and an inorganic layer (not shown). The encapsulation substrate 300 may include glass or polymer resin.

[0085] The display element layer 200 may include a circuit layer, an organic light-emitting diode (OLED), and an insulating layer IL between the circuit layer and the OLED. The circuit layer includes a thin-film transistor (TFT), and the OLED is a display element electrically connected to the TFT. The TFT and the OLED electrically connected thereto may be arranged or disposed in the display area DA, and some or a predetermined number of wirings WL of the display element layer 200 may be located or disposed in the first extension area EA1 (e.g., ...). Figure 9 (as shown in the diagram) and in the second region A2. Wiring WL can provide a predetermined signal or voltage to pixels spaced apart from each other and between which the first region A1 is located. Although in Figure 3A The diagram shows that the wiring WL may not overlap with the sealing material 350 in the display area DA and the second area A2, but in the embodiment, a portion of the sealing material 350 may also be arranged or disposed on the wiring WL.

[0086] The display panel 1-P may include a through-hole 10H corresponding to the first region A1. For example, the substrate 100 and the encapsulation substrate 300 may each include a through-hole 100H and a through-hole 300H, both corresponding to the first region A1. The display element layer 200 may include a through-hole corresponding to the first region A1.

[0087] Although not shown, elements such as an input sensing element, an anti-reflective element, and a transparent window may be arranged or disposed on the display panel 1-P. The input sensing element can sense touch input, and the anti-reflective element may include a polarizer and a delay element, or a color filter and a black matrix.

[0088] Component 1-C may be located or disposed in the first area A1. Component 1-C may include electronic components that can use light or sound. For example, the electronic components may be sensors (such as infrared sensors) that can emit and / or receive light, cameras that can receive light to capture images, sensors that can output and sense light or sound to measure distance or identify fingerprints, small lamps that can output light, and speakers that can output sound. Electronic components using light can use light in various wavelengths, including visible light, infrared light, and ultraviolet light. Figure 3A As shown, in the case where the display panel 1-P may include a through hole 10H corresponding to the first region A1, light or sound that can be output from or received by electronic components can be used more effectively.

[0089] and Figure 3AUnlike embodiments where the display panel 1-P may include a through hole 10H corresponding to the first region A1, the display panel 1-P may not include a through hole. For example, as... Figure 3B As shown, although the package substrate 300 may include a through-hole 300H corresponding to the first region A1, the substrate 100 may not include a through-hole.

[0090] Optionally, such as Figure 3C and Figure 3D As shown, neither the substrate 100 nor the package substrate 300 may include through-holes. Figure 3C In this process, sealing material 350 can be arranged or placed in the second region A2 to surround the first region A1.

[0091] and Figure 3C The sealing material is different from 350, in Figure 3D In this configuration, the sealing material 350 may not be disposed around the first region A1. The sealing material 360 may be positioned or disposed in the peripheral region PA and can seal the display element layer 200 from external air by bonding the substrate 100 to the encapsulation substrate 300. Although not shown, in Figures 3A to 3C In the display device 1, sealing material 360 can be provided or configured to surround the display area DA.

[0092] Figure 3D The insulating layer IL may include an opening IL-OP corresponding to the first region A1. In an embodiment, any element may be omitted or disposed in the region between the substrate 100 and the package substrate 300, the region corresponding to the first region A1. In an embodiment, a portion of the inorganic insulating layer(s), such as a buffer layer(s), may be retained in the first region A1 of the substrate 100.

[0093] like Figures 3B to 3D As shown, even if the substrate 100 may not include the through-hole 100H, the light transmittance of the electronic components can be ensured while removing the portion of the display element layer 200 corresponding to the first region A1. The display device 1 may include... Figures 3B to 3D In the case of the display panel 1-P shown, light-utilizing electronic components can be appropriately used as electronic components.

[0094] Despite Figures 3A to 3D The diagram shows that component 1-C can be located or disposed below display panel 1-P (e.g., located or disposed on one side of base 100), but at least a portion of component 1-C can be inserted into... Figure 3A The inner surface of the through hole 10H is overlapped with the side surface of the through hole 10H of the display panel 1-P.

[0095] Component 1-C may include components other than the electronic components described above. In embodiments where the display panel 1-P is used as a smartwatch or a vehicle dashboard, component 1-C may be a component indicating predetermined information (e.g., vehicle speed and other measurable information), such as clock hands or pointers. Alternatively, component 1-C may include components that can enhance the aesthetics of the display panel 1-P, such as accessories.

[0096] Figures 4A to 4C It is according to the embodiment along Figure 2A A schematic cross-sectional view of display device 1 taken by line III-III'.

[0097] With reference Figure 3A Unlike the display panel 1-P described above, which includes an encapsulation substrate 300 as an encapsulation member and a sealing material 350, the display panel 1-P according to the embodiment may include a thin film encapsulation layer 300' as an encapsulation member. In this case, the flexibility of the display panel 1-P can be improved. In the following description, the differences are mainly described for ease of description.

[0098] The thin-film encapsulation layer 300' may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Regarding this, Figure 4A A first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 are shown, as well as an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0099] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 may comprise a polymeric material. Polymeric materials may include acrylic resins, epoxy resins, polyimide, and polyethylene.

[0100] The display panel 1-P may include through-holes 10H corresponding to the first region A1. For example, the substrate 100, the display element layer 200, and the thin-film encapsulation layer 300' may each include through-holes 100H, 200H, and 300H, all corresponding to the first region A1. The first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330, and the organic encapsulation layer 320 may each include holes corresponding to the first region A1. The size of the holes in the organic encapsulation layer 320 may be larger than the size of the holes in the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. The first inorganic encapsulation layer 310 may contact the second inorganic encapsulation layer 330 around the first region A1.

[0101] and Figure 3AUnlike the display panel 1-P which includes the through hole 10H corresponding to the first region A1, the display panel 1-P may not include the through hole. For example... Figure 4B As shown, the display element layer 200 and the thin film encapsulation layer 300' may each include through holes 200H and 300H, which are respectively corresponding to the first region A1, but the substrate 100 may not include through holes.

[0102] Optionally, such as Figure 4C As shown, none of the substrate 100, display element layer 200, and thin-film encapsulation layer 300' may include the through-holes corresponding to the first region A1. For example... Figure 4B and Figure 4C As shown, even if the substrate 100 may not include the through hole 100H, the transmittance of the electronic element as component 1-C can still be ensured as described above, even if the portion of the display element layer 200 that corresponds to the first region A1 is removed.

[0103] In such Figure 4C In cases where the thin-film encapsulation layer 300' shown may not include through-holes, at least one inorganic encapsulation layer and at least one organic encapsulation layer may both cover or overlap the substrate 100 in the first region A1. In this case, the portion of the display element layer 200 between the substrate 100 and the thin-film encapsulation layer 300' that corresponds to the first region A1 can be removed. Although in Figure 4A The diagram shows that all insulating layers IL corresponding to the first region A1 can be removed, but in the embodiment, only some layers of insulating layers IL that can be multiple layers can be removed.

[0104] Despite Figures 4A to 4C The diagram shows that component 1-C can be located or disposed below the display panel 1-P (e.g., located or disposed on one side of the base 100), but at least a portion of component 1-C can be inserted into... Figure 4A In the embodiment, the inner surface of the through hole 10H is superimposed on the side surface of the defined through hole 10H of the display panel 1-P.

[0105] Figure 5 This is an equivalent circuit diagram of the pixels of the display device 1 according to an embodiment.

[0106] Reference Figure 5Pixel P may include pixel circuitry PC and an organic light-emitting diode (OLED) electrically connected to the pixel circuitry PC. The pixel circuitry PC is electrically connected to a scan line SL and a data line DL. The pixel circuitry PC may include a driving thin-film transistor Td, a switching thin-film transistor Ts, and a storage capacitor Cst. The switching thin-film transistor Ts may be electrically connected to the scan line SL and the data line DL, and may transmit data signals transmitted via the data line DL to the driving thin-film transistor Td in response to a scan signal input via the scan line SL.

[0107] The storage capacitor Cst can be electrically connected to the switching thin-film transistor Ts and the driving thin-film transistor Td, and can store a voltage corresponding to the difference between the voltage transmitted from the switching thin-film transistor Ts and the driving voltage ELVDD supplied to the driving voltage line PL. The driving voltage ELVDD and the second supply voltage ELVSS can have a potential difference that allows the organic light-emitting diode (OLED) to emit light.

[0108] The driving thin-film transistor Td can be electrically connected to the driving voltage line PL and the storage capacitor Cst, and the driving current flowing from the driving voltage line PL through the organic light-emitting diode (OLED) can be controlled in response to the voltage stored in the storage capacitor Cst. The OLED can emit light with a predetermined brightness by using the driving current. The OLED can emit, for example, red, green, blue, or white light.

[0109] although Figure 5 The illustration shows a pixel P comprising two thin-film transistors and one storage capacitor, but the embodiment is not limited to this. In an embodiment, the pixel circuit PC of pixel P may include three or more thin-film transistors or two or more storage capacitors. Therefore, various modifications can be made. For example, the pixel circuit PC of pixel P may include seven thin-film transistors and one storage capacitor.

[0110] Figure 6 This is a schematic cross-sectional view of pixels according to an embodiment.

[0111] Reference Figure 6 Display elements such as organic light-emitting diodes (OLEDs) and thin-film transistors (TFTs) electrically connected to them can be located or disposed in the display area DA. The electrical connection of the OLED to the TFT can be understood as the pixel electrode 210 being electrically connected to the TFT. Although in Figure 6 The image shows that the pixel electrode 210 can be electrically connected to the thin-film transistor TFT via the connecting metal 155, but in the embodiment, the connecting metal 155 may be omitted.

[0112] Thin-film transistors (not shown) may be present, and may even be arranged or disposed in a peripheral region PA outside the display region DA of the substrate 100. The thin-film transistors located in or disposed in the peripheral region PA may be part of a circuit unit that can control electrical signals applied to, for example, the display region DA.

[0113] A buffer layer 110 may be disposed or formed on a substrate 100 on which a thin-film transistor (TFT) may be formed or formed. The buffer layer 110 may include inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride. The buffer layer 110 may improve the top surface of the substrate 100, or prevent impurities from penetrating from the substrate 100 into the semiconductor layer 211 of the thin-film transistor (TFT), or minimize the penetration of impurities from the substrate 100 into the semiconductor layer 211 of the thin-film transistor (TFT).

[0114] The thin-film transistor (TFT) may include a semiconductor layer 211, a gate electrode 213, a source electrode 215a, and a drain electrode 215b. The semiconductor layer 211 may include amorphous silicon, polycrystalline silicon, organic semiconductor materials, or oxide semiconductor materials.

[0115] To ensure insulation between the semiconductor layer 211 and the gate electrode 213, a gate insulating layer 120 may be arranged or disposed between the semiconductor layer 211 and the gate electrode 213. The gate insulating layer 120 may include inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0116] The first interlayer insulating layer 130 and the second interlayer insulating layer 140 may be arranged or disposed on the gate electrode 213. The first interlayer insulating layer 130 and the second interlayer insulating layer 140 may include inorganic materials, such as silicon oxide, silicon nitride, and / or silicon oxynitride. The source electrode 215a and the drain electrode 215b may be arranged or disposed on the second interlayer insulating layer 140. By way of example, the insulating layer including the inorganic material can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This can be applied to the embodiments below and their modifications.

[0117] The top electrode CE2 may be located on or disposed above the gate electrode 213 with the first interlayer insulating layer 130 therebetween. In an embodiment, a portion of the gate electrode 213 may serve as the bottom electrode CE1. The bottom electrode CE1 and the top electrode CE2 may constitute a storage capacitor Cst.

[0118] The first planarization layer 150 and the second planarization layer 160 may be disposed on or on the thin-film transistor (TFT). A bonding metal 155 may be disposed on or on the first planarization layer 150. The TFT can be electrically connected to the pixel electrode 210 via the bonding metal 155. The first planarization layer 150 and the second planarization layer 160 can substantially or substantially planarize the top surface of the TFT.

[0119] The first planarization layer 150 and the second planarization layer 160 may include organic materials, such as benzocyclobutene (BCB) or hexamethyldisiloxane (HMDSO).

[0120] An organic light-emitting diode (OLED) can be located or disposed on the second planarization layer 160 in the display area DA. The OLED may include a pixel electrode 210, a counter electrode 230, and an intermediate layer 220 therebetween, the intermediate layer 220 including an emission layer.

[0121] The pixel defining layer 170 may be disposed or positioned above the first planarization layer 150. The pixel defining layer 170 may define pixels by including openings corresponding to each sub-pixel (e.g., openings exposing at least the central portion of the pixel electrode 210). Figure 6 As shown, the pixel defining layer 170 can prevent arcing or other phenomena at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the counter electrode 230 above the pixel electrode 210. The pixel defining layer 170 may include organic materials such as polyimide or HMDSO.

[0122] Pixel electrode 210 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or mixtures thereof. In embodiments, pixel electrode 210 may include a layer comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) on top of / below / under the reflective layer.

[0123] Intermediate layer 220 may comprise low molecular weight materials or polymeric materials. When intermediate layer 220 comprises low molecular weight materials, although not shown, intermediate layer 220 may have a structure in which, for example, hole injection layer (HIL), hole transport layer (HTL), emitter layer (EML), electron transport layer (ETL), and electron injection layer (EIL) may be stacked in single or composite configurations. Intermediate layer 220 may comprise various organic materials such as copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine (NPB), and tri-8-hydroxyquinoline aluminum (Alq3). By way of example, these layers may be formed by vacuum deposition.

[0124] When the intermediate layer 220 comprises a polymer material, the intermediate layer 220 may have a structure generally comprising an HTL and an EML. In this case, the HTL may comprise poly-3,4-ethylenedioxythiophene (PEDOT), and the EML may comprise polymer materials such as polyphenylenevinylene (PPV) and polyfluorene. The intermediate layer 220 may be formed by screen printing, inkjet printing, and laser-induced thermal imaging (LITI), however, the disclosure is not limited thereto.

[0125] The structure of the intermediate layer 220 is not limited to the above description and can have various structures. For example, the intermediate layer 220 may include a body to cover or overlap with the pixel electrode 210, or include layers patterned to correspond to each of the pixel electrodes 210.

[0126] The counter electrode 230 can be arranged or positioned in the display area DA, and as... Figure 6 As shown, the counter electrode 230 can be arranged or configured to cover or superimpose the display area DA. For example, the counter electrode 230 can be integrally formed throughout the organic light-emitting diode (OLED) to correspond to the pixel electrode 210. The counter electrode 230 can include a conductive material with low work function. For example, the counter electrode 230 can include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode 230 can include a layer on the (semi-)transparent layer comprising the above materials, the layer comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3).

[0127] Because organic light-emitting diodes (OLEDs) are susceptible to damage from external moisture or oxygen, the thin-film encapsulation layer 300' can cover the OLED or be stacked with and protect it. The thin-film encapsulation layer 300' can also cover the display area DA or be stacked with and extend beyond the display area DA. Figure 6 As shown, the thin film encapsulation layer 300' may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0128] The first inorganic encapsulation layer 310 may cover or be stacked with the counter electrode 230, and includes silicon oxide, silicon nitride, and / or silicon oxynitride. Other layers, such as a capping layer, may be disposed or positioned between the first inorganic encapsulation layer 310 and the counter electrode 230. Since the first inorganic encapsulation layer 310 can be formed along the underlying structure, therefore... Figure 6 As shown, the top surface of the first inorganic encapsulation layer 310 may not be flat.

[0129] The organic encapsulation layer 320 may cover or be stacked with the first inorganic encapsulation layer 310. Unlike the first inorganic encapsulation layer 310, the top surface of the organic encapsulation layer 320 may be flat. For example, the top surface of the organic encapsulation layer 320 corresponding to the display area DA may be generally or substantially flat. The organic encapsulation layer 320 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate (salt), polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (within the spirit and scope of the disclosure, e.g., polymethyl methacrylate, polyacrylic acid), or any combination thereof.

[0130] The second inorganic encapsulation layer 330 may cover or be stacked with the organic encapsulation layer 320, and may include silicon oxide, silicon nitride, and / or silicon oxynitride. The second inorganic encapsulation layer 330 may allow the organic encapsulation layer 320 to remain unexposed by contacting the first inorganic encapsulation layer 310 in the peripheral region PA outside the display region DA.

[0131] Since the thin-film encapsulation layer 300' may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330, even if a crack occurs inside the thin-film encapsulation layer 300', such a crack will not connect through the multilayer structure between the first inorganic encapsulation layer 310 and the organic encapsulation layer 320 or between the organic encapsulation layer 320 and the second inorganic encapsulation layer 330. This configuration prevents or minimizes the formation of external moisture or oxygen through pathways, for example, to penetrate into the display area DA.

[0132] There may be situations where processes can be performed to form touch electrodes or touch protective layers, where the touch electrodes have various patterns for touchscreen functions, and the touch protective layers protect the touch electrodes.

[0133] The polarizer 520 can be attached or disposed on the thin-film encapsulation layer 300' by optically transparent adhesive (OCA) 510. A second extension region EA2 (see [reference]) of the peripheral region PA can be attached or disposed, for example, a printed circuit board (not shown) or an electronic chip (not shown). Figure 9 In the case of touch electrodes or touch protective layers disposed on the thin film encapsulation layer 300', the optically transparent adhesive 510 and the polarizing plate 520 may be located on or disposed on these elements.

[0134] Polarizing plate 520 can reduce external light reflection. For example, when external light passes through polarizing plate 520, is reflected by the top surface of counter electrode 230, and then passes through polarizing plate 520 again, the phase of the external light can change because it passes through polarizing plate 520 twice. As a result, destructive interference occurs because the phase of the reflected light becomes different from the phase of the external light entering polarizing plate 520. Therefore, external light reflection can be reduced, and thus visibility can be improved.

[0135] Figure 7 This is a plan view of the wiring around the opening area according to an embodiment. Figure 8A It is along Figure 7 A schematic cross-sectional view of the wiring cut off by lines VIIIa-VIIIa', and Figure 8B It is along Figure 7 A schematic cross-sectional view of the wiring cut off by lines VIIIb-VIIIb'.

[0136] Reference Figure 7 Data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6, and DL7 can extend in the y-direction, and drive voltage lines PL0, PL1, PL2, PL3, PL4, PL5, PL6, and PL7 can also extend in the y-direction. Some or a predetermined number of drive voltage lines PL0 and PL7 can extend continuously across the display area DA, but drive voltage lines PL1, PL2, PL3, PL4, PL5, and PL6 around the first area A1 can be disconnected around the first area A1. The portions of the disconnected drive voltage lines PL1, PL2, PL3, PL4, PL5, and PL6 that can be arranged or positioned above the first area A1 can be electrically connected to sub-wiring (not shown), which is arranged or positioned in the peripheral area PA above and below the display area DA.

[0137] In this embodiment, similar to data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6, and DL7, drive voltage lines PL1, PL2, PL3, PL4, PL5, and PL6 may not be interrupted and may be continuously provided or disposed around the first region A1. In this case, similar to data lines DL1, DL2, DL3, DL4, DL5, and DL6 described below, drive voltage lines PL1, PL2, PL3, PL4, PL5, and PL6 may each include an extension portion extending in the y-direction and a bypass portion surrounding the edge of the first region A1.

[0138] Some or a predetermined number of data lines DL1, DL2, DL3, DL4, DL5, and DL6 may be arranged around the first region A1. For example, data lines DL1, DL2, DL3, DL4, DL5, and DL6 may respectively include extension portions DL1-SP, DL2-SP, DL3-SP, DL4-SP, DL5-SP, and DL6-SP extending in the y-direction, and winding portions DL1-CP, DL2-CP, DL3-CP, DL4-CP, DL5-CP, and DL6-CP that wind around the edge of the first region A1. The winding portions DL1-CP, DL2-CP, DL3-CP, DL4-CP, DL5-CP, and DL6-CP of data lines DL1, DL2, DL3, DL4, DL5, and DL6 may be located or disposed in the first extension region EA1 and the second region A2. Among the data lines DL1, DL2, DL3, DL4, DL5, and DL6, the extensions DL3-SP and DL4-SP of data lines DL3 and DL4 that can be adjacent to the first area A1 can be longer than the extensions DL1-SP and DL6-SP of data lines DL1 and DL6 that can be adjacent to the display area DA.

[0139] Pixel P located above or below the first region A1 can be electrically connected to data lines DL1, DL2, DL3, DL4, DL5, and DL6 arranged around the first region A1, and can receive signals from the corresponding data lines DL1, DL2, DL3, DL4, DL5, and DL6. Among the data lines DL1, DL2, DL3, DL4, DL5, and DL6, the first data line DL1, the second data line DL2, and the third data line DL3 can be bent along the left edge of the first region A1, and the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6 can be bent along the right edge of the first region A1. Although in Figure 7 The diagram shows three data lines that can be arranged or set up around the first area A1, but for ease of explanation and description, the number of data lines can be more than three.

[0140] Reference Figure 7 , Figure 8A and Figure 8B Data lines DL1, DL2, DL3, DL4, DL5, and DL6 may include a first conductive line CL1 and a second conductive line CL2 in the first extension region EA1 and the second region A2. The first conductive line CL1 and the second conductive line CL2 may form bypass portions DL1-CP, DL2-CP, DL3-CP, DL4-CP, DL5-CP, and DL6-CP. In this case, the first conductive line CL1 and the second conductive line CL2 may be arranged alternately or disposed on different layers. The data lines among DL1, DL2, DL3, DL4, DL5, and DL6 that are closest to each other (e.g., the first data line DL1 and the second data line DL2) may be included in the second region A2 or disposed on different layers. This reduces the spacing between data lines DL1, DL2, DL3, DL4, DL5, and DL6 and effectively reduces the non-display area around the first region A1 (e.g., the second region A2).

[0141] Refer to the first data line DL1 shown Figure 8A The first data line DL1 may include a first conductive line CL1 and a third conductive line CL3. The first conductive line CL1 may be located or disposed in the second region A2, and the third conductive line CL3 may be located or disposed in the display region DA. The first conductive line CL1 may be arranged or disposed on the gate insulating layer 120, and may include... Figure 6 The gate electrode 213 is made of the same or similar material. The third conductive line CL3 can be arranged or disposed on the second interlayer insulating layer 140, and can include materials similar to... Figure 6 The source electrode 215a and the drain electrode 215b are made of the same or similar materials.

[0142] The first conductive line CL1 can contact the third conductive line CL3, and can be electrically connected to the third conductive line CL3 through the contact hole CNT. Figure 8A The contact hole CNT can be defined by a first interlayer insulating layer 130 and a second interlayer insulating layer 140. A first data signal transmitted via a first data line DL1 can be transmitted from a third conductive line CL3 in the lower part of the first region A1 to a third conductive line CL3 in the upper part of the first region A1 via the first conductive line CL1.

[0143] Refer to the second data line DL2 shown Figure 8BThe second data line DL2 may include a second conductive line CL2 and a third conductive line CL3. The second conductive line CL2 may be located or disposed in the second region A2, and the third conductive line CL3 may be located or disposed in the display region DA. The second conductive line CL2 may be arranged or disposed on the first interlayer insulating layer 130, and may include... Figure 6 The top electrode CE2 is made of the same or similar material. The third conductive line CL3 can be arranged or disposed on the second interlayer insulation layer 140, and can include materials similar to... Figure 6 The source electrode 215a and the drain electrode 215b are made of the same or similar materials.

[0144] The second conductive wire CL2 can contact the third conductive wire CL3, and can be electrically connected to the third conductive wire CL3 through the contact hole CNT. Figure 8B The contact hole CNT can be defined by the second interlayer insulating layer 140. The second data signal transmitted via the second data line DL2 can be transmitted from the third conductive line CL3 in the lower part of the first region A1 to the third conductive line CL3 in the upper part of the first region A1 via the second conductive line CL2.

[0145] For reference Figure 8A The third conductive line CL3 and Figure 8B The third conductive line CL3 may include different signal lines arranged or set on the same layer. Figure 8A The third conductive line CL3 may include a portion of the first data line DL1. Figure 8B The third conductive line CL3 may include a portion of the second data line DL2.

[0146] In the embodiment, with Figure 8A and Figure 8B Unlike other conductors, the third conductive line CL3 can be arranged or disposed on the first planarization layer 150, and can include the same conductors as the first conductive layer 150. Figure 6 The connecting metal 155 is made of the same or similar material.

[0147] although Figure 8A and Figure 8B The first data line DL1 and the second data line DL2 are shown and described as representative examples, but these structures are equally applicable to the adjacent data lines DL3, DL4, DL5, and DL6. For example, the third data line DL3 and the fifth data line DL5 may have a schematic cross-sectional structure similar to that of the first data line DL1, and the fourth data line DL4 and the sixth data line DL6 may have a schematic cross-sectional structure similar to that of the second data line DL2.

[0148] Scan lines SL0, SL1, SL2, SL3, SL4, and SL5 may extend in the x-direction intersecting with data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6, and DL7. Some or a predetermined number of scan lines SL0 and SL5 may extend continuously across the display area DA, but scan lines SL1, SL2, SL3, and SL4 around the first area A1 may be disconnected around the first area A1. The portions of the disconnected scan lines SL1, SL2, SL3, and SL4 on the left side of the first area A1 may be electrically connected to a first scan drive circuit (not shown) arranged or disposed on the left side of the display area DA, and the portions of the disconnected scan lines SL1, SL2, SL3, and SL4 on the right side of the first area A1 may be electrically connected to a second scan drive circuit (not shown) arranged or disposed on the right side of the display area DA.

[0149] Similar to scan lines SL0, SL1, SL2, SL3, SL4, and SL5, electrode voltage lines HL0, HL1, HL2, HL3, and HL4 may extend in the x-direction intersecting with data lines DL0, DL1, DL2, DL3, DL4, DL5, DL6, and DL7. Some or a predetermined number of electrode voltage lines HL0 and HL4 may extend continuously across the display area DA, but electrode voltage lines HL1, HL2, and HL3 around the first area A1 may be disconnected around the first area A1. The portions of the disconnected electrode voltage lines HL1, HL2, and HL3 on the right and left sides of the first area A1 may be electrically connected to a drive circuit (not shown), which may be adjacent to the first scan drive circuit and the second scan drive circuit.

[0150] like Figure 7 As shown, the spacing between adjacent data lines in the second region A2 (e.g., the interval d between bypass portions (referred to as the first spacing)) can be smaller than the interval D between adjacent data lines in the display region DA (referred to as the second spacing). The display quality of some or a predetermined number of pixels P located or disposed in the display region DA may be degraded due to the parasitic capacitance between adjacent data lines having the first spacing d.

[0151] According to the embodiment, the display device 1 can solve the problem of deteriorated display quality of some or some pixels P by forming wiring of fan-out units 20 electrically connected to data lines DL1, DL2, DL3, DL4, DL5 and DL6, such that some or some wirings can have a relatively wide width.

[0152] Figure 9 yes Figure 2A A magnified plan view of region A.

[0153] Reference Figure 9 In addition to the area surrounding the display area DA, the peripheral area PA may include a first extension area EA1, a curved area BA, and a second extension area EA2 that can extend to one side of the display area DA. The fan-out unit 20 and the drive circuit unit 30 may be arranged or disposed in the peripheral area PA.

[0154] The first extension region EA1 and the second extension region EA2 can be defined as a top region and a bottom region surrounding the curved region BA. For example, the curved region BA can be located or disposed between the first extension region EA1 and the second extension region EA2. The first extension region EA1 may include a region adjacent to the fourth edge E4 and located or disposed between the display region DA and the curved region BA. The second extension region EA2 may include a region that is not visible from the front when the curved region BA can be bent, and the second extension region EA2 is located or disposed between the curved region BA and the drive circuit unit 30.

[0155] As described above, like... Figure 2A and Figure 2B Similar to the peripheral regions PA adjacent to the first edge E1 to the third edge E3 of the display area DA, the first extended region EA1 can include peripheral regions PA that are recognized by the user in the final display device or electronic device (such as a smartphone) including the display device. Since the fan-out unit 20 (which includes wiring harnesses) can be arranged or disposed in the first extended region EA1, it is not easy to reduce the width of the first extended region EA1 compared to other peripheral regions PA (e.g., peripheral regions PA that contact the first edge E1 to the third edge E3 of the display area DA).

[0156] Therefore, the display device 1 according to the embodiment is implemented by dividing the fan-out unit 20 into multiple parts to reduce the width of the first extension region EA1 in the y-direction. Therefore, in the embodiment, the width of the first extension region EA1 in the y-direction can be smaller than the width of the second extension region EA2 in the y-direction.

[0157] Multiple portions can respectively correspond to the first wiring portion 21 and the second wiring portion 22 of the fan-out unit 20. The first wiring portion 21 and the second wiring portion 22 can be separated from each other in the bending region BA and the separation region SA is therebetween.

[0158] Fan-out unit 20 may include wirings W1 and W2, and data signals applied from drive circuit unit 30 may be transmitted to display unit 10 via wirings W1 and W2. Wirings W1 and W2 may be electrically connected to data line DL (see data line DL) that crosses display area DA in the y-direction. Figure 5 It can transmit data signals to the data line DL.

[0159] Wiring W1 and W2 can be arranged or configured to sequentially cross the first extension area EA1, the bend area BA, and the second extension area EA2. For example... Figure 9 As shown, wirings W1 and W2 can be bent at least twice in the plan view. The bendable portions of wirings W1 and W2 can be located or positioned within the first extension region EA1 and the second extension region EA2. Since stress will concentrate in the bending region BA, the bendable portions of wirings W1 and W2 can be formed to avoid deterioration of the bending region BA, which has a high risk of breakage.

[0160] Routing lines W1 and W2 may include straight sections and diagonal sections. The straight sections extend in a direction generally parallel to the y-direction within the first extension region EA1 and the second extension region EA2, while the diagonal sections extend in a diagonal direction intersecting or intersecting the x-direction and the y-direction. Routing lines W1 and W2 may also extend in a curved region BA in a direction generally parallel to the y-direction.

[0161] In the embodiments, such as in Figure 9 In this configuration, the first wiring portion 21 may be located or disposed on two opposite sides with the second wiring portion 22 between them. As a whole, the fan-out unit 20 may be arranged in a substantially symmetrical shape. The first wiring portion 21 may be arranged in a substantially symmetrical shape with respect to the central axis CAX, and the second wiring portion 22 may be arranged or disposed on one side and the other side of the first wiring portion 21.

[0162] In an embodiment, such as Figure 14 As shown, the fan-out unit 20 may include wiring portions 21, 22 and 23, each of which may be divided into at least three parts.

[0163] Figure 10 yes Figure 9 An enlarged plan view of a portion or area, and Figure 11 and Figure 12 yes Figure 10 A schematic cross-sectional view of a portion or area. Figure 11 yes Figure 10 A schematic cross-sectional view of a portion or region taken along lines XIa-XIa', XIb-XIb', and XIc-XIc', and Figure 12 yes Figure 10 A schematic cross-sectional view of a portion or region taken along line XII-XII'.

[0164] Reference Figure 10The first wiring portion 21 may include a first wiring W1, and the second wiring portion 22 may include a second wiring W2. Although for ease of description... Figure 10 The diagram shows that the first wiring portion 21 and the second wiring portion 22 respectively include three first wirings W1 and three second wirings W2, but both the first wiring portion 21 and the second wiring portion 22 may include more than three wirings.

[0165] Figure 10 It can correspond to, for example Figure 2A The first region A1 in the display device 1 may be located or disposed at or near the top center of the display region DA. Because... Figure 2A The first region A1 of the display device 1 can be located or disposed at or near the top center of the display region DA. Therefore, the first wiring portion 21 electrically connected to the data lines DL1, DL2, DL3, DL4, DL5, and DL6 can be located or disposed at the center portion of the fan-out unit 20, with the data lines DL1, DL2, DL3, DL4, DL5, and DL6 arranged in a row around the first region A1. (Refer to...) Figure 10 The first wiring portion 21 may be located or configured closer to the central axis CAX than the second wiring portion 22. This could mean that the first wiring portion 21 is located approximately at or positioned in the center of the fan-out unit 20. In an embodiment, the position of the first wiring portion 21 may be varied depending on the position of the first region A1 within the display region DA.

[0166] In this embodiment, for ease of description, the first wiring W1 is divided into (1-1) wiring W1-1, (1-2) wiring W1-2, and (1-3) wiring W1-3. Each of the first wirings W1-1, W1-2, and W1-3 can be electrically connected to... Figure 7 The first data line DL1, the second data line DL2, and the third data line DL3. Refer to them together. Figure 7 and Figure 10 Wiring (1-1) W1-1 can supply data signals to the first data line DL1, wiring (1-2) W1-2 can supply data signals to the second data line DL2, and wiring (1-3) W1-3 can supply data signals to the third data line DL3.

[0167] Figure 10 First wirings W1-1, W1-2, and W1-3 are shown arranged or positioned on the left side relative to the central axis CAX. Although not shown, the first wirings can also be arranged or positioned symmetrically on the right side relative to the central axis CAX. The first wirings arranged or positioned on the right side relative to the central axis CAX can be electrically connected to... Figure 7The fourth data line DL4, the fifth data line DL5, and the sixth data line DL6.

[0168] In the first extension region EA1, each of the first wirings W1 may include a first portion W1a and a second portion W1b, the first portion W1a extending in a first direction (in other words, the y-direction), and the second portion W1b extending in a second direction intersecting the y-direction. The first portion W1a and the second portion W1b may be distinguished based on curved portions and may be represented by straight and oblique portions of the fan-out unit 20.

[0169] Refer to together Figure 10 and Figure 11 The width wa of the first portion W1a of the first wiring W1 can be greater than the width wb of the second portion W1b of the first wiring W1. In an embodiment, the width wa of the first portion W1a can be about 1.5 to about 2 times the width wb of the second portion W1b, for example, about 1.6 times the width wb of the second portion W1b. The spacing d1 between the first portions W1a of the first wiring W1 can be equal to or greater than the spacing d2 between the second portions W1b of the first wiring W1.

[0170] As a comparative example, when the width of the first portion of the first wiring W1 is the same as the width of the second portion of the first wiring W1, a voltage drop may occur in the data signal transmitted to the data line DL, which is electrically connected to at least some or a predetermined number of the first wiring W1 around the first region A1. This voltage drop can be represented as a brightness reduction defect in the pixel P around the first region A1.

[0171] As described above, at least some or a predetermined number of first wirings W1-1, W1-2, and W1-3 in the first wiring portion 21 can be electrically connected to data lines DL1, DL2, DL3, DL4, DL5, and DL6 having at least a portion of the wiring around the first region A1 (see...). Figure 7 Since the width wa of the first portion W1a of each of the first wirings W1 can be designed to be greater than the width wb of the second portion W1b, voltage drop of the data signals transmitted to the data lines DL1, DL2, DL3, DL4, DL5 and DL6 around the first region A1 can be prevented, thus preventing a decrease in the brightness of the pixel P around the first region A1.

[0172] In the second wiring W2, which is included in the second wiring portion 22, the width of the straight portion and the width of the diagonal portion can be the same. The data line of the display area DA that is electrically connected to the second wiring W2 of the second wiring portion 22 can be sufficiently separated from the first area A1 and can not form a wiring portion surrounding the first area A1, so the problem of reduced brightness of the pixel P that is electrically connected to the data line will not occur.

[0173] Each of the first wirings W1 may include a third portion W1c located or positioned within the bend region BA. Although in Figure 10 The third portion W1c is shown to extend partially into the first extension region EA1 and the second extension region EA2, but the embodiments are not limited thereto.

[0174] In an embodiment, the width wc of the third portion W1c can be greater than the width wa of the first portion W1a. Therefore, in each of the first wirings W1, the width wa of the first portion W1a, the width wb of the second portion W1b, and the width wc of the third portion W1c satisfy the following Equation 1.

[0175] Equation 1

[0176] wc>wa>wb

[0177] In an embodiment, the width wc of the third portion W1c can be the same as the width wa of the first portion W1a. However, even in this case, the width wa of the first portion W1a can be greater than the width wb of the second portion W1b, and the interval d1 or interval d2 can be greater than the interval d3 between the third portions W1c of the first wiring W1.

[0178] Similar to the first wiring portion 21, in the plan view, the width of each of the second wirings W2 in the second wiring portion 22 in the curved region BA can be greater than the width of each of the second wirings W2 in the first extension region EA1 and the second extension region EA2.

[0179] Reference Figure 11 and Figure 12 Each of the first wirings W1 may include a first conductive layer C1, a second conductive layer C2, and a third conductive layer C3. The first conductive layer C1 may be located or disposed in the first extension region EA1, the second conductive layer C2 may be located or disposed in the bending region BA, and the third conductive layer C3 may be located or disposed in the second extension region EA2. Figure 12 As shown, the first conductive layer C1, the second conductive layer C2, and the third conductive layer C3 can be electrically connected to each other.

[0180] The first conductive layer C1 and the third conductive layer C3 can be arranged or disposed on the same layer, and can include the same or similar materials. For example... Figure 11 and Figure 12 As shown, the first conductive layer C1 and the third conductive layer C3 can be disposed or disposed on the gate insulating layer 120. The first conductive layer C1 and the third conductive layer C3 may include components similar to those referenced. Figure 6 The gate electrode 213 is made of the same or similar material. In an embodiment, the first conductive layer C1 and the third conductive layer C3 may include molybdenum (Mo).

[0181] The second conductive layer C2 can be arranged or disposed on different layers from the first conductive layer C1 and the third conductive layer C3, and can include a material different from the materials of the first conductive layer C1 and the third conductive layer C3. For example... Figure 11 and Figure 12 As shown, the second conductive layer C2 can be disposed or formed on the second interlayer insulating layer 140. The second conductive layer C2 may include components similar to those referenced. Figure 6 The source electrode 215a and the drain electrode 215b are made of the same or similar materials. In an embodiment, the second conductive layer C2 may include aluminum (Al).

[0182] Reference Figure 12 The opening OP can be located or positioned within the curved region BA. The opening OP can be formed by removing a portion of the insulating layer IL to expose at least a portion of the substrate 100. For example... Figure 12 As shown, the insulating layer IL may include, for example, a buffer layer 110, a gate insulating layer 120, a first interlayer insulating layer 130, and a second interlayer insulating layer 140. In an embodiment, if the second interlayer insulating layer 140 comprises an organic material, the insulating layer IL may include the buffer layer 110, the gate insulating layer 120, and the first interlayer insulating layer 130.

[0183] The opening OP can be filled with an organic layer OL. Since the inorganic layer is more susceptible to stress than the organic layer OL, the stress on the bending region BA can be reduced by removing the arrangement of the insulating layer IL or a portion of it placed in the bending region BA and then filling the opening OP with the organic layer OL.

[0184] Each of the first wirings W1 may include a first conductive layer C1, a second conductive layer C2, and a third conductive layer C3, wherein the first conductive layer C1 is located or disposed in a first extension region EA1, the second conductive layer C2 is located or disposed in a bending region BA, and the third conductive layer C3 is located or disposed in a second extension region EA2.

[0185] The first conductive layer C1 and the third conductive layer C3 can be arranged or disposed on the same layer, and the second conductive layer C2 can be arranged or disposed on a different layer from the first conductive layer C1 and the third conductive layer C3. For example, in Figure 12 In this process, the first conductive layer C1 and the third conductive layer C3 can be arranged or disposed on the gate insulating layer 120, and the second conductive layer C2 can be arranged or disposed on the organic layer 10 and the interlayer insulating layer 140.

[0186] The first conductive layer C1 and the third conductive layer C3 can be directly electrically connected to the second conductive layer C2 through contact holes formed in the first interlayer insulating layer 130 and the second interlayer insulating layer 140. Since the conductive layers arranged or disposed on different layers around the bending region BA as described above can be electrically connected to each other, the reliability of the wiring of the fan-out unit 20 across the bending region BA can be improved.

[0187] although Figure 11 and Figure 12 The first wiring portion 21 is shown, but the schematic cross-sectional structure of the second wiring portion 22 may be the same as that of the first wiring portion 21, except for the variation in the width of the straight portion.

[0188] Figure 13 This is a plan view of a portion or area of ​​the display device 1 according to an embodiment.

[0189] Figure 13 and Figure 10 Similar, but with Figure 10 The difference lies in the position of the first region A1 within the display region DA. For example, as in... Figure 2A In display device 1, Figure 10 The first wiring portion 21 may correspond to the situation where the first region A1 can be located or positioned at or near the top center of the display region DA. For example, in Figure 2B In display device 1, Figure 13 The first wiring portion 21 may correspond to the case where the first area A1 may be located or set in the upper right or near the display area DA.

[0190] Reference Figure 13 The first wiring portion 21 can be positioned or configured to be farther from the central axis CAX than the second wiring portion 22. Figure 13 It can correspond to, for example Figure 2B The first region A1 in the display device 1 may be located or positioned at or near the upper right of the display region DA. Figure 2BIn the display device 1, since the first region A1 can be located or set at or near the upper right of the display region DA, the first wiring portion 21 can be located or set at or near the upper right of the fan-out unit 20. The first wiring portion 21 is electrically connected to data lines DL1, DL2, DL3, DL4, DL5 and DL6 that can be arranged around the first region A1.

[0191] In an embodiment, where the first region A1 may be located or situated near the upper left of the display region DA, the first wiring portion 21 may be located or situated on the upper left side of the fan-out unit 20. The first wiring portion 21 is electrically connected to data lines DL1, DL2, DL3, DL4, DL5, and DL6 that can be arranged around the first region A1. This may mean that the position of the first wiring portion 21 is not limited to a specific part and can be changed in coordination with the position of the first region A1 within the fan-out unit 20.

[0192] exist Figure 13 In each of the first wirings W1, the width wa of the first portion W1a can be greater than the width wb of the second portion W1b. In an embodiment, the width wa of the first portion W1a can be about 1.5 to about 2 times the width wb of the second portion W1b, for example, about 1.6 times the width wb of the second portion W1b. The spacing d1 between the first portions W1a of the first wiring W1 can be equal to or greater than the spacing d2 between the second portions W1b of the first wiring W1.

[0193] Each of the first wirings W1 may include a third portion W1c located or disposed in the bending region BA. The width wc of the third portion W1c may be greater than the width wa of the first portion W1a. Therefore, in a plan view, the width of each of the first wirings W1 may decrease in the order of the third portion W1c, the first portion W1a, and the second portion W1b. In an embodiment, the width wc of the third portion W1c and the width wa of the first portion W1a may be the same or approximately the same. Even in this case, the width wa of the first portion W1a should be greater than the width wb of the second portion W1b.

[0194] The second wiring section 22, the second wiring W2, can have the same... Figure 10 The structure shown is similar to the one described above.

[0195] Figure 14 and Figure 15 This is a plan view of a portion or area of ​​the display device 1 according to an embodiment.

[0196] Figure 14 and Figure 15 yes Figure 9A modified embodiment. The fan-out unit 20 may include a first wiring portion 21, a second wiring portion 22, and a third wiring portion 23. The first wiring portion 21 may be spaced apart from the second wiring portion 22 in a bend region BA, with a first separation region SA1 therebetween. The second wiring portion 22 may be spaced apart from the third wiring portion 23 in a bend region BA, with a second separation region SA2 therebetween.

[0197] Reference Figure 14 The first wiring portion 21 may be located or disposed at the center of the fan-out unit 20, and the second wiring portion 22 and the third wiring portion 23 may be located or disposed outside the first wiring portion 21, respectively. The third wiring portion 23 may be located or disposed on the outermost side of the fan-out unit 20.

[0198] In embodiments where the first wiring portion 21 can be located or disposed at or near the center of the fan-out unit 20, the first region A1 can be located or disposed at or near the top center of the display region DA. In embodiments where the first region A1 can be located or disposed to the left or right of the center of the display region DA, rather than at or near the center of the display region DA, the first wiring portion 21 can be moved... Figure 14 The location of the second wiring section 22 or the location of the third wiring section 23.

[0199] Reference Figure 15 Fan-out unit 20 may include a first fan-out unit 20A and a second fan-out unit 20B that are substantially symmetrical with respect to the central axis CAX. The first fan-out unit 20A and the second fan-out unit 20B may receive signals from the first drive circuit unit 30A and the second drive circuit unit 30B, respectively.

[0200] The first wiring portion 21 may be located or disposed at the center of the fan-out unit 20, and the second wiring portion 22 and the third wiring portion 23 may be located or disposed outside the first wiring portion 21, respectively. The third wiring portion 23 may be located or disposed on the outermost side of the fan-out unit 20.

[0201] When the first wiring portion 21 can be located or disposed at the center portion of the fan-out unit 20, the first region A1 can be located or disposed at or near the top center of the display region DA. Since the fan-out unit 20 may include a first fan-out unit 20A and a second fan-out unit 20B that can be substantially symmetrical with respect to the central axis CAX, in this case, the arrangement or placement... Figure 7Data lines DL1, DL2 and DL3 on the left side of the first region A1 can be electrically connected to the first wiring portion 21 of the first fan-out unit 20A, and data lines DL4, DL5 and DL6 arranged or set on the right side of the first region A1 can be electrically connected to the second wiring portion 22 of the second fan-out unit 20B.

[0202] As described above, in the display device 1 according to the embodiment, since the width wa of the first portion W1a of each of the first wirings W1 is designed to be greater than the width wb of the second portion W1b, the reduction in brightness of the pixel P around the first region A1 can be prevented, and the display quality can be improved.

[0203] So far, although only display devices have been described, the disclosure is not limited thereto. For example, methods for manufacturing display devices also fall within the scope of the disclosure.

[0204] According to the embodiments, a display device in which emission uniformity of the emission area is improved can be realized. However, the scope of disclosure is not limited to this effect.

[0205] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims.

Claims

1. A display device, the display device comprising: The substrate includes: a first region; a display region surrounding the first region; and a peripheral region surrounding the display region and including a curved region. A display unit is disposed in the display area and includes multiple pixels; A drive circuit is disposed in the peripheral region; and A fan-out unit, disposed in the peripheral region between the display unit and the driving circuit, transmits data signals applied from the driving circuit to the display unit. The fan-out unit includes a first wiring portion and a second wiring portion spaced apart from each other in the curved region. The first wiring portion includes a plurality of first wirings, each of which includes: a first portion extending in a first direction between the display unit and the curved region; and a second portion extending in a second direction intersecting the first direction between the first portion and the display unit. Wherein, the width of the first part is greater than the width of the second part, and The first parts are spaced at the same intervals as each other, and the second parts are spaced at the same intervals as each other.

2. The display device according to claim 1, wherein, A predetermined number of the multiple first wirings are electrically connected to the multiple data lines, and A predetermined number of data lines are routed relative to the first area.

3. The display device according to claim 1, wherein, In the plurality of first wirings, the interval between the first portions is equal to or greater than the interval between the second portions.

4. The display device according to claim 1, wherein, The width of the first portion is 1.5 to 2 times the width of the second portion.

5. The display device according to claim 1, wherein, Each of the plurality of first wirings further includes a third portion disposed in the curved region, and The width of the third part is greater than the width of the first part.

6. The display device according to claim 1, wherein, Each of the plurality of first wirings includes: A first conductive layer is disposed between the display area and the curved area; A second conductive layer is disposed in the bending region; and A third conductive layer is disposed between the curved region and the driving circuit, and The first conductive layer, the second conductive layer, and the third conductive layer are electrically connected to each other.

7. The display device according to claim 6, wherein, The first conductive layer and the third conductive layer comprise the same material.

8. The display device according to claim 6, wherein, The second conductive layer comprises a material different from the material of the first conductive layer and the material of the third conductive layer.

9. The display device according to claim 6, wherein, The first conductive layer and the third conductive layer comprise molybdenum.

10. The display device according to claim 6, wherein, The second conductive layer comprises aluminum.

11. The display device according to claim 6, wherein, The second conductive layer is electrically connected to the first conductive layer and the third conductive layer through a contact hole that passes through an insulating layer disposed outside the curved region.

12. The display device according to claim 6, wherein, The display unit includes: a pixel circuit; and a display element electrically connected to the pixel circuit. The pixel circuit includes a thin-film transistor, the thin-film transistor comprising: a semiconductor layer; a gate electrode stacked with a portion of the semiconductor layer; and an electrode layer disposed above the gate electrode. The first conductive layer and the gate electrode are made of the same material.

13. The display device according to claim 12, wherein, The second conductive layer and the electrode layer comprise the same material.

14. The display device according to claim 1, wherein, The first region includes a transparent region.

15. The display device according to claim 1, wherein, The first region includes the non-display area.

16. The display device according to claim 1, wherein, The first region is located at the top center of the display area.

17. The display device according to claim 16, wherein, The first wiring portion is located at the center of the fan-out unit.

18. The display device according to claim 1, wherein, The first region is located on the upper left side of the display area.

19. The display device according to claim 18, wherein, The first wiring portion is located on the left side relative to the center portion of the fan-out unit.

20. The display device according to claim 1, wherein, The first region is located on the upper right side of the display area.

Images