Schottky Diode and Its Manufacturing Method

Abstract

This application relates to a Schottky diode and a manufacturing method thereof. The Schottky diode includes a nitride channel layer; a nitride barrier layer formed on the nitride channel layer; a nitride cap layer formed on the nitride barrier layer, the nitride cap layer including an active region and a non-active region; a passivation layer formed on the nitride cap layer, the passivation layer including a first groove that penetrates the passivation layer and exposes the nitride cap layer, the first groove corresponding to the active region; a dielectric layer located on the passivation layer and the inner wall of the first groove, and the dielectric layer encloses a second groove, the dielectric layer including a third groove that penetrates the dielectric layer and exposes a part of the active region on the nitride cap layer; an anode layer formed in the second groove and the third groove, and the anode layer is in contact with the active region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a Schottky diode and a manufacturing method thereof. Background Art

[0002] Due to the advantages of high switching frequency and low forward voltage drop of Schottky diodes, they are widely used and can gradually replace silicon in high-power semiconductor devices. However, currently, the anode layer of the Schottky diode is directly formed on the heterostructure layer, which increases the leakage characteristics of the heterostructure layer in a high-temperature environment and does not meet the actual requirements. Summary of the Invention

[0003] This application provides a Schottky diode and a manufacturing method thereof to solve the deficiencies in the related art.

[0004] According to the first aspect of the embodiments of this application, a Schottky diode is provided, including:

[0005] A nitride channel layer;

[0006] A nitride barrier layer, which is formed on the nitride channel layer;

[0007] A nitride capping layer, which is formed on the nitride barrier layer, and the nitride capping layer includes an active region and a non-active region;

[0008] A passivation layer, which is formed on the nitride capping layer, and the passivation layer includes a first groove that penetrates the passivation layer and exposes the nitride capping layer, and the first groove corresponds to the active region;

[0009] A dielectric layer, which is located on the passivation layer and the inner wall of the first groove, and the dielectric layer encloses a second groove, and the dielectric layer includes a third groove that penetrates the dielectric layer and exposes a part of the active region on the nitride capping layer;

[0010] An anode layer, which is formed in the second groove and the third groove, and the anode layer is in contact with the active region.

[0011] Optionally, the nitride capping layer includes a fourth groove formed in the active region, the fourth groove penetrates the nitride capping layer and exposes a part of the nitride barrier layer, and the fourth groove is in communication with the third groove;

[0012] The anode layer includes a first anode layer and a second anode layer, the first anode layer is formed in the second groove, and the second anode layer is formed in the third groove and the fourth groove and is in contact with the nitride barrier layer.

[0013] Optionally, it further includes:

[0014] A fifth groove and a sixth groove, the fifth groove and the sixth groove are respectively located on both sides of the anode layer, and both the fifth groove and the sixth groove penetrate through to the nitride barrier layer;

[0015] A cathode layer, the cathode layer is formed in the fifth groove and the sixth groove and contacts the nitride barrier layer.

[0016] Optionally, a barrier layer may also be provided between the nitride barrier layer and the nitride capping layer.

[0017] Optionally, the activation region is a P-type nitride capping layer.

[0018] Optionally, the nitride capping layer includes a nitride capping layer doped with magnesium element.

[0019] Optionally, the doping concentration of the magnesium element is between 1E16 cm3 - 5E20 / cm3.

[0020] Optionally, the nitride channel layer includes a gallium nitride channel layer, and the nitride barrier layer includes a gallium aluminum nitride barrier layer.

[0021] According to the second aspect of the embodiments of the present application, a method for manufacturing a Schottky diode is provided, including:

[0022] Forming a nitride channel layer;

[0023] Forming a nitride barrier layer on the nitride channel layer;

[0024] Forming a nitride capping layer on the nitride barrier layer;

[0025] Forming a passivation layer on the nitride capping layer;

[0026] Forming a first groove, the first groove penetrates through the passivation layer to expose the nitride capping layer;

[0027] Forming a dielectric layer, the dielectric layer is located on the passivation layer and the inner wall of the first groove, and the dielectric layer forms a second groove;

[0028] Annealing the structure to be processed with the second groove formed thereon to form an activation region in the region of the nitride capping layer corresponding to the first groove and a non-activation region in the region of the nitride capping layer covered by the passivation layer;

[0029] Forming a third groove on the structure to be processed, the third groove penetrates through the dielectric layer to expose a part of the activation region on the nitride capping layer;

[0030] An anode layer is formed in the second groove and the third groove, and the anode layer is in contact with the activation region.

[0031] Optionally, it further includes:

[0032] A fourth groove is formed, the fourth groove penetrates through the nitride cap layer to expose the nitride barrier layer, and the fourth groove is in communication with the third groove;

[0033] The forming of the anode layer in the second groove and the third groove includes:

[0034] A first anode layer is formed in the third groove and the fourth groove;

[0035] A first anode layer is formed in the second groove and is in contact with the nitride barrier layer.

[0036] Optionally, it further includes:

[0037] A fifth groove and a sixth groove are formed, the anode layer is located between the fifth groove and the sixth groove, and both the fifth groove and the sixth groove penetrate to the nitride barrier layer;

[0038] A cathode layer is formed in the fifth groove and the sixth groove.

[0039] The technical solutions provided by the embodiments of the present application may include the following beneficial effects:

[0040] As can be seen from the above embodiments, a Schottky contact is formed between the anode layer and the nitride cap layer in the present application, which can prevent the anode layer from directly contacting the heterostructure layer including the nitride channel layer and the nitride barrier layer, can balance the contradiction between the forward turn-on voltage and the reverse leakage characteristics of the Schottky diode, and can suppress the leakage characteristics of the heterostructure layer in a high-temperature environment; further, the anode layer is in contact with the activation region on the nitride cap layer, and the hole concentration in the activation region is relatively high, which is beneficial to improving the device performance. By providing the barrier layer, in the process of growing other epitaxial layers at high temperature subsequently, using the characteristic that the barrier layer is not easily decomposed at high temperature, the groove will not penetrate through the barrier layer, so that the depth of the groove will not be lower than the barrier layer, and thus the etching depth of the groove can be accurately controlled.

[0041] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0043] Figure 1It is a schematic structural diagram of a Schottky diode shown according to an exemplary embodiment.

[0044] Figure 2 It is a schematic structural diagram of another Schottky diode shown according to an exemplary embodiment.

[0045] Figure 3 It is a schematic structural diagram of yet another Schottky diode shown according to an exemplary embodiment.

[0046] Figure 4 It is a process flow diagram for manufacturing a Schottky diode shown according to an exemplary embodiment.

[0047] Figure 5 It is a manufacturing flow diagram of another Schottky diode shown according to an exemplary embodiment.

[0048] Figure 6 It is a manufacturing flow diagram of yet another Schottky diode shown according to an exemplary embodiment. Detailed implementation manners

[0049] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0051] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "upon determining".

[0052] Figure 1 It is a schematic structural diagram of a Schottky diode 100 shown according to an exemplary embodiment. AsFigure 1 As shown, the Schottky diode 100 may include a nitride channel layer 1, a nitride barrier layer 2, a nitride capping layer 3, a passivation layer 4, and a dielectric layer 5. Among them, the nitride barrier layer 2 is formed on the nitride channel layer 1. The nitride channel layer 1 may be made of one or more materials of GaN and AlN. The nitride barrier layer 2 may be made of one or more materials of AlN, GaN, ALGaN, and InN. The present application does not limit this. Further, a nitride capping layer 3 may be formed on the nitride barrier layer 2, and the nitride capping layer 3 may include an active region 31 and a non-active region 32. The passivation layer 4 is formed on the nitride capping layer 3. The passivation layer 4 has a passivation and protection effect, reduces the surface states of the nitride capping layer 2, and effectively reduces the current collapse effect. The passivation layer 3 may be a combination of one or more of silicon nitride, silicon aluminum nitride, and silicon dioxide. The passivation layer 4 may be formed on the nitride capping layer 3 by a deposition process. The process of depositing the passivation layer 4 may be a combination of one or several processes of PECVD, LPCVD, ALD, and MOCVD.

[0053] The passivation layer 4 may include a first groove that penetrates the passivation layer 4 and exposes a part of the nitride capping layer 3, and the first groove is arranged corresponding to the active region 31. The dielectric layer 5 may be formed on the passivation layer 4 and on the inner wall of the first groove. Through the dielectric layer 5, gate leakage can be reduced and the Schottky diode 100 can have a higher voltage tolerance value. The dielectric layer 5 may include a combination of one or more of an aluminum nitride dielectric layer, a silicon nitride dielectric layer, an aluminum oxide dielectric layer, an aluminum oxynitride dielectric layer, and a silicon dioxide dielectric layer. The present application does not limit this.

[0054] Since the dielectric layer 5 contacts the inner wall of the first groove, a second groove can be formed by the dielectric layer 5. The dielectric layer 5 may further include a third groove that penetrates the dielectric layer 5 and exposes a part of the active region 31 on the nitride capping layer 3. Thus, an inwardly recessed space can be vacated through the first groove, the second groove, and the third groove, and a part of the active region 31 can be exposed through the third groove. Among them, the Schottky diode 100 may further include an anode layer 6 and a cathode layer 7. The anode layer 6 is formed in the second groove and the third groove. Since the third groove exposes the active region 31 on the nitride capping layer 3, the anode layer 6 can form a Schottky contact with the active region 31. Among them, the anode layer 6 may use a metal with a higher work function to realize the Schottky metal. For example, Ni, Au, or Pt metal may be used to form a Schottky contact with the heterostructure layer.

[0055] As can be seen from the above embodiments, a Schottky contact is formed between the anode layer 6 and the nitride cap layer 3, which can prevent the anode layer 6 from directly contacting the heterostructure layer including the nitride channel layer 1 and the nitride barrier layer 2, balance the contradiction between the forward turn-on voltage and the reverse leakage characteristics of the Schottky diode 100, and suppress the leakage characteristics of the heterostructure layer in a high-temperature environment; further, the anode layer 6 contacts the activation region 31 of the nitride cap layer 3, and the hole concentration in the activation region 31 is relatively high, which is beneficial to improving the device performance.

[0056] In this embodiment, the nitride cap layer 3 may include a P-type nitride cap layer, for example, a P-type nitride cap layer formed by doping magnesium elements. Optionally, the P-type nitride cap layer may be obtained by doping magnesium elements based on GaN, wherein the doping concentration of magnesium elements may be between 1E16 cm3 - 5E20 / cm3. Further, the above activation region 31 can be formed by annealing the nitride cap layer 3. In a specific process step, the nitride channel layer 1, the nitride barrier layer 2, the nitride cap layer 3, and the passivation layer 4 can be stacked in this way, and then a first groove penetrating through the nitride cap layer 3 is formed on the passivation layer 4, and then the structure after forming the first groove is placed in an atmosphere without hydrogen for annealing, for example, annealing can be performed in nitrogen, nitric oxide, air, or a mixed gas of nitrogen and oxygen. Since the nitride cap layer 3 corresponding to the first groove region is not blocked by the passivation layer 4, hydrogen atoms overflow and magnesium atoms are activated, thereby forming the activation region 31, while the nitride cap layer 3 in the region blocked by the passivation layer 4 remains semi-insulating because there is no channel for hydrogen atoms to overflow, forming a non-activation region 32.

[0057] In another embodiment, as Figure 2 shown, the nitride cap layer 3 may further include a fourth groove formed in the activation region 31, the fourth groove penetrates through the nitride cap layer 3 and exposes a part of the nitride barrier layer 2, and the fourth groove is in communication with the third groove, so that the anode layer 6 can further contact the nitride barrier layer 2 through the fourth groove. Specifically, the anode layer 6 may include a first anode layer 61 and a second anode layer 62. As Figure 2 shown, the first anode layer 61 may be formed in the second groove, and the first anode layer 61 formed in the second groove may cooperate with the activation region 31 to form a Schottky contact; the second anode layer 62 may be formed in the third groove and the fourth groove, and the second anode layer 62 formed in the third groove and the fourth groove forms an ohmic contact with the heterostructure layer including the nitride channel layer 1 and the nitride barrier layer 2. Optionally, as Figure 2 shown, the side walls of the third groove and the fourth groove may be flush.

[0058] It should be noted that the first groove, the third groove, and the fourth groove in the above embodiments may be formed by an etching process, while the second groove may be formed along the side wall of the first groove when a dielectric layer is sputtered on the surface of the passivation layer 4. And, since the third groove penetrates through the bottom surface of the second groove, the width of the third groove is less than or equal to the width of the second groove.

[0059] In each of the above embodiments, the Schottky diode 100 may further include a fifth groove, a sixth groove, and a cathode layer 7, and the anode layer 6 is located between the fifth groove and the sixth groove. Both the fifth groove and the sixth groove penetrate through to the nitride barrier layer 2. The cathode layer 7 is formed in the fifth groove and the sixth groove, and an ohmic contact is formed between the cathode layer 7 and the nitride barrier layer 2.

[0060] As Figure 3 shown, the Schottky diode 100 may further include a barrier layer 10 located between the nitride barrier layer 2 and the nitride capping layer 3. The barrier layer 10 can be used to define the depth of etching. The barrier layer 10 may include an aluminum gallium nitride layer. By providing the barrier layer, the depth of the fourth groove can be accurately controlled.

[0061] Among them, the fifth groove and the sixth groove may be formed by an etching process, and the cathode layer 7 may be formed in the fifth groove and the sixth groove by a deposition process. Among them, the deposition process is a combination of one or several processes including PECVD, LPCVD, ALD, and MOCVD. The cathode layer 7 may be made of one or more metal materials including Ti, Al, Ni, and Au.

[0062] Based on the above technical solution, the present application also provides a manufacturing method of a Schottky diode. As Figure 4 shown, the manufacturing method may include the following steps:

[0063] In step 501, a nitride channel layer 1 is formed.

[0064] In step 502, a nitride barrier layer 2 is formed on the nitride channel layer 1.

[0065] In step 503, a nitride capping layer 3 is formed on the nitride barrier layer 2.

[0066] In step 504, a passivation layer 4 is formed on the nitride capping layer 3.

[0067] In step 505, a first groove 41 is formed. The first groove 41 penetrates through the passivation layer 4 to expose the nitride capping layer 3.

[0068] In this embodiment, as Figure 5As shown, a nitride channel layer 1, a nitride barrier layer 2, a nitride cap layer 3, and a passivation layer 4 can be sequentially stacked on a substrate, and further, a first groove 41 can be formed in the passivation layer 4 through an etching process. The first groove 41 penetrates the passivation layer 4 and exposes a part of the nitride cap layer 3. Among them, a nitride buffer layer (not shown in the figure) can also be formed between the nitride channel layer 1 and the nitride barrier layer 2, or a nitride nucleation layer (not shown in the figure) can also be formed below the nitride cap layer 3 as in Figure 5 This application does not limit this.

[0069] In step 506, a dielectric layer 5 is formed. The dielectric layer 5 is located on the passivation layer 4 and the inner wall of the first groove 41, and the dielectric layer 5 forms a second groove 51.

[0070] In step 507, the structure to be processed with the second groove is annealed to form an activation region in the region of the nitride cap layer corresponding to the first groove and a non-activation region in the region of the nitride cap layer covered by the passivation layer.

[0071] In this embodiment, as Figure 5 shown, based on the structure obtained in step 505, a dielectric layer 5 can be further formed on the passivation layer 4 through a deposition process. The dielectric layer 5 is in contact with the passivation layer 4, and the dielectric layer 5 can be in contact with the inner wall of the first groove 41, so that a second groove 51 can be formed around it.

[0072] Furthermore, magnesium elements can be doped in a preset region on the nitride cap layer 3. Optionally, magnesium element doping can be based on GaN. Among them, the doping concentration of magnesium elements can be between 1E16 cm3 - 5E20 / cm3. Then, the structure to be processed doped with magnesium elements and having the second groove 51 can be placed in an atmosphere without hydrogen for annealing. Specifically, for example, annealing can be carried out in nitrogen, nitric oxide, air, or a mixed gas of nitrogen and oxygen. Since the nitride cap layer 3 corresponding to the first groove 41 region is not blocked by the passivation layer 4, hydrogen atoms overflow and magnesium atoms are activated, so that the preset region is activated to obtain a P-type nitride cap layer, that is, an activation region 31 is obtained. And for the region of the nitride cap layer 3 blocked by the passivation layer 4, since there is no channel for hydrogen atoms to overflow, the nitride cap layer 3 in the region blocked by the passivation layer 4 still remains semi-insulating, forming a non-activation region 32. Figure 5 The activation region 31 and the non-activation region 32 are marked by the dotted line on the nitride cap layer 3 in

[0073] In step 508, a third groove 52 is formed on the structure to be processed. The third groove 552 penetrates the dielectric layer 5 to expose a part of the activation region 31 on the nitride cap layer 3.

[0074] In step 509, an anode layer is formed in the second groove 51 and the third groove 52, and the anode layer is in contact with the activation region.

[0075] In this embodiment, the third groove 52 can be formed on the structure to be processed after annealing by an etching process. The third groove 52 penetrates through the dielectric layer 5 and exposes a part of the activation region 31. Further, an anode layer 6 can be deposited and formed in the third groove 52 and the second groove 51. The anode layer 6 is in contact with the activation region and forms a Schottky contact with the nitride barrier layer 2.

[0076] Of course, in another embodiment, as Figure 6 shown, Figure 6 in the embodiment, the steps of forming the third groove 52 and the steps before forming the third groove 52 are the same as those in the Figure 5 shown embodiment. And, in the Figure 6 shown embodiment, a fourth groove 33 can also be formed corresponding to the third groove 52. The fourth groove 33 is located on the activation region 31, and the fourth groove 33 penetrates through the activation region 31 and exposes a part of the nitride barrier layer 2. The anode layer 6 can be deposited in the second groove 51, the third groove 52, and the fourth groove 33. The anode layer 6 formed in the second groove 51 can cooperate with the activation region 31 to form a Schottky contact; the anode layer 6 formed in the third groove 52 and the fourth groove 33 forms an ohmic contact with the heterostructure layer including the nitride channel layer 1 and the nitride barrier layer 2.

[0077] Based on the Figure 5 and Figure 6 shown embodiments, the above manufacturing process can further include forming a fifth groove 7 and a sixth groove 8. The anode layer 6 is located between the fifth groove 7 and the sixth groove 8, and both the fifth groove 7 and the sixth groove 8 penetrate through to the nitride barrier layer 2. Further, still taking the Figure 5 , Figure 6 shown, a cathode layer 9 can also be formed in the fifth groove 7 and the sixth groove 8. The cathode layer 9 is in contact with the nitride barrier layer 2 to form an ohmic contact.

[0078] It should be noted that: in the Figure 5 and Figure 6 shown examples, the example is given by taking the cathode layer 9 being formed in the fifth groove 7 and the sixth groove 8 first and then the anode layer being deposited in the second groove 51, the third groove 52, and the fourth groove 33. In fact, in some other embodiments, the anode layer can also be deposited in the second groove 51, the third groove 52, and the fourth groove 33 first, and then the cathode layer 9 is formed in the fifth groove 7 and the sixth groove 8. The present application does not limit the deposition sequence of the anode layer 6 and the cathode layer 9.

[0079] Other embodiments of the present application will be readily contemplated by those skilled in the art upon consideration of the specification and practice of the disclosure herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0080] It should be understood that the present application is not limited to the exact structures already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A Schottky diode, characterized in that, it includes: A nitride channel layer; A nitride barrier layer, which is formed on the nitride channel layer; A nitride capping layer, which is formed on the nitride barrier layer, and the nitride capping layer includes an active region and a non-active region; A passivation layer, which is formed on the nitride capping layer, and the passivation layer includes a first groove that penetrates the passivation layer and exposes the nitride capping layer, and the first groove corresponds to the active region; A dielectric layer, which is located on the passivation layer and the inner wall of the first groove, and the dielectric layer encloses a second groove. The dielectric layer includes a third groove that penetrates the dielectric layer and exposes a part of the active region on the nitride capping layer; An anode layer, which is formed in the second groove and the third groove, and the anode layer is in contact with the active region.

2. The Schottky diode according to claim 1, characterized in that, the nitride capping layer includes a fourth groove formed in the active region, the fourth groove penetrates the nitride capping layer and exposes a part of the nitride barrier layer, and the fourth groove is in communication with the third groove; the anode layer includes a first anode layer and a second anode layer. The first anode layer is formed in the second groove, and the second anode layer is formed in the third groove and the fourth groove and is in contact with the nitride barrier layer.

3. The Schottky diode according to claim 1, characterized in that, the width of the third groove is smaller than that of the second groove.

4. The Schottky diode according to claim 1, characterized in that, it further includes: A fifth groove and a sixth groove, which are respectively located on both sides of the anode layer, and both the fifth groove and the sixth groove penetrate to the nitride barrier layer; A cathode layer, which is formed in the fifth groove and the sixth groove and is in contact with the nitride barrier layer.

5. The Schottky diode according to claim 1, characterized in that, a barrier layer may also be provided between the nitride barrier layer and the nitride capping layer.

6. The Schottky diode according to claim 1, characterized in that, the active region is a P-type nitride capping layer.

7. The Schottky diode according to claim 6, characterized in that, the P-type nitride capping layer is doped with magnesium element.

8. The Schottky diode according to claim 7, characterized in that, The doping concentration of magnesium element is between 1E16 cm 3 -5E20 / cm 3 and 9. The Schottky diode according to claim 1, characterized in that, the nitride channel layer includes a gallium nitride channel layer, and the nitride barrier layer includes a gallium aluminum nitride barrier layer.

10. A manufacturing method of a Schottky diode, characterized in that, it includes: Forming a nitride channel layer; Forming a nitride barrier layer on the nitride channel layer; Forming a nitride capping layer on the nitride barrier layer; Forming a passivation layer on the nitride capping layer; Forming a first groove that penetrates the passivation layer to expose the nitride capping layer; A dielectric layer is formed, which is located on the passivation layer and on the inner wall of the first groove, and the dielectric layer forms a second groove; Anneal the structure to be processed with the second groove formed thereon to form an activation region in the region corresponding to the first groove on the nitride capping layer and a non-activation region in the region of the nitride capping layer covered by the passivation layer; Form a third groove on the structure to be processed, and the third groove penetrates through the dielectric layer to expose a part of the activation region on the nitride capping layer; Form an anode layer in the second groove and the third groove, and the anode layer is in contact with the activation region.

11. The manufacturing method according to claim 10, wherein, it further includes: Form a fourth groove, which penetrates through the nitride capping layer to expose the nitride barrier layer, and the fourth groove is in communication with the third groove; The step of forming the anode layer in the second groove and the third groove includes: Form a first anode layer in the third groove and the fourth groove; Form a first anode layer in the second groove and make it in contact with the nitride barrier layer.

12. The manufacturing method according to claim 10, wherein, it further includes: Form a fifth groove and a sixth groove, the anode layer is located between the fifth groove and the sixth groove, and both the fifth groove and the sixth groove penetrate to the nitride barrier layer; Form a cathode layer in the fifth groove and the sixth groove.

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