Semiconductor structure and method for forming the same

Abstract

The present application discloses a semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a first barrier layer on the surface of the substrate; forming a first opening in the first barrier layer; forming a first electrode layer in the first opening; forming a variable resistance dielectric layer, a second electrode layer and a mask layer in sequence on the surface of the first electrode layer, the variable resistance dielectric layer extending to the surface of the first barrier layer; and forming a second barrier layer on the surface of the first barrier layer, the sidewall of the variable resistance dielectric layer, the sidewall of the second electrode layer, the sidewall of the mask layer and the surface of the mask layer. The semiconductor structure and the method for forming the same disclosed in the present application can form the sidewall of the RRAM unit without introducing new materials and new processes, and there is no need to adaptively adjust the manufacturing process of other logic units other than the RRAM unit.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Resistive Random Access Memory (RRAM) is an emerging next-generation non-volatile memory device. RRAM cells use resistance values ​​rather than charge to store data. RRAM cells work by turning on a filament or conductive path formed by a normally insulating variable resistance dielectric material after a sufficiently high voltage is applied. The variable resistance dielectric material is disposed between the top electrode layer and the bottom electrode layer, so it is also called a variable resistance dielectric layer. In particular, each RRAM cell includes a variable resistance dielectric layer, the resistance of which can be adjusted to represent a logic "0" or a logic "1".

[0003] In the process of forming the RRAM unit, in order to prevent free oxygen from diffusing from the dielectric layer to the variable resistance dielectric layer during the heat treatment, thereby affecting the characteristics of the filament, it is usually necessary to add a spacer to the variable resistance dielectric layer or the RRAM unit. In the prior art, the spacer is obtained by depositing and etching a silicon nitride layer. However, due to the low etching selectivity of the silicon nitride layer and the etch stop layer thereunder, it is difficult to etch the silicon nitride layer while ensuring the stability of the thickness of the etch stop layer. In order to solve this problem, an auxiliary oxide layer is usually added between the etch stop layer and the silicon nitride layer. However, whether adding an auxiliary oxide layer or depositing and etching the silicon nitride layer leads to an increase in materials and process steps, and the newly introduced materials and processes will affect the compatibility with the standard CMOS process.

[0004] Therefore, a method for forming a RRAM cell spacer that is compatible with a standard CMOS process is needed. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a semiconductor structure and a method for forming the same, which can form the sidewalls of the RRAM unit without introducing new materials and new processes, and does not require adaptive adjustments to the manufacturing processes of other logic units other than the RRAM unit.

[0006] One aspect of the present application provides a method for forming a semiconductor structure, which includes: providing a substrate; forming a first barrier layer on the surface of the substrate; forming a first opening in the first barrier layer; forming a first electrode layer in the first opening; forming a variable resistance dielectric layer, a second electrode layer and a mask layer in sequence on the surface of the first electrode layer, the variable resistance dielectric layer extending to the surface of the first barrier layer; and forming a second barrier layer on the surface of the first barrier layer, the sidewalls of the variable resistance dielectric layer, the sidewalls of the second electrode layer, the sidewalls of the mask layer and the surface of the mask layer.

[0007] In some embodiments, the first barrier layer and the second barrier layer are composed of the same material.

[0008] In some embodiments, the same material is carbon-doped silicon nitride or silicon carbide.

[0009] In some embodiments, the substrate includes: a first dielectric layer having a second opening therein; and a first interconnect layer formed in the second opening and contacting the first electrode layer.

[0010] In some embodiments, the method for forming the semiconductor structure also includes: forming a second dielectric layer on the surface of the second barrier layer; forming a third opening penetrating the second dielectric layer, the second barrier layer and the mask layer, the bottom of the third opening exposing the second electrode layer; and forming a second interconnect layer in the third opening.

[0011] In some embodiments, the semiconductor structure further includes a non-RRAM logic unit, and a sum of a thickness of the first barrier layer and a thickness of the second barrier layer is equal to a thickness of the barrier layer in the non-RRAM logic unit.

[0012] In some embodiments, the first barrier layer has a thickness of 95 angstroms to 105 angstroms, the second barrier layer has a thickness of about 45 angstroms to 55 angstroms, and the barrier layer in the non-RRAM logic cell has a thickness of 140 angstroms to 160 angstroms.

[0013] Another aspect of the present application provides a semiconductor structure, which includes: a substrate; a first barrier layer formed on the substrate and having a first opening; a first electrode layer formed in the first opening; a variable resistance dielectric layer formed on the surface of the first barrier layer and extending to the surface of the first electrode layer; a second electrode layer formed on the surface of the variable resistance dielectric layer; a mask layer formed on the surface of the second electrode layer; and a second barrier layer formed on the surface of the first barrier layer, the sidewalls of the variable resistance dielectric layer, the sidewalls of the second electrode layer, the sidewalls of the mask layer, and the surface of the mask layer.

[0014] In some embodiments, the first barrier layer and the second barrier layer are composed of the same material.

[0015] In some embodiments, the same material is carbon-doped silicon nitride or silicon carbide.

[0016] In some embodiments, the substrate includes: a first dielectric layer having a second opening therein; and a first interconnect layer formed in the second opening and contacting the first electrode layer.

[0017] In some embodiments, the semiconductor structure further includes a second dielectric layer and a second interconnect layer, wherein the second dielectric layer is formed on the surface of the second barrier layer, the second interconnect layer is formed in a third opening and contacts the second electrode layer, and the third opening penetrates the second dielectric layer, the second barrier layer and the mask layer.

[0018] In some embodiments, the semiconductor structure further includes a non-RRAM logic unit, and a sum of a thickness of the first barrier layer and a thickness of the second barrier layer is equal to a thickness of the barrier layer in the non-RRAM logic unit.

[0019] In some embodiments, the first barrier layer has a thickness of 95 angstroms to 105 angstroms, the second barrier layer has a thickness of about 45 angstroms to 55 angstroms, and the barrier layer in the non-RRAM logic cell has a thickness of 140 angstroms to 160 angstroms.

[0020] The semiconductor structure and the method for forming the same proposed in this application have the following benefits:

[0021] First, in the present application, the second barrier layer and the first barrier layer together form a dielectric layer structure that completely covers the RRAM unit, which plays a good protective role for the RRAM unit and perfectly replaces the RRAM unit sidewall in the prior art.

[0022] Secondly, in the present application, there is no need to form side walls through an etching process, nor is there a need to form an additional oxide layer. Instead, the second barrier layer is formed using only the same material and process as the first barrier layer, without introducing any new materials and processes. Therefore, it has good compatibility with standard CMOS processes.

[0023] Furthermore, in the present application, the sum of the thicknesses of the first barrier layer and the second barrier layer can be designed to be equal to the preset thickness of the barrier layer in the non-RRAM logic unit, and the material thereof is also the same as the material of the barrier layer in the non-RRAM logic unit, so there is no need to adaptively adjust the formation process of the non-RRAM logic unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present disclosure. Other embodiments may also accomplish the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Among them:

[0025] Figure 1 is a schematic diagram of a semiconductor structure;

[0026] Figure 2 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present application;

[0027] Figures 3 to 20 Schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. Various local modifications to the disclosed embodiments are obvious to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0029] Unless otherwise indicated, or as is apparent from the context of use, any term, abbreviation, acronym, or scientific symbol and notation used herein will be given its ordinary meaning in the technical discipline to which the invention most closely belongs. The following terms, abbreviations, and acronyms may be used throughout the description presented herein and should generally be given the following meanings, unless otherwise contradicted or elaborated by other descriptions set forth herein.

[0030] The following disclosure provides many different embodiments or examples for realizing the different features of the present application. Specific examples of components and arrangements are described below to simplify the present application. Of course, these are merely examples and are not intended to limit the present invention. In addition, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in a direct contact manner, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present application may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0031] Additionally, for ease of description, spatial relative position terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative position terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative position descriptors used herein should be interpreted accordingly.

[0032] In addition, for convenience of description, “first”, “second”, “third”, etc. may be used herein to distinguish different elements in one figure or a series of figures. “First”, “second”, “third”, etc. are not intended to describe the corresponding elements.

[0033] The technical solution of the present application is described in detail below in conjunction with the embodiments and drawings.

[0034] like Figure 1 As shown, a semiconductor structure includes: a first dielectric layer 10, a first metal interconnection layer 20 formed in an opening of the first dielectric layer 10, a barrier layer 30 formed on the first dielectric layer 10 and the first metal interconnection layer 20, a second dielectric layer 80 formed on the barrier layer 30, a second metal interconnection layer 90 formed in an opening penetrating the barrier layer 30 and the second dielectric layer 80 and exposing the first metal interconnection layer 20, a bottom electrode layer 41 formed on the second dielectric layer 80 and the second metal interconnection layer 90, a resistive material layer 42 formed on the bottom electrode layer 41, a top electrode layer 43 formed on the resistive material layer 42, a hard mask layer 44 formed on the top electrode layer 43, a sidewall 70 formed on the sidewalls of the bottom electrode layer 41, the resistive material layer 42, the top electrode layer 43 and the hard mask layer 44, a third dielectric layer 60 formed on the second dielectric layer 80 and the sidewall 70, and a third metal interconnection layer 50 formed in the opening of the third dielectric layer 60 exposing the hard mask layer 44.

[0035] In such a semiconductor structure, in order to form the spacer 70, additional steps such as depositing the second dielectric layer 80, depositing the spacer layer and etching the spacer layer are required, which not only increases the process cost but also affects the compatibility with the standard CMOS process.

[0036] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, such as Figure 2 As shown, the following steps are included:

[0037] Step S101: providing a substrate;

[0038] Step S102: forming a first barrier layer on the surface of the substrate;

[0039] Step S103: forming a first opening in the first barrier layer;

[0040] Step S104: forming a first electrode layer in the first opening;

[0041] Step S105: forming a variable resistance dielectric layer, a second electrode layer and a mask layer in sequence on the surface of the first electrode layer, wherein the variable resistance dielectric layer extends to the surface of the first barrier layer;

[0042] Step S106: forming a second barrier layer on the surface of the first barrier layer, the sidewall of the variable resistance dielectric layer, the sidewall of the second electrode layer, the sidewall of the mask layer and the surface of the mask layer.

[0043] Combine the following Figures 3 to 20 The above steps are described in detail. It should be noted that methods that perform the above and following steps in other sequences also fall within the protection scope of the present disclosure.

[0044] The embodiment of the present application relates to the RRAM region 1000, but in order to illustrate that the technical solution of the present application does not affect the non-RRAM manufacturing process, Figures 3 to 20 A non-RRAM region is also shown as a control.

[0045] like Figure 3 As shown, a first dielectric layer 100 is provided.

[0046] The first dielectric layer 100 may be formed on a semiconductor substrate (not shown in the figure), and the material of the first dielectric layer 100 may be silicon oxide (e.g., SiO2), a low-K or ultra-low-K dielectric (e.g., a dielectric with a dielectric constant K less than about 2). For example, the first dielectric layer 100 may be formed by deposition on a semiconductor substrate (not shown) by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0047] In the embodiment of the present application, the semiconductor substrate is defined as a RRAM region 1000 and a non-RRAM region, the RRAM region 1000 includes RRAM cells, and the non-RRAM region includes logic cells, such as CMOS devices. The semiconductor substrate may also include an interlayer interconnect structure, etc.

[0048] like Figure 4 As shown, a second opening 230 is formed on the first dielectric layer 100 .

[0049] The second opening 230 may be formed by spin coating photoresist on the surface of the first dielectric layer 100, forming an opening pattern in the photoresist after an exposure and development process, and then etching the first dielectric layer 100 to form the second opening 230, and introducing oxygen plasma after etching to remove the remaining photoresist by ashing.

[0050] Optionally, in the non-RRAM region, a fourth opening 240 may be formed on the first dielectric layer 100 , and the fourth opening 240 may be formed simultaneously with the second opening 230 .

[0051] like Figure 5 As shown, a first interconnection layer 210 is formed in the second opening 230. The first interconnection layer 210 may be any interlayer interconnection structure in the semiconductor structure, for example, an interlayer interconnection structure electrically connected to M4.

[0052] The material of the first interconnection layer 210 may be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination of the above materials. The first interconnection layer 210 may be formed in the second opening 230 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating process or other suitable process. When the first interconnection layer 210 is formed by the above process, the material deposited on the surface of the first dielectric layer 100 may be removed by a chemical mechanical polishing process.

[0053] The first dielectric layer 100 and the first interconnection layer 210 located in the first dielectric layer 100 together constitute a substrate.

[0054] Optionally, in the non-RRAM region, a third interconnect layer 220 may be formed in the fourth opening 240 . The material and formation process of the third interconnect layer 220 may be the same as those of the first interconnect layer 210 , and the third interconnect layer 220 may be formed simultaneously with the first interconnect layer 210 .

[0055] like Figure 6 As shown, a first barrier layer 310 is formed on the substrate. More specifically, the first barrier layer 310 is formed on the surface of the first dielectric layer 100 and the surface of the first interconnect layer 210 .

[0056] The first barrier layer 310 is an etch stop layer, and its material can be silicon carbide (SiC), silicon nitride (SiN), carbon-doped silicon nitride (Nitrogen Doped Carbide, NDC), or some other suitable dielectrics, or any combination of the above materials. The first barrier layer 310 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, sputtering or other suitable processes. On the one hand, the first barrier layer 310 acts as a protective layer to prevent subsequent processes (such as etching processes) from damaging the first dielectric layer 100 and the interconnection layer (such as the first interconnection layer 210, the third interconnection layer 220) and other possible devices located in the first dielectric layer 100. On the other hand, the first barrier layer 310 can provide a process basis for forming a first electrode layer 410 (described in detail below), forming a first electrode layer 410 electrically connected to the first interconnection layer 210. Optionally, in the non-RRAM area, the first barrier layer 310 can cover the third interconnection layer 220.

[0057] like Figure 7 As shown, a first opening 400 is formed in the first barrier layer 310. The first opening 400 is located on the first interconnect layer 210, corresponds to the position of the first interconnect layer 210, and only exposes a portion of the first interconnect layer 210.

[0058] The first opening 400 may be formed by spin coating photoresist on the surface of the first barrier layer 310, forming an opening pattern in the photoresist after an exposure and development process, and then etching the first barrier layer 310 to form the first opening 400, and then introducing oxygen plasma after etching to remove the remaining photoresist by ashing.

[0059] like Figure 8 As shown, a first electrode layer 410 is formed on the surface of the first barrier layer 310 and in the first opening 400 . The first electrode layer 410 fills the first opening 400 .

[0060] The first electrode layer 410 is the bottom electrode layer of the RRAM unit, and its material can be a metal material such as tantalum (Ta), titanium (Ti), platinum (Pt), iridium (Ir), ruthenium (Ru), tungsten (W), etc., or a conductive material such as tantalum nitride (TaN), titanium nitride (TiN), etc., or any combination of the above materials. The first electrode layer 410 can also be a composite structure film layer including multiple layers of the above materials. The first electrode layer 410 can be formed by physical vapor deposition, chemical vapor deposition (for example, metal organic chemical vapor deposition), atomic layer deposition, electroplating, sputtering or other suitable processes. The first electrode layer 410 prevents the metal ions in the first interconnect layer 210 from diffusing into the subsequently formed variable resistance dielectric layer 420 (described in detail below), so that the subsequently formed variable resistance dielectric layer 420 maintains good performance, thereby improving the electrical performance of the formed RRAM device.

[0061] like Fig. 9 As shown, the first electrode layer 410 is planarized to remove the first electrode layer 410 located on the surface of the first barrier layer 310 , so that the top of the first electrode layer 410 is flush with the top of the first barrier layer 310 .

[0062] The planarization process may be chemical mechanical polishing (CMP) or other planarization processes.

[0063] like Fig.10 As shown, the variable resistance dielectric layer 420 is formed on the surface of the first barrier layer 310 and the surface of the first electrode layer 410. It can also be considered that the variable resistance dielectric layer 420 extends continuously above the first electrode layer 410.

[0064] The variable resistance dielectric layer 420 is a resistance material layer of the RRAM unit, and the variable resistance dielectric layer 420 is used to form a "filament" that is considered to be an operable mechanism of the RRAM device. At the same time, the variable resistance dielectric layer 420 also acts as an insulating dielectric layer between the first electrode layer 410 and the subsequently formed second electrode layer 430 (described in detail below). The material of the variable resistance dielectric layer 420 is a material with electrically induced resistive switching properties, and the electrical induction means that the resistance of the material will change under a specific external signal, and the resistance of the material will not recover due to the removal of the electrical signal after the change; and the resistance of the material is reversible, and applying one form of electrical signal can reduce the resistance of the material, and applying another form of electrical signal can increase the resistance and restore it to high resistance.

[0065] The material of the variable resistance dielectric layer 420 can be amorphous silicon, polysilicon, copper oxide, aluminum oxide, titanium oxide, tantalum oxide, or hafnium dioxide, or any combination thereof, and can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0066] like Fig.11 As shown, a second electrode layer 430 is formed on the surface of the variable resistance dielectric layer 420 .

[0067] The second electrode layer 430 is the top electrode layer of the RRAM unit, and its material can be a metal material such as silver (Ag), copper (Au), platinum (Pt), tungsten (W), etc., or a conductive material such as tantalum nitride (TaN), titanium nitride (TiN), etc., or any combination of the above materials. The second electrode layer 430 can also be a composite structure film layer including multiple layers of the above materials. The second electrode layer 430 can be formed by physical vapor deposition, chemical vapor deposition (e.g., metal organic chemical vapor deposition), atomic layer deposition, electroplating, sputtering or other suitable processes.

[0068] like Fig.12 As shown, a mask layer 440 is formed on the surface of the second electrode layer 430. The mask layer 440 is a protective layer for the second electrode layer 430 in the subsequent etching process. In the subsequent etching process, the mask layer 440 will be thinned to a certain extent, but will not be completely etched away.

[0069] The mask layer 440 may be a hard mask layer, and the hard mask layer may be a single layer structure or a stacked layer structure. The material of the mask layer 440 may be silicon carbide (SiC), silicon nitride (SiN), NDC, or any combination thereof.

[0070] like Fig.13 As shown, the mask layer 440 is etched by an etching process to remove all the mask layers 44 located in the non-RRAM region and a portion of the mask layer 440 in the RRAM region.

[0071] The above-mentioned etching process can be to spin-coat photoresist on the surface of the mask layer 440, form an opening pattern in the photoresist after an exposure and development process, and then etch the mask layer 440 to remove all the mask layers 44 located in the non-RRAM area and part of the mask layer 440 in the RRAM area, and after etching, introduce oxygen plasma to ash and remove the remaining photoresist.

[0072] like Fig.14 As shown, the second electrode layer 430 is etched by an etching process to remove all the second electrode layer 430 located in the non-RRAM area and part of the second electrode layer 430 in the RRAM area.

[0073] The etching process may be to use the mask layer 440 as a mask to etch the second electrode layer 430 to remove all the second electrode layer 430 located in the non-RRAM region and a portion of the second electrode layer 430 in the RRAM region.

[0074] like Fig.15 As shown, the variable resistance dielectric layer 420 is etched by an etching process to remove all the variable resistance dielectric layer 420 located in the non-RRAM area and part of the variable resistance dielectric layer 420 in the RRAM area.

[0075] The etching process may be to use the mask layer 440 and the second electrode layer 430 as masks to etch the variable resistance dielectric layer 420 to remove all the variable resistance dielectric layer 420 in the non-RRAM region and part of the variable resistance dielectric layer 420 in the RRAM region.

[0076] The second electrode layer 430 , the variable resistance dielectric layer 420 , and the first electrode layer 410 remaining after the etching process constitute a basic RRAM unit, and the device size thereof is set as required.

[0077] like Fig.16 As shown, the second barrier layer 320 is formed on the surface of the first barrier layer 310 , the sidewall of the variable resistance dielectric layer 420 , the sidewall of the second electrode layer 430 , the sidewall of the mask layer 440 , and the surface of the mask layer 440 .

[0078] The material of the second barrier layer 320 can be silicon carbide (SiC), silicon nitride (SiN), NDC, or some other suitable dielectric, or any combination of the above materials. The second barrier layer 320 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating, sputtering or other suitable processes.

[0079] In some embodiments, the second barrier layer 320 and the first barrier layer 310 together form a dielectric layer structure that completely covers the RRAM unit, which is used to protect the RRAM unit and plays the role of the RRAM unit sidewall in the prior art. In this way, the deposition and etching processes that must be performed to form the sidewall in the prior art are omitted, and there is no need to form an additional oxide layer under the etch stop layer (for example, the second barrier layer 320 of the present application), saving process steps and costs.

[0080] Furthermore, the second barrier layer 320 is formed by using only the same material and process as the first barrier layer 310, without introducing any new material and process, and thus has good compatibility with standard CMOS processes. In the non-RRAM region, the second barrier layer 320 and the first barrier layer 310 are equivalent to the barrier layers in the non-RRAM logic unit.

[0081] The thickness of the second barrier layer 320 may be less than or equal to the thickness of the first barrier layer 310. In the embodiment of the present application, the sum H of the thicknesses of the first barrier layer 310 and the second barrier layer 320 may be designed to be equal to the preset thickness of the barrier layer in the non-RRAM logic unit in the non-RRAM region, and the material thereof is also the same as the material of the barrier layer in the non-RRAM logic unit, so there is no need to adaptively adjust the formation process of the non-RRAM logic unit. Therefore, the fourth interconnect layer 910 ( Fig. 20 shown) and the fifth interconnect layer 520 ( Fig. 20 In some embodiments, the thickness of the first barrier layer 310 is 95 angstroms to 105 angstroms, the thickness of the second barrier layer 320 is about 45 angstroms to 55 angstroms, and the preset thickness of the barrier layer in the non-RRAM logic unit is 140 angstroms to 160 angstroms. For example, the thickness of the first barrier layer 310 is 100 angstroms, the thickness of the second barrier layer 320 is about 50 angstroms, and the preset thickness of the barrier layer in the non-RRAM logic unit is 150 angstroms.

[0082] like Fig.17 As shown, a second dielectric layer 600 is formed on the second barrier layer 320. The second dielectric layer 600 is an interlayer dielectric layer (IMD), and therefore, in a portion outside the stack structure formed by the mask layer 440, the second electrode layer 430, and the variable resistance dielectric layer 420, the thickness of the second dielectric layer 600 is greater than the sum of the thicknesses of the mask layer 440, the second electrode layer 430, the variable resistance dielectric layer 420, and the second barrier layer 320.

[0083] The material of the second dielectric layer 600 may be silicon oxide (e.g., SiO2), a low-K or ultra-low-K dielectric (e.g., a dielectric with a dielectric constant K less than about 2). The process for forming the second dielectric layer 600 includes depositing the second dielectric layer 600 on the second barrier layer 320 and performing chemical mechanical polishing on the second dielectric layer 600 to flatten the top thereof. After flattening, a second dielectric layer 600 of a specific thickness is still left on the stack structure formed by the mask layer 440, the second electrode layer 430, and the variable resistance dielectric layer 420, for forming a second interconnect layer 510 ( Fig. 20 The second dielectric layer 600 may be deposited on the second barrier layer 320 by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0084] like Fig.18 As shown, a third opening 530 is formed penetrating the second dielectric layer 600 , the second barrier layer 320 and the mask layer 440 , and the bottom of the third opening 530 exposes the second electrode layer 430 .

[0085] The third opening 530 may be formed by dry etching or wet etching.

[0086] like Fig.19 As shown, in some embodiments, a fifth opening 920 and a sixth opening 540 may be formed in the non-RRAM region, the fifth opening 920 and the sixth opening 540 are connected, and the bottom of the fifth opening 920 exposes the third interconnection layer 220. The fifth opening 920 and the sixth opening 540 may be formed by dry etching or wet etching.

[0087] like Fig. 20 As shown, the second interconnection layer 510 is formed in the third opening 530 .

[0088] The material of the second interconnection layer 510 can be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination of the above materials. The second interconnection layer 510 can be formed in the third opening 530 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating process or other suitable process.

[0089] Optionally, in the non-RRAM region, a fourth interconnect layer 910 may be formed in the fifth opening 920 and a fifth interconnect layer 520 may be formed in the sixth opening 540, and the fourth interconnect layer 910 and the fifth interconnect layer 520 may constitute a Damascus interconnect structure. The material of the fourth interconnect layer 910 may be a metal material such as copper (Cu), aluminum (Al), tantalum (Ta), tungsten (W), cobalt (Co), etc., or a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), etc., or any combination of the above materials. The fourth interconnect layer 910 may be formed in the third opening 530 by physical vapor deposition, chemical vapor deposition, atomic layer deposition, electroplating process or other suitable process. The material and formation process of the fifth interconnect layer 520 may be the same as those of the second interconnect layer 510.

[0090] The embodiment of the present application also provides a semiconductor structure, referring to Figures 3 to 20, the semiconductor structure includes: a substrate, a first barrier layer 310, a first electrode layer 410, a variable resistance dielectric layer 420, a second electrode layer 430, a mask layer 440 and a second barrier layer 320. The substrate includes a first dielectric layer 100 and a first interconnection layer 210, the first dielectric layer 100 has a second opening 230, the first interconnection layer 210 is formed in the second opening 230 and contacts the first electrode layer 410. The first barrier layer 310 is formed on the substrate and has a first opening 400, the bottom of the first opening 400 exposes the first interconnection layer 210. The first electrode layer 410 is formed in the first opening 400. The variable resistance dielectric layer 420 is formed on the surface of the first barrier layer 310 and extends to the surface of the first electrode layer 410. The second electrode layer 430 is formed on the surface of the variable resistance dielectric layer 420. The mask layer 440 is formed on the surface of the second electrode layer 430. The second barrier layer 320 is formed on the surface of the first barrier layer 310 , the sidewalls of the variable resistance dielectric layer 420 , the sidewalls of the second electrode layer 430 , the sidewalls of the mask layer 440 , and the surface of the mask layer 440 .

[0091] In some embodiments, the semiconductor structure further includes a second dielectric layer 600 and a second interconnect layer 510. The second dielectric layer 600 is formed on the surface of the second barrier layer 320. The second interconnect layer 510 is formed in the third opening 530 and contacts the second electrode layer 430. The third opening 530 penetrates the second dielectric layer 600, the second barrier layer 320 and the mask layer 440.

[0092] In summary, after reading this detailed disclosure, it will be apparent to those skilled in the art that the foregoing detailed disclosure may be presented only by way of example and may not be limiting. Although not explicitly stated herein, it will be appreciated by those skilled in the art that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are intended to be proposed by this disclosure and are within the spirit and scope of the exemplary embodiments of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first dielectric layer, the first dielectric layer having a second opening therein and a first interconnection layer formed in the second opening; forming a first barrier layer on the surface of the substrate; forming a first opening in the first barrier layer; forming a first electrode layer in the first opening, wherein an area of ​​the first electrode layer is smaller than an area of ​​the first interconnection layer; forming a variable resistance dielectric layer, a second electrode layer and a mask layer in sequence on the surface of the first electrode layer, wherein the variable resistance dielectric layer extends to the surface of the first barrier layer, wherein the second electrode layer, the variable resistance dielectric layer and the first electrode layer constitute an RRAM unit; as well as A second barrier layer is formed on the surface of the first barrier layer, the sidewall of the variable resistance dielectric layer, the sidewall of the second electrode layer, the sidewall of the mask layer, and the surface of the mask layer, wherein the first barrier layer and the second barrier layer are composed of the same material, which is carbon-doped silicon nitride or silicon carbide, and the second barrier layer and the first barrier layer are used as sidewalls of the RRAM unit.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming a second dielectric layer on a surface of the second barrier layer; forming a third opening penetrating the second dielectric layer, the second barrier layer and the mask layer, wherein the bottom of the third opening exposes the second electrode layer; as well as A second interconnect layer is formed in the third opening.

3. The method for forming a semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a non-RRAM logic cell, and a sum of a thickness of the first barrier layer and a thickness of the second barrier layer is equal to a thickness of the barrier layer in the non-RRAM logic cell.

4. The method for forming a semiconductor structure according to claim 3, characterized in that: The thickness of the first barrier layer is 95 angstroms to 105 angstroms, the thickness of the second barrier layer is 45 angstroms to 55 angstroms, and the thickness of the barrier layer in the non-RRAM logic cell is 140 angstroms to 160 angstroms.

5. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a first dielectric layer, the first dielectric layer having a second opening therein and a first interconnection layer formed in the second opening; A first barrier layer formed on the substrate and having a first opening; A first electrode layer is formed in the first opening, and an area of ​​the first electrode layer is smaller than an area of ​​the first interconnection layer; a variable resistance dielectric layer formed on a surface of the first barrier layer and extending to a surface of the first electrode layer; A second electrode layer is formed on a surface of the variable resistance dielectric layer, wherein the second electrode layer, the variable resistance dielectric layer and the first electrode layer constitute an RRAM unit; a mask layer formed on a surface of the second electrode layer; as well as A second barrier layer is formed on the surface of the first barrier layer, the sidewall of the variable resistance dielectric layer, the sidewall of the second electrode layer, the sidewall of the mask layer and the surface of the mask layer, wherein the first barrier layer and the second barrier layer are composed of the same material, which is carbon-doped silicon nitride or silicon carbide, and the second barrier layer and the first barrier layer are used as sidewalls of the RRAM unit.

6. The semiconductor structure according to claim 5, characterized in that: Also includes: A second dielectric layer formed on a surface of the second barrier layer; as well as A second interconnection layer is formed in the third opening and contacts the second electrode layer. The third opening penetrates the second dielectric layer, the second barrier layer and the mask layer.

7. The semiconductor structure according to claim 5, characterized in that: The semiconductor structure further includes a non-RRAM logic cell, and a sum of a thickness of the first barrier layer and a thickness of the second barrier layer is equal to a thickness of the barrier layer in the non-RRAM logic cell.

8. The semiconductor structure according to claim 7, characterized in that: The thickness of the first barrier layer is 95 angstroms to 105 angstroms, the thickness of the second barrier layer is 45 angstroms to 55 angstroms, and the thickness of the barrier layer in the non-RRAM logic cell is 140 angstroms to 160 angstroms.

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