Memory device

Abstract

A memory device is provided, the memory device comprising: a plurality of first conductive lines disposed on a substrate and spaced apart from each other in a first direction parallel to a top surface of the substrate; a plurality of cover plates located on a sidewall of each of the plurality of first conductive lines, the plurality of cover plates having a top surface at a vertical level equal to the vertical level of the top surface of the plurality of first conductive lines and a bottom surface at a vertical level higher than the bottom surface of the plurality of first conductive lines; and an insulating layer located on the substrate, the insulating layer filling the space between the plurality of first conductive lines and covering the sidewalls of the plurality of cover plates.

Description

[0001] Korean Patent Application No. 10-2019-0178507, entitled "Memory Device", filed with the Korean Intellectual Property Office on December 30, 2019, is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to a memory device. Background Technology

[0003] In line with the trend towards lighter and more compact electronic products, the demand for high integration of memory devices has increased. Memory devices with a three-dimensional intersection structure in which memory cells are arranged at the intersection of two intersecting conductive lines have been considered. Summary of the Invention

[0004] An embodiment can be implemented by providing a memory device comprising: a plurality of first conductive lines disposed on a substrate and spaced apart from each other in a first direction parallel to the top surface of the substrate; a plurality of cover plates located on the sidewalls of each of the plurality of first conductive lines, the plurality of cover plates having a top surface at a vertical level equal to the vertical level of the top surface of the plurality of first conductive lines and a bottom surface at a vertical level higher than the bottom surface of the plurality of first conductive lines; and an insulating layer located on the substrate, the insulating layer filling the space between the plurality of first conductive lines and covering the sidewalls of the plurality of cover plates.

[0005] An embodiment can be implemented by providing a memory device comprising: a plurality of first conductive lines located on a substrate and spaced apart from each other in a first direction parallel to the top surface of the substrate; a plurality of second conductive lines located on the substrate and spaced apart from each other in a second direction parallel to the top surface of the substrate at a vertical level lower than the plurality of first conductive lines; a plurality of memory cells respectively disposed between the plurality of first conductive lines and the plurality of second conductive lines; and a plurality of cover plates located on the sidewall of each of the plurality of first conductive lines, the plurality of cover plates having a top surface at a vertical level equal to the vertical level of the top surface of the plurality of first conductive lines and a bottom surface at a vertical level higher than the bottom surface of the plurality of first conductive lines.

[0006] An embodiment can be implemented by providing a memory device comprising: a plurality of first conductive lines located on a substrate and spaced apart from each other in a first direction parallel to the top surface of the substrate; a plurality of second conductive lines located on the substrate and spaced apart from each other in a second direction parallel to the top surface of the substrate at a vertical horizontal position lower than the plurality of first conductive lines; a plurality of first memory cells respectively located between the plurality of first conductive lines and the plurality of second conductive lines; a plurality of first cover plates located on the upper sidewall of each of the plurality of first conductive lines; and an insulating layer located on the substrate, the insulating layer filling the space between the plurality of first conductive lines, wherein the upper sidewalls of the plurality of first conductive lines are covered by the plurality of first cover plates, and the lower sidewalls of the plurality of first conductive lines are covered by the insulating layer. Attached Figure Description

[0007] Features will be apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 This is an equivalent circuit diagram of a memory device according to an example embodiment;

[0009] Figure 2 This is a perspective view showing a schematic structure of a memory device according to an example embodiment;

[0010] Figure 3 It shows along Figure 2 A sectional view taken by lines A1-A1' and A2-A2';

[0011] Figure 4 yes Figure 3 A magnified view of region CX1;

[0012] Figure 5 This is a cross-sectional view showing a memory device according to an example embodiment;

[0013] Figure 6 This is a cross-sectional view showing a memory device according to an example embodiment;

[0014] Figure 7 This is a layout diagram illustrating a memory device according to an example embodiment;

[0015] Figure 8 Is with Figure 2 The sectional views corresponding to lines A1-A1' and A2-A2';

[0016] Figures 9 to 17 This is a cross-sectional view of a stage in a method for manufacturing a memory device according to an example embodiment; and

[0017] Figures 18 to 26 This is a cross-sectional view of a stage in a method for manufacturing a memory device according to an example embodiment. Detailed Implementation

[0018] Figure 1 This is an equivalent circuit diagram of the memory device 10 according to an example embodiment.

[0019] Reference Figure 1 The memory device 10 may be included in the first direction ( Figure 1 Multiple letter lines WL1, WL2, WL3, and WL4 extending in the X direction and in the second direction perpendicular to the first direction ( Figure 1 Multiple bit lines BL1, BL2, BL3, and BL4 extend in the Y direction. Multiple memory cells MC can be connected to multiple word lines WL1, WL2, WL3, and WL4, and multiple bit lines BL1, BL2, BL3, and BL4, respectively. Each of the multiple memory cells MC may include a variable resistive memory unit RMU for storing information and a switching unit SWU for selecting the memory cell MC. The switching unit SWU may be referred to as a selection device or an access device.

[0020] In one embodiment, as the switching component SWU of the selected memory cell MC via multiple word lines WL1, WL2, WL3, and WL4 and multiple bit lines BL1, BL2, BL3, and BL4 is turned on, a voltage can be applied to the variable resistance memory component RMU of the selected memory cell MC, allowing current to flow within the variable resistance memory component RMU. In another embodiment, the variable resistance memory component RMU may include a phase change material layer capable of reversibly transitioning between a first state and a second state. In yet another embodiment, the variable resistance memory component RMU may include a suitable variable resistor having a resistance value that varies according to the applied voltage. In yet another embodiment, the resistance of the variable resistance memory component RMU can reversibly transition between a first state and a second state based on the voltage applied to the variable resistance memory component RMU of the selected memory cell MC.

[0021] Based on the change in resistance of the variable resistance memory unit (RMU), the memory cell MC can store digital information such as "0" or "1", and can erase digital information from the memory cell MC. In one embodiment, data can be written to the memory cell MC in a high resistance state "0" and a low resistance state "1". In another embodiment, the memory cell MC can store various resistance states.

[0022] Random or desired memory cells MC can be addressed by selecting word lines WL1, WL2, WL3, and WL4 and bit lines BL1, BL2, BL3, and BL4. Memory cells MC can be programmed by applying preset signals between word lines WL1, WL2, WL3, and WL4 and bit lines BL1, BL2, BL3, and BL4. Information about the resistance value of the variable resistance memory unit RMU constituting the corresponding memory cell MC can be read by measuring the current value through bit lines BL1, BL2, BL3, and BL4.

[0023] Figure 2 This is a perspective view showing a schematic structure of a memory device 100 according to an example embodiment. Figure 3 It shows along Figure 2 A sectional view taken from lines A1-A1' and A2-A2'. Figure 4 yes Figure 3 A magnified view of region CX1.

[0024] Reference Figures 2 to 4 The substrate 110 may include a memory cell region and a peripheral circuit region, and multiple memory cells MC may be arranged on the memory cell region.

[0025] In the peripheral circuit region, multiple transistors constituting a driving circuit for driving multiple memory cells MC can be formed on the substrate 110. In an embodiment, the driving circuit can be a peripheral circuit capable of processing data input to / output from the multiple memory cells MC, such as a page buffer, latch circuit, cache circuit, column decoder, sense amplifier, data input / output circuit, row decoder, etc. The peripheral circuit region can be arranged on one side of the memory cell region or at one side of the memory cell region, or it can be arranged at a different vertical level than the memory cell region, so as to be vertically superimposed on at least a portion of the memory cell region.

[0026] The lower insulating layer 112 may be on the substrate 110. The lower insulating layer 112 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. In an embodiment, the lower insulating layer 112 may cover at least a portion of the drive circuitry on the substrate 110.

[0027] Multiple first conductive lines 120 extending in a first direction (X direction) may be on a lower insulating layer 112. Multiple second conductive lines 160 may extend in a second direction (Y direction) at a vertical horizontal position higher than the multiple first conductive lines 120 (e.g., at a greater distance from the substrate 110 in the vertical direction (Z direction, third direction) than the multiple first conductive lines 120). The multiple first conductive lines 120 may be spaced apart from each other in the second direction (Y direction) to extend (e.g., longitudinally) in the first direction (X direction), and the multiple second conductive lines 160 may be spaced apart from each other in the first direction (X direction) to extend (e.g., longitudinally) in the second direction (Y direction). The multiple first conductive lines 120 may correspond, for example, to multiple word lines WL1, WL2, WL3, and WL4 (see reference). Figure 1 The multiple word lines WL correspond to, for example, multiple bit lines BL1, BL2, BL3 and BL4 (see reference). Figure 1 Multiple bit lines BL correspond to each other. As used herein, the terms "first", "second", etc. are arbitrarily assigned and are not construed as permanently designating a particular element, nor are the elements required to be included in order.

[0028] The plurality of first conductive lines 120 and the plurality of second conductive lines 160 may be formed of metal, conductive metal nitride, conductive metal oxide, or combinations thereof. In embodiments, the plurality of first conductive lines 120 and the plurality of second conductive lines 160 may be formed of W, WN, Au, Ag, Cu, Al, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, alloys thereof, or combinations thereof. In embodiments, one of the plurality of first conductive lines 120 and the plurality of second conductive lines 160 may include a metal layer and a conductive barrier layer covering at least a portion of the metal layer. The conductive barrier layer may be formed of, for example, Ti, TiN, Ta, TaN, or combinations thereof. As used herein, the term "or" is not an exclusive term; for example, "A or B" will include A, B, or A and B.

[0029] Multiple memory cells MC can be located between multiple first conductive lines 120 and multiple second conductive lines 160. In an embodiment, in a plan view, the multiple memory cells MC can be arranged at the intersection of the multiple first conductive lines 120 and multiple second conductive lines 160. Each of the multiple memory cells MC may include a variable resistor memory component 140 for storing information and a switch component 130 for selecting the memory cell MC.

[0030] Each of the plurality of memory cells MC may include a switching component 130 and a variable resistance memory component 140 sequentially arranged on each of the plurality of first conductive lines 120. The switching component 130 may include a first electrode 132, a switching material layer 134, and a second electrode 136, while the variable resistance memory component 140 may include a variable resistance material layer 142 and a third electrode 144. In an embodiment, the variable resistance memory component 140 may further include a heating electrode between the second electrode 136 and the variable resistance material layer 142.

[0031] In the implementation method, with Figure 3 As shown, the variable resistance memory component 140 and the switching component 130 can be sequentially arranged on the plurality of first conductive lines 120. In one embodiment, based on the top surface of the substrate 110, the variable resistance memory component 140 can be arranged at a lower level than the switching component 130 (e.g., closer to the substrate 110 in the Z direction). In this case, a heating electrode can be further arranged between the variable resistance memory component 140 and the plurality of first conductive lines 120.

[0032] A first insulating layer 122 (filling the space between adjacent first conductive lines 120 among a plurality of first conductive lines 120) may be on a lower insulating layer 112, and a second insulating layer 152 may surround the sidewalls of a plurality of memory cells MC. A third insulating layer 162 (filling the space between adjacent second conductive lines 160 among a plurality of second conductive lines 160) may be on a second insulating layer 152.

[0033] In one embodiment, the first insulating layer 122, the second insulating layer 152, and the third insulating layer 162 may include insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc. In another embodiment, at least one of the first insulating layer 122, the second insulating layer 152, and the third insulating layer 162 may include an air space and an insulating material layer surrounding the air space.

[0034] A pair of cover sheets 164 may be on the sidewall of each of the plurality of second conductive lines 160. The pair of cover sheets 164 may be disposed on the upper sidewall 160SU (e.g., the sidewall away from the substrate 110 in the Z direction) of each of the plurality of second conductive lines 160, and the pair of cover sheets 164 may not cover the lower sidewall 160SL (e.g., the sidewall close to the substrate 110 in the Z direction) of each of the plurality of second conductive lines 160. The pair of cover sheets 164 may be between the upper sidewall 160SU of each of the plurality of second conductive lines 160 and the third insulating layer 162, but may not be between the lower sidewall 160SL of each of the plurality of second conductive lines 160 and the third insulating layer 162.

[0035] In one embodiment, the pair of capping sheets 164 may comprise a material having etch selectivity relative to the plurality of second conductive lines 160. In another embodiment, the pair of capping sheets 164 may comprise a material having a high-step coverage that can be formed by an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. In yet another embodiment, the pair of capping sheets 164 may comprise, for example, silicon oxide, silicon nitride, silicon carbide, silicon carbide, or silicon.

[0036] In the implementation method, such as Figure 4 As shown, the top surfaces of a pair of cover sheets 164 (e.g., the surfaces facing away from the substrate 110 in the Z direction) may be at the same or equal level as the top surface level LV1 of the plurality of second conductive lines 160 (e.g., the level of the surfaces facing away from the substrate 110 in the Z direction) (e.g., coplanar with the top surface level LV1 of the plurality of second conductive lines 160 or at the same distance from the substrate 110 in the Z direction). The bottom surfaces of a pair of cover sheets 164 (e.g., the surfaces facing the substrate 110) may be at a level LV3 that is higher than the bottom surface level LV2 of the plurality of second conductive lines 160 (e.g., the level of the surfaces facing the substrate 110) (e.g., farther from the substrate 110 in the Z direction than the bottom surface level LV2 of the plurality of second conductive lines 160).

[0037] In one embodiment, the top surface of the third insulating layer 162 may be at the same level as the top surface level LV1 of the plurality of second conductive lines 160, for example, coplanar with the top surface level LV1 of the plurality of second conductive lines 160, and the bottom surface of the third insulating layer 162 may be at a level LV4 that is lower than the bottom surface level LV2 of the plurality of second conductive lines 160 (e.g., closer to the substrate 110 in the Z direction than the bottom surface level LV2 of the plurality of second conductive lines 160). In another embodiment, the top surface of the second insulating layer 152 may contact (e.g., directly contact) the bottom surface of the third insulating layer 162, and may be at a level LV4 that is lower than the bottom surface level LV2 of the plurality of second conductive lines 160. This may be because in the patterning process of the plurality of second conductive lines 160, the second conductive layer 160L (refer to...) Figure 11 The second insulating layer 152 can be over-etched to form sidewalls of multiple second conductive lines 160 with vertical profiles. Therefore, a portion of the upper part of the second insulating layer 152 can be etched to a predetermined height, thereby reducing the top surface level of the second insulating layer 152.

[0038] In one embodiment, the plurality of second conductive lines 160 may have a first height h11 in the vertical direction (Z direction), and a pair of capping sheets 164 may have a second height h12 in the vertical direction (Z direction) that is less than or shorter than the first height h11. In one embodiment, the first height h11 may be, for example, from about 30 nm to about 150 nm. In one embodiment, the second height h12 of the pair of capping sheets 164 may be, for example, from about 40% to about 90% of the first height h11.

[0039] In one embodiment, the plurality of second conductive lines 160 may have a first width w11 in a first direction (X direction), and the ratio of the first height h11 to the first width w11 may be from about 0.5 to about 5. In another embodiment, a pair of cover sheets 164 may have a first thickness w12 in the first direction (X direction), for example, from about 1 nm to about 4 nm.

[0040] The outer sidewalls 164SO of a pair of cover sheets 164 may contact (e.g., directly contact) the third insulating layer 162, and the inner sidewalls 164SI of a pair of cover sheets 164 may contact (e.g., directly contact) the upper sidewall 160SU of each of the plurality of second conductive lines 160. The outer sidewalls 164SO of a pair of cover sheets 164 may be aligned with the lower sidewalls 160SL of each of the plurality of second conductive lines 160 (e.g., to form a flat or continuous surface). In an embodiment, the outer sidewalls 164SO of a pair of cover sheets 164 and the lower sidewalls 160SL of each of the plurality of second conductive lines 160 may be arranged in a straight line or may be coplanar with each other. In an embodiment, the upper portion of the third insulating layer 162 may cover the outer sidewalls 164SO of a pair of cover sheets 164, and the lower portion of the third insulating layer 162 may cover the lower sidewalls 160SL of the plurality of second conductive lines 160.

[0041] In the manufacturing process according to the embodiment, the second conductive layer 160L (see reference) can be etched. Figure 12 Part of it can be formed by etching the sidewalls 160LH of the second conductive layer 160L (refer to...) Figure 12 A pair of cover plates 164 are formed on the surface, and the remaining thickness of the second conductive layer 160L can be etched again. Through the manufacturing process described above, the upper sidewalls 160SU of the multiple second conductive lines 160 can be formed first, a pair of cover plates 164 can be formed on the upper sidewalls 160SU, and the lower sidewalls 160SL of the multiple second conductive lines 160 can be formed by using the pair of cover plates 164 as etching masks.

[0042] like Figure 4As shown, a pair of capping sheets 164 may include tapered portions 164P at their bottom (e.g., a portion near the substrate 110 in the Z direction). Portions of the upper sidewalls 160SU of the plurality of second conductive lines 160 that contact the tapered portions 164P may protrude outwards (e.g., along or complementary to the shape of the tapered portions 164P). In an embodiment, the second conductive layer 160L (see reference) is etched... Figure 12 In part of the process, the sidewall 160LH of the second conductive layer 160L (refer to...) Figure 12 ) and bottom 160LB (reference) Figure 12 It can be etched into a rounded shape and arranged on the cover liner 164L on the bottom 160LB (see reference). Figure 13 A portion of the material can be removed together with the second conductive layer 160L to form a tapered portion 164P on the bottom of the cover 164 remaining on the sidewall 160LH of the second conductive layer 160L.

[0043] In one embodiment, the third insulating layer 162 may fill the space between adjacent second conductive lines 160 among the plurality of second conductive lines 160, and may have a bottom surface (e.g., a surface facing the substrate 110) at a level lower than the bottom surfaces of the plurality of second conductive lines 160 (e.g., closer to the substrate 110 in a third-order direction than the bottom surfaces of the plurality of second conductive lines 160). In one embodiment, as... Figure 4 As shown, when the width of the bottom surface of the plurality of second conductive lines 160 is substantially the same as the width of the top surface of the third electrode 144, the third insulating layer 162 may surround a portion of the sidewall of the third electrode 144. In embodiments, as... Figure 6 As shown, the width of the top surface of the third electrode 144 may be narrower than or less than the width of the bottom surface of the plurality of second conductive lines 160. In this case, the sidewalls of the third electrode 144 may be surrounded by the second insulating layer 152, and the third electrode 144 may not be in direct contact with the third insulating layer 162.

[0044] The switching component 130 may include a first electrode 132, a switching material layer 134, and a second electrode 136. The switching material layer 134 may be a current regulating layer capable of controlling the flow of current. The switching material layer 134 may include a material layer having a resistance that varies according to the magnitude of the voltage between its two ends; for example, the switching material layer 134 may include a material layer with bidirectional threshold switching (OTS) characteristics. When a voltage smaller than the threshold voltage is applied to the switching material layer 134, the switching material layer 134 maintains a high-resistance state in which a small current flows, while when a voltage larger than the threshold voltage is applied to the switching material layer 134, the switching material layer 134 changes to a low-resistance state and current begins to flow. In an embodiment, when the current flowing through the switching material layer 134 becomes less than the holding current, the switching material layer 134 may change to a high-resistance state.

[0045] The switching material layer 134 may comprise a chalcogenide material as an OTS material layer. In embodiments, the switching material layer 134 may comprise, for example, silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), indium (In), or combinations thereof. In embodiments, the switching material layer 134 may comprise approximately 14% silicon (Si), approximately 39% tellurium (Te), approximately 37% arsenic (As), approximately 9% germanium (Ge), and / or approximately 1% indium (In). Here, percentages are atomic percentages where the total atomic composition is 100%, and the same applies below. In embodiments, the switching material layer 134 may comprise silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), or combinations thereof. In one embodiment, the switching material layer 134 may include about 5% concentration of silicon (Si), about 34% concentration of tellurium (Te), about 28% concentration of arsenic (As), about 11% concentration of germanium (Ge), about 21% concentration of sulfur (S), and / or about 1% concentration of selenium (Se). In another embodiment, the switching material layer 134 may include silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), sulfur (S), selenium (Se), antimony (Sb), or combinations thereof. In yet another embodiment, the switching material layer 134 may include about 21% concentration of tellurium (Te), about 10% concentration of arsenic, about 15% concentration of germanium (Ge), about 2% concentration of sulfur (S), about 50% concentration of selenium (Se), and / or about 2% concentration of antimony (Sb).

[0046] In some embodiments, the switching material layer 134 may include various types of material layers capable of selecting components. In some embodiments, the switching material layer 134 may include, for example, diodes, tunnel junctions, PNP diodes or bipolar junction transistors (BJTs), hybrid ion-electron conductors (MIECs), etc.

[0047] The first electrode 132 and the second electrode 136 can be layers serving as current paths and can be formed of a conductive material. In an embodiment, each of the first electrode 132 and the second electrode 136 can be formed of a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In an embodiment, each of the first electrode 132 and the second electrode 136 may include, for example, a TiN layer.

[0048] The variable resistance memory component 140 may include a variable resistance material layer 142 and a third electrode 144. In one embodiment, the variable resistance material layer 142 may include a phase change material that reversibly changes between an amorphous and a crystalline state based on heat (e.g., heating time). In another embodiment, the variable resistance material layer 142 may include a material having a phase that can be reversibly changed by Joule heating generated by a voltage applied to both ends of the variable resistance material layer 142 and having a resistance that can change due to the phase change. In another embodiment, the phase change material may be in a high-resistivity state in the amorphous phase and in a low-resistivity state in the crystalline phase. The high-resistivity state may be defined as "0" and the low-resistivity state may be defined as "1" to store data in the variable resistance material layer 142.

[0049] In embodiments, the variable resistance material layer 142 may include one or more elements from Group VI of the periodic table (chalcogenides) and selectively include one or more chemical modifiers from Groups III, IV, or V. In embodiments, the variable resistance material layer 142 may include, for example, Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, Ge1Sb4Te7, etc. In embodiments, the variable resistance material layer 142 may include, for example, Ge-Te, Sb-Te, In-Se, Ga-Sb, In-Sb, As-Te, Al-Te, Bi-Sb-Te, In-Sb-Te, Ge-Sb-Te, Te-Ge-As, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, In-Ge-Te, Ge-Sn-Te, Ge-Bi-Te, Ge-Te-Se, As-Sb-Te , Sn-Sb-Bi, Ge-Te-O, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pt, In-Sn-Sb-Te, As-Ge-Sb-Te or combinations thereof.

[0050] Each element forming the variable resistance material layer 142 can have various stoichiometry. The crystallization temperature, melting temperature, phase transition rate based on crystallization energy, and data retention characteristics of the variable resistance material layer 142 can be adjusted according to the stoichiometry of each element. In embodiments, the variable resistance material layer 142 may also include impurities, such as carbon (C), nitrogen (N), oxygen (O), bismuth (Bi), or tin (Sn). In embodiments, the variable resistance material layer 142 may also include metallic materials, such as aluminum (Al), gallium (Ga), zinc (Zn), titanium (Ti), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), ruthenium (Ru), palladium (Pd), hafnium (Hf), tantalum (Ta), iridium (Ir), platinum (Pt), zirconium (Zr), thallium (Tl), lead (Pb), or polonium (Po).

[0051] The variable resistance material layer 142 may have a multilayer structure in which two or more layers with different physical properties are stacked. Barrier layers preventing material diffusion between the multiple layers may be further arranged between the multiple layers. In one embodiment, the variable resistance material layer 142 may have a superlattice structure in which multiple layers comprising different types of materials are alternately stacked. In another embodiment, the variable resistance material layer 142 may have a structure in which a first layer formed of Ge-Te and a second layer formed of Sb-Te are alternately stacked. In another embodiment, both the first and second layers may comprise various types of materials as described above.

[0052] In one embodiment, the phase change material may be a variable resistance material layer 142. In another embodiment, the variable resistance material layer 142 may include various types of materials with resistance variation characteristics.

[0053] In an embodiment, when the variable resistive material layer 142 comprises a transition metal oxide, the memory device 100 may be a resistive random access memory (ReRAM). At least one electrical path can be created or eliminated in the variable resistive material layer 142 comprising the transition metal oxide through programming operations. When an electrical path is created, the variable resistive material layer 142 may have a low resistance value, while when an electrical path is eliminated, the variable resistive material layer 142 may have a high resistance value. The memory device 100 can store data by utilizing the difference between the resistance values ​​of the variable resistive material layer 142 as described above.

[0054] When the variable resistance material layer 142 is formed of a transition metal oxide, the transition metal oxide may include metals such as Ta, Zr, Ti, Hf, Mn, Y, Ni, Co, Zn, Nb, Cu, Fe, or Cr. In an embodiment, the transition metal oxide may be, for example, Ta₂O. 5-x ZrO2-x TiO 2-x HfO 2-x MnO 2-x Y2O 3-x NiO 1-y Nb2O 5-x CuO 1-y or Fe2O 3-x The material can be formed in a single layer or multiple layers. In the embodiment, x and y can be selected in the ranges of 0 ≤ x ≤ 1.5 and 0 ≤ y ≤ 0.5, respectively, in the material shown above.

[0055] In an embodiment, when the variable resistance material layer 142 has a magnetic tunnel junction (MTJ) structure including two electrodes formed of magnetic material and a dielectric between the two magnetic material electrodes, the memory device 100 may be a magnetic random access memory (MRAM).

[0056] The two electrodes can be a fixed magnetized layer and a free magnetized layer, respectively, and the dielectric between the fixed magnetized layer and the free magnetized layer can be a tunnel barrier layer. The fixed magnetized layer can have a magnetization direction fixed in one direction, while the free magnetized layer can have a magnetization direction that can be changed to be parallel or antiparallel to the magnetization direction of the fixed magnetized layer. In one embodiment, the magnetization directions of the fixed magnetized layer and the free magnetized layer can be parallel to one surface of the tunnel barrier layer. The magnetization directions of the fixed magnetized layer and the free magnetized layer can be perpendicular to one surface of the tunnel barrier layer.

[0057] When the magnetization direction of the free magnetization layer is parallel to the magnetization direction of the fixed magnetization layer, the variable resistivity material layer 142 can have a first resistance value. When the magnetization direction of the free magnetization layer is antiparallel to the magnetization direction of the fixed magnetization layer, the variable resistivity material layer 142 can have a second resistance value different from the first resistance value. The memory device 100 can store data by using the difference between the resistance values ​​described above. The magnetization direction of the free magnetization layer can be changed by the spin torque of electrons in the programming current.

[0058] The magnetization fixation layer and the magnetization free layer may include magnetic materials. In one embodiment, the magnetization fixation layer may further include an antiferromagnetic material that fixes the magnetization direction of the ferromagnetic material included in the magnetization fixation layer. In another embodiment, the tunnel barrier layer may be formed of oxides of, for example, Mg, Ti, Al, MgZn, or MgB.

[0059] The third electrode 144 may be a layer serving as a current path and may be formed of a conductive material. In embodiments, the third electrode 144 may be formed of a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In embodiments, the third electrode 144 may include a conductive material capable of generating sufficient heat to alter the phase of the variable resistance material layer 142. In embodiments, the third electrode 144 may be formed of a high-melting-point metal material, a nitride containing a high-melting-point metal material, or a carbon-based conductive material (e.g., TiN, TiSiN, TiAlN, TaSiN, TaAlN, TaN, WSi, WN, TiW, MoN, NbN, TiBN, ZrSiN, WSiN, WBN, ZrAlN, MoAlN, TiAl, TiON, TiAlON, WON, TaON, C, SiC, SiCN, CN, TiCN, TaCN, or a combination thereof). In embodiments, the third electrode 144 may include a conductive layer formed of a metal, a conductive metal nitride, or a conductive metal oxide, and at least one conductive barrier layer covering at least a portion of the conductive layer. In an embodiment, the conductive barrier layer may be formed of a metal oxide, a metal nitride, or a combination thereof.

[0060] In some cross-point type memory devices, multiple memory cells can be formed at the intersection of multiple bit lines and multiple word lines. During the process of etching a second conductive layer to form multiple bit lines, if the second conductive layer is not completely etched, tails may form at the bottom of the bit lines, or etching residues may adhere to the bottom of the bit lines, reducing the gap between the bit lines. Because etching residues adhere to the bottom of the bit lines, electrical short circuits may occur between adjacent cells, or the etching rate of the memory cells may decrease due to the reduced gap between the bit lines when patterning memory cells after patterning the bit lines. Furthermore, if the second conductive layer is over-etched to prevent tails as described above, the sidewall portions of the bit lines may be unintentionally etched or eroded instead of the exposed material beneath the bit lines, resulting in bowing of the second conductive layer. In this case, depressions may form in the sidewalls of the bit lines, and the bit line resistance may increase due to the reduced volume of the bit lines.

[0061] In the memory device 100 according to an embodiment, etching can be stopped before the second conductive layer 160L is completely etched. A pair of capping sheets 164 can be formed on the sidewalls 160LH of the second conductive layer 160L, and the second conductive layer 160L can be over-etched to form a plurality of second conductive lines 160. Therefore, while the second conductive layer 160L is being over-etched, the pair of capping sheets 164 can serve as a protective layer to prevent etching or erosion of the sidewalls 160LH of the second conductive layer 160L. Thus, the formation of undesirable erosion, bowing, or depressions on the sidewalls of the plurality of second conductive lines 160 can be reduced or prevented, and the sidewalls of the plurality of second conductive lines 160 can have a vertical or relatively flat profile. As a result, the etch rate reduction in subsequent patterning processes of the memory cells can be reduced or prevented, and the plurality of second conductive lines 160 can have relatively low resistance. Therefore, the memory device 100 can have high reliability.

[0062] Figure 5 This is a cross-sectional view showing a memory device 100A according to an example embodiment. Figure 5 Is with Figure 2 A sectional view of the portions corresponding to lines A1-A1' and A2-A2'. Figure 5 Zhongyu Figures 1 to 4 In the accompanying drawings, the same reference numerals indicate the same elements.

[0063] Reference Figure 5 The outer walls of a pair of cover plates 164, the lower sidewall of each of the plurality of second conductive lines 160, and the sidewall of each of the plurality of memory cell MCAs can be arranged in a straight line. The lower sidewalls of the plurality of second conductive lines 160 can be continuously connected to the sidewalls of the plurality of memory cell MCAs without kinks or step differences.

[0064] In one embodiment, the outer walls of a pair of cover sheets 164, the lower sidewall of each of the plurality of second conductive lines 160, and the sidewall of each of the plurality of memory cell MCAs can be tilted at a predetermined tilt angle. In another embodiment, the outer walls of the pair of cover sheets 164 and the lower sidewalls of the plurality of second conductive lines 160 can be substantially vertical, while the sidewalls of the plurality of memory cell MCAs can be tilted at a predetermined tilt angle. In another embodiment, the width of the plurality of memory cell MCAs can increase downwards such that the width of the bottom surface of the plurality of memory cell MCAs (e.g., the width in the X direction) is greater than the width of its top surface. In another embodiment, the two sidewalls of the plurality of second conductive lines 160 and the sidewalls of the plurality of memory cell MCAs can be covered by a third insulating layer 162A.

[0065] In an embodiment, the third insulating layer 162A may have a top surface at the same level as the top surfaces of the plurality of second conductive lines 160 (e.g., a top surface at the same distance from the substrate 110 as the top surfaces of the plurality of second conductive lines 160 in the Z direction, or a top surface coplanar with the top surfaces of the plurality of second conductive lines 160), and may have a bottom surface on the top surfaces of the plurality of first conductive lines 120. The two sidewalls of each of the plurality of memory cells MCAs spaced apart from each other in the second direction (Y direction) may be covered by the second insulating layer 152, and the two sidewalls of each of the plurality of memory cells MCAs spaced apart from each other in the first direction (X direction) may be covered by the third insulating layer 162A.

[0066] In the manufacturing process according to the embodiment, the memory cell stack MCS (refer to) can be patterned by using a linear mask pattern as an etching mask. Figure 18 To form the memory cell pattern MCP (refer to) Figure 19 A portion of the second conductive layer 160L on the memory cell pattern MCP can be etched to form a cover 164, and the second conductive layer 160L can be etched again to form a plurality of second conductive lines 160. Thereafter, portions of the memory cell pattern MCP exposed through the spaces between the plurality of second conductive lines 160 can be etched to form a plurality of memory cells MCA. A third insulating layer 162A can be formed to fill the spaces between adjacent second conductive lines 160 and between adjacent memory cells MCA.

[0067] In some manufacturing processes of cross-point type memory devices, a memory cell stack MCS can be patterned using a linear mask extending in a first direction (X direction) to first form a memory cell pattern MCP. A second conductive layer 160L can be patterned using a linear mask extending in a second direction (Y direction) to form bit lines. The memory cell pattern MCP can then be patterned to form a memory cell MCA. When the second conductive layer 160L is not completely etched, tails may form at the bottom of the bit lines, or etching residues may adhere to the bottom of the bit lines, thereby reducing the gap between the bit lines. The etching rate of the memory cell pattern MCP can be reduced by decreasing the gap between the bit lines. Over-etching the second conductive layer 160L can prevent tails from forming. However, in an over-etching process, the etchant used to etch the second conductive layer 160L may unintentionally etch the sidewall portions of the second conductive layer 160L instead of etching the exposed material beneath the second conductive layer 160L (e.g., the carbon-based electrode material forming the third electrode 144), thus potentially causing bowing of the second conductive layer 160L. In this case, a dent may form in the sidewall of the bit line, and the bit line resistance may increase due to the reduced volume of the bit line.

[0068] However, in the memory device 100A according to the embodiment described above, etching can be stopped before the second conductive layer 160L is completely etched. A capping liner 164 can be formed on the sidewalls 160LH and bottom 160LB of the second conductive layer 160L, and then the second conductive layer 160L can be over-etched to form a plurality of second conductive lines 160. Therefore, while the second conductive layer 160L is being over-etched, a pair of capping liners 164 can serve as a protective layer to prevent etching or erosion of the sidewalls 160LH of the second conductive layer 160L. As a result, undesirable erosion, bowing, or depression formation of the sidewalls of the plurality of second conductive lines 160 can be reduced or prevented, and the sidewalls of the plurality of second conductive lines 160 can have a vertical or relatively flat profile. Therefore, a reduction in the etching rate during the patterning process of the memory cell pattern MCP can be reduced or prevented, and the plurality of second conductive lines 160 can have relatively low resistance. Therefore, the memory device 100A can have high reliability.

[0069] Figure 6 This is a cross-sectional view showing a memory device 100B according to an example embodiment. Figure 6 Is with Figure 2 A sectional view of the portions corresponding to lines A1-A1' and A2-A2'. Figure 6 Zhongyu Figures 1 to 5 In the accompanying drawings, the same reference numerals indicate the same elements.

[0070] Reference Figure 6Each of the plurality of memory cells (MCBs) may include a switching element 130 and a variable resistor memory element 140 formed by an inlay method. For example, the switching element 130 may be surrounded by a lower mold layer 152L, and the width of the top surface of the switching element 130 may be slightly larger than the width of the bottom surface of the switching element 130. Similarly, the variable resistor memory element 140 may be surrounded by an upper mold layer 152B, and the width of the top surface of the variable resistor memory element 140 may be slightly larger than the width of the bottom surface of the variable resistor memory element 140.

[0071] In the manufacturing process according to the embodiment, a lower mold layer 152L having multiple holes can be formed. A first electrode 132, a switching material layer 134, and a second electrode 136 can be sequentially filled into the lower mold layer 152L. Unwanted material layers remaining on the top surface of the lower mold layer 152L can be removed by a chemical mechanical polishing (CMP) process or the like to form a switching component 130. Similarly, an upper mold layer 152B having multiple holes can be formed. A variable resistance material layer 142 and a third electrode 144 can be sequentially filled into the upper mold layer 152B. Unwanted material layers remaining on the top surface of the upper mold layer 152B can be removed by a CMP process or the like to form a variable resistance memory component 140.

[0072] The third insulating layer 162B may have a bottom surface at a level lower than the bottom surface of the plurality of second conductive lines 160, and the bottom surface and lower sidewalls of the third insulating layer 162B may be surrounded by the upper mold layer 152B. This may be because the second conductive layer 160L (refer to) can be executed during the patterning process of the plurality of second conductive lines 160. Figure 11 The upper part of the upper mold layer 152B can be removed together at a predetermined height, and the third insulating layer 162B can fill the space.

[0073] In one embodiment, the width (width in the X direction) of the top surface of the variable resistance memory component 140 (e.g., the surface facing away from the substrate 110 in the Z direction) can be smaller than the width (width in the X direction) of the bottom surface of the plurality of second conductive lines 160, and the top surface of the variable resistance memory component 140 can be completely covered by the plurality of second conductive lines 160. In another embodiment, the variable resistance memory component 140 may not contact the third insulating layer 162B. As a result, in the second conductive layer 160L (refer to...) Figure 11 In the over-etching process, the top surface or sidewall of the variable resistor memory component 140 can be covered by the upper mold layer 152B and not exposed to the etching environment, thus preventing damage or deterioration of the variable resistor material layer 142.

[0074] Figure 7This is a layout diagram showing a memory device 200 according to an example embodiment. Figure 8 Is with Figure 2 The sectional views corresponding to lines A1-A1' and A2-A2'. Figure 7 and Figure 8 Zhongyu Figures 1 to 6 In the accompanying drawings, the same reference numerals indicate the same elements.

[0075] Reference Figure 7 and Figure 8 The memory device 200 may include a first memory cell block BLK1 and a second memory cell block BLK2 on a substrate 110. The substrate 110 may include a first memory cell region MCR1, a second memory cell region MCR2, and a peripheral region PR. The first memory cell block BLK1 may be on the first memory cell region MCR1, and the second memory cell block BLK2 may be on the second memory cell region MCR2. Each of the first memory cell block BLK1 and the second memory cell block BLK2 may include a reference from... Figures 1 to 6 At least one of the described memory devices 100, 100A and 100B.

[0076] The memory device 200 may include a plurality of first conductive lines 120 extending in a first direction (X direction) (a plurality of first conductive lines 120 corresponding to a plurality of first word lines WLA), a plurality of second conductive lines 160 extending in a second direction (Y direction) (a plurality of second conductive lines 160 corresponding to a plurality of bit lines BL), and a plurality of third conductive lines 260 extending in the first direction (X direction) (a plurality of third conductive lines 260 corresponding to a plurality of second word lines WLB).

[0077] Multiple first conductive lines 120 and multiple second conductive lines 160 can have the same characteristics as referenced. Figures 2 to 6 The characteristics described are similar. Specifically, a pair of cover plates 164 can be arranged on the upper sidewall 160SU of each of the plurality of second conductive lines 160 (refer to...). Figure 4 )superior.

[0078] like Figure 8 As shown, a pair of cover plates 264 can be disposed on two sidewalls of each of the plurality of third conductive lines 260. The pair of cover plates 264 on the two sidewalls of each of the plurality of third conductive lines 260 can have similar characteristics to the pair of cover plates 164 on the two sidewalls of each of the plurality of second conductive lines 160. In an embodiment, the plurality of third conductive lines 260 and the pair of cover plates 264 can be formed by a method similar to that used to form the plurality of second conductive lines 160 and the pair of cover plates 164.

[0079] Multiple memory cells MC1 can be located between multiple first conductive lines 120 and multiple second conductive lines 160, and multiple memory cells MC2 can be located between multiple second conductive lines 160 and multiple third conductive lines 260. The multiple second conductive lines 160 can be used as common bit lines for both the multiple memory cells MC1 and the multiple memory cells MC2.

[0080] Each of the plurality of memory cells MC2 may include a switching component 230 and a variable-resistance memory component 240. The switching component 230 may include a first electrode 232, a switching material layer 234, and a second electrode 236; the variable-resistance memory component 240 may include a variable-resistance material layer 242 and a third electrode 244. The plurality of memory cells MC1 and MC2 may have the same characteristics as referenced... Figures 1 to 4 The description describes multiple memory cells (MCs) with similar characteristics.

[0081] Additionally, multiple memory cells MC2 may be surrounded by a fourth insulating layer 252, and the space between adjacent third conductive lines 260 may be filled with a fifth insulating layer 262. The fifth insulating layer 262 may have a bottom surface at a level lower than the bottom surface of the multiple third conductive lines 260.

[0082] like Figure 7 As shown, the first contact CO1 can be on multiple third conductive lines 260 of the first memory cell block BLK1, and the second contact CO2 can be on multiple third conductive lines 260 of the second memory cell block BLK2. Additionally, the first memory cell block BLK1 and the second memory cell block BLK2 can share multiple second conductive lines 160, and the third contact CO3 can be on multiple second conductive lines 160.

[0083] In the implementation method, such as Figure 8 As shown, multiple second conductive lines 160 can be used as common bit lines for both multiple memory cells MC1 and multiple memory cells MC2. In an embodiment, multiple additional conductive lines can be further formed between the multiple second conductive lines 160 and the multiple memory cells MC2 to serve as bit lines connecting the multiple memory cells MC2, and a pair of capping sheets may or may not be formed on the two sidewalls of each of the multiple additional conductive lines.

[0084] In the implementation method, such as Figure 8 The diagram illustrates two stacked layers in which multiple memory cells MC1 and multiple memory cells MC2 can be vertically stacked. In an embodiment, one or more memory cell components, including additional word lines, additional memory cells, and additional bit lines, may be further formed above the multiple memory cells MC2.

[0085] Figures 9 to 17 This is a cross-sectional view of a stage in a method of manufacturing a memory device 100 according to an example embodiment.

[0086] Reference Figure 9 A lower insulating layer 112 can be formed on the substrate 110. A first conductive layer can be formed on the lower insulating layer 112 and patterned to form a plurality of first conductive lines 120. Subsequently, an insulating layer can be formed on the plurality of first conductive lines 120 and the lower insulating layer 112, and the upper part of the insulating layer can be planarized to expose the top surface of the plurality of first conductive lines 120 to form a first insulating layer 122.

[0087] In one embodiment, a hard mask can be formed by a dual patterning method to form multiple first conductive lines 120, and multiple first conductive lines 120 can be patterned by using a hard mask.

[0088] Subsequently, a memory cell stack (MCS) comprising a first electrode material layer 132L, a preliminary switch material layer 134L, a second electrode material layer 136L, a preliminary variable resistor material layer 142L, and a third electrode material layer 144L can be formed on multiple first conductive lines 120.

[0089] Reference Figure 10 The memory cell stack (MCS) can be patterned to form a switching component 130 including a first electrode 132, a switching material layer 134, and a second electrode 136, as well as a variable resistance memory component 140 including a variable resistance material layer 142 and a third electrode 144.

[0090] In one embodiment, an island-type mask layer can be formed on the memory cell stack MCS, and the mask layer can be used as an etching mask to pattern the memory cell stack MCS to form the switching component 130 and the variable resistance memory component 140.

[0091] In one embodiment, a first electrode material layer 132L, a preliminary switch material layer 134L, and a second electrode material layer 136L can first be formed and patterned to form a switch component 130. Then, a preliminary variable resistance material layer 142L and a third electrode material layer 144L can be formed and patterned to form a variable resistance memory component 140.

[0092] In one embodiment, a memory cell stack (MCS) can be formed. First, a preliminary variable resistance material layer 142L and a third electrode material layer 144L can be patterned to initially form a variable resistance memory component 140. Then, a first electrode material layer 132L, a preliminary switching material layer 134L, and a second electrode material layer 136L can be patterned to form a switching component 130. In another embodiment, prior to forming the switching component 130, a process for forming a liner on the sidewalls of the variable resistance memory component 140 can be further performed.

[0093] In one implementation, a memory cell stack MCS can be formed and the memory cell stack MCS can be patterned first using a first linear mask that extends longitudinally in a second direction (Y direction), and then the memory cell stack MCS can be patterned to have multiple island shapes using a second linear mask that extends longitudinally in a first direction (X direction).

[0094] Subsequently, insulating material can be formed on the switching component 130 and the variable resistor memory component 140, and the upper part of the insulating material can be planarized or etched back to expose the top surface of the variable resistor memory component 140 to form a second insulating layer 152.

[0095] Reference Figure 11 A second conductive layer 160L can be formed on the second insulating layer 152. In an embodiment, the second conductive layer 160L can be formed in the Z direction with a first height h11 of, for example, about 30 nm to about 150 nm (see reference). Figure 4 ).

[0096] Subsequently, a lower layer 310 and a mask pattern 320 can be formed on the second conductive layer 160L. The lower layer 310 and the mask pattern 320 can have a linear shape extending in a second direction (Y direction). The mask pattern 320 can have a hole 320H, and the top surface of the second conductive layer 160L can be exposed by the hole 320H.

[0097] Reference Figure 12 A mask pattern 320 can be used as an etching mask to remove a predetermined height of the second conductive layer 160L exposed by the hole 320H. Because the predetermined height of the second conductive layer 160L is removed, the sidewalls 160LH and bottom 160LB of the second conductive layer 160L below the hole 320H can be exposed.

[0098] In an embodiment, the etching height of the second conductive layer 160L can be approximately 40% to approximately 90% of the first height h11 of the second conductive layer 160L. The etching height of the second conductive layer 160L can be determined based on the etching profile of the second conductive layer 160L; for example, the sidewalls 160LH of the second conductive layer 160L can be determined with a height having a vertical sidewall profile. In an embodiment, such as... Figure 12 As shown, the boundary between the bottom 160LB and the sidewall 160LH of the second conductive layer 160L can be rounded or curved.

[0099] Reference Figure 13 A cover layer 164L can be formed on the mask pattern 320 and the bottom 160LB and sidewall 160LH of the second conductive layer 160L.

[0100] In one embodiment, the capping layer 164L can be formed using an ALD or CVD process, for example, silicon oxide, silicon nitride, silicon carbide, silicon carbide, or silicon. In another embodiment, the capping layer 164L can be formed with a first thickness w12 of about 1 nm to about 4 nm (see reference). Figure 4 It can be conformally formed on the inner wall of the hole 320H and on the bottom 160LB and sidewall 160LH of the second conductive layer 160L.

[0101] Reference Figure 14 An anisotropic etching process can be performed on the cover 164L to remove the cover 164L from the bottom 160LB of the second conductive layer 160L and the top surface of the mask pattern 320, leaving a pair of cover 164 on the sidewall of each of the holes 320H and the sidewall 160LH of the second conductive layer 160L.

[0102] Reference Figure 15 The bottom 160LB of the second conductive layer 160L exposed by the hole 320H can be removed using a mask pattern 320 and a pair of cover plates 164 as an etching mask to form multiple second conductive lines 160.

[0103] In one embodiment, a portion of the upper part of the second insulating layer 152 can be removed together with the process of removing the bottom 160LB of the second conductive layer 160L. The level of the top surface of the second insulating layer 152 exposed at the bottom of the hole 320H can be lower than the level of the bottom surface of the second conductive layer 160L. Therefore, each of the plurality of second conductive lines 160 can be completely separated from the adjacent second conductive lines 160, and sufficient spacing between the plurality of second conductive lines 160 can be ensured.

[0104] In the process of removing the bottom 160LB of the second conductive layer 160L, a pair of capping sheets 164 may cover the upper part of the sidewalls 160LH of the second conductive layer 160L to help prevent undesirable etching, erosion, or bowing of the sidewalls 160LH of the second conductive layer 160L. Therefore, the multiple second conductive lines 160 may have substantially vertical or flat sidewall profiles.

[0105] Reference Figure 16 A third insulating layer 162 can be formed on multiple second conductive lines 160 and mask pattern 320. The third insulating layer 162 can fill the interior of the hole 320H and contact the sidewalls of a pair of caps 164.

[0106] Reference Figure 17 This allows the upper part of the third insulating layer 162 to be planarized, exposing the top surfaces of the multiple second conductive lines 160. In this case, the mask pattern 320 and the lower layer 310 can also be removed together.

[0107] As a result, memory device 100 can be manufactured.

[0108] According to the method for manufacturing the memory device 100 described above, etching can be stopped before the second conductive layer 160L is completely etched. A pair of capping sheets 164 can be formed on the sidewalls 160LH of the second conductive layer 160L, and then the second conductive layer 160L can be over-etched to form a plurality of second conductive lines 160. While the second conductive layer 160L is being over-etched, the pair of capping sheets 164 can act as a protective layer to prevent etching or erosion of the sidewalls of the second conductive layer 160L. Therefore, the formation of undesirable erosion, bowing, or depressions on the sidewalls of the plurality of second conductive lines 160 can be reduced or prevented, and the sidewalls of the plurality of second conductive lines 160 can have a vertical or relatively flat profile. As a result, the reduction in etching rate in subsequent patterning processes of the memory cell MC can be reduced or prevented, and the plurality of second conductive lines 160 can have relatively low resistance. Therefore, the memory device 100 can have high reliability.

[0109] Figures 18 to 26 This is a cross-sectional view of a stage in a method for manufacturing a memory device 100A according to an example embodiment.

[0110] Reference Figure 18 , can execute reference Figure 9 The described process is used to form multiple first conductive lines 120 and memory cell stacks (MCS).

[0111] Reference Figure 19A linear mask pattern extending in a first direction (X direction) can be formed on the memory cell stack MCS. The linear mask pattern can be used to pattern the memory cell stack MCS to form a memory cell pattern MCP extending in the first direction (X direction). The memory cell pattern MCP may include a first electrode pattern 132P, a switching material layer pattern 134P, a second electrode pattern 136P, a variable resistor material layer pattern 142P, and a third electrode pattern 144P, each extending in the first direction (X direction).

[0112] Subsequently, the spaces between the memory cell patterns (MCPs) can be filled with an insulating material, and then the insulating material can be planarized to expose the top surface of the memory cell patterns (MCPs) to form a second insulating layer 152. Here, the linear mask pattern can also be removed together.

[0113] Reference Figure 20 A second conductive layer 160L can be formed on the memory cell pattern MCP and the second insulating layer 152. Subsequently, a lower layer 310 having a linear shape and extending in a second direction (Y direction) and a mask pattern 320 can be formed on the second conductive layer 160L. The mask pattern 320 may have a hole 320H, and the top surface of the second conductive layer 160L may be exposed by the hole 320H.

[0114] Reference Figure 21 A mask pattern 320 can be used as an etching mask to remove a predetermined height of the second conductive layer 160L exposed by the hole 320H. Because the predetermined height of the second conductive layer 160L is removed, the sidewalls 160LH and bottom 160LB of the second conductive layer 160L below the hole 320H can be exposed.

[0115] Reference Figure 22 A capping layer 164L can be formed on the mask pattern 320 and the bottom 160LB and sidewall 160LH of the second conductive layer 160L. The capping layer 164L can be conformally formed on the inner wall of the hole 320H and the bottom 160LB and sidewall 160LH of the second conductive layer 160L.

[0116] Reference Figure 23 An anisotropic etching process can be performed on the cover 164L to remove the cover 164L disposed on the bottom 160LB of the second conductive layer 160L and the top surface of the mask pattern 320, leaving a pair of cover 164s on the sidewall of the hole 320H and the sidewall 160LH of the second conductive layer 160L.

[0117] Subsequently, a mask pattern 320 and a pair of capping sheets 164 can be used as an etching mask to remove the bottom 160LB of the second conductive layer 160L exposed by the hole 320H to form multiple second conductive lines 160.

[0118] In an embodiment, during the process of removing the bottom 160LB of the second conductive layer 160L to form a plurality of second conductive lines 160, a pair of capping sheets 164 may cover the upper portion of the sidewalls 160LH of the second conductive layer 160L to help prevent undesirable etching, erosion, or bowing of the sidewalls 160LH of the second conductive layer 160L. Therefore, the plurality of second conductive lines 160 may have substantially vertical or flat sidewall profiles, and sufficient spacing between the plurality of second conductive lines 160 can be ensured.

[0119] Reference Figure 24 The memory cell pattern MCP can be patterned using a mask pattern 320 and a pair of cover plates 164 as etching masks to sequentially form the variable resistance memory component 140 and the switching component 130.

[0120] In this embodiment, the sidewalls of the variable resistor memory component 140 and the switch component 130 can be tilted at a preset tilt angle.

[0121] Reference Figure 25 A third insulating layer 162A can be formed on the switching component 130, the variable resistor memory component 140, the multiple second conductive lines 160, and the mask pattern 320. The third insulating layer 162A can fill the interior of the hole 320H, contact the top surface of the multiple first conductive lines 120 exposed at the bottom of the hole 320H, and contact the sidewalls of a pair of cover plates 164.

[0122] Reference Figure 26 This process can planarize the upper part of the third insulating layer 162A, exposing the top surfaces of the multiple second conductive lines 160. In this process, the mask pattern 320 and the lower layer 310 can also be removed together.

[0123] As a result, a memory device 100A can be formed.

[0124] According to the method for manufacturing memory device 100A described above, while the second conductive layer 160L is being over-etched, a pair of capping sheets 164 can serve as a protective layer to help prevent etching or erosion of the sidewalls of the second conductive layer 160L. Therefore, undesirable erosion, bowing, or depression formation of the sidewalls of the plurality of second conductive lines 160 can be reduced or prevented, and the sidewalls of the plurality of second conductive lines 160 can have a vertical or relatively flat profile. As a result, the reduction in etching rate during the patterning process of the memory cell pattern MCP can be reduced or prevented, and the plurality of second conductive lines 160 can have relatively low resistance. Therefore, memory device 100A can have high reliability.

[0125] Through summarization and review, it was found that when there are defects in the patterning process of conductive lines in the manufacturing process of cross-point structures, the resistance of the conductive lines may increase, and therefore there may be changes in the electrical performance between cells of the memory device or the reliability of the memory device may be degraded.

[0126] One or more embodiments may provide a memory device having a cross-point array structure.

[0127] One or more embodiments may provide a crosspoint type memory device capable of ensuring stable operation of memory cells by preventing undesirable patterning or bowing of conductive lines in the patterning process of the crosspoint array.

[0128] One or more embodiments may provide a method for manufacturing a cross-point type memory device that prevents poor patterning or bowing of conductive lines during the patterning process of the cross-point array.

[0129] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with specific embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated at the time of filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A memory device, the memory device comprising: Multiple first conductive lines are arranged on the substrate and spaced apart from each other in a first direction parallel to the top surface of the substrate; Multiple cover plates are located on the sidewall of each of the plurality of first conductive lines, the plurality of cover plates having a top surface at a vertical level equal to the vertical level of the top surface of the plurality of first conductive lines and a bottom surface at a vertical level higher than the bottom surface of the plurality of first conductive lines. An insulating layer, located on a substrate, fills the space between the plurality of first conductive lines and covers the sidewalls of the plurality of cappings; as well as A plurality of memory cells, each of which includes an electrode in contact with a corresponding first conductive line, located at a vertical level lower than the plurality of first conductive lines.

2. The memory device according to claim 1, wherein: The upper part of the insulating layer contacts the sidewalls of the plurality of cover sheets, and The lower part of the insulating layer contacts the sidewall of the plurality of first conductive lines.

3. The memory device according to claim 1, wherein, The insulating layer has a top surface at a vertical level equal to the vertical level of the top surface of the plurality of first conductive lines and a bottom surface at a vertical level lower than the bottom surface of the plurality of first conductive lines.

4. The memory device according to claim 1, wherein, The sidewalls of the plurality of cover sheets are aligned with the sidewalls of the plurality of first conductive lines to form a straight line with the sidewalls of the plurality of first conductive lines.

5. The memory device according to claim 1, further comprising: Multiple second conductive lines are arranged on the substrate and spaced apart from each other in a second direction parallel to the top surface of the substrate at a vertical level lower than the multiple first conductive lines. The plurality of memory cells are respectively arranged between the plurality of first conductive lines and the plurality of second conductive lines.

6. The memory device according to claim 5, wherein, Each of the plurality of memory units includes: Switching components, including bidirectional threshold switching materials; and Memory components, including variable resistance materials, In each of the plurality of memory cells, the electrode in contact with the corresponding first conductive line is an electrode of a switching component or a memory component.

7. A memory device, the memory device comprising: Multiple first conductive lines are located on the substrate and spaced apart from each other in a first direction parallel to the top surface of the substrate; Multiple second conductive lines are located on the substrate and are spaced apart from each other in a second direction parallel to the top surface of the substrate at a vertical level lower than the multiple first conductive lines. Multiple memory cells are respectively arranged between the multiple first conductive lines and the multiple second conductive lines; as well as Multiple cover plates are located on the sidewall of each of the plurality of first conductive lines, the plurality of cover plates having a top surface at a vertical level equal to the top surface of the plurality of first conductive lines and a bottom surface at a vertical level higher than the bottom surface of the plurality of first conductive lines. Each of the plurality of memory cells includes an electrode in contact with a corresponding first conductive line.

8. The memory device according to claim 7, wherein, The lower sidewalls of the plurality of first conductive lines are not covered by the plurality of capping sheets.

9. The memory device according to claim 7, wherein: The plurality of first conductive lines each have a first height in a third direction perpendicular to the top surface of the substrate. The plurality of covers all have a second height in a third direction, and The second height is 40% to 90% of the first height.

10. The memory device according to claim 9, wherein: The first height is 30nm to 150nm, and Each of the multiple cover sheets has a thickness of 1 nm to 4 nm.

11. The memory device according to claim 7, wherein: The plurality of first conductive lines each have a first height in a third direction perpendicular to the top surface of the substrate, and each have a first width in the first direction. The ratio of the first height to the first width is 0.5 to 5.

12. The memory device of claim 7, further comprising: An insulating layer fills the space between the plurality of first conductive lines and has a top surface at a vertical level equal to the vertical level of the top surface of the plurality of first conductive lines and a bottom surface at a vertical level lower than the bottom surface of the plurality of first conductive lines.

13. The memory device according to claim 12, wherein: The upper part of the insulating layer contacts the sidewalls of the plurality of cover sheets, and The lower part of the insulating layer contacts the sidewall of the plurality of first conductive lines.

14. A memory device, the memory device comprising: Multiple first conductive lines are located on the substrate and spaced apart from each other in a first direction parallel to the top surface of the substrate; Multiple second conductive lines are located on the substrate and are spaced apart from each other in a second direction parallel to the top surface of the substrate at a vertical level lower than the multiple first conductive lines. Multiple first memory cells are respectively located between the multiple first conductive lines and the multiple second conductive lines; Multiple first cover plates are located on the upper sidewall of each of the multiple first conductive lines; as well as An insulating layer, located on the substrate, fills the space between the plurality of first conductive lines. The upper sidewalls of the plurality of first conductive wires are covered by the plurality of first cover plates, and the lower sidewalls of the plurality of first conductive wires are covered by an insulating layer. Each of the plurality of first memory cells includes an electrode in contact with a corresponding first conductive line.

15. The memory device according to claim 14, wherein, The insulating layer has a top surface at a vertical level equal to the vertical level of the top surface of the plurality of first conductive lines and a bottom surface at a vertical level lower than the bottom surface of the plurality of first conductive lines.

16. The memory device according to claim 14, wherein, The lower sidewalls of the plurality of first conductive lines are not covered by the plurality of first cover plates.

17. The memory device of claim 14, further comprising: Multiple third conductive lines are located on the substrate and are spaced apart from each other in a second direction at a vertical horizontal height higher than the multiple first conductive lines; Multiple second memory cells are respectively located between the multiple first conductive lines and the multiple third conductive lines; as well as Multiple second cover plates are located on the upper sidewall of each of the multiple third conductive lines.

18. The memory device of claim 17, further comprising: An insulating layer, located on a substrate, fills the space between the plurality of third conductive lines and has a top surface at a vertical level equal to the top surface of the plurality of third conductive lines and a bottom surface at a vertical level lower than the bottom surface of the plurality of third conductive lines.

19. The memory device according to claim 17, wherein: Each of the plurality of first memory cells and the plurality of second memory cells includes a switching component and a memory component arranged upwards on a third side perpendicular to the top surface of the substrate. The switching component includes a first electrode, a switching material layer comprising a bidirectional threshold switching material, and a second electrode. The memory component includes a variable resistance material layer and a third electrode, and In each of the plurality of first memory cells, the electrode in contact with the corresponding first conductive line is the third electrode of the memory component.

20. The memory device of claim 14, wherein: The bottoms of the plurality of first covers are tapered, and The sidewalls of the plurality of first cover sheets are aligned with the lower sidewalls of the plurality of first conductive lines.

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