Semiconductor device and method for manufacturing a semiconductor wafer

Abstract

Semiconductor devices and methods for fabricating semiconductor wafers are disclosed. In embodiments, a method for fabricating a semiconductor wafer includes epitaxially growing a III-V semiconductor on a first surface of a hetero wafer having a thickness t w , the first surface capable of supporting epitaxial growth of at least one III-V semiconductor layer, the wafer having a second surface opposite the first surface; removing portions of the III-V semiconductor to create a plurality of mesas comprising the III-V semiconductor disposed on the first surface of the wafer; applying an insulating layer to regions of the wafer disposed between the mesas; and gradually removing portions of the second surface of the wafer, exposing the insulating layer in regions adjacent to the mesas and creating a processed second surface.

Description

BACKGROUND OF THE INVENTION

[0001] To date, transistors used in power electronics applications have typically been fabricated using silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated gate bipolar transistors (IGBTs). More recently, silicon carbide (SiC) power devices have been considered. Group-III-N semiconductor devices such as gallium nitride (GaN) devices are now emerging as attractive candidates for carrying large currents, supporting high voltages, and providing very low on-resistance and fast switching times. However, further improvements are desirable. SUMMARY OF THE INVENTION

[0002] According to the present invention, a method for fabricating a semiconductor wafer includes: epitaxially growing a Group-III-V semiconductor on a first surface of a heterogeneous wafer having a thickness t ,

[0006] ,

[0005] ,

[0004] , w , , where the first surface is capable of supporting epitaxial growth of at least one Group-III-V semiconductor layer, the wafer having a second surface opposite the first surface; removing portions of the Group-III-V semiconductor to create a plurality of mesa structures including the Group-III-V semiconductor disposed on the first surface of the heterogeneous wafer; applying an insulating layer to regions of the heterogeneous wafer disposed between the mesa structures; and gradually removing portions of the second surface of the heterogeneous wafer to expose the insulating layer in regions adjacent to the mesa structures and create a processed second surface.

[0003] In some embodiments, the method further includes removing portions of the first surface of the heterogeneous wafer to form a processed first surface in regions laterally adjacent to the mesa structures and to form an interface extending across the width of the mesa structures between the first surface of the heterogeneous wafer and the Group-III-V semiconductor structure.

[0004] In some embodiments, gradually removing portions of the second surface of the heterogeneous wafer includes reducing the thickness t w of the heterogeneous wafer under the mesa structures to a thickness t, where t ≤ 20 μm, or t ≤ 2 μm or t ≤ 1 μm. In some embodiments, t = 0. In some embodiments, 0 μm < t ≤ 20 μm, or 0 μm < t ≤ 2 μm or 0 μm < t ≤ 1 μm.

[0005] In some embodiments, removing portions of the second surface of the wafer includes at least one of the group consisting of grinding the second surface of the wafer, polishing the second surface of the wafer, chemically mechanically polishing the second surface of the wafer, and etching the second surface of the wafer.

[0006] In some embodiments, applying the insulating layer includes: depositing the insulating layer onto the area between the countertop and the countertop, such that the insulating layer has a thickness at least as large as the height of the countertop and the countertop is covered by the insulating layer; and planarizing the insulating layer to form a planarized surface including the upper surface of the countertop and the upper surface of the insulating layer.

[0007] In some embodiments, the method further includes: forming a structured mask on an insulating layer, the structured mask having an opening above a mesa having a lateral area smaller than the lateral area of ​​the mesa; removing a portion of the insulating layer within the opening and reducing the thickness of the portion of the insulating layer disposed above the mesa; and gradually removing portions of the mask and the insulating layer to produce a planarized surface including an upper surface of the mesa and an upper surface of the insulating layer.

[0008] In some embodiments, the method further includes forming a stop layer on a region of the wafer disposed between mesa, and optionally forming a stop layer on a side of the mesa, and removing a portion of the second surface of the wafer includes the stop layer exposed in a region adjacent to the mesa.

[0009] In some embodiments, the stop layer comprises carbon or amorphous hydrogenated carbon.

[0010] In some embodiments, the method further includes forming a cavity that is laterally adjacent to the side of the tabletop.

[0011] In some embodiments, the method further includes forming a metallization structure on a III-V semiconductor, the metallization structure providing a source, gate, and drain for a transistor structure.

[0012] In some embodiments, the metallization structure includes source fingers, gate fingers, and drain fingers disposed on the top surface of each mesa. Each mesa may provide a discrete transistor device. Each of the source fingers, gate fingers, and drain fingers may include one or more metal layers, and each may have an elongated shape, such as a strip. The source fingers, gate fingers, and drain fingers may extend substantially parallel to each other.

[0013] In some embodiments, the metallization structure further includes a source bus, a drain bus, and a gate bus or gate channel, wherein the source bus electrically couples a first source finger disposed on a first mesa with a second source finger disposed on a second mesa, the drain bus electrically couples a first drain finger disposed on a first mesa with a second drain finger disposed on a second mesa, and the gate bus or gate channel electrically couples a first gate finger disposed on a first mesa with a second gate finger disposed on a second mesa.

[0014] Two or more mesa are electrically coupled together via a source bus, a drain bus, and a gate bus to form a single transistor device. In some embodiments, the source bus, drain bus, and gate bus are at least partially disposed on an insulating layer.

[0015] In some embodiments, more than one source finger and / or more than one drain finger and / or more than one gate finger may be arranged on each mesa. For example, the fingers on a single mesa may have a mirror-symmetrical arrangement of source, gate, drain, gate, source or drain, gate, source, gate, drain.

[0016] In some embodiments, the metallization structure includes: gate fingers and drain fingers disposed on each mesa; a drain bus electrically coupling a first drain finger disposed on a first mesa to a second drain finger disposed on a second mesa, the drain bus being arranged at least partially on an insulating layer to be laterally adjacent to the first and second mesa; and a gate bus electrically coupling a first gate finger disposed on a first mesa to a second gate finger disposed on a second mesa, the gate bus being arranged at least partially on an insulating layer to be laterally adjacent to the first and second mesa.

[0017] In some embodiments, the drain bus is arranged on a first side laterally adjacent to the first mesa and the second mesa, and the gate bus is arranged on a second side laterally adjacent to the first mesa and the second mesa, the second side being opposite to the first side.

[0018] In some embodiments, the metallized structure further includes at least one source via in an insulating layer located between the first mezzanine and the second mezzanine.

[0019] At least one source via can be electrically coupled to a source region extending between a first mesa and a second mesa disposed on an insulating layer, and electrically coupled to a metal layer on a machined second surface.

[0020] The source region can extend vertically to the drain bus and the gate bus is positioned to extend between the adjacent first and second sides.

[0021] In some embodiments, the metal layer on the processed second surface may extend continuously and uninterruptedly across the entire processed second surface. In some embodiments, the metal layer comprises a plurality of discrete regions disposed on the processed second surface. One or more source vias located between pairs of mesa may be coupled to the single or multiple discrete regions.

[0022] In some embodiments, the III-V semiconductor is a III-nitride and the hetero wafer is single-crystal silicon.

[0023] In some embodiments, the method further includes forming a parasitic channel suppression region at the interface between the III-V semiconductor and the first surface, wherein the parasitic channel suppression region includes an amorphous layer, a polycrystalline layer, or a high defect density region.

[0024] In some embodiments, forming a parasitic channel suppression region includes implanting material into a first surface of the wafer and then epitaxially growing a III-V semiconductor on the first surface, or implanting material into a processed second surface of the wafer.

[0025] In some embodiments, the substance comprises at least one of the group consisting of Ar, Kr, Xe, Ne, He, N, O, H, Fe, C, Si, and Al. The substance may be an ion.

[0026] In some embodiments, the injected material includes materials injected with two or more different energies.

[0027] According to the present invention, a semiconductor device is provided, comprising: a plurality of mesa, each mesa comprising a III-V group semiconductor; an insulating matrix having an upper surface and a lower surface, wherein the side surfaces of the mesa are embedded in the insulating matrix, and the top surface of the mesa is substantially coplanar with the upper surface of the insulating matrix; and a metallization structure. The metallization structure includes gate fingers and drain fingers disposed on the top surface of each mesa, a drain bus electrically coupling a first drain finger disposed on a first mesa to a second drain finger disposed on a second mesa, and a gate bus electrically coupling a first gate finger disposed on a first mesa to a second gate finger disposed on a second mesa.

[0028] In some embodiments, a III-V semiconductor includes an epitaxial multilayer structure based on a III-nitride.

[0029] In some embodiments, the drain bus and the gate bus are at least partially disposed on the upper surface of the insulating substrate.

[0030] In some embodiments, the metallized structure further includes a source region disposed on an insulating layer and extending between a first mesa and a second mesa. The source region may be formed of a conductive layer such as a metal layer.

[0031] In some embodiments, the metallized structure further includes: a source via extending through an insulating matrix, the source via being electrically coupled to a source region; and a metal layer on the lower surface of the insulating layer.

[0032] In some embodiments, the metal layer completely covers the back surface of the semiconductor device, or the metal layer comprises a plurality of discrete regions disposed on the back surface of the semiconductor device.

[0033] In some embodiments, the drain bus is arranged on a first side laterally adjacent to the first mesa and the second mesa, and the gate bus is arranged on a second side laterally adjacent to the first mesa and the second mesa, the second side being opposite to the first side.

[0034] The source region can extend vertically to the drain bus and the gate bus is positioned to extend between the adjacent first and second sides.

[0035] In some embodiments, the metallization structure includes a source bus, and the source bus, drain bus, and gate bus are arranged laterally adjacent to the side of the mesa and on the upper surface of the insulating substrate.

[0036] In some embodiments, the metallization structure includes source fingers disposed on the top surface of each mesa, and the source fingers, gate fingers, and drain fingers are positioned on the top surface of the mesa and on the upper surface of the insulating matrix, and extend into the respective source bus, gate bus, and drain bus.

[0037] For example, the tabletop can be arranged in one or more rows or in an array of rows and columns.

[0038] In some embodiments, the semiconductor device further includes a support layer having a first surface capable of supporting the epitaxial growth of at least one group III nitride and a second surface opposite to the first surface, a mesa being disposed on the first surface and the second surface being coplanar with the lower surface of the insulating matrix.

[0039] In some embodiments, the lower surface of the mesa is substantially coplanar with the lower surface of the insulating matrix. In these embodiments, the mesa may have been epitaxially grown on a support layer that has subsequently been completely removed and does not form part of the final semiconductor device.

[0040] Those skilled in the art will recognize the additional features and advantages upon reading the following detailed description and examining the accompanying drawings. Attached Figure Description

[0041] The elements in the accompanying drawings are not necessarily to scale with respect to each other. The same reference numerals indicate corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the accompanying drawings and are described in detail below.

[0042] Figure 1 (which includes) Figures 1a to 1e The illustration shows a method for manufacturing a semiconductor wafer according to an embodiment.

[0043] Figure 2 (which includes here) Figures 2a to 2d The illustration shows a method for manufacturing a semiconductor wafer according to an embodiment.

[0044] Figure 3 (which includes a total of) Figures 3a to 3c The illustration shows a method for planarizing a semiconductor wafer that can be used in the methods illustrated in Figures 1 and 2.

[0045] Figure 4 The illustration shows a cross-sectional view of a portion of a semiconductor wafer according to an embodiment.

[0046] Figure 5 The illustration shows a cross-sectional view of a portion of a semiconductor wafer according to an embodiment.

[0047] Figure 6 The illustration shows a cross-sectional view of a portion of a semiconductor wafer according to an embodiment.

[0048] Figure 7 The figure shows a top view of a semiconductor device according to an embodiment.

[0049] Figure 8A The figure shows a top view of a semiconductor device according to an embodiment.

[0050] Figure 8B The diagram follows Figure 8A The cross-sectional view of line AA.

[0051] Figure 9 The figure shows a top view of a semiconductor device according to an embodiment.

[0052] Figure 10 The illustration shows a flowchart of a method for manufacturing a semiconductor wafer according to an embodiment. Detailed Implementation

[0053] In the following detailed description, reference is made to the accompanying drawings, which form a part herein, and which illustrate specific embodiments in which the invention may be practiced. In this regard, directional terms such as “top,” “bottom,” “front,” “rear,” “front end,” “end,” etc., are used to indicate orientation with reference to the described figures(s). Because components of the embodiments may be positioned in many different orientations, these directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. The following detailed description of the invention should not be viewed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0054] Many exemplary embodiments will now be explained. In this context, the same structural features in the various figures are identified by the same or similar reference numerals. In the context of this description, “lateral” or “lateral direction” should be understood to mean a direction or extension generally parallel to the lateral extension of the semiconductor material or semiconductor carrier. Thus, the lateral direction generally extends parallel to these surfaces or sides. In contrast, the term “vertical” or “vertical direction” is understood to mean a direction generally perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Thus, the vertical direction travels in the thickness direction of the semiconductor material or semiconductor carrier.

[0055] As used in this specification, when an element such as a layer, region, or substrate is referred to as "on another element" or "extending to another element," it may be directly on or directly extending to the other element, or there may be intermediate elements. In contrast, when an element is referred to as "directly on another element" or "extending directly to another element," there are no intermediate elements.

[0056] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there can be intermediate elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0057] As used herein, the term "Group III nitride" refers to a compound semiconductor that includes nitrogen (N) and at least one Group III element (including aluminum (Al), gallium (Ga), indium (In), and boron (B)), and includes, for example, but is not limited to, any of its alloys, such as aluminum gallium nitride (Al). x Ga (1-x) N), Indium gallium nitride (In) y Ga (1-y) N), aluminum indium gallium nitride (Al) x In y Ga (1-x-y) N), gallium arsenide phosphide (GaAs) a P b N (1-a-b) ) and aluminum indium gallium arsenide phosphide (Al x In y Ga (1-x-y) As a PbN (1-a-b) AlGaN and AlGaN refer to the components represented by the expression Al. x Ga (1-x) N describes the alloy, where 0 < x < 1.

[0058] In some III-V semiconductor devices, a III-V semiconductor multilayer structure is epitaxially grown on a support substrate comprising different materials, which may also be referred to as a heterogeneous substrate. In some embodiments, the substrate is a wafer. The III-V semiconductor multilayer structure is patterned to form a plurality of discrete mesa spaced apart from each other by regions of the support substrate. These regions of the support substrate may be filled with an insulating material (e.g., oxide or nitride), which may form a surface substantially coplanar with the upper surface of the mesa. One or more devices (e.g., transistor devices) are formed in some or all of the mesa on the support substrate. The insulating material may also be used to reduce substrate or wafer bending, which may be caused by compressive or tensile stresses arising from differences in lattice parameters between the III-V semiconductor and the support substrate. The resulting structure may be referred to as a composite wafer.

[0059] Figure 1 includes Figures 1a to 1e The illustration shows a method for manufacturing a semiconductor wafer 10 according to an embodiment. Figure 1a The figure shows a figure with a thickness of t. w Epitaxial growth of a III-V semiconductor 11 on a first surface 12 of a heterojunction wafer 13. The first surface 12 of the heterojunction wafer 13 is capable of supporting the epitaxial growth of at least one III-V semiconductor layer. The heterojunction wafer has a second surface 14 opposite to the first surface 12.

[0060] As used herein, the term "heterogeneous" wafer refers to a wafer formed of a material different from that of a III-V semiconductor. For example, heterogeneous wafer 13 may include silicon and may be formed from a single-crystal silicon wafer or from an epitaxial silicon layer formed on a further substrate. The III-V semiconductor may be, for example, gallium arsenide or gallium nitride-based semiconductors.

[0061] The III-V semiconductor 11 may include one or more layers that may have the same or different compositions. In some embodiments, for example, the III-V semiconductor is a III-nitride-based semiconductor. In some embodiments, the III-V semiconductor 11 includes a multilayer stack formed of III-nitride layers with different compositions. Figure 6 The figure illustrates an example of a multilayer stack that can be epitaxially grown on the first surface 12.

[0062] The heterostructure wafer 13 may have a diameter of six inches or eight inches and a thickness of 250 µm. A III-V semiconductor 11 is epitaxially grown on the first surface 12 of the semiconductor wafer 13 to form a continuous, uninterrupted layer.

[0063] As in Figure 1b As shown in the diagram, as in Figure 1bAs schematically indicated by arrow 18, a portion of the III-V semiconductor 11 is removed to form a plurality of mesa 15, one of which, illustrated in FIG. 1, comprises III-V semiconductors disposed on a first surface 12 of the heterojunction wafer 13 and spaced apart from each other by regions of the first surface 12, which may be referred to as non-device regions. In this embodiment, the first surface 12 remains substantially flat after the mesa is formed. Each of the mesa 15 includes a side surface 16 and a top surface 17, and the mesa 15 are positioned on the first surface 12 spaced apart from each other. The mesa 15 can be considered to protrude from the first surface 12 of the wafer 13.

[0064] Figure 1c The diagram illustrates the application of an insulating layer 19 to a region between mesas 15 on the first surface 12 of a heterojunction wafer 13, i.e., a non-device region applied to the first surface 12. At least the side surfaces 16 of the mesas 15 are embedded in the insulating layer 19. The insulating layer 19 has a top surface 20 that is substantially coplanar with the top surface 17 of the mesas 15. The mesas 15 are thus embedded in and completely surrounded laterally by the insulating layer 19. The insulating layer 19 may comprise oxides and / or nitrides and may comprise one or more sublayers. At this stage of the method, a composite layer comprising lateral regions of different components (i.e., the III-V semiconductor material of the mesas 15 and the insulating material of the layer 19) is formed on the first surface 12 of the wafer 13.

[0065] As in Figure 1d As illustrated in the diagram, as schematically indicated by arrow 21, a portion of the second surface 14 of the wafer 13 is then gradually removed. The portion of the second surface 14 of the wafer 13 can be removed by one or more of grinding, polishing, chemical mechanical polishing, and etching. A carrier substrate or wafer can be applied to the first side, i.e., the mesa 15 and the insulating layer 19, and serves as a support during the removal of the second surface 14. Figure 1d As shown in the diagram, the insulating layer 19 in the area adjacent to the mesa 15 is exposed to create a processed second surface. The processed second surface includes island-shaped portions of the III-V group material of the mesa 15 and is partially surrounded by the insulating layer 19. The processed second surface can be considered as a coplanar surface 24, which includes the area formed by the lower surface 22 of the mesa 15 and the lower surface 23 of the insulating layer 19.

[0066] exist Figure 1e In the embodiment illustrated in the figure, the semiconductor substrate 13 has been completely removed, resulting in a thickness t. wThe size is gradually reduced to 0 across the entire lateral region. The resulting structure can be considered as a composite wafer 10, which includes island-like portions of III-V group material provided by mesa 15, which extends from the upper surface 38 to the lower surface 24 of the composite wafer 10 and has side surfaces 16 embedded within a matrix formed by an insulating layer 19. The matrix has an upper surface 20 and a lower surface 23, which are substantially coplanar with the upper and lower surfaces of the mesa 15 to form a substantially flat composite wafer 10.

[0067] In some embodiments, a semiconductor device may be formed within the mesa 15 before a portion of the second surface 14 of the wafer 13 is gradually removed. In some embodiments, one or more electrodes 25 may be formed on the upper surface 17 of the mesa 15. For example, each mesa may provide a transistor device and include a source electrode, a gate electrode, and a drain electrode on the top surface 17. In some embodiments, two or more mesa 15 may be formed together to form a semiconductor device. A conductive redistribution structure may be provided, extending on the top surface 20 of the insulating layer 19 and also extending on the top surface 17 of the mesa 15.

[0068] Figure 2 (which includes here) Figures 2a to 2d The illustration shows a method for manufacturing a semiconductor wafer 10 according to an embodiment.

[0069] In the method illustrated in Figure 2, a III-V semiconductor 11 is epitaxially grown on the first surface 12 of a heterostructure wafer 13, as shown in... Figure 1a As illustrated in Figure 2, as indicated by arrow 18, portions of the III-V semiconductor 11 are removed to create a plurality of mesa 15, which include III-V semiconductors 11 spaced apart from each other by portions of the first surface 12 on the first surface 12 of the heterostructure wafer 13. In the embodiment illustrated in Figure 2, after the III-V semiconductors 11 have been removed from the region of the first surface 12 to create mesa 15 comprising only III-V material protruding from the first surface 12 of the heterostructure wafer 13, the removal process continues, and portions of the wafer 13 are also removed to form the processed first surface 12' in a region laterally adjacent to the mesa 15 (i.e., in the non-device region). Thus, the first surface 12 of the wafer 13 includes: having a thickness t w The protruding area is capped by a III-V semiconductor 11; and the recess has a bottom formed by a newly processed first surface 12' and a side 26 substantially aligned vertically with the side 16 of the III-V semiconductor material of the mesa 15. An interface 27 is formed between the III-V semiconductor material 11 and the heterostructure 13, extending across the width of the mesa 15 and located in a plane above the plane of the new first surface 12'. In the area positioned laterally adjacent to the mesa 15 and not covered by the III-V semiconductor material, the heterostructure 13 has a diameter less than t.w thickness t r .

[0070] As in Figure 2b As shown in the diagram, an insulating material 19 is then applied to the area of ​​the wafer 13 located between the mesa 15, such that the recesses in the first surface 12 are filled with the insulating material 19, and the sides 16 of the mesa 15, in addition to the sides 26 and bottom 12' of the recesses, are also filled with the insulating layer 19. The insulating layer 19 has a top surface 20 that is substantially coplanar with the top surface 17 of the mesa 15. A device can then be formed in the mesa 15, for example, by applying a metallization structure 25 to the top surface 17 of the mesa 15.

[0071] As in Figure 2c As illustrated in the diagram, as schematically indicated by arrow 21, the method continues by gradually removing a portion of the second surface 14 of the wafer 13 to expose the insulating material 19 in the laterally adjacent area to the mesa 15 and create a new surface 24. Due to the formation of recesses 12' in the first surface 12, the first surface 12 of the wafer 13 is positioned in the laterally adjacent area to the mesa 15 with the initial wafer thickness t. w Compared to the thickness of wafer 13 beneath the III-V material of mesa 15, it has a reduced thickness t. r When the insulating layer 19 is exposed in the new second surface 24, the material of the wafer 13 located below the III-V group material of the mesa 15 remains at the bottom of the mesa 15, such that the new surface 24 includes island-shaped portions 28 formed by material of the heterogeneous wafer 13 (e.g., silicon) that is laterally surrounded by the exposed surface 23 of the insulating material 19.

[0072] In these embodiments, the thickness t of wafer 13 below mesa 15 w The thickness is reduced to a value t, where t is less than 20 μm, less than 2 μm, or less than 1 μm. The thickness of the wafer in the region laterally adjacent to the mesa 15 is reduced to 0. Since a portion of the wafer remains below the mesa 15, t is greater than 0. This retained portion of the heterojunction wafer 13 may have a minimum thickness of, for example, 0.1 μm. In some embodiments, 0 μm < t ≤ 20 μm, or 0 μm < t ≤ 2 μm, or 0 μm < t ≤ 1 μm. In some embodiments, 0.1 μm < t ≤ 20 μm, or 0.1 μm < t ≤ 2 μm, or 0.1 μm < t ≤ 1 μm.

[0073] Figure 2dThe diagram illustrates a flat composite wafer 10 having a structure including a mesa 15 comprising a first bottom substrate 29 formed of a retained material of a heterojunction wafer 13 and a III-V semiconductor layer 11. The mesa 15 is laterally surrounded by an insulating material 19, such that its top surface is formed by the top surface 17 of an island-like portion of the III-V material formed through the top surface 17 of the mesa 15 and the top surface 20 of the insulating material 19. The lower surface of the composite wafer comprises island-like portions of the heterojunction substrate 13 surrounded laterally by the insulating material 19. The lower surface of the composite wafer forms a substantially coplanar lower surface 24 comprising the lower surface 28 of the mesa 15 and the lower surface 23 of the insulating material 19. The lower surface 28 of the mesa 15 comprises the material of the heterojunction substrate but not the III-V semiconductor material. An interface 27 formed between the III-V semiconductor layer 11 and the first surface 12 of the heterojunction substrate extends across the entire width of the mesa 15 and is defined by the insulating layer 19.

[0074] The bottom substrate 29 provides mechanical support for the III-V semiconductor. Due to the reduced thickness of the bottom substrate 29, the structure illustrated in 2d can be useful for manufacturing semiconductor devices having lower thermal resistance between the back side of the III-V semiconductor and a further substrate (e.g., a die pad) on which the bottom substrate 29 is mounted. Additionally, because the thickness of the bottom substrate 29 through which the vias extend is reduced, this structure can be useful for manufacturing semiconductor devices with through-body vias.

[0075] After the insulating material 19 is applied to the first surface 12 of the heterojunction substrate 13 in the region adjacent to the protruding mesa 15, a planarization process can be performed to form a flat surface including the top surface 17 of the mesa 15 and the top surface 20 of the insulating material 19. An embodiment of the method for forming this flat surface is illustrated with reference to FIG3.

[0076] Figure 3 includes a total of Figures 3a to 3c The illustrations depict methods for planarizing semiconductor wafers that can be used in the methods illustrated in Figures 1 and 2. (As shown in...) Figure 3a As shown in the diagram, an insulating layer 19 is initially applied to the first surface 12 of the wafer 13, such that it completely covers the mesa 15 and the first surface 12 of the wafer 13 in the position between the mesa 15, such that the insulating layer 19 has an outer contour 31 including a protrusion 30 located above the mesa 15 and a recess 32 located in the region between the mesa 15. The edge of the mesa 15 is completely covered by the insulating material 19 and is located below the protrusion 30. The protrusion 30 has a lateral area A greater than that of the mesa 15. m The horizontal area A pThe recess 32 includes a lower surface 31 located in a plane above the plane of the top surface 17 of the platform 15. The recess 31 has a lateral area A smaller than that between adjacent platforms 15. r The horizontal area A i .

[0077] Figure 3b The diagram illustrates a mask 33 applied to an initial insulating layer 19 and openings 34 formed in the mask 33 at locations above each mesa 15. The mask can be a soft mask or a hard mask formed of photoresist. The openings 34 have a lateral area A at their bottom that is smaller than that of the mesa 15. m The horizontal area A b The portion of the insulating material 19 exposed at the bottom of the opening 34 is removed to create a recess 36 in the insulating layer 19 surrounded by a protrusion 35 formed in the insulating material 19. The outer peripheral edge of the tabletop 15 is covered by a thicker portion of the insulating layer provided by the protrusion 35.

[0078] The recess 36 has a bottom 37 formed of the material of the insulating layer 19, so that the top surface 17 of the platform 15 is still covered by the remaining portion of the insulating layer 19. The bottom 37 may lie in a plane similar to the plane in which the bottom 31 of the recess 32 is located. The mask 33 and the insulating layer 19 are then gradually removed, so that the top surface 17 of the platform 15 is exposed and the thickness of the insulating layer 19 is reduced, so that the top surface 20 of the insulating layer 19 in the region between the platforms 15 is substantially coplanar with the top surface 17 of the platform 15 and forms a planarized surface 38, as shown in Figure 3c As shown in the diagram.

[0079] Therefore, the insulating layer 19 is removed from the area above the central portion of the platform 15 in two stages: first by forming a recess 36 in the initial protruding portion 30 of the insulating layer 19; and then by removing the remaining protruding portion 35 covering the outer peripheral area of ​​the platform 15 and surrounding the recess 36, subsequently forming a planarized composite surface 38, as shown in Figure 3c As shown in the diagram.

[0080] Figure 4 The illustration shows an embodiment of wafer 10 in which a stop layer 40 is formed on a region of the first surface 12 of wafer 13 at a location between mesa 15s before the application of the insulating layer 19. In other methods not illustrated, the stop layer 40 is additionally formed on the side surface 16 of the mesa, and in embodiments where the mesa 15 includes a bottom substrate 29, it is formed on the side surface 26 of the bottom substrate 29. The insulating layer 19 is then applied according to one of the embodiments described herein. The stop layer 40 functions as a stop layer during the removal of the second surface 14 of wafer 13. The stop layer 40 may comprise carbon or amorphous carbon, amorphous hydrogenated carbon.

[0081] In some embodiments, a stop layer 41 may be applied to the top surface 17 of the mesa 15 prior to the application of the insulating layer 19. The stop layer 41 functions as a stop layer during the removal of the insulating layer 19 as the planarized surface is formed. The stop layer 41 may comprise carbon or amorphous carbon, amorphous hydrogenated carbon.

[0082] Figure 5 The illustration shows an embodiment of wafer 10, wherein mesa 15 includes a bottom substrate 29. A parasitic channel suppression region 50 is formed at the interface 27 between the III-V semiconductor 11 and a first surface 12 of the heterostructure substrate 13. The parasitic channel suppression layer 50 has a lateral extension corresponding to the lateral extension of mesa 15 and intersects with the side surface 16 of mesa 15. The parasitic channel region 50 may include an amorphous layer, a polycrystalline layer, a high defect density region, or implanted material.

[0083] In III-V semiconductor devices (such as GaAs-based or GaN-based devices) formed on a heterogeneous substrate (such as silicon), parasitic conductive channels may form at the interface between the substrate and the III-V semiconductor device. Coupling between the device's electrodes (such as the drain electrode in the case of a transistor device) and these parasitic electron or hole channels can lead to losses and limit performance. A parasitic channel suppression region 50 is used to mitigate or eliminate the effects of such parasitic channels or to prevent their formation.

[0084] The parasitic channel suppression region 50 may take the form of a region with reduced charge mobility and / or a region with reduced charge density.

[0085] The charge mobility reduction region 50 is used to impede the movement of charge at the interface 27 formed between the III-V semiconductor and the first surface 12 of the heterostructure 13, and thus reduce RF loss due to the formation of parasitic conductive channels between the drain electrode 57 and the electrodes on the back of the device.

[0086] The effects of these parasitic charge channels can be reduced by providing a parasitic channel suppression region 50 that hinders or suppresses charge mobility at the boundary or interface between the III-V semiconductor and the heterostructure.

[0087] In some embodiments, a parasitic channel suppression region is provided that is high in resistance, thereby preventing or hindering the movement of free charges. In these embodiments, parasitic channel suppression provides a charge mobility reduction region. The charge mobility reduction region may include an amorphous layer or region, a polycrystalline layer or region, or a high-defect layer or region. The charge mobility reduction region may also include a combination of amorphous and / or polycrystalline portions.

[0088] In some embodiments, a parasitic channel suppression region is provided that reduces charge density by providing a charge density reduction region at the boundary or interface between the III-V semiconductor and the heterostructure. The charge density reduction region may include traps for trapping free charges, thus reducing charge density and preventing the formation of parasitic conductive electron channels or hole channels.

[0089] In some embodiments, a combination of charge traps for reducing the density of free charges and high-resistivity regions for preventing the movement of free charges is used to suppress parasitic channels.

[0090] In some embodiments, any parasitic channels of mobile charge present at the III V / substrate interface just below the device are directly and physically interrupted, and the charge is compensated by adjusting the composition of the layer located in the region of the interface (i.e., above and below the interface).

[0091] In some embodiments, a parasitic channel suppression region 50 is formed by implanting material into a first surface 12 of a wafer 13 and then epitaxially growing a III-V semiconductor 11 on the first surface 12 thereafter.

[0092] In other embodiments, the parasitic channel suppression region 50 may be formed by implanting material into the second surface 14 of the wafer 13. The material can be implanted into the new second surface 24 after a portion of the wafer 13 has been removed to expose a portion of the insulating layer 19. This is due to the initial thickness t of the heterogeneous wafer 13. w This method is easier to implement than the reduced thickness t of the retained portion of the bottom substrate 29 located at the bottom of the mesa 15.

[0093] In some embodiments, by injecting such as Ar + The implanted material is used to form a region of reduced charge mobility. The implanted material can include one of the following groups: Ar, Kr, Xe, Ne, He, N, O, H, Fe, C, Si, and Al. The implanted material can be ions.

[0094] In some embodiments, the material may be injected at two or more different energies to increase the injection depth and thickness of the charge mobility reduction region 50. In a particular example, the material is Ar. + Ions, which are 1e 13 cm -2 up to 5e 15 cm -2 or 1e 14 cm -2 up to 5e 15 cm -2The injection dose was injected at energies ranging from 20 keV to 250 keV. In one example, the material was injected at 50 keV with 3e 14 cm -2 The ion implantation dose and at 250 keV with 3e 14 cm -2 The ion implantation dose was injected.

[0095] In some embodiments, the charge mobility reduction region 50 is replaced by a charge density reduction region comprising charge traps. The charge mobility reduction region may consist of a region with high trap density, where electrons or holes occupy the traps. In this case, the number of electrons or holes available for current conduction is reduced. Due to the reduced density of free electrons or holes at the interface, the resistance of the charge mobility reduction region 50 increases. In some embodiments, a combination of high trap density and polycrystalline, amorphous, or high defect density structures is used.

[0096] Epitaxial group III nitride-based multilayer structures (such as those described above for HEMT) have large polarization charges and are epitaxially grown at high temperatures. Therefore, including parasitic channel suppression regions can be particularly advantageous for group III nitride-based multilayer structures.

[0097] To reduce RF losses and improve device efficiency, in a first aspect, this disclosure seeks to suppress current flow in parasitic channels by suppressing the movement of electrons in these channels. In some embodiments, this is achieved by providing a charge mobility reduction region at the boundary between the III-V semiconductor material and the substrate. The parasitic electron channels are considered to still exist and be capacitively coupled to the drain electrode and the electrode on the back surface of the substrate. However, the charge mobility reduction region prevents current flow through the parasitic electron channels, thereby preventing RF losses.

[0098] The charge mobility reduction region can be a high-resistance region, which can be formed by creating an amorphous, polycrystalline, or high-defect-density region at a location where parasitic electron channels are formed (e.g., at the boundary between the III-V semiconductor layer and the substrate). The charge mobility reduction region can be formed by implantation, and locally disrupts the crystallinity of the substrate and the epitaxial III-nitride layer. An increase of at least 4 to 5 percentage points in drain efficiency can be achieved. Drain efficiency is the ratio of (RF output power delivered to the load) to (DC power supplied to the transistor drain terminal).

[0099] In a second aspect, this disclosure seeks to suppress current flow in parasitic channels by reducing the charge density in regions where parasitic channels are formed. This is achieved by providing a charge density reduction region at the boundary between the III-V semiconductor layer and the substrate. The charge density reduction region may include traps for trapping charge, thus preventing the formation of parasitic conductive electron or hole channels.

[0100] The charge density reduction region can be an amorphous, polycrystalline, or high-defect-density region formed at locations where parasitic electron channels are formed (e.g., at the boundary between a III-V semiconductor layer and the substrate). The charge density reduction region can be formed by implantation, and locally disrupts the crystallinity of the substrate and the epitaxial III-nitride layer, forming charge traps in these regions.

[0101] In some embodiments, the parasitic channel suppression region may include a combination of a high trap density for reducing charge density and a locally increased resistivity for reducing charge mobility.

[0102] Figure 6 The illustration shows a cross-sectional view of a portion of a semiconductor wafer 10 according to an embodiment. Figure 6 In the embodiment illustrated, at least one cavity 60 is disposed on a first surface 12 of the heterojunction wafer 13 that is laterally adjacent to the mesa 15. The cavity 60 is formed and defined by one or more insulating layers 61 and is filled with gas or a vacuum. For example, the cavity 60 may be defined by insulating layers 61 disposed on the side 16 of the adjacent mesa 15, on the side 26 of the bottom substrate 29 (if present), and on the first surface 12 of the heterojunction wafer 13 disposed between the adjacent mesa 15 in a non-device region. The padded recess may be capped by a further insulating layer 62 to seal and close the cavity 60. The cavity 60 may be filled with gas or a vacuum, which may be the same as or similar to the gas or vacuum present in the apparatus used for depositing the cap 62. Figure 6 In the embodiment illustrated, wafer 10 includes a cavity 60 in place of insulating material 19. The cavity 60 may form part of a final semiconductor device.

[0103] Figure 6 The illustration also includes an embodiment of a III-V semiconductor layer 11 comprising a multilayer III-V nitride structure 70 epitaxially grown on a first surface 12.

[0104] The multilayer group III nitride structure 70 can be used as a reference to Figure 1 to 70. Figure 5 III-V semiconductor layer 11 in any of the described embodiments.

[0105] The multilayered group III nitride-based structure 70 may include: a group III nitride buffer structure 71 grown on a first surface 12 of the heterostructure 13; a group III nitride channel layer 72 grown on the group III nitride buffer structure 71; and a group III nitride barrier layer 73 grown on the group III nitride channel layer 72. The group III nitride barrier layer 73 may include aluminum gallium nitride and the group III nitride channel layer 72 may include gallium nitride, such that a heterojunction 74 is formed between the group III nitride channel layer 72 and the group III nitride barrier layer 73, the heterojunction 74 being capable of supporting a two-dimensional charge gas, such as a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG).

[0106] The group III nitride-based buffer structure 71 for a silicon substrate may include an AlN initiation layer on the silicon substrate, which may have a thickness of several hundred nanometers (nm), followed by Al x Ga (1-x) The N-layer sequence, with each layer again having a thickness of several hundred nanometers, reduces the Al content from approximately 50% to 75% to 10% to 25% before growing the GaN layer with the AlGaN back barrier. Alternatively, a superlattice buffer can be used. The AlN initiation layer on the silicon substrate is used again. Depending on the superlattice chosen, AlN and Al... x Ga (1-x) N pairs of sequences, where AlN layer and Al x Ga (1-x) The thickness of N ranges from 5 to 15 nm. Depending on the desired breakdown voltage, the superlattice can include between 20 and 100 pairs. Alternatively, Al, as described above, can be used. x Ga (1-x) N-layer sequences can be used in combination with the superlattices mentioned above.

[0107] In some embodiments not shown, the conductive electrodes may be disposed on the second surface 28 of the mesa 15 or on the bottom substrate 29 (if present). The conductive electrodes may be coupled to ground potential.

[0108] As discussed above, a semiconductor device manufactured from a wafer according to any of the embodiments described above may include a single mesa 15 such that the single mesa 15 provides a transistor device, or may include a plurality of mesa 15 electrically coupled together by a conductive redistribution structure or a metallization structure to form a single transistor device.

[0109] Figure 7 The figure shows a top view of a semiconductor device 80 according to an embodiment. The semiconductor device 80 may be manufactured using a method according to any of the embodiments described herein.

[0110] The semiconductor device 80 includes a plurality of mesa 15 and an insulating layer 19 providing an insulating matrix 19 for the semiconductor device 80. Side surfaces 16 of the mesa 15 are embedded in the insulating matrix 19, and the top surface 17 of the mesa 15 is substantially coplanar with the upper surface 20 of the insulating matrix 19. Each mesa 15 may include a III-V semiconductor (such as a III-nitride) and may include an epitaxial III-nitride-based multilayer structure (e.g., see reference 19). Figure 6 (Described structure). The mesa 15 is provided with insulating layers 19 of the insulating matrix of the semiconductor device 80, which are spaced apart from each other and electrically insulated.

[0111] The tabletop 15 can be arranged as a single row or two or more rows. The tabletop can also be arranged as an array or, for example, as rows and columns.

[0112] The semiconductor device 80 includes a metallization structure 81 located on its upper surface 82. The upper surface 82 of the semiconductor device 80 is provided by the upper surface 20 of an insulating layer 19 providing an insulating matrix 19 and the top surface 17 of a mesa 15.

[0113] The metallization structure 81 includes source fingers 85, gate fingers 86, and drain fingers 87 disposed on the top surface 17 of each mesa 15. The source fingers 85, gate fingers 86, and drain fingers 87 may be formed of one or more metal layers, and each has an elongated strip shape. The source fingers 85, gate fingers 86, and drain fingers 87 extend substantially parallel to each other. On each mesa 15, the gate fingers 86 are positioned laterally between the source fingers 85 and drain fingers 87. The metallization structure 81 further includes a source bus 88 that electrically couples the source fingers 85 disposed on two or more or all of the mesa 15 to each other. The metallization structure 81 also includes a drain bus 89 electrically coupling two or more or all of the drain fingers 87 to each other and a gate bus or gate channel 90 electrically coupling two or more or all of the gate fingers 86 to each other.

[0114] The metallization structure 81 electrically couples the mesa 15 together, so that two or more mesa 15 form a single switch or transistor device.

[0115] Source bus 88 is located on the upper surface 20 of the insulating layer 19 at a position laterally adjacent to and spaced apart from the side of the mesa 15. Each source finger 85 is arranged not only on the top surface 17 of the mesa 15 but also extends to the source bus 88 on the upper surface 20 of the insulating matrix 19. The source bus 88 may extend substantially perpendicular to the source finger 85. Each drain finger 87 is also located on the top surface 17 of the mesa 15 and on the upper surface 20 of the insulating matrix 19 and extends to the drain bus 89, which is located on the upper surface 20 of the insulating matrix 19 at a position laterally adjacent to and spaced apart from the side 16 of the mesa 15. The drain bus 89 may be located on the side of the mesa 15 opposite to the source bus 88, so that the source fingers 85 and drain fingers 86 extend from the mesa 15 to the insulating matrix 19 in opposite directions.

[0116] Each gate finger 86 is also located on the top surface 17 of the mesa 15 and the upper surface 20 of the insulating matrix 19 and extends to the gate bus 90. The gate bus 90 can be positioned laterally adjacent to the source bus 88 and can extend substantially parallel to the source bus 88. Typically, the gate fingers 86 and the gate bus 90 have a smaller thickness compared to the source fingers 85 and are a further insulating layer utilized by the metallization structure 81 (in Figure 7 (Not visible in the top view) Covered so that the gate fingers 86 extend below the source bus 88 and are electrically insulated from the source bus 88 by this additional insulating layer.

[0117] In some embodiments, more than three fingers are arranged on each tabletop 15. In some embodiments, the fingers are arranged symmetrically on each tabletop 15. Figure 7 In the embodiment illustrated, five fingers are arranged on each mesa 15, and have a source-gate-drain arrangement. However, a drain-gate-source arrangement can also be used. The arrangement of the fingers on each mesa 15 of the semiconductor device can be the same or different.

[0118] In some embodiments, each of the mesa 15 may include a support layer such that the lower surface of the semiconductor device 80 includes a plurality of islands of material of the support layer that are laterally surrounded by the material of the insulating matrix 19. In some embodiments, the semiconductor device 80 also includes a parasitic channel suppression region at the interface between the III-V semiconductor and the first surface of the support substrate, according to any of the embodiments described herein.

[0119] In some embodiments, the lower surface of the semiconductor device 80 includes island-shaped portions of a III-V semiconductor material forming a mesa 15, which are laterally surrounded by the material of an insulating matrix 19. In these embodiments, the mesa 15 is not located on a support layer.

[0120] Figure 8A The figure shows a top view of the semiconductor device 100 according to an embodiment, and Figure 8B The semiconductor device 100 shown in the figure is along the edge of Figure 8A A cross-sectional view of line AA as indicated in the diagram. Semiconductor device 100 may be manufactured using a method according to any of the embodiments described herein.

[0121] The semiconductor device 100 includes a plurality of mesa 15 embedded in an insulating layer 19 that provides the insulating matrix of the semiconductor device 100. In this embodiment, the back surface 111 of the semiconductor device is formed by the lower surface 23 of the coplanar insulating layer 19 and the lower surface 22 of the mesa 15.

[0122] The side surface 16 of the platform 15 is embedded in the insulating substrate 19, and the top surface 17 of the platform 15 is substantially coplanar with the upper surface 20 of the insulating substrate 19, as shown in Figure 7 As illustrated in the embodiment. In this embodiment, each platform 15 has an elongated strip-like shape, and multiple platforms 15 are arranged in a single row, wherein the long sides of the platforms extend substantially parallel to each other.

[0123] Semiconductor device 100 includes a metallization structure 101 located on an upper surface 102 of semiconductor device 100. The upper surface 102 of semiconductor device 100 is provided by an upper surface 20 of an insulating layer and a top surface 17 of a mesa 15. The metallization structure 101 electrically couples the mesa 15 together, thereby forming a single switch or transistor device from multiple mesa 15. The metallization structure 101 differs in its layout from the metallization structure 81 of semiconductor device 80.

[0124] The metallization structure 101 includes two drain fingers 87 located on each mesa 15, extending to and electrically coupled together via a drain bus 89, the drain bus 89 extending substantially perpendicular to the length of the drain fingers 87 and positioned laterally adjacent to a first side 103 of the mesa 15 on the upper surface 20 of the insulating substrate 19. The drain fingers 87 are positioned toward the center of the top surface 17 of each mesa 15. Two gate fingers 86 are also located on the top surface 17 of each mesa 15, such that they are positioned between the drain fingers 87 and the longitudinal side edges 104 of the mesa 15. The gate fingers 86 are electrically coupled together via a gate bus 90 extending substantially perpendicular to the length of the gate fingers 86. In this embodiment, the gate bus 90 is positioned adjacent to a second side 105 of the mesa 15, the second side 105 being opposite the drain bus 89 of the mesa 15, which is adjacent to the first side 103 where it is positioned.

[0125] Instead of a single source bus, the metallization structure 101 includes a plurality of source regions 106, each source region 106 extending between a pair of adjacent mesas in the mesas 15. Each source region 106 may be formed of a conductive layer, such as a metal layer that may include one or more sublayers. Each source region 106 has an elongated longitudinal portion 107 located on each of two closely adjacent mesas 15 and adjacent to a gate finger 86, such that the gate finger 86 is positioned laterally between a drain finger 87 and the longitudinal portion 107. The longitudinal portion 107 extends substantially parallel to the gate finger 86 and the drain finger 87 and may be considered to provide the source finger.

[0126] The longitudinal portions 107, 107' are electrically coupled by a plurality of traverse portions 108 extending over the intermediate portion of the insulating substrate 19. In the embodiment illustrated in FIG8, adjacent traverse portions 108 are electrically coupled by longitudinal connecting portions 109 located entirely on the insulating substrate 19. In the embodiment illustrated in FIG8, a plurality of these structures are located between the long sides 104 of the pairs of mesa 15. However, in other embodiments, a single source region 106 or a plurality of source regions 106 may be used, the single source region 106 having a substantially rectangular shape extending between each pair of mesa 15, and each of the plurality of source regions 106 having a substantially rectangular shape and each extending between the pairs of mesa 15.

[0127] Source region 106 is electrically coupled to the back surface of semiconductor device 100 through one or more conductive source vias 110. The source vias 110 are located between mesa 15 and extend through insulating matrix 19. The source vias 110 may be completely surrounded laterally by insulating matrix 19 and may not extend through the III-V semiconductor material of the mesa 15 or through any supporting substrate, which in some embodiments is located below the mesa 15.

[0128] For example, one or more source vias 110 may be located below each longitudinal connection portion 109. Each of the source vias 110 may have an elongated shape and extend substantially parallel to the long side 104 of the platform 15, or may have a shape such as circular, square, or hexagonal in a plan view.

[0129] The back surface 111 of the semiconductor device 100 may include a metal layer 112 that extends continuously and uninterruptedly over the entire back surface 111, such that each source region 106 is connected to a common source connection on the back surface 111 of the semiconductor device 100. In other embodiments, the metal layer 112 on the back surface 111 of the semiconductor device 100 includes a plurality of discrete portions spaced apart from each other. One source region 106 may be connected to a single discrete portion within the discrete portions. However, two or more source regions 106 may be connected to a common discrete portion within the discrete portions.

[0130] Figure 9 The figure shows a top view of a semiconductor device 120 according to an embodiment, which has a plurality of elongated mesas 15 embedded in an insulating substrate 19, as illustrated in the embodiment of FIG. 8. The semiconductor device 120 has a metallization structure 121 having a layout similar to that of metallization structure 101, wherein a drain bus 89 is positioned adjacent to a first side 103 and a gate bus 90 is positioned abutting against opposing sides 105 of the mesas 15. The metallization structure 121 also includes a plurality of source regions 106, each source region 106 located between and extending between pairs of mesas 15. Each source region 106 is electrically coupled to a back surface of the semiconductor device 120 through a plurality of source vias 110 located between the pairs of mesas 15 in the insulating substrate 19. Figure 10 The source region 106 is not visible in the top view so that the arrangement of the gate fingers 86 can be seen more clearly.

[0131] exist Figure 9In the embodiment illustrated, the gate finger 86 includes a first longitudinal portion 122 that extends parallel to the drain finger 87 and has a length such that it is entirely located on the top surface 17 of the mesa 15. A gate bus 90 is electrically coupled to the first longitudinal portion 122 of the gate finger 86 via a second longitudinal portion 123 that extends from the gate bus 90 on the upper surface 20 of the insulating substrate 19 and extends to the top surface 17 of the mesa 15. The second longitudinal portion 123 extends substantially parallel to the drain finger 87 and extends to the first longitudinal portion 122 of the gate bus 86. The second longitudinal portion 123 is laterally spaced from the longitudinal portion 122 in the lateral direction. The second longitudinal portion 123 is electrically coupled to the first longitudinal portion 122 via one or more lateral portions 124. In this embodiment, the plurality of lateral portions 124 are positioned at intervals along the length of the longitudinal portions 122, 123. The first longitudinal portion 122 is positioned laterally between the second longitudinal portion 123 and the drain finger 87.

[0132] The second longitudinal portion 123 provides a redistribution structure from the gate bus 90 to the first longitudinal portion 122 providing the gate fingers 86.

[0133] Figure 10 The figure shows a flowchart 130 of a method for manufacturing a semiconductor wafer according to an embodiment.

[0134] In frame 131, with a thickness t w A heterojunction wafer has a first surface on which a III-V semiconductor is epitaxially grown. The first surface is capable of supporting the epitaxial growth of at least one III-V semiconductor layer. The heterojunction wafer has a second surface opposite to the first surface. In block 132, portions of the III-V semiconductor are removed to create a plurality of mesas comprising the III-V semiconductor disposed on the first surface of the wafer. In block 133, an insulating layer is applied to the region of the wafer disposed between the mesas. In block 134, portions of the second surface of the wafer are gradually removed, exposing the insulating layer in the region adjacent to the mesas, thus creating the processed second surface.

[0135] Optionally, after removal, a portion of the III-V semiconductor is removed to create a plurality of mesas including the III-V semiconductor disposed on a first surface of the wafer. The portion of the first surface of the wafer is removed to form a processed first surface in a laterally adjacent region to the mesas, and to form an interface between the first surface of the wafer and the III-V semiconductor structure, the interface extending across the width of the mesas. Optionally, gradually removing a portion of the second surface of the wafer includes removing a portion of the wafer with a thickness t below the mesas. w Reduce to a thickness t, where t≤20μm, or t≤2μm or t≤1μm.

[0136] For ease of description, spatially relative terms such as "below," "below," "lower part," "above," and "upper part" are used to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device other than those depicted in the figures. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, areas, sections, etc., without any intention of limitation. Throughout the description, the same terms refer to the same elements.

[0137] As used herein, the terms “having,” “comprising,” “including,” and “including” are open-ended terms that indicate the presence of a stated element or feature but do not exclude additional elements or features. The quantifiers “a,” “an,” and the pronoun “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise. It is to be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein can be combined with each other.

[0138] While specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various substitutions and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only to the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor wafer, the method comprising: With thickness t w III-V semiconductors are epitaxially grown on the first surface of the heterostructure wafer, the first surface being capable of supporting the epitaxial growth of at least one III-V semiconductor layer, and the heterostructure wafer having a second surface opposite to the first surface; Remove portions of the III-V semiconductor to create multiple mesas including the III-V semiconductor disposed on a first surface of the heterojunction wafer; An insulating layer is applied to the area of ​​the heterostructure wafer that is arranged between the mesa; Metallization structures are formed on III-V semiconductors, and the metallization structures provide the source, gate, and drain for the transistor structure; The metallization structure includes gate fingers and drain fingers arranged on each mesa; A drain bus electrically couples a first drain finger disposed on a first mesa to a second drain finger disposed on a second mesa, the drain bus being arranged at least partially on an insulating layer to be laterally adjacent to the first and second mesa; and A gate bus electrically couples a first gate finger disposed on a first mesa with a second gate finger disposed on a second mesa, the gate bus being arranged at least partially on an insulating layer to be laterally adjacent to the first and second mesa. Gradually remove a portion of the second surface of the heterogeneous wafer, exposing the insulating layer in the region adjacent to the mesa, and produce the processed second surface.

2. The method of claim 1, further comprising removing a portion of the first surface of the heterojunction wafer to form a processed first surface in a region laterally adjacent to the mesa and to form an interface between the first surface of the heterojunction wafer and the III-V semiconductor structure, the interface extending along the width direction of the mesa.

3. The method according to claim 1, wherein, Gradually removing a portion of the second surface of the heterogeneous wafer includes removing the thickness t of the wafer below the mesa. w Reduce to a thickness t, where t≤20μm, or t≤2μm or t≤1μm.

4. The method according to any one of claims 1 to 3, wherein, The portion for removing the second surface of a heterogeneous wafer includes at least one of the group consisting of a milled second surface of a wafer, a polished second surface of a wafer, a chemically mechanically polished second surface of a wafer, and an etched second surface of a wafer.

5. The method according to any one of claims 1 to 3, wherein applying the insulating layer comprises: An insulating layer is deposited onto the countertop and the area between the countertops, such that the insulating layer has a thickness at least as large as the height of the countertop, and the countertop is covered by the insulating layer. The insulating layer is planarized to form a planarized surface that includes the upper surface of the platform and the upper surface of the insulating layer.

6. The method of claim 5, further comprising: A structured mask is formed on an insulating layer. The structured mask has an opening above the mesa, and the opening has a lateral area smaller than the lateral area of ​​the mesa. Remove a portion of the insulation layer inside the opening and reduce the thickness of the portion of the insulation layer arranged above the tabletop; as well as Gradually remove portions of the mask and insulating layer to create a planarized surface that includes the upper surface of the mesa and the upper surface of the insulating layer.

7. The method according to any one of claims 1 to 3, further comprising forming a stop layer on the area of ​​the wafer disposed between mesa and optionally on the side of the mesa, and removing a portion of the second surface of the wafer includes the stop layer exposed in the area adjacent to the mesa.

8. The method according to any one of claims 1 to 3, wherein more than one source finger and / or more than one drain finger and / or more than one gate finger are arranged on each mesa.

9. The method of claim 8, wherein the drain bus is arranged laterally adjacent to a first side of the first mesa and the second mesa, and the gate bus is arranged laterally adjacent to a second side of the first mesa and the second mesa, the second side being opposite to the first side.

10. The method of claim 8, wherein the metallized structure further comprises at least one source via in an insulating layer located between the first mesa and the second mesa, wherein, The at least one source via is electrically coupled to a source region disposed on an insulating layer and extending between a first mesa and a second mesa, and is electrically coupled to a metal layer on a machined second surface.

11. The method according to any one of claims 1 to 3, wherein, III-V semiconductors are III-nitrides, and heterojunction wafers are single-crystal silicon.

12. A semiconductor device, comprising: Multiple mesa, each mesa comprising an epitaxial group III nitride-based multilayer structure; An insulating substrate having an upper surface and a lower surface, wherein the sides of a mesa are embedded in the insulating substrate, and the top surface of the mesa is substantially coplanar with the upper surface of the insulating substrate; and Metallized structures, including: Gate fingers and drain fingers are arranged on the top surface of each mesa; A drain bus that electrically couples a first drain finger disposed on a first platform to a second drain finger disposed on a second platform; and A gate bus electrically couples a first gate finger disposed on a first mesa with a second gate finger disposed on a second mesa. The drain bus and gate bus are at least partially arranged on the upper surface of the insulating substrate.

13. The semiconductor device of claim 12, wherein the metallization structure further comprises: The source region is arranged on the insulating layer and extends between the first mesa and the second mesa.

14. The semiconductor device according to claim 12 or 13, wherein, The metallized structure further includes: The source via extends through the insulating substrate, and the source via is electrically coupled to the source region; and A metal layer on the lower surface of the insulating layer.

15. The semiconductor device according to claim 14, wherein, The metal layer completely covers the back surface of the semiconductor device, or the metal layer comprises multiple discrete regions disposed on the back surface of the semiconductor device.

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