Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. A method includes: forming a fin extending above a semiconductor substrate; forming a photoresist structure above the fin; patterning a serpentine cut pattern in the photoresist structure to form a cut mask, wherein the serpentine cut pattern extends above the fin, wherein the serpentine cut pattern includes alternating bridge regions and cut regions, wherein each cut region extends along a first direction, wherein each bridge region extends between adjacent cut regions along a second direction, wherein the second direction is within 30° of an orthogonal direction relative to the first direction; and performing an etching process using the cut mask as an etching mask.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a plurality of fins extending above a semiconductor substrate; forming a photoresist structure above the plurality of fins; patterning a serpentine cut pattern in the photoresist structure to form a cut mask, wherein the serpentine cut pattern extends above the plurality of fins, wherein the serpentine cut pattern comprises alternating bridging regions and cut regions, wherein each cut region extends along a first direction, wherein each bridging region extends between adjacent cut regions along a second direction, wherein the second direction is within 30° relative to an orthogonal direction to the first direction; and performing an etching process using the cut mask as an etching mask.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a plurality of fins protruding from a substrate; forming source / drain regions on the plurality of fins; forming an interlayer dielectric ILD above the source / drain regions; and forming source / drain contacts, comprising: forming a mask layer above the ILD; patterning a cut pattern in the mask layer, wherein the cut pattern comprises a first straight portion and a second straight portion, wherein the first straight portion is connected through the second straight portion, wherein an angle between each first straight portion and an adjacent second straight portion connected to the first straight portion is in a range of 90° to 120°; etching an opening in the ILD to expose the source / drain regions, wherein the etching uses the patterned mask layer as an etching mask; and depositing a conductive material within the opening.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a plurality of fins protruding from a semiconductor substrate, wherein the fins extend along a first direction; a first isolation structure surrounding fins among the plurality of fins; and a second isolation structure above the semiconductor substrate and at least partially within the first isolation structure, wherein the second isolation structure comprises a series of connected first portions and second portions, wherein the first portion extends along a second direction orthogonal to the first direction, wherein the second portion extends along a third direction at a first angle relative to the second direction, wherein the first angle is between 0° and 30°, and wherein adjacent fins among the plurality of fins are isolated from each other by the first portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 2C and Figure 2D Perspective and cross-sectional views are shown of intermediate stages in forming a fin field effect transistor (FinFET) device, according to some embodiments.

[0009] Figure 3 , Figure 4A , Figure 4B , Figure 4C , Figure 5A , Figure 5B and Figure 5C Cross-sectional and plan views are shown of intermediate stages in forming a kerf mask for use in forming a FinFET device, according to some embodiments.

[0010] Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B and Fig. 11CCross-sectional and plan views are shown of intermediate stages in forming source / drain contacts for a FinFET device, according to some embodiments.

[0011] Fig.12 and Fig.13 A plan view of a notched region in a source / drain contact of a FinFET device is shown in accordance with some embodiments.

[0012] Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B and Fig.18C Cross-sectional and plan views are shown of intermediate stages in forming a notched region in a fin of a FinFET device, according to some embodiments.

[0013] Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A , Fig. 23B and Fig.23C Cross-sectional and plan views are shown of intermediate stages in forming a notched region in a fin of a FinFET device, according to some embodiments.

[0014] Fig.24A , Fig. 24B , Fig.24C , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig.26C , Fig.27A , Fig.27B and Fig.27C Cross-sectional and plan views are shown of intermediate stages in forming a notched region in a dummy gate stack of a FinFET device, according to some embodiments.

[0015] Fig.28A , Fig.28B , Fig.28C , Fig.29A , Fig.29B , Fig.29C , Fig. 30A , Fig. 30B , Fig. 30C , Fig.31A , Fig.31B and Fig.31C Cross-sectional and plan views are shown of intermediate stages in forming a notched region in a gate stack of a FinFET device, according to some embodiments.

[0016] Fig.32A , Fig.32B , Fig.32C , Fig.32D , Fig.33A , Fig.33B , Fig.33C , Fig.34A , Fig.34B , Fig.34C , Fig.35A , Fig.35B and Fig.35C Cross-sectional and plan views are shown of intermediate stages in forming a kerf region in a metal line of a FinFET device, according to some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] According to various embodiments, a semiconductor device and a method for forming the same are provided. Specifically, a serpentine cut mask is used to form a cut between source / drain contacts of a FinFET device. The serpentine cut mask includes a straight cut portion connected by a straight bridging portion, wherein the cut portion and the bridging portion are substantially perpendicular to each other. By having a substantially vertical straight portion, the effect of rounding during the photolithography step can be reduced, which can reduce the size of the cut area. Reducing the size of the cut area in this way can allow for larger sized source / drain contacts, which can improve the conductivity and contact resistance of the source / drain contacts. Using a serpentine cut mask as described herein can also allow for a larger overlap window during processing, which can allow for a smaller minimum spacing between the cut areas without increasing the risk of bridging or other process defects.

[0020] In various views and illustrative embodiments, the same reference number is used to designate the same element. In some of the illustrated embodiments, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concept of the present disclosure. The FinFET shown can be electrically coupled in a way to operate as, for example, one transistor or multiple transistors (e.g., two or more transistors). Other types of transistors (e.g., planar transistors, gate-all-around (Gate-All-Around, GAA) transistors, etc.) can also adopt embodiments of the present disclosure. The embodiments discussed herein will provide examples to enable the subject matter of the present disclosure to be performed or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the intended scope of different embodiments. Similar reference numbers and characters in the following figures represent similar components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order. Some of the embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Similarly, some embodiments consider aspects used in planar devices (e.g., planar FETs).

[0021] Figure 1A A three-dimensional view is shown of an intermediate step in forming a FinFET structure in accordance with some embodiments. Figure 1AReference cross sections used in subsequent figures are also shown. Cross section CC is along the longitudinal axis of the fin 24 and in the direction of current flow, for example, between the source / drain regions 42 of the FinFET. Cross section DD is perpendicular to cross section CC and along the longitudinal axis of the dummy gate stack 30. Cross section DD is in a direction perpendicular to the direction of current flow, for example, between the source / drain regions 42 of the FinFET. Cross section BB is parallel to cross section DD and extends through the source / drain regions 42 of the FinFET. Cross section EE is parallel to cross section CC and is located between adjacent source / drain regions 42 of the FinFET. For clarity, subsequent figures refer to these reference cross sections. The fin 24, source / drain regions 42 and dummy gate stack 30 are described in more detail below.

[0022] Figure 1A The structure shown includes a wafer 10, which also includes a substrate 20. The substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which can be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 20 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 20 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0023] exist Figure 1A, a fin 24 formed in a substrate 20 is shown. The fin 24 is a semiconductor strip, and may also be referred to as a "semiconductor fin 24", "semiconductor strip 24" or "strip 24". According to some embodiments of the present disclosure, the fin 24 is part of the original substrate 20, and therefore the material of the fin 24 is the same as the material of the substrate 20. In some embodiments, the fin 24 is formed by etching a portion of the substrate 20 to form a groove. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic. The fin 24 may be patterned by any suitable method. For example, the fin 24 may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern fins 24. In some embodiments, the mask (or other layer) may remain on fins 24. In some embodiments, fins 24 may be separated by a width W2 (see Figure 2D ), the width W2 is between about 20 nm and about 60 nm, but other widths are possible.

[0024] In some embodiments, fin 24 may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 20, and a trench may be etched through the dielectric layer to expose the underlying substrate 20. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 24. For example, Figure 1A The fin 24 in the substrate 20 may be recessed, and a material different from the fin 24 may be epitaxially grown on the recessed fin 24. In such embodiments, the fin 24 includes the recessed material and the epitaxially grown material arranged on the recessed material. Therefore, the fin 24 may be formed of a semiconductor material different from that of the substrate 20. According to some embodiments, the fin 24 is formed of: silicon; germanium; a compound semiconductor including silicon phosphide, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenic phosphide; or a combination thereof.

[0025] In another embodiment, a dielectric layer may be formed over the top surface of substrate 20, and trenches may be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a different material than substrate 20, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form fins 24. In some embodiments where a homoepitaxial or heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may eliminate previous and subsequent implants, but in situ doping and implant doping may be used together.

[0026] In the embodiments shown above, the fins can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0027] like Figure 1A As shown, shallow trench isolation (STI) regions 22 can be formed between the fins 24. The STI regions 22 may include materials such as oxides (e.g., silicon oxide), nitrides, etc., or combinations thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert the deposited material to another material, e.g., oxide), etc., or combinations thereof. Other materials formed by any acceptable method may be used. Once the material is formed, an annealing process may be performed. Although the STI regions 22 are shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 20 and the fins 24. Thereafter, a fill material such as the material discussed above may be formed over the liner.

[0028] After forming the material of STI region 22, a planarization process may be performed to remove the material of STI region 22 and expose fin 24. The planarization process may be, for example, chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process may expose fin 24 such that after the planarization process is completed, the top surface of fin 24 is flush with the top surface of STI region 22. In an embodiment where a mask remains on fin 24, the planarization process may expose the mask or remove the mask such that after the planarization process is completed, the top surface of the mask or fin 24, respectively, is flush with the top surface of STI region 22.

[0029] The STI region 22 may be recessed so that the top portion of the fin 24 protrudes higher than the remainder of the STI region 22. The top surface of the STI region 22 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dished), or a combination thereof. The STI region 22 may be recessed using an acceptable etching process, for example, an etching process that is selective to the material of the STI region 22 (e.g., etching the material of the STI region 22 at a faster rate than etching the material of the fin 24). The etching may be performed, for example, using a dry etching process, such as a process in which HF and NH3 are used as etching gases. According to an alternative embodiment of the present disclosure, the recessing of the STI region 22 is performed using a wet etching process. For example, oxide removal using dilute hydrofluoric acid (dHF) may be used.

[0030] Further references Figure 1A , forming a dummy gate stack 30 on the top surface and sidewalls of the fin 24. Each dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 formed on the dummy gate dielectric 32. Each dummy gate stack 30 may also include a mask layer 36 on the dummy gate electrode 34. The mask layer 36 may include one or more layers. The dummy gate stack 30 may span a single fin 24 and / or STI region 22, or multiple fins 24 and / or STI regions 22. The dummy gate stack 30 also has a length direction perpendicular to the length direction of the fin 24.

[0031] The dummy gate dielectric 32 may include, for example, silicon oxide, silicon nitride, combinations thereof, and the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate electrode 34 may be deposited on the dummy gate dielectric 32, and then planarized, for example, by CMP. The mask layer 36 may be deposited on the dummy gate electrode 34. The dummy gate electrode 34 may be a conductive or non-conductive material, and may be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate electrode 34 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known and used in the art for depositing selected materials. The dummy gate electrode 34 may be made of other materials having high etching selectivity relative to the etching of the isolation region. The mask layer 36 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, or a combination thereof. Note that dummy gate dielectric 32 is shown covering fins 24 and STI regions 22 , but in other embodiments, dummy gate dielectric 32 may be deposited such that dummy gate dielectric 32 does not extend over the surface of STI regions 22 .

[0032] Next, a gate spacer 38 is formed on the sidewall of the dummy gate stack 30. In some embodiments, thermal oxidation or deposition followed by anisotropic etching can form the gate spacer 38. According to some embodiments of the present disclosure, the gate spacer 38 is formed of a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, etc., and can be a single-layer structure or a multi-layer structure including multiple dielectric layers. After forming the gate spacer 38, an implantation for a lightly doped source / drain (LDD) region (not explicitly shown) can be performed. In some embodiments, after implanting the LDD region, one or more layers of gate spacers 38 are formed.

[0033] Still reference Figure 1A According to some embodiments, epitaxial source / drain regions 42 are formed in fins 24. An etching step (hereinafter referred to as source / drain recessing) may be performed to etch portions of fins 24 that are not covered by dummy gate stack 30 and gate spacers 38. The recessing may be an anisotropic etching process that does not etch portions of fins 24 that are directly below dummy gate stack 30 and gate spacers 38. The top surface of the recessed fin 24 may be lower than the top surface of STI region 22, as shown in FIG. Figure 1A For example, the fins 24 may be etched using a selective etch such as NF3 and NH3, HF and NH3, etc. In other embodiments, the fins 24 are not recessed before forming the epitaxial source / drain regions 42.

[0034] According to some embodiments, epitaxial source / drain regions 42 are then formed on the recessed portions of fins 24. Epitaxial source / drain regions 42 may be formed, for example, by selectively growing (one or more) semiconductor materials from the recessed portions of fins 24 to obtain Figure 1A The structure shown. According to some embodiments, the epitaxial source / drain region 42 includes silicon germanium, silicon, carbon silicon, germanium, etc., or a combination thereof. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities may be in-situ doped during the epitaxial growth process. For example, when the resulting FinFET is a p-type FinFET, silicon germanium, germanium, germanium tin, boron-doped silicon germanium (SiGeB), boron-doped germanium, etc., or a combination thereof may be grown. When the resulting FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbide (SiC), phosphorus-doped silicon carbide (SiCP), etc. may be grown. According to alternative embodiments of the present disclosure, the epitaxial source / drain region 42 is formed of a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or a multilayer thereof. The epitaxial source / drain regions 42 may also have surfaces that are raised from the corresponding surfaces of the fins 24 and may have facets. Figure 1A The structures shown are formed of structures, but the embodiments and techniques described herein can be used with Figure 1A The structures shown may be used together with other structures, embodiments or devices.

[0035] As a result of the epitaxial process used to form epitaxial source / drain regions 42, the upper surfaces of the epitaxial source / drain regions may have facets that extend laterally outward beyond the sidewalls of fins 24. In some embodiments, these facets cause adjacent source / drain regions 42 of the same FinFET to merge. Figure 1B Shown with Figure 1A 3D view of a structure similar to that shown in FIG. 4, except that adjacent source / drain regions 42 are merged. In other embodiments, such as Figure 1A As shown, adjacent source / drain regions 42 remain separated after the epitaxial process is completed. In other embodiments, fins 24 extend over STI regions 22, and gate spacers 38 are formed to cover a portion of the sidewalls of fins 24 extending over STI regions 22, thereby preventing epitaxial growth.

[0036] Steering FIG. 2A to FIG. 2D ,exist Figure 1A A first inter-layer dielectric (ILD) 48 is deposited over the structure as shown. Figure 2B Shown along Figure 1A The cross section of the cross section BB shown, Figure 2C A cross section along cross section CC is shown, and Figure 2D A cross section along cross section DD is shown. The first ILD 48 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or flowable CVD (FCVD). The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 46 is disposed between the first ILD 48 and the epitaxial source / drain regions 42 and the gate spacer 38. The CESL 46 may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, low-k material, etc.) having an etch rate different from that of the material of the overlying first ILD 48. A planarization process such as a CMP process or a mechanical grinding process may be performed to level the top surface of the first ILD 48. In some embodiments, the first ILD 48 may have a thickness T1 between about 50 nm and about 80 nm (see Figure 2B ). Other thicknesses are possible.

[0037] According to some embodiments, the dummy gate dielectric 32, the dummy gate electrode 34, and the mask layer 36 are removed, and a replacement gate stack 60 is formed. In some embodiments, the dummy gate dielectric 32, the dummy gate electrode 34, and the mask layer 36 may be removed using an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate dielectric 32, the dummy gate electrode 34, and the mask layer 36 without etching the first ILD 48 or the gate spacer 38. In some embodiments, a wet etching process or an oxide removal process may be used. In some embodiments, the dummy gate dielectric 32 is removed in a first region of the die (e.g., a core logic region) and remains in a second region of the die (e.g., an input / output region). The removal of the dummy gate dielectric 32 and the dummy gate electrode 34 forms a groove that exposes the channel region of the corresponding fin 24. During the removal, the dummy gate dielectric 32 may be used as an etch stop layer when etching the dummy gate electrode 34. The dummy gate dielectric 32 may then optionally be removed after removing the dummy gate electrode 34 .

[0038] According to some embodiments, the replacement gate stack 60 includes a gate dielectric layer 52 and a gate electrode 56. The gate dielectric layer 52 is conformally deposited in the recess, for example on the top surface and sidewalls of the fin 24 and on the sidewalls of the gate spacer 38. The gate dielectric layer 52 may also be formed on the top surface of the STI 22. According to some embodiments, the gate dielectric layer 52 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 52 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 52 may have a k value greater than about 7.0 and may include metal oxides or silicates of aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 52 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc., or a combination thereof. In embodiments where a portion of the dummy gate dielectric 32 remains in the recess, the gate dielectric layer 52 includes the material of the dummy gate dielectric 32 (e.g., SiO2).

[0039] The gate electrode 56 is deposited on the gate dielectric layer 52 and fills the remaining portion of the groove. The gate electrode 56 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although in Figure 2A and Figure 2D A single layer gate electrode 56 is shown in FIG, but the gate electrode 56 may include any number of liner layers, any number of work function adjustment layers, and fill materials. A planarization process such as CMP may be performed to remove the material of the gate electrode 56 and excess portions of the gate dielectric layer 52 that are above the top surface of the ILD 48. The material of the gate electrode 56 and the remaining portions of the gate dielectric layer 52 thus form a replacement gate 60 of the resulting FinFET. The gate electrode 56 and the gate dielectric layer 52 may be collectively referred to as a "replacement gate stack 60," "gate stack 60," or "gate structure 60." The replacement gate stack 60 may extend along the sidewalls of the channel region of the fin 24. In some embodiments, the gate stack 60 and the gate spacer 38 may have a width W1 between about 9 nm and about 30 nm (see FIG. 1 ). Figure 2C ), but other widths are possible. In some embodiments, the gate stack 60 may have a pitch P1 between about 39 nm and about 60 nm (see Figure 2C ), but other spacing distances are possible.

[0040] The formation of the gate dielectric layer 52 in different regions of the wafer 10 may occur simultaneously, such that the gate dielectric layer 52 in each region is formed of the same material, and the formation of the gate electrode 56 may occur simultaneously, such that the gate electrode 56 in each region is formed of the same material. In some embodiments, the gate dielectric layer 52 in each region may be formed by a different process, such that the gate dielectric layer 52 may be a different material, and / or the gate electrode 56 in each region may be formed by a different process, such that the gate electrode 56 may be a different material. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0041] Still reference Figure 2A-2D According to some embodiments, a hard mask 62 may be formed over the gate stack 60. The hard mask 62 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, etc., or a combination thereof. The formation of the hard mask 62 may include using one or more etching processes to recess the gate stack 60 (including the gate dielectric layer 52 and the corresponding overlying gate electrode 56) to form a groove, so that the groove is formed directly above the gate stack 60 and between the opposing portions of the gate spacer 38. Figure 2A and Figure 2C As shown, the gate spacer 38 may also be etched. Then, a dielectric material is filled into the recess, and a planarization process is performed to remove excess portions of the dielectric material. The remaining portions of the dielectric material form a hard mask 62. In some embodiments, one or more additional dielectric layers may be formed over the recessed gate electrode 56 before forming the hard mask 62, which may include, for example, an etch stop layer.

[0042] exist Figure 3 In some embodiments, a second ILD 64 is deposited over the first ILD 48. In some embodiments, the second ILD 64 is a flowable film formed by a flowable CVD (FCVD) method. In some embodiments, the second ILD 64 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. In some embodiments, the second ILD 64 can have a thickness between about 10nm and about 90nm. Other thicknesses are possible.

[0043] Still refer to Figure 3According to some embodiments, a hard mask layer 66 is formed over the second ILD 64. In some embodiments, the hard mask layer 66 may be formed of a material including a metal, for example, a material including the following: titanium nitride (TiN); titanium; tantalum nitride; tantalum; a metal-doped carbide (e.g., tungsten carbide (WC), etc.); and / or a metalloid (e.g., silicon nitride, boron nitride, silicon carbide, etc.); or a combination thereof. In some embodiments, the material composition of the hard mask layer 66 may be determined to provide a high etch selectivity relative to other layers such as the second ILD 64 and / or relative to other subsequently formed layers. The hard mask layer 66 may be formed by a process such as CVD, ALD, etc. However, any suitable process and material may be used. In some embodiments, the thickness of the hard mask layer 66 is between about 10 nm and about 30 nm, but other thicknesses are also possible.

[0044] In some embodiments, a cap layer 67 is formed over the hard mask layer 66. The cap layer 67 may be, for example, an oxide (e.g., silicon oxide, etc.), which may be formed using FCVD, CVD, PECVD, etc. In some embodiments, the cap layer 67 is a low temperature oxide (e.g., an oxide deposited using a process temperature of 200°C or less). Other suitable techniques or materials may be used. In some embodiments, the cap layer 67 may have a thickness between about 20nm and about 60nm. Other thicknesses are possible. According to some embodiments, a mask layer 68 is then formed over the cap layer 67. The mask layer 68 may be formed of a suitable material that provides high etching selectivity relative to other layers such as the cap layer 67 or the hard mask layer 66. For example, the mask layer 68 may include silicon or amorphous silicon, but other materials are also possible. In some embodiments, the mask layer 68 may have a thickness between about 20nm and about 50nm. Other thicknesses are possible.

[0045] Figures 3 to 11C The formation of source / drain contacts 112 (see FIG. Figures 11A-11C ) various views of the intermediate steps of . Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A and Fig.11A A plan view of the structure is shown. Figure 3 , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B and Fig. 11B Shown along Figure 1AA cross-sectional view of reference cross section BB is shown. Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 10C and Fig. 11C Shown along Figure 1A A cross-sectional view of reference cross section CC is shown. The various views shown in the drawings are illustrative examples, and other configurations or arrangements different from those shown are considered to be within the scope of the present disclosure. In some of the drawings, some features have been omitted for clarity.

[0046] exist FIG. 4A to FIG. 4C In some embodiments, a photoresist structure 69 is formed on the mask layer 68, and the photoresist structure 69 is patterned to have a cutout pattern 74. The cutout pattern 74 is used to define the adjacent source / drain contacts 112 (see Figures 11A-11C )Separated cutout area 111. Figure 4A A plan view illustrating a cut pattern 74 over a plurality of gate stacks 60 (which may include gate spacers 38 ) and a plurality of fins 24 (which may include epitaxial source / drain regions 42 ) is shown in accordance with some embodiments. Figure 4A are illustrative examples, and some features and layers are omitted for clarity. Additionally, the cutout pattern 74, gate stack 60, fin 24, and / or epitaxial source / drain regions 42 may be different than shown, or have a different configuration than shown. For example, similar to Figure 1B In the embodiment shown, two or more fins 24 may be adjacent. As another example, portions of the cutout pattern 74 may have different sizes, different quantities, or different arrangements than shown. Other variations or configurations besides these are possible and are considered within the scope of the present disclosure. Figure 4B Shows that along with Figure 4A The cross section BB shown in FIG. 5 is a view of a cross section similar to that in FIG. 6 , wherein the cross section is parallel to the gate stacks 60 and between the two gate stacks 60 . Figure 4C Shows that along with Figure 4A The cross section CC shown in FIG. 2 is a view of a cross section similar to that in FIG. 2 , wherein the cross section is parallel to the fin 24 and along the fin 24 .

[0047] Figure 4A-4C The illustrated photoresist structure 69 is a three-layer photoresist structure including a bottom layer 70 , a middle layer 71 , and an upper layer 72 . Figure 4A-4CThe photoresist structure 69 is shown after the upper layer 72 has been patterned to have a cut pattern 74. In other embodiments, the photoresist structure 69 may have other numbers of layers. In some cases, the use of a three-layer photoresist structure 69 may allow for improved clarity of the cut pattern 74. The upper layer 72 may be formed of a photoresist (e.g., a photosensitive material) including an organic material, and may be a positive photosensitive material or a negative photosensitive material. In some embodiments, the bottom layer 70 is formed of a polymer material and may be a bottom anti-reflective coating (BARC) layer. The intermediate layer 71 may include an inorganic material, which may be a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), etc., or a combination thereof. The intermediate layer 71 may have a high etching selectivity relative to the upper layer 72 and / or the bottom layer 70. The various layers of the photoresist structure 69 may be sequentially blanket deposited using, for example, a spin coating process and / or an appropriate deposition process. Although a three-layer photoresist structure 69 is discussed herein, in other embodiments, the photoresist structure 69 may be a single-layer structure or a double-layer structure (e.g., including only a bottom layer 70 and an upper layer 72 without an intermediate layer 71). The type of structure used (e.g., a single-layer, double-layer, or triple-layer) may depend on the photolithography process used. For example, in an extreme ultraviolet (EUV) photolithography process, a single-layer or double-layer may be used. Figure 4A-4C The depicted photoresist structure 69 is an example, and photoresist structures including other layers, materials, or combinations thereof are possible.

[0048] A suitable photolithography process may be used to form pattern 74 in upper layer 72. In some embodiments, cut pattern 74 defines a cut mask 76 (see Figure 5A-Figure 5C ). Subsequently, the upper layer 72 can be used as an etching mask for patterning the middle layer 71 (not shown separately in the figure) using an etching process. The etching process can be anisotropic so that the openings in the upper layer 72 extend through the middle layer 71. The middle layer 71 is then used as an etching mask for patterning the bottom layer 70 (not shown separately in the figure) using an etching process. The etching process can be anisotropic so that the openings in the middle layer 71 extend through the bottom layer 70. As part of etching the bottom layer 70, the upper layer 72 can be consumed.

[0049] refer to Figure 4A According to some embodiments, the cutout pattern 74 may include one or more serpentine portions 74S and a plurality of island portions 74I. The serpentine portions 74S and the island portions 74I extend across two or more gate stacks 60 (e.g., along the CC direction) to define a subsequently formed cutout region 111 that isolates (e.g., “cuts”) adjacent source / drain contacts 112 (see Figures 11A-11C). Some example locations where the cutout region 111 is subsequently formed are Figure 4A . A pair of adjacent cutout regions 111 has a separation distance D1, which may be different for different pairs of cutout regions 111. In some cases, using both serpentine portions 74S and island portions 74I for the cutout pattern 74 may allow the formation of closer cutout regions 111 without unnecessarily bridging the cutout pattern 74 or increasing contact resistance due to rounding of the source / drain contacts 112, which will be described in more detail below. By forming cutout regions 111 with a smaller separation distance D1, the area of ​​the source / drain contacts 112 may be increased, and the density of the source / drain contacts 112 may be increased. For example, in some cases, the techniques described herein may allow the formation of cutout regions 111 with a separation distance D1 between about 5 nm and about 30 nm, for example, less than 16 nm, but other distances are possible.

[0050] like Figure 4A As shown, the serpentine portion 74S may include a continuous region of the cutout pattern 74, which includes a plurality of cutout portions 74C and a plurality of bridge portions 74B. The cutout portion 74C is a substantially straight region of the serpentine portion 74S, which extends between adjacent gate stacks 60 (e.g., substantially along the CC direction) to define a subsequently formed cutout region 111. The cutout portion 74C may extend between two or more adjacent gate stacks 60. The bridge portion 74B is a substantially straight region of the serpentine portion 74S, which extends along the gate stack 60 (e.g., substantially along the BB direction) and extends between the cutout portions 74C. The bridge portion 74B may extend over one or more adjacent fins 24. The bridge portion 74B is connected to the cutout portion 74C, and the bridge portion 74B and the cutout portion 74C may be approximately perpendicular. The different parallel cutout portions 74C may be vertically offset (eg, offset along the BB direction), and thus the serpentine portion 74S may have a curved or meandering shape, meandering over some locations where the cutout regions 111 are to be subsequently formed. Figure 4A As shown, the serpentine portion 74S may include a series of connected similarly shaped regions (e.g., including periodic or repeating shapes), but the shapes of the regions or their arrangements may be different from those shown. In other embodiments, some or all of the serpentine portions 74S do not have repeating shapes. Figure 4A The serpentine portion 74S shown in FIG. 7 is an example, and in other embodiments, the serpentine portion 74S may include a bridge portion 74B and a cutout portion 74C having different dimensions or being at a different location than shown.

[0051] like Figure 4AAs shown, the bridge portion 74B can extend substantially along a direction at an angle A1 relative to the connected cutout portion 74C. Angle A1 can be measured at one end of the bridge portion 74B and on a side of the bridge portion 74B facing the cutout portion 74C on the opposite end of the bridge portion 74B. Figure 4A The bridge portion 74B is shown to be approximately perpendicular to (e.g., orthogonal to) the cutout portion 74C, and therefore has an angle A1 of approximately 90°. However, in other embodiments, the angle A1 can be between approximately 60° and approximately 90°. In some embodiments, the angle A1 is within approximately 30° of the longitudinal direction of the gate stack 60. In this manner, the angle A1' formed by the bridge portion 74B and the adjacent cutout portion 74C can be between approximately 90° and approximately 120°. By forming the serpentine portion 74S at an angle A1 greater than approximately 60° (e.g., having a nearly vertical portion), a cutout region 111 with less rounding can be formed, and the area of ​​the source / drain contact 112 can be increased (which will be for Fig.12 described in more detail).

[0052] The island portion 74I is separated from other island portions 74I or from the serpentine portion 74S. The island portion 74I may extend between two or more gate stacks 60 (eg, in the CC direction) and may have different sizes. Figure 4A As shown, some island portions 74I may be located between the cutout portions 74C of the serpentine portion 74S. In some embodiments, some island portions 74I may be located between the bridge portions 74B of the serpentine portion 74S. In some embodiments, some island portions 74I may be located between two different serpentine portions 74S (not shown).

[0053] FIG. 5A to FIG. 5C Patterning of mask layer 68 to form kerf mask 76 is shown in accordance with some embodiments. Figure 5A-Figure 5C Shown with Figure 4A-4CSimilar view. The mask layer 68 can be patterned using the patterned photoresist structure 69 as an etching mask. In this way, the cut mask 76 is patterned using the previously described cut pattern 74 and thus has a similar pattern. For example, similar to the cut pattern 74, the cut mask 76 can have an island portion 76I and a serpentine portion 76S. In addition, the serpentine portion 76S may include a bridging portion 76B and a cut portion 76C, similar to the bridging portion 74B and the cut portion 74C of the cut pattern 74. The patterning of the mask layer 68 can be performed using an anisotropic etching process so that the opening in the patterned photoresist structure extends through the mask layer 68, thereby transferring the cut pattern 74 to the mask layer 68. The etching process can be, for example, an anisotropic dry etching process, and can be performed using a process gas such as Cl2, NF3, HBr, CF4, etc., or a combination thereof.

[0054] The size or shape of the notch mask 76 can be approximately the same as the notch pattern 74. For example, the notch mask 76 can have a bridge portion 76B extending from the notch portion 76C at an angle A1, wherein the angle A1 is between about 60° and about 90°. In some cases, having an angle A1 greater than about 60° can reduce rounding of the notch mask 76 during patterning, and thus can allow the source / drain contacts 112 to have a larger contact area (which will be for Figure 12-13 100 ). In some embodiments, the bridging portion 76B can have a length LB between about 5 nm and about 30 nm, although other lengths are possible. The bridging portion 76B can have a width WB between about 0.5 nm and about 25 nm, although other widths are possible. In some embodiments, the width WB can be between about 0.016% and about 100% of the width W1 of the gate stack 60 and the spacer 38. In some cases, a bridging portion 76B having a smaller width WB can allow the source / drain contact 112 to have an increased area. This is discussed below with respect to Fig.13 Detailed description. In some embodiments, the cutout portion 76C may have a length LC between about 39 nm and about 60 nm, but other lengths are possible. In some embodiments, the length LC may be between about 100% and about 180% of the pitch P1 of the gate stack 60. In some embodiments, the length LC may be such that the sides of the cutout portion 76C protrude beyond the sides of the connected bridge portion 76B. Fig.13 This is illustrated in the embodiment shown. In some embodiments, the cutout portion 76C can have a width WC between about 15 nm and about 200 nm, but other widths are possible. The width WC defines the width of each cutout region 111, and therefore defines the adjacent source / drain contact 112 (see FIG. Figures 11A-11C and Fig.12 ) between adjacent fins 24. In some embodiments, width WC may be between about 25% and about 1000% of width W2 between adjacent fins 24. In some embodiments, a smaller width WC may allow source / drain contacts 112 to have an increased area.

[0055] exist FIG. 6A to FIG. 6C In accordance with some embodiments, a photoresist structure 79 is formed over kerf mask 76 and patterned to form openings 83 . Figure 6A-6C Shown with Figure 5A-Figure 5C Opening 83 may define a larger area of ​​wafer 10 in which contact opening 84 and kerf region 111 are subsequently formed (see Figure 9A-9C and Figures 11A-11C ). In this way, the opening 83 can extend between adjacent gate stacks 60 and over the epitaxial source / drain regions 42 along the BB direction. Fig. 6A The notch mask 76 is indicated in dashed outline in FIG.

[0056] Figure 6A-6C The illustrated photoresist structure 79 is a three-layer photoresist structure including a bottom layer 80 , a middle layer 81 , and an upper layer 82 . Figure 6A-6C The photoresist structure 79 shown may be similar to that for Figure 4A-4C The photoresist structure 69 described above is similar to the photoresist structure 69. For example, the bottom layer 80 can be similar to the bottom layer 70, the middle layer 81 can be similar to the middle layer 71, or the upper layer 82 can be similar to the upper layer 72. The various layers of the photoresist structure 79 can be sequentially blanket deposited using, for example, a spin coating process and / or an appropriate deposition process. Figure 6B-6C As shown, a bottom layer 80 is formed on the cap layer 67 and the cut mask 76. An intermediate layer 81 is formed on the bottom layer 80, and an upper layer 82 is formed on the intermediate layer 81. Figure 6A-6C The depicted photoresist structure 79 is an example, and photoresist structures including other layers, materials, or combinations thereof are possible.

[0057] Figure 6A-6CThe photoresist structure 79 is shown after the upper layer 82 has been patterned using, for example, a suitable photolithography process. Subsequently, the upper layer 82 can be used as an etching mask for patterning the middle layer 81 (not shown separately in the figure) using an etching process. The etching process can be anisotropic so that the openings 83 in the upper layer 82 extend through the middle layer 81. The middle layer 81 is then used as an etching mask for patterning the bottom layer 80 (not shown separately in the figure) using an etching process. The etching process can be anisotropic so that the openings in the middle layer 81 extend through the bottom layer 80. As part of etching the bottom layer 70, the upper layer 82 can be consumed. In some embodiments, two or more photolithography patterning steps (e.g., using a multi-patterning process) can be used to form the openings 83 in the photoresist structure 79.

[0058] exist 7A to 7C In accordance with some embodiments, patterned photoresist structure 79 and kerf mask 76 are used as a combined etch mask to pattern contact openings 84 in capping layer 67 . Figure 7A-7C Shown with Figure 6A-6C Contact opening 84 may define a larger area of ​​wafer 10 in which source / drain contacts 112 may be formed (see FIG. Figures 11A-11C ). The contact opening 84 is separated from the cutout region 111 in the BB direction. For reference, the cutout region 111 and the region where the cutout mask 76 has been previously formed are Figure 7A-7C Indicated by the dashed outline. Figure 7A-7C As shown, the notch area 111 can be defined by the notch mask 76. The patterning of the cap layer 67 can be performed using an anisotropic etching process so that the opening 83 in the patterned photoresist structure 79 extends through the cap layer 67, except for the area where the notch mask 76 is present. The etching process can be, for example, an anisotropic dry etching process, and can be performed using a process gas such as Cl2, NF3, HBr, CF4, etc., or a combination thereof. The patterning of the cap layer 67 can remove the remaining portions of the photoresist structure 79 or the notch mask 76, or these remaining portions can be removed after the patterning of the cap layer 67 using, for example, an ashing process, a wet chemical process, etc. In some cases, portions of the notch mask 76 can remain after the patterning of the cap layer 67.

[0059] exist FIG. 8A to FIG. 8C In accordance with some embodiments, contact opening 84 formed in capping layer 67 is extended through hard mask layer 66 using an etching process. Figure 8A-8C Shown with Figure 7A-7CSimilar views. The etching of hard mask layer 66 can be performed using an anisotropic etching process so that the contact opening 84 in the patterned cap layer 67 extends through the hard mask layer 66. The etching process can be, for example, an anisotropic dry etching process and can be performed using a process gas such as Cl2, NF3, HBr, CF4, etc., or a combination thereof. The etching of hard mask layer 66 can thin the remaining portion of cap layer 67, or remove the remaining portion of cap layer 67. In some embodiments, a single etching process is used to pattern cap layer 67 and hard mask layer 66.

[0060] exist 9A to 9C In accordance with some embodiments, contact openings 84 formed in hard mask layer 66 are extended through second ILD 64 , first ILD 48 , and CESL 46 to expose epitaxial source / drain regions 42 . Figure 9A-9C Shown with Figure 8A-8C Similar views. In some cases, using a cut pattern 94 having relatively vertical portions as previously described may allow more of the epitaxial source / drain regions 42 to be exposed by the contact openings 84, which may reduce contact resistance and improve device performance.

[0061] According to some embodiments, one or more dry etching processes may be used to etch Figure 9A-9C The contact opening 84 shown. The etching process can have a high etching selectivity to the second ILD 64, the first ILD 48 and / or the CESL 46 relative to the hard mask layer 66. In some embodiments, the dry etching process may include anisotropic plasma etching with a plasma generated at a power of about 50 watts to about 500 watts, and may be performed at a pressure of about 3 mTorr to about 200 mTorr. In some embodiments, the dry etching process may use one or more process gases, such as CF4, C4F6, C4F8, CH2F2, CHF3, other fluorine-based gases, O2, CO, CO2, H2, CH4, etc., or other types of process gases. In some embodiments, the etching process may be followed by a wet cleaning process, which may include the use of dHF (e.g., dilute HF), SC-1, etc. Other etching techniques may be used in other embodiments. During etching, the cap layer 67 may be consumed, and the hard mask layer 66 may be at least partially consumed.

[0062] exist FIG. 10A to FIG. 10C In accordance with some embodiments, a contact material 112 ′ is formed over the structure and within the contact opening 84 . Figure 10A-10C Shown with Figure 9A-9CSimilar views. The contact material 112' may include a liner and a conductive material (not shown separately in the figure). The liner may be, for example, a diffusion barrier layer, an adhesion layer, etc., and may include materials such as titanium, titanium nitride, tantalum, tantalum nitride, etc., or a combination thereof. The conductive material may include, for example, copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc., or a combination thereof. The liner and / or the conductive material may be formed using a suitable process, such as ALD, CVD, PVD, electroplating, etc., or a combination thereof. In some embodiments, a silicide (not shown in the figure) may be formed at the interface between the epitaxial source / drain region 42 and the contact material 112'.

[0063] exist FIG. 11A to FIG. 11C In accordance with some embodiments, a planarization process such as CMP is performed on the contact material 112 ′ to form the source / drain contacts 112 . Figures 11A-11C Shown with Figure 10A-10C Similar views. In some embodiments, planarization removes the upper portion of the hard mask layer 66, the second ILD 64, and the contact material 112'. The remaining liner and conductive material form the source / drain contact 112. In some embodiments, the planarization process can also thin the first ILD 48. After the planarization process, the top surface of the source / drain contact 112 can be substantially flush with the top surface of the first ILD 48.

[0064] Although not explicitly shown, it will be readily understood by those skilled in the art that Figures 11A-11C Further process steps may be performed on the structures in the second ILD 614. For example, a gate contact may be formed to contact the gate stack 60, or various intermetallic dielectrics (IMDs) and their corresponding metallizations may be formed over the first ILD 48. Embodiments including a gate contact 612A formed in the second ILD 614, a source / drain contact 612B, and a metal line 616 formed in the IMD 618 will be described below with respect to Figure 32A-Figure 35C Give a description.

[0065] like Figures 11A-11CAs shown, the source / drain contacts 112 can be separated in the BB direction by the cut region 111 including the first ILD 48. In some embodiments, the cut region 111 can have a cut length D2 (in the BB direction) between about 15nm and about 220nm, but other lengths are possible. In some cases, forming the cut region 111 using the technology described herein can allow a smaller cut length D2, which can increase the contact area of ​​the source / drain contact 112, which can improve the contact resistance and reduce the sensitivity to process variations. Forming the cut region 111 as described herein can also allow a smaller minimum separation distance D1 between the cut regions 111 without increasing the risk of bridging during the photolithography or etching steps. In this way, the density, spacing, yield and electrical performance of the device can be improved. In some embodiments, the source / drain contact 112 can have a length D3 (in the BB direction) between about 25nm and about 500nm, but other lengths are also possible. In some embodiments, source / drain contacts 112 may have a width W3 (in the CC direction) between about 15 nm and about 50 nm, although other widths are possible. In some embodiments, source / drain contacts 112 may be separated by a width W4 (in the CC direction) between about 9 nm and about 30 nm, although other widths are possible. In some cases, width W4 is about the same as width W1 (see FIG. Figure 2C ) are roughly the same.

[0066] In some cases, the lithography or etching steps may form the notch mask 76 with rounded corners. By forming the notch mask 76 with a serpentine portion 76S (having an angle A1 greater than about 60° (e.g., having a relatively vertical portion)), the notch mask 76 can be formed to have less rounding, and the area of ​​the notch region 111 can be formed to have a smaller area. By forming the notch region 111 with a smaller area, the area of ​​the source / drain contact 112 can be increased accordingly. Increasing the area of ​​the source / drain contact 112 can increase conductivity, and can increase the contact area between the source / drain contact 112 and the epitaxial source / drain region 42, which can reduce contact resistance. In addition, by forming the notch region 111 with less rounding and a smaller area, the notch region 111 can be more densely patterned during the lithography and etching steps without increasing the risk of the notch region 111 not being completely separated (e.g., "bridging"). For example, by reducing the rounding or area of ​​the cutout region 111, the cutout region 111 may be formed to have a smaller separation distance D1 (see Figure 4A ). In this way, finer feature sizes can be formed without sacrificing yield or device reliability.

[0067] exist Fig.12This increase in area of ​​the source / drain contact 112 is shown in FIG. Fig.12 Shown with Fig.11A An example plan view of an area similar to area 113 is shown in FIG. Fig.12 The illustrated region 113 includes source / drain contacts 112 separated by cutout region 111. Example cutout region 111A is shown separating source / drain contacts 112A and 112B. For purposes of illustration, Fig.12 Also shown are the profile of the serpentine portion 76S-A of the notch mask having a relatively large vertical angle A1 (e.g., greater than about 60°) and the profile of the serpentine portion 76S-B of the notch mask having a relatively small vertical angle A2 (e.g., less than about 60°).

[0068] In some embodiments, by using a serpentine portion 76S-A having a steeper angle A1, rounding during the photolithography and etching steps can be reduced, and a kerf region 111 having a smaller kerf length D2 can be formed. In some cases, the shallower angle A2 of the serpentine portion 76S-B may result in increased rounding of the kerf mask 76 during photolithography patterning, which may result in an increase in the kerf length D2-B. The rounded kerf mask 76 may result in the kerf region 111A having a rounded region 111A′ (in Fig.12 The circular region 111A′ can increase the cut length of the cut region 111A, such as Fig.12 In some embodiments, the use of the serpentine portion 76S-A having a steeper angle A1 can reduce the rounding of the kerf mask 76, which can reduce the size of the circular region 111A'. In the absence of the circular region 111A', a kerf region 111A with a smaller kerf length can be formed, such as Fig.12 As shown by the shorter incision length D2-A.

[0069] for Fig.12In the example shown, serpentine portion 76S-A is used instead of serpentine portion 76S-B, and the area of ​​source / drain contacts 112A and 112B is increased by reducing the size of circular area 111A' and reducing the cut length D2. Therefore, in some embodiments, using a cut mask 76 with a relatively large angle A1 can form a source / drain contact 112 with a larger area and a smaller cut length D2 than using a cut mask 76 with a relatively small angle A2. In some embodiments, angle A1 can be greater than about 60°, but other angles are possible. In some embodiments, the cut area 111 can be formed with little or no rounding, and thus can be formed to have substantially straight sides (e.g., as shown in cut area 111A). In some embodiments, the cut area 111 can be formed to have a circular area 111A' on one side and none on the other side. For example, a circular area 111A' at the source / drain contact 112B may be formed for the cutout region 111A, but a circular area 111A' at the source / drain contact 112A may not be formed for the same cutout region 111A. In this way, the cutout portion 76C (and the resulting cutout region 111) may have a straight side and a concave side. In other cases, the cutout portion 76C (and the resulting cutout region 111) may have a straight side and a convex side, a concave side and a convex side, or two convex sides. Increasing the area of ​​the source / drain contact 112 by using a larger angle A1 as described herein can improve device performance by increasing conductivity and reducing contact resistance.

[0070] In some cases, a source / drain contact 112 having a larger area may be formed using a serpentine portion 76S with a bridge portion 76B having a smaller width WB. Fig.13 This increase in area of ​​the source / drain contact 112 is shown in FIG. Fig.13 Shown with Fig.11A Example plan view of an area similar to area 113 marked in FIG. 1 (note that Fig.13 The area shown in FIG. 1 is wider than area 113 in the CC direction). Fig.13 Region 113 is shown including source / drain contacts 112 separated by cutout region 111. Example cutout region 111C is shown separating source / drain contacts 112C and 112D. For illustration purposes, Fig.13 Also shown are the profile of the serpentine portion 76S-C of the kerf mask having a relatively smaller width WB-C and the profile of the serpentine portion 76S-D of the kerf mask having a relatively larger width WB-D.

[0071] like Fig.13As shown, the larger width WB-D of the bridge portion 76B may cause the serpentine portion 76S-D to overlap with the source / drain contact 112. The area where the serpentine portion 76S-D overlaps with the source / drain contact 112 is defined by the overlap region 112C′ (at Fig.13 The cutout region 111C is formed in the overlap region 112C', and thus the presence of the overlap region 112C' may reduce the area of ​​the subsequently formed source / drain contact 112. By forming a serpentine portion 76S-C having a smaller width WB-C, the size of the overlap region 112C' is reduced or eliminated. In this way, the reduction in the area of ​​the source / drain contact 112 due to the overlap region 112C' can be avoided. In some embodiments, the width WB is between about 0.016% and about 100% of the width W2, but other percentages are possible. In some cases, the width WB can be determined based on the angle A1. As previously described, forming a source / drain contact 112 with a larger area can improve device performance by increasing conductivity and reducing contact resistance.

[0072] FIG. 11A to FIG. 11C An embodiment is shown in which a notch mask 76 having a serpentine portion 76S is used to form a notch region 111 between source / drain contacts 112. The serpentine portion 76S has a bridge portion 76B that is approximately perpendicular to the adjacent notch portion 76C, which can allow, for example, a larger area for the source / drain contact 112. However, a notch mask having a vertical serpentine portion can be used to form "notches" in other features or structures. FIG. 14A to FIG. 35C According to some embodiments, a method for Figures 11A-11C An example process flow for forming “cutouts” among other features during the formation of a similar FinFET device is shown. Figure 14A-Figure 35C The process flow in uses a serpentine pattern with approximately orthogonal sections, similar to the serpentine section 76S. Figure 14A-Figure 35C One or more of the process flows shown may be used, for example, Figures 11A-11C used during the formation of the device shown. FIG. 14A to FIG. 18C An intermediate step of forming a notch region 211 in the fin 24 prior to forming the STI region 22 is shown. FIG. 19A to FIG. 23C An intermediate step of forming a notch region 311 in the fin 24 after forming the STI region 22 is shown. Figure 24A-Figure 27C An intermediate step of forming a notched region 411 in the dummy gate stack 30 is shown. Figures 28A-31C An intermediate step of forming a notched region 511 in the replacement gate stack 60 is shown. Figure 32A-Figure 35C An intermediate step of forming kerf regions 611 in metal lines 616A-B is shown. Figure 14A-Figure 35CThe process flows shown are illustrative examples, and the techniques described herein and variations thereof may be combined or used to form other structures. Figure 14A-Figure 35C The island-like portion of the cutout pattern is not shown (e.g., similar to Figure 4A , but it should be understood that the cut pattern may include various arrangements or combinations of island portions and / or serpentine portions.

[0073] FIG. 14A to FIG. 18C The formation of a cutout region 211 in the fin 24 is shown in accordance with some embodiments. Fig.14A , Fig.15A , Fig.16A , Fig.17A and Fig.18A A plan view of wafer 200 is shown. Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B and Fig.18B Shown along Fig.14A The cross-sectional view of the reference cross section DD shown in FIG. 1 also corresponds to Figure 1A Reference cross section DD shown. Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C and Fig.18C Shown along Fig.14A The cross-sectional view of the reference cross section CC shown also corresponds to Figure 1A Reference cross section CC shown.

[0074] Figure 14A-Figure 14C A wafer 200 is shown with fins 24 formed in a substrate 50. The fins 24 may be formed in the same manner as previously described for Figure 1A In a similar manner as described above. Figure 15A-Figure 15C In the embodiment of the present invention, a photoresist structure 269 is formed and patterned to have an opening in the serpentine pattern 274S. The photoresist structure 269 may be similar to Figure 4A-4C The photoresist structure 69 shown in FIG. 1 and may be formed in a similar manner. Fig.15A As shown, the serpentine pattern 274S includes a bridge portion 274B and a cutout portion 274C (the bridge portion 274B and the cutout portion 274C may be approximately orthogonal to each other), similar to Figure 4A-4C The serpentine pattern 274S exposes the fin 24 where the cutout area 211 is to be formed (see Figure 16A-16C The serpentine pattern 274S may be formed in the photoresist structure 269 using appropriate photolithography techniques.

[0075] exist Figure 16A-16CIn FIG. 2 , an etching process is performed using the patterned photoresist structure 269 as an etching mask to etch the fin 24 and form the cutout region 211. For reference, in FIG. Fig.16A The serpentine pattern 274S is shown in FIG. The etching process may include one or more suitable etching processes, for example, a dry etching process and / or a wet etching process. The cutout region 211 is a region where the fin 24 has been removed and is defined by the serpentine pattern 274S.

[0076] exist Figure 17A-17C In the embodiment of the present invention, an insulating material 22 is deposited on the wafer 200 and within the cutout region 211. The insulating material 22 may be similar to that for Figure 1A The STI regions 22 may be formed of materials similar to those described above. Figures 18A-18C In the embodiment, the insulating material 22 is recessed to form the STI region 22. The recess can be similar to the previous embodiment for Figure 1A The STI region 22 surrounds the fins 24 and forms a notch between the fins 24 in the notch region 211. By forming the notch region 211 between the fins 24 using a serpentine pattern 274S having approximately orthogonal portions, rounding can be reduced, which can reduce the separation distance between the notch regions 211 without increasing the risk of process defects.

[0077] FIG. 19A to FIG. 23C A cutout region 311 is shown formed in the fin 24 in accordance with some embodiments. Fig.19A , Fig. 20A , Fig.21A , Fig.22A and Fig.23A A plan view of wafer 300 is shown. Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B and Fig. 23B Shown along Fig.19A The cross-sectional view of the reference cross section DD shown in FIG. 1 also corresponds to Figure 1A Reference cross section DD shown. Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C and Fig.23C Shown along Fig.19A The cross-sectional view of the reference cross section CC shown also corresponds to Figure 1A Reference cross section CC shown.

[0078] Figure 19A-Figure 19C A wafer 300 is shown with fins 24 formed in a substrate 50 in accordance with some embodiments. The fins 24 may be formed in the same manner as previously described for Figure 1A or Figures 14A-16C In a similar manner as described above. Figure 20A-20C In the embodiment, STI region 22 is formed to surround fin 24. STI region 22 may be formed in the same manner as previously described for Figure 1A In a similar manner as described above. Figure 21A-Figure 21C In the embodiment of the present invention, a photoresist structure 369 is formed and patterned to have an opening in the serpentine pattern 374S. The photoresist structure 369 may be similar to Figure 4A-4C The photoresist structure 69 shown in FIG. 1 and may be formed in a similar manner. Fig.21A As shown, the serpentine pattern 274S includes portions that may be approximately orthogonal to each other, similar to Figure 4A-4C The serpentine portion 74S and Fig.16A The serpentine pattern 274S shown. The serpentine pattern 374S exposes the fin 24 where the cutout area 311 is to be formed (see Figure 22A-22C The serpentine pattern 374S may be formed in the photoresist structure 369 using appropriate photolithography techniques.

[0079] exist Figure 22A-22C In the embodiment of the present invention, an etching process is performed using the patterned photoresist structure 369 as an etching mask to etch the fin 24 and form the cutout region 311. In some embodiments, the etching process may selectively etch the fin 24 when etching the STI region 22, such as Fig. 22B As shown. The etching process may include one or more suitable etching processes, for example, a dry etching process and / or a wet etching process. The cutout region 311 is a region where the fin 24 has been removed, and is defined by the serpentine pattern 374S.

[0080] exist Figure 23A-23C In the embodiment of the present invention, a filling material 302 is deposited on the wafer 300 and within the cutout region 311. The filling material 302 may include one or more suitable dielectric materials, such as oxides, nitrides, etc., or a combination thereof. The filling material 302 may be deposited using a suitable process. In some embodiments, an etch-back process is performed to remove an upper portion of the filling material 302, such as Figure 23B-Figure 23C As shown. The etch-back process may include one or more suitable etching processes, for example, a dry etching process and / or a wet etching process. By using a serpentine pattern 374S having approximately orthogonal portions to form the cutout regions 311 between the fins 24, rounding may be reduced, which may reduce the separation distance between the cutout regions 311 without increasing the risk of process defects.

[0081] FIG. 24A to FIG. 27C The formation of a notched region 411 in the dummy gate stack 30 (eg, in the dummy gate dielectric 32 and the dummy gate electrode 34 ) is shown in accordance with some embodiments. Fig.24A , Fig.25A , Fig.26A and Fig.27A A plan view of wafer 400 is shown. Fig. 24B , Fig.25B , Fig.26B and Fig.27B Shown along Fig.24A The cross-sectional view of the reference cross section DD shown in FIG. 1 also corresponds to Figure 1A Reference cross section DD shown. Fig.24C , Fig.25C , Fig.26C and Fig.27C Shown along Fig.24A The cross-sectional view of the reference cross section EE shown also corresponds to Figure 1A The reference cross section EE is shown. The reference cross section EE is parallel to the longitudinal direction of the fin 24 (at Fig.24A ), but is located between the fins 24.

[0082] Figure 24A-24C 4 shows a wafer 400 having a dummy gate dielectric 32, a dummy gate electrode 34, and a mask layer 36 formed over the fin 24. The dummy gate dielectric 32, the dummy gate electrode 34, and the mask layer 36 may be formed in the same manner as previously described for the fin 24. Figure 1A In a similar manner as described. Figure 25A-Figure 25C In the process, the dummy gate dielectric 32, the dummy gate electrode 34 and the mask layer 36 are patterned to form the dummy gate stack 30. The dummy gate stack 30 may be formed using appropriate photolithography and etching techniques.

[0083] exist Figure 26A-26C In the embodiment of the present invention, a photoresist structure 469 is formed and patterned to have an opening in the serpentine pattern 474S. The photoresist structure 469 may be similar to Figure 4A-4C The photoresist structure 69 shown in FIG. 1 and may be formed in a similar manner. Fig.26A As shown, the serpentine pattern 474S includes portions that may be approximately orthogonal to each other, similar to Figure 4A-4C The serpentine portion 74S and Fig.16A The serpentine pattern 274S shown. The serpentine pattern 474S exposes the cutout region 411 in the mask layer 36 (see Figure 27A-27C The serpentine pattern 474S may be formed in the photoresist structure 469 using appropriate photolithography techniques.

[0084] exist Figure 27A-27CIn the embodiment, an etching process is performed using the patterned photoresist structure 469 as an etching mask to etch the mask layer 36 and the dummy gate stack 30, thereby forming a cutout region 411. In some embodiments, the etching process may selectively etch the mask layer 36 and the dummy gate stack 30 when etching the STI region 22, such as Figure 27B-Figure 27C As shown. The etching process may include one or more suitable etching processes, such as a dry etching process and / or a wet etching process. The cutout region 411 is an area where the dummy gate stack 30 has been removed and is defined by the serpentine pattern 474S. By forming the cutout region 411 between the dummy gate stacks 430 using a serpentine pattern 474S having approximately orthogonal portions, rounding may be reduced, which may reduce the separation distance between the cutout regions 411 without increasing the risk of process defects.

[0085] FIG. 28A to FIG. 31C The formation of a notched region 511 in the replacement gate stack 60 (eg, in the gate dielectric layer 52 and the gate electrode 56 ) is shown in accordance with some embodiments. Fig.28A , Fig.29A , Fig. 30A and Fig.31A A plan view of wafer 500 is shown. Fig.28B , Fig.29B , Fig. 30B and Fig.31B Shown along Fig.28A The cross-sectional view of the reference cross section DD shown in FIG. 1 also corresponds to Figure 1A Reference cross section DD shown. Fig.28C , Fig.29C , Fig. 30C and Fig.31C Shown along Fig.28A The cross-sectional view of the reference cross section EE shown also corresponds to Figure 1A The reference cross section EE is shown. The reference cross section EE is parallel to the longitudinal direction of the fin 24 (at Fig.28A ), but is located between the fins 24.

[0086] Figure 28A-28C Wafer 500 is shown with replacement gate stack 60 formed over fins 24 and separated by regions of first ILD 48. Replacement gate stack 60 has gate dielectric layer 52 and gate electrode 56 (not separately shown in the figure) with gate spacers 38 along sidewalls and covered by hard mask 62. Figure 28A-28C The structure shown is similar to that for Figure 2A-2C The structures described are not shown in the Figure 28A-28C CESL46 is depicted in FIG. Figure 28A-28C The structure shown can be used with Figure 2A-2C is formed in a similar manner as described.

[0087] exist Figure 29A-29C In the embodiment, a photoresist structure 569 is formed and patterned to have openings in the serpentine pattern 574S. The photoresist structure 469 may be similar to Figure 4A-4C The photoresist structure 69 shown in FIG. 1 and may be formed in a similar manner. Fig.29A As shown, the serpentine pattern 574S includes portions that may be approximately orthogonal to each other, similar to Figure 4A-4C The serpentine portion 74S and Fig.16A The serpentine pattern 274S shown. The serpentine pattern 574S exposes the cutout region 511 in the hard mask 62 (see Figure 30A-Figure 30C The serpentine pattern 574S may be formed in the photoresist structure 569 using appropriate photolithography techniques.

[0088] exist Figure 30A-Figure 30C In the embodiment, an etching process is performed using the patterned photoresist structure 569 as an etching mask to etch the hard mask 62 and the replacement gate stack 60, thereby forming the cutout region 511. Fig. 30C As shown, in some embodiments, the first ILD 48 and / or the gate spacer 38 may also be partially etched. In some embodiments, the etching process may selectively etch the hard mask 62 and the replacement gate stack 60 when etching the first ILD 48 and / or the gate spacer 38. The etching process may include one or more suitable etching processes, such as a dry etching process and / or a wet etching process. The cutout region 511 is an area where the replacement gate stack 60 has been removed and is defined by the serpentine pattern 574S.

[0089] exist Figure 31A-Figure 31C In the embodiment, a filling material 502 is deposited on the wafer 500 and within the cutout region 511. The filling material 502 may include one or more suitable dielectric materials, such as oxides, nitrides, etc., or a combination thereof. The filling material 502 may be deposited using a suitable process. In some embodiments, after the filling material 502 is deposited, an etch-back process and / or a planarization process (e.g., a CMP or grinding process) is performed, such as Figure 31A-Figure 31C By forming the kerf regions 511 between the replacement gate stacks 60 using a serpentine pattern 574S having approximately orthogonal portions, rounding can be reduced, which can reduce the separation distance between the kerf regions 511 without increasing the risk of process defects.

[0090] FIG. 32A to FIG. 35C A kerf region 611 is shown formed in a metal line 616 in accordance with some embodiments. Fig.32A , Fig.33A , Fig.34Aand Fig.35A A plan view of wafer 600 is shown. Fig.32B , Fig.33B , Fig.34B and Fig.35B Shown along Fig.32A The cross-sectional view of the reference cross section DD shown in FIG. 1 also corresponds to Figure 1A Reference cross section DD shown. Fig.32C , Fig.33C , Fig.34C and Fig.35C Shown along Fig.32A The cross-sectional view of the reference cross section EE shown also corresponds to Figure 1A The reference cross section EE is shown. The reference cross section EE is parallel to the longitudinal direction of the fin 24 (at Fig.32A ), but is located between the fins 24. Fig.32D Shown along Fig.32A The cross-sectional view of the reference cross section CC shown in FIG. 1 also corresponds to Figure 1A Reference cross section CC shown.

[0091] Figure 32A-Figure 32D A wafer 600 is shown with vias 614A-B and metal lines 616A-B formed over gate stack 60 and source / drain contacts 112. Via 614A contacts gate stack 60, and via 614B contacts source / drain contacts 112. Metal line 616A contacts via 614A, and metal line 616B contacts via 614B. In some embodiments, vias 614A-B are formed by: Figures 11A-11C A second ILD 615 is deposited on the structure shown, and then through the opening in the second ILD 615 to form a through hole 614A-B. The second ILD 615 can be formed of a suitable dielectric material and can be deposited using a suitable process. The second ILD 615 can be similar to the first ILD 108. The opening for the through hole 614A is formed to pass through the second ILD 615 and the hard mask 62, and the opening for the through hole 614B is formed to pass through the second ILD 615. One or more suitable photolithography and etching processes can be used to form the opening. Conductive material can be deposited in the opening to form the through hole 614A-B. The conductive material can include a liner, which is not shown separately in the figure. Although shown as being formed in the same cross section, it should be understood that each of the through hole 614A and the through hole 614B can be formed in different cross sections.

[0092] An intermetallic dielectric (IMD) 618 may then be deposited over the second ILD 615 and the vias 614A-B. The IMD 618 may be a suitable dielectric layer formed using a suitable deposition process. An opening may then be patterned in the IMD 618, exposing the vias 614A-B, and a conductive material may be deposited in the opening to form metal lines 616A-B. The conductive material may include a liner, which is not separately shown in the figure. The processes described above for forming the vias 614A-B and the metal lines 616A-B are examples, and other processes are possible.

[0093] exist Figure 33A-Figure 33C In the embodiment of the present invention, a photoresist structure 669 is formed and patterned to have an opening in the serpentine pattern 674S. The photoresist structure 669 may be similar to Figure 4A-4C The photoresist structure 69 shown in FIG. 1 and may be formed in a similar manner. Fig.33A As shown, the serpentine pattern 674S includes portions that may be approximately orthogonal to each other, similar to Figure 4A-4C The serpentine portion 74S and Fig.16A The serpentine pattern 274S shown. The serpentine pattern 674S exposes the metal line 616B to form the cut area 611 (see Figure 34A-Figure 34C The serpentine pattern 674S may be formed in the photoresist structure 669 using appropriate photolithography techniques.

[0094] exist Figure 34A-Figure 34C 6, an etching process is performed using the patterned photoresist structure 669 as an etching mask to etch the metal lines 616A-B, thereby forming a kerf region 611. In some embodiments, the etching process may selectively etch the metal lines 616A-B when etching the IMD 618 and / or the second ILD 615. The etching process may include one or more suitable etching processes, such as a dry etching process and / or a wet etching process. The kerf region 611 is an area where the metal lines 616A-B have been removed and is defined by the serpentine pattern 674S.

[0095] exist Figure 35A-Figure 35C In the embodiment, a filling material 602 is deposited on the wafer 600 and within the cutout region 611. The filling material 602 may include one or more suitable dielectric materials, such as oxides, nitrides, etc., or a combination thereof. The filling material 602 may be deposited using a suitable process. In some embodiments, after the filling material 602 is deposited, an etch-back process and / or a planarization process (e.g., a CMP or grinding process) is performed, such as Figure 35A-Figure 35CBy forming the cutout regions 611 between the replacement gate stacks 60 using a serpentine pattern 674S having approximately orthogonal portions, rounding can be reduced, which can reduce the separation distance between the cutout regions 611 without increasing the risk of process defects.

[0096] Embodiments can achieve advantages. The described technology can allow the formation of source / drain contacts with smaller cuts and more closely spaced cuts without increasing the risk of bridging or shorting. Specifically, a cut mask with a serpentine pattern can be used, the serpentine pattern including approximately orthogonal portions. For example, the serpentine pattern can have straight portions, the angles between which are greater than about 60°. Specifically, using a serpentine cut mask as described herein to form the cut can reduce rounding during the photolithography step, and thus can allow smaller cuts. By forming smaller cuts, the size of the source / drain contacts can be increased, which can improve conductivity and reduce contact resistance. The technology described herein can also allow more closely spaced cuts without increasing the risk of bridging or other process defects. In addition, the window for process overlap during cut formation can be increased, which improves process reliability and yield.

[0097] In some embodiments, a method includes: forming a fin extending above a semiconductor substrate; forming a photoresist structure above the fin; patterning a serpentine cut pattern in the photoresist structure to form a cut mask, wherein the serpentine cut pattern extends above the fin, wherein the serpentine cut pattern includes alternating bridge regions and cut regions, wherein each cut region extends along a first direction, wherein each bridge region extends between adjacent cut regions along a second direction, wherein the second direction is within 30° of an orthogonal direction relative to the first direction; and performing an etching process using the cut mask as an etching mask. In an embodiment, the etching process removes the fin in the cut region, and the cut region is defined by an opening in the cut mask corresponding to the serpentine cut pattern. In an embodiment, the method includes: forming an isolation region surrounding the fin, wherein the photoresist structure is formed above the isolation region. In an embodiment, a method includes: forming a gate stack extending over a fin; forming a source / drain region in the fin, wherein the source / drain region is adjacent to the gate stack; and forming an insulating layer over the fin and around the gate stack, wherein a photoresist structure is formed over the insulating layer and over the gate stack. In an embodiment, an etching process etches the insulating layer to expose the source / drain region. In an embodiment, an etching process removes the gate stack in a cutout region, wherein the cutout region is defined by an opening in a cutout mask corresponding to a serpentine cutout pattern. In an embodiment, a method includes: replacing the gate stack with a replacement gate stack after performing the etching process. In an embodiment, a method includes: forming a patterned photoresist layer over the cutout mask, wherein the etching process also uses the patterned photoresist layer as an etching mask. In an embodiment, a method includes: forming a metal line above a fin, wherein a photoresist structure is formed above the metal line, wherein an etching process removes the metal line in a cutout area, wherein the cutout area is defined by an opening in a cutout mask corresponding to a serpentine cutout pattern; and depositing a fill material in the cutout area.

[0098] In some embodiments, a method includes: forming a fin protruding from a substrate; forming a source / drain region on the fin; forming an interlayer dielectric (ILD) above the source / drain region; and forming a source / drain contact, including: forming a mask layer above the ILD; patterning a cut pattern in the mask layer, wherein the cut pattern includes a first straight portion and a second straight portion, wherein the first straight portion is connected by the second straight portion, wherein the angle between each first straight portion and an adjacent second straight portion connected to the first straight portion is in the range of 90° to 120°; etching an opening in the ILD to expose the source / drain region, wherein the etching uses the patterned mask layer as an etching mask; and depositing a conductive material in the opening. In an embodiment, the distance between two first straight portions connected by one second straight portion is less than 16 nm. In an embodiment, each second straight portion extends over at least one fin. In an embodiment, the first straight portion is located between adjacent fins. In an embodiment, each first straight portion includes a straight sidewall parallel to a sidewall of a first fin of the fin. In an embodiment, the first straight portion includes a concave sidewall opposite the straight sidewall. In an embodiment, the cut pattern includes a third straight portion, wherein the third straight portion is separated from the first straight portion and the second straight portion. In an embodiment, the method includes: forming a patterned photoresist over the patterned mask layer, wherein the patterned photoresist covers the second straight portion, wherein etching the opening in the ILD uses the patterned mask layer and the patterned photoresist as a combined etch mask.

[0099] In some embodiments, a device includes: a fin protruding from a semiconductor substrate, wherein the fin extends along a first direction; a first isolation structure surrounding the fin; a second isolation structure on the semiconductor substrate and at least partially within the first isolation structure, wherein the second isolation structure includes a series of connected first and second portions, wherein the first portion extends in a second direction orthogonal to the first direction, wherein the second portion extends in a third direction at a first angle relative to the second direction, wherein the first angle is between 0° and 30°, and wherein adjacent fins are isolated from each other by the first portion. In an embodiment, the distance between the two first portions is less than 16 nm. In an embodiment, the second portion is located between adjacent fins.

[0100] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0101] Example 1. A method for manufacturing a semiconductor device, comprising: forming a plurality of fins extending above a semiconductor substrate; forming a photoresist structure above the plurality of fins; patterning a serpentine cut pattern in the photoresist structure to form a cut mask, wherein the serpentine cut pattern extends above the plurality of fins, wherein the serpentine cut pattern includes alternating bridging regions and cut regions, wherein each cut region extends along a first direction, wherein each bridging region extends between adjacent cut regions along a second direction, wherein the second direction is within 30° relative to an orthogonal direction to the first direction; and performing an etching process using the cut mask as an etching mask.

[0102] Example 2. The method of Example 1, wherein the etching process removes the plurality of fins in a kerf region, wherein the kerf region is defined by an opening in the kerf mask corresponding to the serpentine kerf pattern.

[0103] Example 3. The method of Example 2, further comprising: forming an isolation region surrounding a fin of the plurality of fins, wherein the photoresist structure is formed over the isolation region.

[0104] Example 4. The method according to Example 1 further includes: forming a plurality of gate stacks extending above the plurality of fins; forming a plurality of source / drain regions in the plurality of fins, wherein the source / drain regions are adjacent to gate stacks in the plurality of gate stacks; and forming an insulating layer above the plurality of fins and around gate stacks in the plurality of gate stacks, wherein the photoresist structure is formed above the insulating layer and above the plurality of gate stacks.

[0105] Example 5. The method of Example 4, wherein the etching process etches the insulating layer to expose the plurality of source / drain regions.

[0106] Example 6. The method of Example 4, wherein the etching process removes the plurality of gate stacks in a kerf region, wherein the kerf region is defined by an opening in the kerf mask corresponding to the serpentine kerf pattern.

[0107] Example 7. The method of Example 6 further includes: replacing the plurality of gate stacks with a plurality of replacement gate stacks after performing the etching process.

[0108] Example 8. The method of Example 1 further includes: forming a patterned photoresist layer over the kerf mask, wherein the etching process also uses the patterned photoresist layer as an etching mask.

[0109] Example 9. The method according to Example 1 further includes: forming a plurality of metal lines above the plurality of fins, wherein the photoresist structure is formed above the plurality of metal lines, wherein the etching process removes the plurality of metal lines in a cutout area, wherein the cutout area is defined by an opening in the cutout mask corresponding to the serpentine cutout pattern; and depositing a filling material in the cutout area.

[0110] Example 10. A method for manufacturing a semiconductor device, comprising: forming a plurality of fins protruding from a substrate; forming source / drain regions on the plurality of fins; forming an interlayer dielectric ILD above the source / drain regions; and forming source / drain contacts, comprising: forming a mask layer above the ILD; patterning a cut pattern in the mask layer, wherein the cut pattern comprises a first straight portion and a second straight portion, wherein the first straight portion is connected through the second straight portion, wherein an angle between each first straight portion and an adjacent second straight portion connected to the first straight portion is in the range of 90° to 120°; etching an opening in the ILD to expose the source / drain regions, wherein the etching uses the patterned mask layer as an etching mask; and depositing a conductive material within the opening.

[0111] Example 11. The method according to Example 10, wherein a distance between two first straight portions connected by a second straight portion is less than 16 nm.

[0112] Example 12. The method of Example 10, wherein each second straight portion extends over at least one fin of the plurality of fins.

[0113] Example 13. The method of Example 10, wherein the first straight portion is located between adjacent fins of the plurality of fins.

[0114] Example 14. The method of Example 10, wherein each first straight portion includes a straight sidewall parallel to a sidewall of a first fin of the plurality of fins.

[0115] Example 15. The method of Example 14, wherein the first straight portion includes a concave sidewall opposite the straight sidewall.

[0116] Example 16. The method of Example 10, wherein the cut pattern further comprises a third straight portion, wherein the third straight portion is separated from the first straight portion and the second straight portion.

[0117] Example 17. The method according to Example 10 further includes: forming a patterned photoresist on the patterned mask layer, wherein the patterned photoresist covers the second straight portion, and wherein etching an opening in the ILD uses the patterned mask layer and the patterned photoresist as a combined etching mask.

[0118] Example 18. A semiconductor device comprising: a plurality of fins protruding from a semiconductor substrate, wherein the fins extend along a first direction; a first isolation structure surrounding fins among the plurality of fins; and a second isolation structure above the semiconductor substrate and at least partially within the first isolation structure, wherein the second isolation structure comprises a series of connected first and second portions, wherein the first portion extends along a second direction orthogonal to the first direction, wherein the second portion extends along a third direction at a first angle relative to the second direction, wherein the first angle is between 0° and 30°, and wherein adjacent fins among the plurality of fins are isolated from each other by the first portions.

[0119] Example 19. The semiconductor device of Example 18, wherein a distance between the two first portions is less than 16 nm.

[0120] Example 20. The semiconductor device of Example 18, wherein the second portion is located between adjacent fins of the plurality of fins.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a plurality of fins extending above the semiconductor substrate; forming a photoresist structure over the plurality of fins; patterning a serpentine cut pattern in the photoresist structure to form a cut mask, wherein the serpentine cut pattern extends over the plurality of fins, wherein the serpentine cut pattern includes alternating bridge regions and cut regions, wherein each cut region extends along a first direction, wherein each bridge region extends between adjacent cut regions along a second direction, wherein the second direction is within 30° of an orthogonal direction with respect to the first direction, and wherein each bridge region has parallel sidewalls; and An etching process is performed using the kerf mask as an etching mask.

2. The method according to claim 1, wherein: The etching process removes the plurality of fins in a kerf region defined by openings in the kerf mask corresponding to the serpentine kerf pattern.

3. The method according to claim 2, further comprising: An isolation region is formed around a fin of the plurality of fins, wherein the photoresist structure is formed over the isolation region.

4. The method according to claim 1, further comprising: forming a plurality of gate stacks extending over the plurality of fins; forming a plurality of source / drain regions in the plurality of fins, wherein the source / drain regions are adjacent to a gate stack in the plurality of gate stacks; and An insulating layer is formed over the plurality of fins and around gate stacks of the plurality of gate stacks, wherein the photoresist structure is formed over the insulating layer and over the plurality of gate stacks.

5. The method according to claim 4, wherein: The etching process etches the insulating layer to expose the plurality of source / drain regions.

6. The method according to claim 4, wherein: The etching process removes the plurality of gate stacks in a kerf region, wherein the kerf region is defined by an opening in the kerf mask corresponding to the serpentine kerf pattern.

7. The method according to claim 6, further comprising: After performing the etching process, the plurality of gate stacks are replaced with a plurality of replacement gate stacks.

8. The method according to claim 1, further comprising: A patterned photoresist layer is formed over the kerf mask, wherein the etching process also uses the patterned photoresist layer as an etching mask.

9. The method according to claim 1, further comprising: forming a plurality of metal lines over the plurality of fins, wherein the photoresist structure is formed over the plurality of metal lines, wherein the etching process removes the plurality of metal lines in a kerf region, wherein the kerf region is defined by an opening in the kerf mask corresponding to the serpentine kerf pattern; and A filling material is deposited in the cutout region.

10. A method for manufacturing a semiconductor device, comprising: forming a plurality of fins protruding from the substrate; forming source / drain regions on the plurality of fins; forming an interlayer dielectric ILD on the source / drain region; as well as Forming source / drain contacts, including: forming a mask layer over the ILD; patterning a cut pattern in the mask layer, wherein the cut pattern includes a first straight portion and a second straight portion, wherein the first straight portions are connected by the second straight portions, each second straight portion has a constant width between adjacent first straight portions of the second straight portion, and wherein an angle between each first straight portion and an adjacent second straight portion connected to the first straight portion is in a range of 90° to 120°; etching openings in the ILD to expose the source / drain regions, wherein the etching uses the patterned mask layer as an etch mask; and A conductive material is deposited within the opening.

11. The method according to claim 10, wherein: The distance between two first straight portions connected by one second straight portion is less than 16 nm.

12. The method according to claim 10, wherein: Each second straight portion extends over at least one fin of the plurality of fins.

13. The method according to claim 10, wherein: The first straight portion is located between adjacent fins among the plurality of fins.

14. The method according to claim 10, wherein: Each first straight portion includes a straight sidewall parallel to a sidewall of a first fin of the plurality of fins.

15. The method according to claim 14, wherein: The first straight portion includes a concave sidewall opposite the straight sidewall.

16. The method according to claim 10, wherein: The cut pattern further includes a third straight portion, wherein the third straight portion is separated from the first straight portion and the second straight portion.

17. The method according to claim 10, further comprising: A patterned photoresist is formed over the patterned mask layer, wherein the patterned photoresist covers the second straight portion, wherein etching an opening in the ILD uses the patterned mask layer and the patterned photoresist as a combined etch mask.

18. A semiconductor device comprising: a plurality of fins protruding from the semiconductor substrate, wherein the fins extend along a first direction; a first isolation structure surrounding a fin among the plurality of fins; and A second isolation structure is above the semiconductor substrate and at least partially within the first isolation structure, wherein the second isolation structure includes a series of connected first parts and second parts, wherein the first part extends along a second direction orthogonal to the first direction, wherein the second part extends along a third direction at a first angle relative to the second direction, wherein the first angle is between 0° and 30°, and wherein adjacent fins among the plurality of fins are isolated from each other by the first part.

19. The semiconductor device according to claim 18, wherein: The distance between the two first portions is less than 16 nm.

20. The semiconductor device according to claim 18, wherein The second portion is located between adjacent fins among the plurality of fins.

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