Memory device

Abstract

A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes peripheral circuitry and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through-hole, and a lower bonding pad disposed on a bottom surface of the upper structure and connected to the through-hole. Except for the uppermost upper structure, each upper structure also includes an upper bonding pad disposed on its top surface and connected to the through-hole. The bit line includes a gap that horizontally separates a first portion of the bit line from a second portion, and in a plan view, the gap between the through-hole and the bit line overlaps.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0006744, filed on January 17, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates herein to memory devices. More specifically, the present invention relates to memory devices comprising an array of stacked memory cells. Background Technology

[0004] The increasing demand for multifunctional, high-performance, and miniaturized information communication devices necessitates high-capacity and highly integrated memory devices. Therefore, memory devices comprising multiple stacked memory cell arrays have been developed. In such memory devices, stacking the memory cell arrays reduces the planar area occupied by the memory cell arrays. Summary of the Invention

[0005] Embodiments of the present invention provide a memory device whose planar area and performance can be easily adjusted.

[0006] Embodiments of the present invention provide a memory device comprising a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes peripheral circuitry and an upper bonding pad connected to the peripheral circuitry and disposed on a top surface of the lower structure. Each of the plurality of upper structures has a bottom surface and includes a stacked structure having a plurality of gate layers stacked vertically, a plurality of channel structures each passing through the stacked structure vertically, a bit line disposed below the stacked structure and connected to the plurality of channel structures, a through-hole passing through the stacked structure vertically, and a lower bonding pad disposed on the bottom surface and connected to the through-hole. Each of the plurality of upper structures, except for the uppermost upper structure, also includes a top surface and an upper bonding pad disposed on the top surface and connected to the through-hole. The bit line of each of the plurality of upper structures includes a first portion extending in a horizontal direction orthogonal to the vertical direction, a second portion extending in a horizontal direction, and a gap separating the first portion and the second portion of the bit line in a horizontal direction. In a plan view, the through-hole of each of the plurality of upper structures overlaps with the gap of the bit line. The bottommost of a plurality of upper structures is stacked vertically on a lower structure such that the lower bonding pad of the bottommost upper structure contacts the upper bonding pad of the lower structure. The plurality of upper structures includes a first upper structure and a second upper structure stacked vertically. The lower bonding pad of the second upper structure contacts the upper bonding pad of the first upper structure.

[0007] Embodiments of the present invention also provide a memory device including a first structure and a second structure stacked on the first structure. The first structure includes peripheral circuitry, a first upper bonding pad connected to the peripheral circuitry, and a second upper bonding pad connected to the peripheral circuitry. The second structure includes a first lower bonding pad connected to the first upper bonding pad of the first structure, a first through-hole connected to the first lower bonding pad of the second structure, a third upper bonding pad connected to the first through-hole of the second structure, a second lower bonding pad connected to the second upper bonding pad of the first structure, a first bit line connected to the second lower bonding pad of the second structure, and a memory cell array connected to the first bit line of the second structure. The first bit line of the second structure includes a first portion, a second portion, and a first gap between the first portion of the first bit line of the second structure and the second portion of the first bit line of the second structure. The first lower bonding pad of the second structure is not connected to the first portion and the second portion of the first bit line of the second structure.

[0008] Embodiments of the present invention also provide a memory device including a first structure and a second structure on the first structure. The first structure includes peripheral circuitry, a first upper bonding pad connected to the peripheral circuitry, and a second upper bonding pad connected to the peripheral circuitry. The second structure includes a first lower bonding pad connected to the first upper bonding pad of the first structure, a first through-feature connected to the first lower bonding pad of the second structure, a first lower line connecting the first lower bonding pad of the second structure to the first through-feature of the second structure, a third upper bonding pad connected to the first through-feature of the second structure, a second lower bonding pad connected to the second upper bonding pad of the first structure, a first line connected to the second lower bonding pad of the second structure, and a memory cell array connected to the first line of the second structure. The first line of the second structure includes a first portion, a second portion, and a first gap between the first portion of the first line of the second structure and the second portion of the first line of the second structure. The first lower line of the second structure is not connected to the first portion and the second portion of the first line of the second structure. Attached Figure Description

[0009] The embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A block diagram of a memory device according to an embodiment of the present invention is shown;

[0011] Figure 2 A circuit diagram is shown of one of the memory blocks included in a memory cell array included in a memory device according to an embodiment of the present invention;

[0012] Figure 3A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0013] Figure 4 A cross-sectional view of the lower structure included in a memory device according to an embodiment of the present invention is shown;

[0014] Figure 5A and Figure 5B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0015] Figure 6A and Figure 6B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0016] Figure 7A and Figure 7B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0017] Figure 8A and Figure 8B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0018] Figure 9A and Figure 9B Cross-sectional and plan views of the lower structure included in a memory device according to an embodiment of the present invention are shown;

[0019] Figure 10A and Figure 10B Cross-sectional and plan views of the lower structure included in a memory device according to an embodiment of the present invention are shown;

[0020] Figure 11A and Figure 11B Cross-sectional and plan views of the lower structure included in a memory device according to an embodiment of the present invention are shown;

[0021] Figure 12A and Figure 12B Cross-sectional and plan views of the lower structure included in a memory device according to an embodiment of the present invention are shown;

[0022] Figure 13A and Figure 13B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0023] Figure 14A and Figure 14B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0024] Figure 15A and Figure 15B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0025] Figure 16A and Figure 16B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0026] Figure 17A and Figure 17B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0027] Figure 18A and Figure 18B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0028] Figure 19A and Figure 19B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0029] Figure 20A and Figure 20B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0030] Figure 21A and Figure 21B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0031] Figure 22A and Figure 22B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0032] Figure 23 A plan view of the upper structure included in a memory device according to an embodiment of the present invention is shown;

[0033] Figure 24 A plan view of the upper structure included in a memory device according to an embodiment of the present invention is shown;

[0034] Figure 25 A plan view of the upper structure included in a memory device according to an embodiment of the present invention is shown;

[0035] Figure 26A plan view of the upper structure included in a memory device according to an embodiment of the present invention is shown;

[0036] Figure 27 A plan view of the upper structure included in a memory device according to an embodiment of the present invention is shown;

[0037] Figure 28 A plan view of the upper structure included in a memory device according to an embodiment of the present invention is shown;

[0038] Figure 29 A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0039] Figure 30 A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0040] Figure 31 A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0041] Figure 32 A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0042] Figure 33 A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0043] Figure 34 A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0044] Figure 35A , Figure 35B , Figure 35C and Figure 35D A cross-sectional view is shown illustrating a method for manufacturing a memory device according to an embodiment of the concept of the present invention;

[0045] Figure 36A and Figure 36B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0046] Figure 37A and Figure 37B Cross-sectional and plan views of the upper structure included in a memory device according to an embodiment of the present invention are shown;

[0047] Figure 38 A plan view of the upper structure included in a memory device according to an embodiment of the present invention is shown;

[0048] Figure 39 A plan view of the upper structure included in a memory device according to an embodiment of the present invention is shown;

[0049] Figure 40 A plan view of the upper structure included in a memory device according to an embodiment of the present invention is shown;

[0050] Figure 41 A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0051] Figure 42 A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0052] Figure 43 A cross-sectional view of a memory device according to an embodiment of the present invention is shown;

[0053] as well as

[0054] Figure 44 A cross-sectional view of a memory device according to an embodiment of the present invention is shown. Detailed Implementation

[0055] As is conventional in the field of the present invention, embodiments can be described and illustrated as blocks that perform one or more described functions. These blocks, referred to herein as units or modules, are physically implemented by analog and / or digital circuitry such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits, etc., and may optionally be driven by firmware and / or software. For example, the circuitry may be implemented in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware performing some functions of the block and a processor performing other functions of the block. Without departing from the scope of the present invention, each block of an embodiment may be physically divided into two or more interacting and discrete blocks. Similarly, without departing from the scope of the present invention, the blocks of an embodiment may be physically combined into more complex blocks.

[0056] Figure 1 A block diagram of a memory device 10 according to an embodiment of the present invention is shown.

[0057] refer to Figure 1 The memory device 10 may include multiple memory cell arrays (MCAs) (although in Figure 1 Only a single memory cell array is shown in the diagram, along with peripheral circuitry PC. The peripheral circuitry PC may include a row decoder 12, a page buffer 13, and control logic (e.g., control circuitry) 14.

[0058] Each of the multiple memory cell arrays (MCA) may include multiple memory blocks BLK1, BLK2 to BLKz (hereinafter referred to as memory blocks BLK1 to BLKz). Each of the memory blocks BLK1 to BLKz may include multiple memory cells for storing data. Each of the multiple memory cell arrays (MCA) may include multiple non-volatile memory cells that retain data stored therein even when the power supplied to it is interrupted. For example, each of the multiple memory cell arrays (MCA) may include electrically erasable programmable read-only memory (EEPROM) cells, flash memory cells, phase-change random access memory (PRAM) cells, resistive random access memory (RRAM) cells, magnetic random access memory (MRAM) cells, ferroelectric random access memory (FRAM) cells, or combinations thereof. In the following, embodiments will be described in detail based on the assumption that the memory cell array (MCA) includes multiple NAND flash memory cells. The memory cell array (MCA) may be connected to a common-source line (CSL). The common-source line (CSL) may be controlled by control logic 14.

[0059] The row decoder 12 can be connected to the memory cell array MCA via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). The row decoder 12 can select at least one memory block from multiple memory blocks BLK1 to BLKz in response to an address ADDR provided from the memory controller (not shown). The row decoder 12 can also select at least one of the word lines WL, serial select lines (SSL), and ground select lines (GSL) of the selected memory block in response to an address ADDR provided from the memory controller (not shown).

[0060] Page buffer 13 can be connected to the memory cell array MCA via multiple bit lines BL. Page buffer 13 can select at least one bit line BL from the multiple bit lines BL. Page buffer 13 can store data DATA input from the memory controller (not shown) in the memory cell array MCA. In addition, page buffer 13 can output data DATA read from the memory cell array MCA to the memory controller (not shown).

[0061] Control logic 14 controls the overall operation of memory device 10. Specifically, control logic 14 controls the operation of line decoder 12 and page buffer 13. For example, control logic 14 controls memory device 10 to perform a storage operation corresponding to the command CMD provided from memory controller (not shown). Furthermore, control logic 14 can generate various internal control signals for memory device 10 in response to the control signal CTRL provided from memory controller (not shown).

[0062] Figure 2A memory device 10 according to an embodiment of the present invention is shown (see Figure 1 The memory cell array MCA included in ) (see Figure 1 The circuit diagram of a BLK1 memory block included in the document.

[0063] refer to Figure 2 The memory block BLK1 may include multiple NAND strings NS11 to NS33 (e.g., NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33). Figure 2 In the illustration, a memory block BLK1 is shown as comprising nine NAND strings NS11 to NS33, but the number of NAND strings included in a memory block BLK1 is not limited to this. Each of the NAND strings NS11 to NS33 may include at least one string select transistor SST connected in series with each other, a plurality of memory cells MC1 to MC8 (e.g., MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8), and at least one ground select transistor GST. Figure 2 In the diagram, each of the NAND strings NS11 to NS33 is illustrated as including a string select transistor SST, eight memory cells MC1 to MC8, and a ground select transistor GST, but the number of string select transistors, memory cells, and ground select transistors included in each of the NAND strings NS11 to NS33 is not limited thereto.

[0064] NAND strings NS11 to NS33 can be connected between multiple bit lines BL1 to BL3 (e.g., BL1, BL2, and BL3) and the common-source line CSL. The gate of the string select transistor SST can be connected to string select lines SS1 to SS3 (e.g., SS1, SS2, and SS3), the gates of memory cells MC1 to MC8 can be connected to word lines WL1 to WL8 (e.g., WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8), and the gate of the ground select transistor GST can be connected to ground select lines GSL1 to GSL3 (e.g., GSL1, GSL2, and GSL3). The common-source line CSL can be connected together to multiple NAND strings NS11 to NS33. Furthermore, word lines WL1 to WL8 can be connected together to multiple NAND strings NS11 to NS33.

[0065] Figure 3 A cross-sectional view of a memory device 10 according to an embodiment of the present invention is shown.

[0066] refer to Figure 3 The memory device 10 may include a plurality of structures S1 to S5 stacked in the vertical direction (Z direction). Figure 3In the illustration, the memory device 10 is shown to include five structures S1 to S5, but is not limited thereto, and may include more or fewer structures. Here, the lowest first structure S1 may be referred to as the lower structure, and each of the other structures (e.g., the second to fifth structures) S2 to S5 may be referred to as the upper structure. The lower structure S1 may include a plurality of upper bonding pads UBP1 disposed on the top surface of the lower structure S1. The upper structure S2 may include a plurality of lower bonding pads LBP2 disposed on the bottom surface of the upper structure S2. In addition to the uppermost upper structure S5, each of the upper structures S2 to S5 may also include a plurality of upper bonding pads UBP2 disposed on the top surface of each of the upper structures S2 to S4.

[0067] The lowest upper structure S2 among multiple upper structures S2 to S5 can be stacked on the lower structure S1 in the vertical direction (Z direction), such that the lower bonding pad LBP2 of the lowest upper structure S2 contacts the upper bonding pad UBP1 of the lower structure S1. Therefore, the lower bonding pad LBP2 of the lowest upper structure S2 can be connected to the upper bonding pad UBP1 of the lower structure S1. The lower bonding pad LBP2 of the third structure S3 can contact the upper bonding pad UBP2 of the second structure S2. Therefore, the lower bonding pad LBP2 of the third structure S3 can be connected to the upper bonding pad UBP2 of the second structure S2. Similarly, the lower bonding pad LBP2 of the fourth structure S4 can contact the upper bonding pad UBP2 of the third structure S3, and the lower bonding pad LBP2 of the fifth structure S5 can contact the upper bonding pad UBP2 of the fourth structure S4. Therefore, the lower bonding pad LBP2 of the fourth structure S4 can be connected to the upper bonding pad UBP2 of the third structure S3, and the lower bonding pad LBP2 of the fifth structure S5 can be connected to the upper bonding pad UBP2 of the fourth structure S4.

[0068] The upper bonding pad UBP1 of the lower structure S1, the lower bonding pads LBP2 of the upper structures S2 to S5, and the upper bonding pads UBP2 of the upper structures S2 to S4 may include conductive materials, such as copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or combinations thereof. In some embodiments, the planar area (i.e., the area of ​​the cross-section perpendicular to the Z direction) of each of the upper bonding pads UBP1 of the lower structure S1, the lower bonding pads LBP2 of the upper structures S2 to S5, and the upper bonding pads UBP2 of the upper structures S2 to S4 may be approximately 1 μm × 1 μm or larger.

[0069] The lower structure S1 may include Figure 4 The lower structure S1a shown in the figure Figure 9A and Figure 9B The lower structure S1Xb shown in the figure Figure 10A and Figure 10B The lower structure S1Yb shown in the figure Figure 11A and Figure 11B The lower structure S1Xc shown in the figure Figure 12A and Figure 12B The lower structure S1Yc, or a combination thereof, is shown in the figure.

[0070] Each of the superstructures S2 to S5 may include Figure 5A and Figure 5B The upper structure S2Xa shown in the figure Figure 6A and Figure 6B The upper structure S2Ya shown in the figure Figure 7A and Figure 7B The upper structure S2Xb shown in the figure Figure 8A and Figure 8B The upper structure S2Yb shown in the figure Figure 13A and Figure 13B The upper structure S2XYa shown in the figure Figure 14A and Figure 14B The upper structure S2XYb shown in the figure Figure 15A and Figure 15B The upper structure S2XYc shown in the figure Figure 16A and Figure 16B The upper structure S2XYd shown in the figure Figure 17A and Figure 17B The upper structure S2XYe shown in the figure Figure 18A and Figure 18B The upper structure S2XYf shown in the figure Figure 19A and Figure 19B The upper structure S2XYg shown in the figure Figure 20A and Figure 20B The upper structure S2XYh shown in the figure Figure 21A and Figure 21B The upper structure S2XYi shown in the figure Figure 22A and Figure 22B The upper structure S2XYj shown in the figure Figure 23 The upper structure S2XYk shown in the figure Figure 24 The upper structure S2XYl shown in the figure Figure 25 The upper structure S2XYm shown in the figure Figure 26 The upper structure S2XYn shown in the figure Figure 27 The upper structure S2XXa shown in the figure Figure 28 The upper structure S2XXb, or a combination thereof, is shown in the figure.

[0071] Figure 4A cross-sectional view of the lower structure S1a included in a memory device according to an embodiment of the present invention is shown.

[0072] refer to Figure 4 The lower structure S1a may include a peripheral circuit PC and an upper bonding pad UBP1a connected to the peripheral circuit PC. In some embodiments, the peripheral circuit PC may include a substrate SUB, a plurality of active components (e.g., transistors TR) on the substrate SUB, a plurality of passive components (e.g., capacitors (not shown) or resistors (not shown)) on the substrate SUB, and interconnects ICN connecting the active components to the passive components. The lower structure S1a may also include an insulating layer IL1 covering the peripheral circuit PC. The upper bonding pad UBP1a may be disposed on the insulating layer IL1.

[0073] The substrate SUB may include semiconductor materials, such as group IV semiconductor materials, group III-V semiconductor materials, group II-VI semiconductor materials, or combinations thereof. Group IV semiconductor materials may include, for example, silicon (Si), germanium (Ge), or combinations thereof. Group III-V semiconductor materials may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), indium gallium arsenide (InGaAs), or combinations thereof. Group II-VI semiconductor materials may include, for example, zinc telluride (ZnTe), cadmium sulfide (CdS), or combinations thereof. The insulating layer IL1 may include insulating materials, such as silicon oxide, silicon nitride, or combinations thereof.

[0074] Figure 5A and Figure 5B A cross-sectional view and a bottom view of the upper structure S2Xa included in a memory device according to an embodiment of the present invention are shown. Figure 5A The cross-sectional view in the middle is along Figure 5B The bottom view shown is intercepted by bit line BL1, and Figure 5B The bottom view shows that bit lines BL1, BL2 and BL3 overlap with the lower connection pad LCP2Xa.

[0075] refer to Figure 5A and Figure 5B The upper structure S2Xa may include a memory cell array MCA, a common-source line CSL on the memory cell array MCA, multiple bit lines (e.g., the first bit line to the fourth bit line) BL1 to BL4 connected to the memory cell array MCA, and a connection to the lower structure S1 (see...). Figure 3 The upper bonding pad UBP1 on the upper bonding pad, the lower bonding pad LBP2Xa, and the through-hole THV connected to the lower bonding pad LBP2Xa.

[0076] The memory cell array (MCA) may include a stacked structure 110 and a plurality of channel structures 120 extending through the stacked structure 110 in the vertical direction (Z direction). The stacked structure 110 may include a plurality of gate layers 111 stacked in the vertical direction (Z direction). The stacked structure 110 may also include a plurality of interlayer insulating layers 112 separating the plurality of gate layers 111 from each other. The plurality of gate layers 111 and the plurality of interlayer insulating layers 112 may be stacked alternately in the vertical direction (Z direction).

[0077] Each channel structure 120 may be formed in a channel via 120H extending vertically (Z-direction) through the stacked structure 110. Each channel structure 120 may include a channel layer 121 on the top and side surfaces of the channel via 120H and a pad 124 on the bottom surface of the channel via 120H. The channel layer 121 and the pad 124 may include a semiconductor material. In some embodiments, each channel structure 120 may also include a gate insulating layer 123 between the side surface of the channel via 120H and the channel layer 121. In some embodiments, the gate insulating layer 123 may include a barrier insulating layer, a charge storage layer, and a tunnel insulating layer. The barrier insulating layer, the charge storage layer, and the tunnel insulating layer may each include an oxide layer, a nitride layer, and an oxide layer, respectively. In some embodiments, the channel via 120H may also include a filling insulating layer 122 to fill the empty space defined by the channel layer 121. In other embodiments, the channel via 120H may have a cylindrical shape and may not include a filling insulating layer 122.

[0078] A common-source line (CSL) may be disposed on the stacked structure 110. The common-source line (CSL) may contact the channel layer 121 of each channel structure 120. The common-source line (CSL) may include a semiconductor material. In some embodiments, the upper structure S2Xa may include an upper insulating layer IL2u on the common-source line (CSL).

[0079] Bit lines BL1 to BL4 may be disposed below the stack structure 110. Bit lines BL1 to BL4 may be connected to multiple channel structures 120. Bit lines BL1 to BL4 may extend in the X direction and may be separated from each other in the Y direction. The first bit line BL1 may include a first portion P1 extending in the horizontal direction (X direction), a second portion P2 extending in the horizontal direction (X direction), and a first gap G1 separating the first portion P1 and the second portion P2 in the horizontal direction (X direction).

[0080] In some embodiments, the upper structure S2Xa may further include a plurality of vias V connecting the channel structure 120 to bit lines BL1 to BL4. The vias V may include a conductive material. In some embodiments, the upper structure S2Xa may further include a lower insulating layer IL2l below the stack structure 110. A lower bonding pad LBP2Xa may be disposed below the lower insulating layer IL2l. The lower bonding pad LBP2Xa may be connected to the through-hole THV, but in situations such as... Figure 5A and Figure 5B In the case shown, the lower bonding pad LBP2Xa is not connected to the first part P1 and the second part P2 of the first bit line BL1.

[0081] In some embodiments, the through-hole THV can pass through the memory cell array MCA. Specifically, the through-hole THV can pass through the stack structure 110 in the vertical direction (Z direction). The through-hole THV can also pass through the common source line CSL. The through-hole THV can also pass through the upper insulating layer IL2u. The through-hole THV can include a conductive material. The through-hole THV can be disposed in the through-hole THVH. In some embodiments, the upper structure S2Xa can also include a through-hole insulating layer ILt between the side surface of the through-hole THVH and the through-hole THV. In some embodiments, in a plan view, the through-hole THV can overlap with the first gap G1 of the first bit line BL1.

[0082] In some embodiments, the upper structure S2Xa may further include an upper bonding pad UBP2 connected to the through-hole member THV. The upper bonding pad UBP2 may be disposed on the upper end of the through-hole member THV. In some embodiments, the upper structure S2Xa may further include an internal pad IP connecting the through-hole member THV to the upper bonding pad UBP2. The internal pad IP may include a conductive material.

[0083] In some embodiments, the upper structure S2Xa may further include a lower connection pad LCP2Xa that connects a first portion P1 of the first line BL1 to a second portion P2 of the first line BL1. The lower connection pad LCP2Xa may have any shape for connecting the first portion P1 of the first line BL1 to the second portion P2 of the first line BL1. The lower connection pad LCP2Xa may be disposed on the bottom surface of the upper structure S2Xa. The bottom surface of the lower connection pad LCP2Xa may be disposed along the same plane as the bottom surface of the lower bonding pad LBP2Xa. The lower bonding pad LBP2Xa may include a conductive material. The lower connection pad LCP2Xa may include a material substantially the same as the material of the lower bonding pad LBP2Xa. Here, the inclusion of substantially the same material in two components may indicate or imply that the compositional difference between the two components is within the compositional difference between the two components that occurs due to process limitations in cases where the two components are simultaneously formed from the same source material using the same equipment.

[0084] In some embodiments, the upper structure S2Xa may further include a first via V1Xa connecting the lower bonding pad LBP2Xa to the through-hole THV. In some embodiments, the upper structure S2Xa may further include a second via V2Xa connecting the lower connection pad LCP2Xa to a first portion P1 of the first line BL1, and a third via V3Xa connecting the lower connection pad LCP2Xa to a second portion P2 of the first line BL1. The first via V1Xa, the second via V2Xa, and the third via V3Xa may include a conductive material.

[0085] exist Figure 5B The bottom view shows bit lines BL1 to BL4, lower connection pad LCP2Xa, and lower bonding pad LBP2Xa, while other structural features are omitted to simplify the figures. Similarly, in the following figures, certain structural features are omitted from the bottom view to simplify the figures.

[0086] Figure 6A and Figure 6B A cross-sectional view and a bottom view of the upper structure S2Ya included in a memory device according to an embodiment of the present invention are shown. Figure 6A The cross-sectional view is along Figure 6B The bit line BL1 in the bottom view is intercepted, and Figure 6B The bottom view shows bit lines BL1, BL2 and BL3 overlapping with the lower bonding pad LBP2Ya. Figure 6A and Figure 6B The upper structure S2Ya in the middle is similar to Figure 5A and Figure 5B The upper structure S2Xa is shown below, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0087] refer to Figure 6A and Figure 6B ,and Figure 5A and Figure 5B Compared to the upper structure S2Xa shown, the lower bonding pad LBP2Ya can be connected to the first portion P1 and the second portion P2 of the first line BL1 and the through-hole THV. The lower bonding pad LBP2Ya can have any shape for connecting the through-hole THV to the first portion P1 and the second portion P2 of the first line BL1. In some embodiments, the upper structure S2Ya may include a first via V1Ya connecting the lower bonding pad LBP2Ya to the through-hole THV, a second via V2Ya connecting the lower bonding pad LBP2Ya to the first portion P1 of the first line BL1, and a third via V3Ya connecting the lower bonding pad LBP2Ya to the second portion P2 of the first line BL1.

[0088] Figure 7A and Figure 7B A cross-sectional view and a bottom view of the upper structure S2Xb included in a memory device according to an embodiment of the present invention are shown. Figure 7A The cross-sectional view in the middle is along Figure 7B The bottom view shown is intercepted by bit line BL1, and Figure 7B The bottom view shows that bit lines BL1, BL2 and BL3 overlap with the second lower line LL2Xb. Figure 7A and Figure 7B The upper structure S2Xb in the middle is similar to Figure 5A and Figure 5B The upper structure S2Xa is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0089] refer to Figure 7A and Figure 7B ,and Figure 5A and Figure 5BCompared to the upper structure S2Xa shown, the upper structure S2Xb may include a first lower line LL1Xb connecting the lower bonding pad LBP2Xb to the through-hole THV. The upper structure S2Xb may also include a second lower line LL2Xb connecting a first portion P1 of the first line BL1 to a second portion P2 of the first line BL1. The second lower line LL2Xb is not connected to the lower bonding pad LBP2Xb. The second lower line LL2Xb may have any shape for connecting the first portion P1 of the first line BL1 to the second portion P2 of the first line BL1. The bottom surface of the first lower line LL1Xb may be disposed on the same plane as the bottom surface of the second lower line LL2Xb. The first lower line LL1Xb and the second lower line LL2Xb may include conductive materials. The first lower line LL1Xb may include a material substantially the same as the material of the second lower line LL2Xb.

[0090] Figure 8A and Figure 8B A cross-sectional view and a bottom view of the upper structure S2Yb included in a memory device according to an embodiment of the present invention are shown. Figure 8A The cross-sectional view in the middle is along Figure 8B The bottom view shown is intercepted by bit line BL1, and Figure 8B The bottom view shows that bit lines BL1, BL2 and BL3 overlap with the lower line LL1Yb. Figure 8A and Figure 8B The upper structure S2Yb in the middle is similar to Figure 6A and Figure 6B The upper structure S2Ya is shown below, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0091] refer to Figure 8A and Figure 8B ,and Figure 6A and Figure 6B Compared to the upper structure S2Ya shown, the upper structure S2Yb may further include a lower line LL1Yb that connects the through-hole THV, the first portion P1 and the second portion P2 of the first line BL1 to the lower bonding pad LBP2Yb. The lower line LL1Yb may have any shape for connecting the lower bonding pad LBP2Yb to the through-hole THV and the first portion P1 and the second portion P2 of the first line BL1. The lower line LL1Yb may include a conductive material.

[0092] Figure 9A and Figure 9B Cross-sectional and plan views of the lower structure S1Xb included in a memory device according to an embodiment of the present invention are shown. Figure 9A The cross-sectional view in the middle is along Figure 9BThe bit line BL1 in the planar diagram shown is intercepted, and Figure 9B The plan view shows that the upper connection pad UCP1Xb overlaps with bit lines BL1, BL2 and BL3. Figure 9A and Figure 9B The lower structure S1Xb in the middle is similar to Figure 4 The lower structure S1a is shown below, and descriptions of similar elements and structures will be omitted below.

[0093] refer to Figure 9A and Figure 9B ,and Figure 4 Compared to the lower structure S1a shown, the lower structure S1Xb may include a common source line CSL on the insulating layer IL1 on the peripheral circuit PC, a memory cell array MCA on the common source line CSL, multiple bit lines (e.g., the first bit line to the fourth bit line) BL1 to BL4 connected to the memory cell array MCA, and a through-hole THV connecting the upper bonding pad UBP1Xb to the peripheral circuit PC.

[0094] The memory cell array (MCA) may include a stacked structure 110 and multiple channel structures 120, each passing through the stacked structure 110 in the vertical direction (Z direction). The stacked structure 110 may include multiple gate layers 111 stacked on peripheral circuitry (PC) in the vertical direction (Z direction). The stacked structure 110 may also include multiple interlayer insulating layers 112 separating the multiple gate layers 111 from each other. The multiple gate layers 111 and the multiple interlayer insulating layers 112 may be stacked alternately in the vertical direction (Z direction). The channel structure 120 may include channel layers 121 on the bottom and side surfaces of a channel via 120H and pads 124 on the top surface of the channel via 120H. The channel layers 121 of the channel structure 120 may contact the common source line (CSL).

[0095] Bit lines BL1 to BL4 can be disposed on the stack structure 110 and can be connected to multiple channel structures 120. The first bit line BL1 may include a first portion P1 extending in the horizontal direction (X direction), a second portion P2 extending in the horizontal direction (X direction), and a first gap G1 separating the first portion P1 and the second portion P2 in the horizontal direction (X direction). In some embodiments, the lower structure S1Xb may also include multiple vias V connecting the channel structures 120 to the bit lines BL1 to BL4.

[0096] In some embodiments, the lower structure S1Xb may include an upper insulating layer IL1u on the stacked structure 110. An upper bonding pad UBP1Xb may be disposed on the upper insulating layer IL1u. The upper bonding pad UBP1Xb may be connected to the through-hole THV, but in this case, as... Figure 9A and Figure 9BAs shown, the upper bonding pad UBP1Xb is not connected to the first part P1 and the second part P2 of the first bit line BL1.

[0097] In some embodiments, the through-hole THV can pass through the memory cell array MCA. Specifically, the through-hole THV can pass through the stack structure 110 in the vertical direction (Z direction). The through-hole THV can also pass through the common source line CSL. The through-hole THV can also pass through the insulating layer IL1. The through-hole THV can be disposed in the through-hole THVH. In some embodiments, the lower structure S1Xb can also include a through-hole insulating layer ILt between the side surface of the through-hole THVH and the through-hole THV. In some embodiments, in a plan view, the through-hole THV can overlap with the first gap G1 of the first line BL1.

[0098] In some embodiments, the lower structure S1Xb may further include an upper connection pad UCP1Xb that connects a first portion P1 of the first line BL1 to a second portion P2 of the first line BL1. The upper connection pad UCP1Xb may have any shape for connecting the first portion P1 of the first line BL1 to the second portion P2 of the first line BL1. The upper connection pad UCP1Xb may be disposed on the top surface of the lower structure S1Xb. The top surface of the upper connection pad UCP1Xb may be disposed on the same plane as the top surface of the upper bonding pad UBP1Xb. The upper connection pad UCP1Xb may include a conductive material. The upper connection pad UCP1Xb may include a material substantially the same as the material of the upper bonding pad UBP1Xb.

[0099] In some embodiments, the lower structure S1Xb may further include a first via V1Xb connecting the upper bonding pad UBP1Xb to the through member THV. In some embodiments, the lower structure S1Xb may further include a second via V2Xb connecting the upper bonding pad UCP1Xb to a first portion P1 of the first line BL1, and a third via V3Xb connecting the upper bonding pad UCP1Xb to a second portion P2 of the first line BL1. The first via V1Xb, the second via V2Xb, and the third via V3Xb may include a conductive material.

[0100] Figure 10A and Figure 10B Cross-sectional and plan views of the lower structure S1Yb included in a memory device according to an embodiment of the present invention are shown. Figure 10A The cross-sectional view is along Figure 10B The bit line BL1 in the planar diagram is intercepted, and Figure 10B The plan view shows that the upper bonding pad UBP1Yb overlaps with bit lines BL1, BL2 and BL3. Figure 10A and Figure 10BThe lower structure S1Yb in the middle is similar to Figure 9A and Figure 9B The lower structure S1Xb is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0101] refer to Figure 10A and Figure 10B ,and Figure 9A and Figure 9B Compared to the lower structure S1Xb shown, the upper bonding pad UBP1Yb can be connected to the first portion P1 and the second portion P2 of the first line BL1 and the through-hole THV. The upper bonding pad UBP1Yb can have any shape for connecting the through-hole THV to the first portion P1 and the second portion P2 of the first line BL1. In some embodiments, the lower structure S1Yb may include a first via V1Yb connecting the upper bonding pad UBP1Yb to the through-hole THV, a second via V2Yb connecting the upper bonding pad UBP1Yb to the first portion P1 of the first line BL1, and a third via V3Yb connecting the upper bonding pad UBP1Yb to the second portion P2 of the first line BL1.

[0102] Figure 11A and Figure 11B Cross-sectional and plan views of the lower structure S1Xc included in a memory device according to an embodiment of the present invention are shown. Figure 11A The cross-sectional view in the middle is along Figure 11B The bit line BL1 in the planar diagram shown is intercepted, and Figure 11B The plan view shows that the second upper line UL2Xc overlaps with bit lines BL1, BL2 and BL3. Figure 11A and Figure 11B The lower structure S1Xc is similar to Figure 9A and Figure 9B The lower structure S1Xb is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0103] refer to Figure 11A and Figure 11B ,and Figure 9A and Figure 9BCompared to the lower structure S1Xb shown, the lower structure S1Xc may include a first upper line UL1Xc connecting the upper bonding pad UBP1Xc to the through-hole THV. The lower structure S1Xc may also include a second upper line UL2Xc connecting a first portion P1 of the first line BL1 to a second portion P2 of the first line BL1. In this case, as shown, the second upper line UL2Xc is not connected to the upper bonding pad UBP1Xc. The second upper line UL2Xc may have any shape for connecting the first portion P1 of the first line BL1 to the second portion P2 of the first line BL1. The top surface of the first upper line UL1Xc may be disposed on the same plane as the top surface of the second upper line UL2Xc. The first upper line UL1Xc and the second upper line UL2Xc may include conductive materials. The first upper line UL1Xc may include a material substantially the same as the material of the second upper line UL2Xc.

[0104] Figure 12A and Figure 12B Cross-sectional and plan views of the lower structure S1Yc included in a memory device according to an embodiment of the present invention are shown. Figure 12A The cross-sectional view in the middle is along Figure 12B The bit line BL1 in the planar diagram shown is intercepted, and Figure 12B The plan view shows that the upper line UL1Yc overlaps with the bit lines BL1, BL2 and BL3. Figure 12A and Figure 12B The lower structure S1Yc is similar to Figure 10A and Figure 10B The lower structure S1Yb is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0105] refer to Figure 12A and Figure 12B ,and Figure 10A and Figure 10B Compared to the lower structure S1Yb shown, the lower structure S1Yc may further include a through-hole element THV and an upper line UL1Yc that connects the first portion P1 and the second portion P2 of the first line BL1 to the upper bonding pad UBP1Yc. The upper line UL1Yc may have any shape for connecting the upper bonding pad UBP1Yc to the through-hole element THV and the first portion P1 and the second portion P2 of the first line BL1. The upper line UL1Yc may include a conductive material.

[0106] Figure 13A and Figure 13B A cross-sectional view and a bottom view of the upper structure S2XYa included in a memory device according to an embodiment of the present invention are shown. Figure 13A The cross-sectional view is along Figure 13BThe bit line BL1 in the bottom view is intercepted, and Figure 13B The bottom view shows bit lines BL1, BL2 and BL3 overlapping with the first lower bonding pad LCP2Xa and the second lower bonding pad LBP2Ya. Figure 13A and Figure 13B The upper structure S2XYa in the middle is similar to that in the middle. Figure 5A and Figure 5B as well as Figure 6A and Figure 6B The upper structures S2Xa and S2Ya are shown in the figure, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0107] refer to Figure 13A and Figure 13B The upper structure S2XYa may include a connection to the lower structure S1 (see...). Figure 3 The first upper bonding pad UBP1 (see) Figure 3 The first lower bonding pad LBP2Xa, the first through-part THV1 connected to the first lower bonding pad LBP2Xa, the first upper bonding pad UBP2-1 connected to the first through-part THV1, and the connection to the lower structure S1 (see...) Figure 3 The second upper bonding pad UBP1 (see) Figure 3 The upper structure S2XYa includes a second lower bonding pad LBP2Ya, a first line BL1 connected to the second lower bonding pad LBP2Ya, and a memory cell array MCA connected to the first line BL1. In some embodiments, the upper structure S2XYa may include... Figure 5A and Figure 5B The upper structure S2Xa shown is Figure 6A and Figure 6B The combination of the upper structure S2Ya shown.

[0108] The first lower bonding pad LBP2Xa and the second lower bonding pad LBP2Ya can be disposed on the bottom surface of the upper structure S2XYa. The first first line BL1 may include a first portion P1, a second portion P2, and a first gap G1 between the first portion P1 and the second portion P2. The first lower bonding pad LBP2Xa is not connected to the first portion P1 and the second portion P2 of the first first line BL1. The first upper bonding pad UBP2-1 can be disposed at the upper end of the first through-hole THV1. In some embodiments, the upper structure S2XYa may further include a first internal pad IP1 that connects the first through-hole THV1 to the first upper bonding pad UBP2-1.

[0109] In some embodiments, the first through-hole THV1 may pass through the memory cell array MCA. Specifically, the first through-hole THV1 may pass through the stacked structure 110 in the vertical direction (Z direction). The first through-hole THV1 may be disposed in the first through-hole THVH1. In some embodiments, the upper structure S2XYa may further include a first through-hole insulating layer ILt1 between the side surface of the first through-hole THVH1 and the first through-hole THV1. In some embodiments, in a plan view, the first through-hole THV1 may overlap with the first gap G1 of the first bit line BL1.

[0110] In some embodiments, the upper structure S2XYa may further include a first lower connection pad LCP2Xa that connects the first portion P1 of the first bit line BL1 to the second portion P2 of the first bit line BL1. The first lower connection pad LCP2Xa is not connected to the first lower bonding pad LBP2Xa. In some embodiments, the upper structure S2XYa may further include a first via V1Xa that connects the first lower bonding pad LBP2Xa to the first through member THV1, a second via V2Xa that connects the first lower connection pad LCP2Xa to the first portion P1 of the first bit line BL1, and a third via V3Xa that connects the first lower connection pad LCP2Xa to the second portion P2 of the first bit line BL1.

[0111] In some embodiments, the upper structure S2XYa may further include a second through-hole THV2 connected to the second lower bonding pad LBP2Ya and a second upper bonding pad UBP2-2 connected to the second through-hole THV2. That is, the second through-hole THV2 and the first line BL1 may be connected to the second lower bonding pad LBP2Ya. In some embodiments, the upper structure S2XYa may further include a second internal pad IP2 connecting the second through-hole THV2 to the second upper bonding pad UBP2-2.

[0112] In some embodiments, the first line BL1 may further include a third portion P3 and a second gap G2 between the second portion P2 and the third portion P3 of the first line BL1. The second lower bonding pad LBP2Ya may be connected to the second portion P2 and the third portion P3 of the first line BL1. In some embodiments, the upper structure S2XYa may further include a fourth via V1Ya connecting the second lower bonding pad LBP2Ya to the second through member THV2, a fifth via V2Ya connecting the second lower bonding pad LBP2Ya to the second portion P2 of the first line BL1, and a sixth via V3Ya connecting the second lower bonding pad LBP2Ya to the third portion P3 of the first line BL1.

[0113] In some embodiments, the second through-hole THV2 may pass through the memory cell array MCA. Specifically, the second through-hole THV2 may pass through the stacked structure 110 in the vertical direction (Z direction). The second through-hole THV2 may be disposed in the second through-hole THVH2. In some embodiments, the upper structure S2XYa may further include a second through-hole insulating layer ILt2 between the side surface of the second through-hole THVH2 and the second through-hole THV2. In some embodiments, in a plan view, the second through-hole THV2 may overlap with the second gap G2 of the first line BL1.

[0114] Figure 14A and Figure 14B A cross-sectional view and a bottom view of the upper structure S2XYb included in a memory device according to an embodiment of the present invention are shown. Figure 14A The cross-sectional view in the middle is along Figure 14B The bottom view shown is intercepted by bit line BL1, and Figure 14B The bottom view shows bit lines BL1, BL2 and BL3 overlapping with the second lower bonding pad LBP2Ya. Figure 14A and Figure 14B The upper structure S2XYb is similar to Figure 13A and Figure 13B The upper structure S2XYb is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0115] refer to Figure 14A and Figure 14B ,and Figure 13A and Figure 13B Compared to the upper structure S2XYa shown, the second lower bonding pad LBP2Ya can be connected to the first portion P1 of the first line BL1, the second through member THV2, and the second and third portions P2 and P3 of the first line BL1. In some embodiments, the upper structure S2XYb may include a first via V1Ya connecting the second lower bonding pad LBP2Ya to the second through member THV2, a second via V2Ya connecting the second lower bonding pad LBP2Ya to the second portion P2 of the first line BL1, a third via V3Ya connecting the second lower bonding pad LBP2Ya to the third portion P3 of the first line BL1, a fourth via V4Ya connecting the second lower bonding pad LBP2Ya to the first portion P1 of the first line BL1, and a fifth via V1Xa connecting the first lower bonding pad LBP2Xa to the first through member THV1.

[0116] Figure 15A and Figure 15B A cross-sectional view and a bottom view of the upper structure S2XYc included in a memory device according to an embodiment of the present invention are shown. Figure 15A The cross-sectional view is along Figure 15B The bit line BL1 in the bottom view is intercepted, and Figure 15B The bottom view shows bit lines BL1, BL2 and BL3 overlapping with the first lower connection pad LCP2Xa and the lower line LL1Yb. Figure 15A and Figure 15B The upper structure S2XYc is similar to Figure 13A and Figure 13B The upper structure S2XYc is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0117] refer to Figure 15A and Figure 15B ,and Figure 13A and Figure 13B Compared to the upper structure S2XYa shown, the upper structure S2XYc may further include a second through-hole member THV2 and a lower line LL1Yb that connects the second portion P2 and the third portion P3 of the first line BL1 to the second lower bonding pad LBP2Yb. In some embodiments, the upper structure S2XYc may include Figure 5A and Figure 5B The upper structure S2Xa shown is Figure 8A and Figure 8B The combination of the upper structure S2Yb shown.

[0118] Figure 16A and Figure 16B Cross-sectional and bottom views of the upper structure included in a memory device according to an embodiment of the present invention are shown. Figure 16A The cross-sectional view in the middle is along Figure 16B The bottom view shown is intercepted by bit line BL1, and Figure 16B The bottom view shows bit lines BL1, BL2 and BL3 overlapping with the second lower bonding pad LBP2Yb and the lower line LL1Yb. Figure 16A and Figure 16B The upper structure S2XYd in the middle is similar to Figure 15A and Figure 15B The upper structure S2XYc is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0119] refer to Figure 16A and Figure 16B ,and Figure 15A and Figure 15BCompared to the upper structure S2XYc shown, the second lower bonding pad LBP2Yb can be connected to the first portion P1 of the first line BL1 and the lower line LL1Yb. In some embodiments, the upper structure S2XYd may include a first via V1Xa connecting the first lower bonding pad LBP2Xa to the first through member THV1 and a second via V4Xa connecting the second lower bonding pad LBP2Yb to the first portion P1 of the first line BL1.

[0120] Figure 17A and Figure 17B A cross-sectional view and a bottom view of the upper structure S2XYe included in a memory device according to an embodiment of the present invention are shown. Figure 17A The cross-sectional view in the middle is along Figure 17B The bit line BL1 shown in the bottom view is intercepted, and Figure 17B The bottom view shows that bit lines BL1, BL2 and BL3 overlap with the second lower bonding pad LBP2Yb and the lower line LL1Yb. Figure 17A and Figure 17B The upper structure S2XYe is similar to Figure 15A and Figure 15B The upper structure S2XYc is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0121] refer to Figure 17A and Figure 17B ,and Figure 15A and Figure 15B Compared to the upper structure S2XYc shown, the lower line LL1Yb can connect the second through-hole THV2 and the third portion P3 of the first line BL1 to the second lower bonding pad LBP2Yb. The second lower bonding pad LBP2Yb can be connected to the first portion P1 of the first line BL1 and the lower line LL1Yb. In some embodiments, the upper structure S2XYe may further include a first via V1Xa connecting the first lower bonding pad LBP2Xa to the first through-hole THV1, a second via V4Xa connecting the second lower bonding pad LBP2Yb to the first portion P1 of the first line BL1, and a third via V5Xa connecting the second lower bonding pad LBP2Yb to the second portion P2 of the first line BL1.

[0122] Figure 18A and Figure 18B A cross-sectional view and a bottom view of the upper structure S2XYf included in a memory device according to an embodiment of the present invention are shown. Figure 18A The cross-sectional view in the middle is along Figure 18B The bottom view shown is intercepted by bit line BL1, and Figure 18BThe bottom view shows that bit lines BL1, BL2 and BL3 overlap with the second lower line LL2Xb and the second lower bonding pad LBP2Ya. Figure 18A and Figure 18B The upper structure S2XYf in the middle is similar to Figure 13A and Figure 13B The upper structure S2XYa is shown below, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0123] refer to Figure 18A and Figure 18B ,and Figure 13A and Figure 13B Compared to the upper structure S2XYa shown, the upper structure S2XYf may further include a first lower line LL1Xb connecting the first lower bonding pad LBP2Xb to the first through member THV1 and a second lower line LL2Xb connecting the first portion P1 of the first line BL1 to the second portion P2 of the first line BL1. As shown, the second lower line LL2Xb is not connected to the first lower bonding pad LBP2Xb. In some embodiments, the upper structure S2XYf may include Figure 7A and Figure 7B The upper structure S2Xb shown is Figure 6A and Figure 6B The combination of the upper structure S2Ya shown.

[0124] Figure 19A and Figure 19B A cross-sectional view and a bottom view of the upper structure S2XYg included in a memory device according to an embodiment of the present invention are shown. Figure 19A The cross-sectional view in the middle is along Figure 19B The bit line BL1 in the bottom view is intercepted, and Figure 19B The bottom view shows that bit lines BL1, BL2 and BL3 overlap with the second lower line LL2Xb and the second lower bonding pad LBP2Ya. Figure 19A and Figure 19B The upper structure S2XYg is similar to Figure 18A and Figure 18B The upper structure S2XYf is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0125] refer to Figure 19A and Figure 19B ,and Figure 18A and Figure 18BCompared to the upper structure S2XYf shown, the second lower line LL2Xb can be connected to the second lower bonding pad LBP2Ya. The second lower bonding pad LBP2Ya can be connected to the second portion P2 of the first line BL1 via the second lower line LL2Xb. The upper structure S2XYg may include a first via V1Ya connecting the second lower bonding pad LBP2Ya to the second through member THV2 and a second via V3Ya connecting the second lower bonding pad LBP2Ya to the third portion P3 of the first line BL1.

[0126] Figure 20A and Figure 20B A cross-sectional view and a bottom view of the upper structure S2XYh included in a memory device according to an embodiment of the present invention are shown. Figure 20A The cross-sectional view in the middle is along Figure 20B The bottom view shown is intercepted by bit line BL1, and Figure 20B The bottom view shows that bit lines BL1, BL2 and BL3 overlap with the second lower line LL2Xb and the second lower bonding pad LBP2Ya. Figure 20A and Figure 20B The upper structure S2XYh in the middle is similar to Figure 18A and Figure 18B The upper structure S2XYf is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0127] refer to Figure 20A and Figure 20B ,and Figure 18A and Figure 18B Compared to the upper structure S2XYf shown, the second lower line LL2Xb can be connected to the first portion P1 of the first line BL1 and the second lower bonding pad LBP2Ya. The second lower line LL2Xb can be connected to the second portion P2 of the first line BL1 via the second lower bonding pad LBP2Ya.

[0128] Figure 21A and Figure 21B A cross-sectional view and a bottom view of the upper structure S2XYi included in a memory device according to an embodiment of the present invention are shown. Figure 21A The cross-sectional view in the middle is along Figure 21B The bottom view shown is intercepted by bit line BL1, and Figure 21B The bottom view shows that bit lines BL1, BL2 and BL3 overlap with the second lower line LL2Xb and the third lower line LL1Yb. Figure 21A and Figure 21B The upper structure S2XYi is similar to Figure 18A and Figure 18BThe upper structure S2XYf is shown, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0129] refer to Figure 21A and Figure 21B ,and Figure 18A and Figure 18B Compared to the upper structure S2XYf shown, the upper structure S2XYi may further include a second through-hole member THV2 and a third lower line LL1Yb that connects the second portion P2 and the third portion P3 of the first line BL1 to the second lower bonding pad LBP2Yb. In some embodiments, the upper structure S2XYi may include Figure 7A and Figure 7B The upper structure S2Xb shown is Figure 8A and Figure 8B The combination of the upper structure S2Yb shown.

[0130] Figure 22A and Figure 22B A cross-sectional view and a bottom view of the upper structure S2XYj included in a memory device according to an embodiment of the present invention are shown. Figure 22A The cross-sectional view in the middle is along Figure 22B The bottom view shown is intercepted by bit line BL1, and Figure 22B The bottom view shows that bit lines BL1, BL2 and BL3 overlap with the third lower line LL1Yb. Figure 22A and Figure 22B The upper structure S2XYj is similar to Figure 21A and Figure 21B The upper structure S2XYi is shown below, and the following description will focus mainly on the differences between them, while omitting the description of similar elements and structures.

[0131] refer to Figure 22A and Figure 22B ,and Figure 21A and Figure 21B Compared to the upper structure S2XYi shown, the third lower line LL1Yb can connect to the first portion P1 of the first line BL1, the second through-hole THV2, and the second portion P2 and the third portion P3 of the first line BL1. In other words, the third lower line LL1Yb can connect the second lower bonding pad LBP2Yb to the first portion P1, the second portion P2, the third portion P3 of the first line BL1, and the second through-hole THV2.

[0132] Figure 23 A bottom view of the upper structure S2XYk included in a memory device according to an embodiment of the present invention is shown.

[0133] refer to Figure 23The first line BL1 may include a first portion P1, a second portion P2, and a gap G1 between the first portion P1 and the second portion P2. In the plan view, the first through-piece THV1 may overlap with the gap G1 of the first line BL1. The first lower bonding pad LBP2Xa may be connected to the first through-piece THV1. The first lower connecting pad LCP2Xa may connect the first portion P1 of the first line BL1 to the second portion P2 of the first line BL1, and as shown, the first lower connecting pad LCP2Xa is not connected to the first lower bonding pad LBP2Xa.

[0134] A second bit line BL2 extending parallel to the first bit line BL1 may include a first portion P1, a second portion P2, and a first gap G1 between the first portion P1 and the second portion P2. In the bottom view, a second through-piece THV2 may overlap with the gap G1 of the second bit line BL2. A second lower bonding pad LBP2Ya may be connected to the second through-piece THV2 and the first portion P1 and the second portion P2 of the second bit line BL2. As shown, the second lower bonding pad LBP2Ya is not connected to the first lower bonding pad LCP2Xa.

[0135] In some embodiments, the upper structure S2XYk may include a first via V1Xa connecting the first through member THV1 to the first lower bonding pad LBP2Xa, a second via V2Xa connecting the first part P1 of the first bit line BL1 to the first lower bonding pad LCP2Xa, a third via V3Xa connecting the second part P2 of the first bit line BL1 to the first lower bonding pad LCP2Xa, a fourth via V1Ya connecting the second through member THV2 to the second lower bonding pad LBP2Ya, a fifth via V2Ya connecting the first part P1 of the second bit line BL2 to the second lower bonding pad LBP2Ya, and a sixth via V3Ya connecting the second part P2 of the second bit line BL2 to the second lower bonding pad LBP2Ya.

[0136] Figure 24 A bottom view of the upper structure S2XYl included in a memory device according to an embodiment of the present invention is shown.

[0137] refer to Figure 24 ,and Figure 23 Compared to the upper structure S2XYk shown, the upper structure S2XYl may further include a second through-hole component THV2 and a lower line LL1Yb connecting the second lower bonding pad LBP2Yb to the second through-hole component THV2 and the first portion P1 and the second portion P2 of the second bit line BL2. The lower line LL1Yb is not connected to the first bonding pad LCP2Xa. The lower line LL1Yb is disposed on the second lower bonding pad LBP2Yb.

[0138] Figure 25 A bottom view of the upper structure S2XYm included in a memory device according to an embodiment of the present invention is shown.

[0139] refer to Figure 25 ,and Figure 23 Compared to the upper structure S2XYk shown, the upper structure S2XYm may include a first lower line LL2Xb that connects the first portion P1 of the first bit line BL1 to the second portion P2 of the first bit line BL1, and the first lower line LL2Xb is not connected to the first lower bonding pad LBP2Xb and the second lower bonding pad LBP2Ya.

[0140] In some embodiments, the upper structure S2XYm may include a first via V1Ya connecting the second through member THV2 to the second lower bonding pad LBP2Ya, a second via V2Ya connecting the first portion P1 of the second bit line BL2 to the second lower bonding pad LBP2Ya, a third via V3Ya connecting the second portion P2 of the second bit line BL2 to the second lower bonding pad LBP2Ya, and a fourth via V1Xa connecting the first through member THV1 to the first lower bonding pad LBP2Xb.

[0141] Figure 26 A bottom view of the upper structure S2XYn included in a memory device according to an embodiment of the present invention is shown.

[0142] refer to Figure 26 ,and Figure 25 Compared to the upper structure S2XYm shown, the upper structure S2XYn may further include a second through-hole THV2 and a second lower line LL1Yb that connects the second lower bonding pad LBP2Yb to the first portion P1 and the second portion P2 of the second bit line BL2. The second lower line LL1Yb is not connected to the first lower line LL2Xb. The upper structure S2XYn may include a first via V1Xa that connects the first through-hole THV1 to the first lower bonding pad LBP2Xb.

[0143] Figure 27 A bottom view of the upper structure S2XXa included in a memory device according to an embodiment of the present invention is shown.

[0144] refer to Figure 27 The first line BL1 may include a first portion P1, a second portion P2, a third portion P3, a first gap G1 between the first portion P1 and the second portion P2, and a second gap G2 between the second portion P2 and the third portion P3. In the plan view, the first through member THV1 may overlap with the first gap G1 of the first line BL1, and the second through member THV2 may overlap with the second gap G2 of the first line BL1.

[0145] The first lower bonding pad LBP2Xa-1 can be connected to the first through-piece THV1, and as shown, the first lower bonding pad LBP2Xa-1 is not connected to the first portion P1, the second portion P2, and the third portion P3 of the first line BL1. The second lower bonding pad LBP2Xa-2 can be connected to the second through-piece THV2, and also as shown, the second lower bonding pad LBP2Xa-2 is not connected to the first portion P1, the second portion P2, and the third portion P3 of the first line BL1. The lower connecting pad LCP2Xa can connect the first portion P1 of the first line BL1 to the second portion P2 of the first line BL1, and can connect the second portion P2 of the first line BL1 to the third portion P3 of the first line BL1.

[0146] The upper structure S2XXa may include a first via V1Xa connecting the first through member THV1 to the first lower bonding pad LBP2Xa-1, a second via V2Xa connecting the first part P1 of the first line BL1 to the lower bonding pad LCP2Xa, a third via V3Xa connecting the second part P2 of the first line BL1 to the lower bonding pad LCP2Xa, a fourth via V4Xa connecting the third part P3 of the first line BL1 to the lower bonding pad LCP2Xa, and a fifth via V1Ya connecting the second through member THV2 to the second lower bonding pad LBP2Xa-2.

[0147] Figure 28 A bottom view of the upper structure S2XXb included in a memory device according to an embodiment of the present invention is shown.

[0148] refer to Figure 28 The first lower connection pad LCP2Xa-1 connects the first portion P1 of the first bit line BL1 to the second portion P2 of the first bit line BL1, and as shown, the first lower connection pad LCP2Xa-1 is not connected to the first lower bonding pad LBP2Xa-1. The first lower connection pad LCP2Xa-1 can have any shape that connects the first portion P1 of the first bit line BL1 to the second portion P2 of the first bit line BL1 and is not connected to the first lower bonding pad LBP2Xa-1.

[0149] A fifth bit line BL5 extending parallel to the first bit line BL1 may include a first portion P1, a second portion P2, and a first gap G1 between the first portion P1 and the second portion P2. In a plan view, a second through-hole THV2 may overlap with the first gap G1 of the fifth bit line BL5. A second lower bonding pad LBP2Xa-2 may be connected to the second through-hole THV2. A second lower connection pad LCP2Xa-2 may connect the first portion P1 of the fifth bit line BL5 to the second portion P2 of the fifth bit line BL5, and as shown, the second lower connection pad LCP2Xa-2 is not connected to the second lower bonding pad LBP2Xa-2 and the first lower connection pad LCP2Xa-1. The second lower connection pad LCP2Xa-2 may have any shape that connects the first portion P1 of the fifth bit line BL5 to the second portion P2 of the fifth bit line BL5 and does not connect the second lower bonding pad LBP2Xa-2 and the first lower connection pad LCP2Xa-1.

[0150] In some embodiments, the upper structure S2XXb may include a first via V1Xa-1 connecting the first through member THV1 to the first lower bonding pad LBP2Xa-1, a second via V2Xa-1 connecting the first part P1 of the first bit line BL1 to the first lower bonding pad LCP2Xa-1, a third via V3Xa-1 connecting the second part P2 of the first bit line BL1 to the first lower bonding pad LCP2Xa-1, a fourth via V1Xa-2 connecting the second through member THV2 to the second lower bonding pad LBP2Xa-2, a fifth via V2Xa-2 connecting the first part P1 of the fifth bit line BL5 to the second lower bonding pad LCP2Xa-2, and a sixth via V3Xa-2 connecting the second lower bonding pad LCP2Xa-2 to the second lower bonding pad LCP2Xa-2.

[0151] Figure 29 A cross-sectional view of a memory device 10YY according to an embodiment of the present invention is shown.

[0152] refer to Figure 29 The memory device 10YY may include a first structure S1 to a third structure S3 stacked in the vertical direction (Z direction). For example, the first structure S1 may be the one referenced above. Figure 4 The lower structure S1a is described, and each of the second structure S2 and the third structure S3 can be referenced above. Figure 6A and Figure 6BThe upper structure S2Ya is described. The first line BL1 of the third structure S3 can be connected to the lower bonding pad LBP2Ya of the third structure S3, and can be connected to the lower bonding pad LBP2Ya of the second structure S2 through the upper bonding pad UBP2 of the second structure S2 and the through-hole THV of the second structure S2. The first line BL1 of the second structure S2 can be connected to the lower bonding pad LBP2Ya of the second structure S2. Therefore, the first line BL1 of the second structure S2 and the first line BL1 of the third structure S3 can be connected to the same transistor of the peripheral circuit PC. That is, the first line BL1 of the second structure S2 and the first line BL1 of the third structure S3 can be connected to the same node.

[0153] Figure 30 A cross-sectional view of a memory device 10YX according to an embodiment of the present invention is shown.

[0154] refer to Figure 30 The memory device 10YX may include a first structure S1 to a third structure S3 stacked in the vertical direction (Z direction). For example, the first structure S1 may be the one referenced above. Figure 4 The lower structure S1a and the second structure S2 described above can be referenced above. Figure 6A and Figure 6B The upper structure S2Ya is described, and the third structure S3 can be the above reference. Figure 5A and Figure 5B The upper structure S2Xa is described. The first line BL1 of the third structure S3 is not connected to the lower bonding pad LBP2Xa of the third structure S3; therefore, the first line BL1 of the third structure S3 is not connected to the lower bonding pad LBP2Ya of the second structure S2. On the other hand, the first line BL1 of the second structure S2 can be connected to the lower bonding pad LBP2Ya of the second structure S2. Therefore, the first line BL1 of the second structure S2 and the first line BL1 of the third structure S3 can be connected to different transistors in the peripheral circuit PC. That is, the first line BL1 of the second structure S2 and the first line BL1 of the third structure S3 can be connected to different nodes.

[0155] Figure 31 A cross-sectional view of a memory device 10XY according to an embodiment of the present invention is shown.

[0156] refer to Figure 31 The memory device 10XY may include a first structure S1 to a third structure S3 stacked in the vertical direction (Z direction). For example, the first structure S1 may be the one referenced above. Figure 4 The lower structure S1a and the second structure S2 described above can be referenced above. Figure 5A and Figure 5BThe upper structure S2Xa is described, and the third structure S3 can be the above reference. Figure 6A and Figure 6B The upper structure S2Ya is described. The first line BL1 of the third structure S3 can be connected to the lower bonding pad LBP2Ya of the third structure S3. Therefore, the first line BL1 of the third structure S3 can be connected to the lower bonding pad LBP2Xa of the second structure S2 through the upper bonding pad UBP2 of the second structure S2 and the through-hole THV of the second structure S2. On the other hand, the first line BL1 of the second structure S2 is not connected to the lower bonding pad LBP2Xa of the second structure S2. Therefore, the first line BL1 of the second structure S2 and the first line BL1 of the third structure S3 can be connected to different transistors in the peripheral circuit PC. That is, the first line BL1 of the second structure S2 and the first line BL1 of the third structure S3 can be connected to different nodes.

[0157] Figure 32 A cross-sectional view of a memory device 10XX according to an embodiment of the present invention is shown.

[0158] refer to Figure 32 The memory device 10XX may include a first structure S1 to a third structure S3 stacked in a vertical direction (Z direction). For example, the first structure S1 may be the one referenced above. Figure 4 The lower structure S1a is described, and each of the second structure S2 and the third structure S3 can be referenced above. Figure 5A and Figure 5B The lower structure S2Xa is described. The first line BL1 of the third structure S3 is not connected to the lower bonding pad LBP2Xa of the third structure S3, and the first line BL1 of the second structure S2 is not connected to the lower bonding pad LBP2Xa of the second structure S2. That is, the electrical path formed by the through-hole THV of the second structure S2 and the through-hole THV of the third structure S3 is not used for the electrical connection between the first line BL1 of the second structure S2 and the third structure S3 and the peripheral circuit PC.

[0159] refer to Figures 3 to 32Interconnected through-holes (e.g., THV, THV1, and THV2) and bonding pads (e.g., LBP2Xa, LBP2Xb, LBP2Ya, LBP2Yb, UBP2, UBP1a, UBP1Xb, UBP1Yb, UBP1Xc, and UBP1Yc) can serve as electrical paths between bit lines (e.g., BL1) of the structure (e.g., S1 to S5) and peripheral circuitry PC. By appropriately selecting the bonding pads (e.g., LBP2Xa, LBP2Xb, LBP2Ya, LBP2Yb, UBP2, UBP1a, UBP1Xb, UBP1Yb, UBP1Xc, and UBP1Yc) and lower lines (e.g., LL1Xb, LL2Xb, and LL1Yb) for each structure (e.g., S1 to S5), the bit lines (e.g., BL1) of the structures (e.g., S1 to S5) can be connected to or not connected to the electrical path to the peripheral circuit PC. Therefore, the bit lines (e.g., BL1) of different structures (e.g., S1 to S5) can be easily connected to the same node or different nodes. For example, in an embodiment, the first bit line BL1 of the second structure S2 and the first bit line BL1 of the third structure S3 can be connected to different nodes, and the first bit line BL1 of the second structure S2 and the first bit line BL1 of the fourth structure S4 can be connected to the same node.

[0160] When bit lines BL1, which are connected to different structures S1 to S5, are connected to the same node, the number of transistors TR required by the peripheral circuit PC can be reduced, thus reducing the planar area of ​​the memory device, but potentially decreasing its performance. Conversely, when bit lines BL1, which are connected to different structures S1 to S5, are connected to different nodes, the performance of the memory device can be increased, but the number of transistors TR required by the peripheral circuit PC can increase, leading to an increase in the planar area of ​​the memory device. Therefore, the planar area and performance of the memory device according to this embodiment can be easily adjusted.

[0161] Figure 33 A cross-sectional view of a memory device 10XXa according to an embodiment of the present invention is shown.

[0162] refer to Figure 33 The memory device 10XXa may include a first structure S1 to a third structure S3 stacked in a vertical direction (Z direction). The first structure S1 may include peripheral circuitry, each similar to the one described above. Figure 4 The peripheral circuit PC is described as having a first part PC1 and a second part PC2 that are separate from each other, a first upper bonding pad UBP1a-1 connected to the first part PC1 of the peripheral circuit, and a second upper bonding pad UBP1a-2 connected to the second part PC2 of the peripheral circuit.

[0163] The second structure S2 can be similar to Figure 5Aand Figure 5B The structure shown may include a first lower bonding pad LBP2Xa-1 connected to a first upper bonding pad UBP1a-1 of the first structure S1, a first through-hole THV1 connected to the first lower bonding pad LBP2Xa-1, a first upper bonding pad UBP2-1 connected to the first through-hole THV1, a memory cell array MCA through which the first through-hole THV1 passes, and a first bit line BL1 connected to the memory cell array MCA. The second structure S2 may also include a second lower bonding pad LBP2Xa-2 connected to a second upper bonding pad UBP1a-2 of the first structure S1, a second through-hole THV2 connected to the second lower bonding pad LBP2Xa-2, and a second upper bonding pad UBP2-2 connected to the second through-hole THV2. In some embodiments, the second through-hole THV2 of the second structure S2 does not pass through the memory cell array MCA of the second structure S2 and may be located at an external portion of the second structure S2 outside the memory cell array MCA of the second structure S2.

[0164] The third structure S3 can be similar to Figure 5A and Figure 5B The structure shown may include a first lower bonding pad LBP2Xa-1 connected to a first upper bonding pad UBP2-1 of the second structure S2, a first through-hole THV1 connected to the first lower bonding pad LBP2Xa-1, a first upper bonding pad UBP2-1 connected to the first through-hole THV1, a memory cell array MCA through which the first through-hole THV1 passes, and a first bit line BL1 connected to the memory cell array MCA. The third structure S3 may also include a second lower bonding pad LBP2Xa-2 connected to a second upper bonding pad UBP2-2 of the second structure S2, a second through-hole THV2 connected to the second lower bonding pad LBP2Xa-2, and a second upper bonding pad UBP2-2 connected to the second through-hole THV2. In some embodiments, the second through-hole THV2 of the third structure S3 does not pass through the memory cell array MCA of the third structure S3 and may be located at an external portion of the third structure S3 outside the memory cell array MCA of the third structure S3.

[0165] The first line BL1 of the second structure S2 is not connected to the first lower bonding pad LBP2Xa-1 and the second lower bonding pad LBP2Xa-2 of the second structure S2. The first line BL1 of the third structure S3 is not connected to the first lower bonding pad LBP2Xa-1 and the second lower bonding pad LBP2Xa-2 of the third structure S3. The memory device 10XXa may also include a connection line CL disposed on the third structure S3 and connecting the first upper bonding pad UBP2-1 of the third structure S3 to the second upper bonding pad UBP2-2 of the third structure S3.

[0166] Therefore, the first part of the peripheral circuit PC1 can be connected to the second part of the peripheral circuit PC2 through the first upper bonding pad UBP1a-1 of the first structure S1, the first lower bonding pad LBP2Xa-1 of the second structure S2, the first through-hole THV1 of the second structure S2, the first upper bonding pad UBP2-1 of the second structure S2, the first lower bonding pad LBP2Xa-1 of the third structure S3, the first through-hole THV1 of the third structure S3, the first upper bonding pad UBP2-1 of the third structure S3, the connecting line CL, the second upper bonding pad UBP2-2 of the third structure S3, the second through-hole THV2 of the third structure S3, the second lower bonding pad LBP2Xa-2 of the third structure S3, the second upper bonding pad UBP2-2 of the second structure S2, the second through-hole THV2 of the second structure S2, the second lower bonding pad LBP2Xa-2 of the second structure S2, and the second upper bonding pad UBP1a-2 of the first structure S1. In other words, the first line BL1 of the second structure S2 and the third structure S3 is not connected to the first through member THV1 and the second through member THV2 of the second structure S2 and the third structure S3, and the first through member THV1 and the second through member THV2 of the second structure S2 and the third structure S3 can be used as an electrical path between the first part PC1 and the second part PC2 of the peripheral circuit.

[0167] Figure 34 A cross-sectional view of a memory device 10XXb according to an embodiment of the present invention is shown.

[0168] refer to Figure 34 , as referenced above Figure 33 Compared to the described memory device 10XXa, similar to the first through-piece THV1 of the second structure S2, the second through-piece THV2 of the second structure S2 can pass through the memory cell array MCA of the second structure S2. Furthermore, the second through-piece THV2 of the third structure S3 can pass through the memory cell array MCA of the third structure S3.

[0169] Figures 35A to 35D A cross-sectional view is shown of a method for manufacturing a memory device according to an embodiment of the present invention.

[0170] refer to Figure 35A The second structure S2 can be formed on the first substrate 131. However, the upper bonding pad of the second structure S2 (e.g., UBP2) (see...) Figure 35C The second structure S2 may not have been formed yet. Figure 5A and Figure 5B The upper structure S2Xa shown in the figure Figure 6A and Figure 6B The upper structure S2Ya shown in the figure Figure 7A and Figure 7B The upper structure S2Xb shown in the figure Figure 8A and Figure 8B The upper structure S2Yb shown in the figure Figure 13A and Figure 13B The upper structure S2XYa shown in the figure Figure 14A and Figure 14B The upper structure S2XYb shown in the figure Figure 15A and Figure 15B The upper structure S2XYc shown in the figure Figure 16A and Figure 16B The upper structure S2XYd shown in the figure Figure 17A and Figure 17B The upper structure S2XYe shown in the figure Figure 18A and Figure 18B The upper structure S2XYf shown in the figure Figure 19A and Figure 19B The upper structure S2XYg shown in the figure Figure 20A and Figure 20B The upper structure S2XYh shown in the figure Figure 21A and Figure 21B The upper structure S2XYi shown in the figure Figure 22A and Figure 22B The upper structure S2XYj shown in the figure Figure 23 The upper structure S2XYk shown in the figure Figure 24 The upper structure S2XYl shown in the figure Figure 25 The upper structure S2XYm shown in the figure Figure 26 The upper structure S2XYn shown in the figure Figure 27 The upper structure S2XXa shown in the figure Figure 28 The upper structure S2XXb, or a combination thereof, is shown in the figure.

[0171] refer to Figure 35B This can form a first structure S1. The first structure S1 may include... Figure 4 The lower structure S1a shown in the figure Figure 9A and Figure 9B The lower structure S1Xb shown in the figure Figure 10A and Figure 10B The lower structure S1Yb shown in the figure Figure 11A and Figure 11B The lower structure S1Xc shown in the figure Figure 12A and Figure 12B The lower structure S1Yc, or a combination thereof, is shown in the figure.

[0172] Subsequently, the second structure S2 can be aligned with the first structure S1, such that the lower bonding pad LBP2Xa of the second structure S2 contacts the upper bonding pad UBP1a of the first structure S1, and the first structure S1 can be bonded to the second structure S2. In some embodiments, when heat and / or pressure are applied to the first structure S1 and the second structure S2, the upper bonding pad UBP1a of the first structure S1 and the lower bonding pad LBP2Xa of the second structure S2 can be reflowed, so that the upper bonding pad UBP1a of the first structure S1 and the lower bonding pad LBP2Xa of the second structure S2 can be bonded together.

[0173] refer to Figure 35B and Figure 35C The first substrate 131 can be removed from the second structure S2. Subsequently, the upper bonding pad UBP2 can be formed on the inner pad IP of the second structure S2.

[0174] refer to Figure 35D Similar to the reference above Figure 35A As described above, a third structure S3 may be formed on the second substrate 132. However, the upper bonding pad of the third structure S3 may not be formed. Subsequently, the third structure S3 may be aligned on the second structure S2 such that the lower bonding pad LBP2Ya of the third structure S3 contacts the upper bonding pad UBP2 of the second structure S2, and the second structure S2 may be bonded to the third structure S3. In some embodiments, when heat and / or pressure are applied to the second structure S2 and the third structure S3, the upper bonding pad UBP2 of the second structure S2 and the lower bonding pad LBP2Ya of the third structure S3 may be reflowed, thus allowing the upper bonding pad UBP2 of the second structure S2 and the lower bonding pad LBP2Ya of the third structure S3 to bond together. By using a method similar to the above reference... Figures 35B to 35D The method described above can also be used to stack other structures on the third structure S3.

[0175] Therefore, a memory device according to the embodiment can be manufactured. According to the method of manufacturing the memory device, a first structure S1 including peripheral circuitry PC and second structures S2 and third structures S3, each including a memory cell array MCA, can be manufactured separately and can be joined to each other, thereby preventing the previously manufactured peripheral circuitry PC from being damaged by heat and stress occurring during the manufacturing of the memory cell array MCA. Furthermore, a memory device with enhanced integration can be manufactured by stacking the first structure S1 to the third structure S3.

[0176] Figure 36A and Figure 36B A cross-sectional view and a bottom view of the upper structure S2Xc included in a memory device according to an embodiment of the present invention are shown.

[0177] refer to Figure 36Aand Figure 36B ,and Figure 5A and Figure 5B Compared to the upper structure S2Xa shown, the upper structure S2Xc may further include a first lower line LL1c connecting the second via V2Xc and the first portion P1 of the first line BL1, and a second lower line LL2c connecting the third via V3Xc and the second portion P2 of the first line BL1. In some embodiments, the width and spacing of the first lower line LL1c and the second lower line LL2c may be greater than the width and spacing of the first to fourth lines BL1 to BL4, so that the second via V2Xc and the third via V3Xc can be easily aligned in the first lower line LL1c and the second lower line LL2c, respectively.

[0178] Figure 37A and Figure 37B A cross-sectional view and a bottom view of the upper structure S2Yc included in a memory device according to an embodiment of the present invention are shown.

[0179] refer to Figure 37A and Figure 37B ,and Figure 6A and Figure 6B Compared to the upper structure S2Ya shown, the upper structure S2Yc may further include a first lower line LL1c connecting the second via V2Yc and the first portion P1 of the first line BL1, and a second lower line LL2c connecting the third via V3Yc and the second portion P2 of the first line BL1. In some embodiments, the width and spacing of the first lower line LL1c and the second lower line LL2c may be greater than the width and spacing of the first to fourth lines BL1 to BL4, so that the second via V2Yc and the third via V3Yc can be easily aligned in the first lower line LL1c and the second lower line LL2c, respectively.

[0180] Figure 38 A bottom view of the upper structure S2XYo included in a memory device according to an embodiment of the present invention is shown. Figure 39 A bottom view of the upper structure S2XYp included in a memory device according to an embodiment of the present invention is shown.

[0181] refer to Figure 38 and Figure 39The first line BL1 and the second line BL2 may each include a first portion P1, a second portion P2, and a gap G1 between the first portion P1 and the second portion P2. A first via V1 may be disposed on a first through-piece THV1. A second via V2 and a fourth via V4 may be disposed on the first portion P1 of the first line BL1. A third via V3 and a fifth via V5 may be disposed on the second portion P2 of the first line BL1. A sixth via V6 may be disposed on the second through-piece THV2. A seventh via V7 and a ninth via V9 may be disposed on the first portion P1 of the second line BL2. An eighth via V8 and a tenth via V10 may be disposed on the second portion P2 of the second line BL2.

[0182] exist Figure 38 In the upper structure S2XYo shown, the first lower bonding pad LBP2a-1 can be connected to the first through-hole THV1 via the first via V1, connected to the first portion P1 of the first bit line BL1 via the second via V2, and connected to the second portion P2 of the first bit line BL1 via the third via V3. The second lower bonding pad LBP2a-2 can be connected to the second through-hole THV2 via the sixth via V6. The lower connection pad LCP2a-2 can be connected to the first portion P1 of the second bit line BL2 via the ninth via V9, and connected to the second portion P2 of the second bit line BL2 via the tenth via V10. The fourth via V4 and the fifth via V5 can be provided on the first bit line BL1, but as shown in the figure, the fourth via V4 and the fifth via V5 are not used for connection. The seventh via V7 and the eighth via V8 can be provided on the second bit line BL2, but the seventh via V7 and the eighth via V8 are also not used for connection. Each of the fourth via V4, fifth via V5, seventh via V7, and eighth via V8 that is not connected to the first lower bonding pad LBP2a-1, the second lower bonding pad LBP2a-2, and the lower connecting pad LCP2a-2 can be referred to as a residual via.

[0183] In some embodiments, the superstructure S2XYo may further include at least one dummy pad, each dummy pad being disposed on at least one remaining via and not used for connection. For example, the superstructure S2XYo may further include a first dummy pad LDP1 on the fourth remaining via V4 and a second dummy pad LDP2 on the fifth remaining via V5. In some embodiments, dummy pads may not be provided on the seventh remaining via V7 and the eighth remaining via V8. In other embodiments, with Figure 38The illustrations differ, and multiple dummy pads can be respectively disposed on the seventh remaining via V7 and the eighth remaining via V8. In some embodiments, the first dummy pad LDP1 and the second dummy pad LDP2 may not contact any conductive elements other than the fourth remaining via V4 and the fifth remaining via V5. Therefore, the first dummy pad LDP1 and the second dummy pad LDP2 can electrically isolate the fourth remaining via V4 and the fifth remaining via V5, respectively.

[0184] exist Figure 39 In the upper structure S2XYp shown, the first lower bonding pad LBP2a-1 can be connected to the first through-hole THV1 via the first via V1. The lower connection pad LBP2a-1 can be connected to the first portion P1 of the first bit line BL1 via the fourth via V4, and to the second portion P2 of the first bit line BL1 via the fifth via V5. The second lower bonding pad LBP2a-2 can be connected to the second through-hole THV2 via the sixth via V6, to the first portion P1 of the second bit line BL2 via the seventh via V7, and to the second portion P2 of the second bit line BL2 via the eighth via V8. The second via V2 and the third via V3 can be disposed on the first bit line BL1, but are not used for connection. The ninth via V9 and the tenth via V10 can be disposed on the second bit line BL2, but are not used for connection. Each of the second via V2, third via V3, ninth via V9, and tenth via V10 that is not connected to the first lower bonding pad LBP2a-1 and the second lower bonding pad LBP2a-2 and the lower connecting pad LCP2a-1 can be referred to as a residual via.

[0185] In some embodiments, the upper structure S2XYp may further include at least one dummy pad, each dummy pad being disposed on at least one remaining via and not used for connection. For example, the upper structure S2XYp may further include a third dummy pad LDP3 on the ninth remaining via V9 and a fourth dummy pad LDP4 on the tenth remaining via V10. In some embodiments, dummy pads may not be disposed on the second remaining via V2 and the third remaining via V3. In other embodiments, with Figure 39 Different illustrations exist, and multiple dummy pads can be respectively disposed on the second remaining via V2 and the third remaining via V3. In some embodiments, the third dummy pad LDP3 and the fourth dummy pad LDP4 may not contact any conductive elements other than the ninth remaining via V9 and the tenth remaining via V10. Therefore, the third dummy pad LDP3 and the fourth dummy pad LDP4 can electrically isolate the ninth remaining via V9 and the tenth remaining via V10, respectively.

[0186] As described above, the first vias V1 to the tenth vias V10 can be formed in advance and appropriately, regardless of the connection relationships between the first lower bonding pad LBP2a-1 and the second lower bonding pad LBP2a-2, the first lower connecting pad LCP2a-1 and the second lower connecting pad LCP2a-2, and the first bit line BL1 to the fourth bit line BL4. Then, based on the connection relationships between the first lower bonding pad LBP2a-1 and the second lower bonding pad LBP2a-2, and the first lower connecting pad LCP2a-1 and the second lower connecting pad LCP2a-2, only some of the first vias V1 to the tenth vias V10 can be used. For example, in the state where the first vias V1 to the tenth vias V10 are formed, such as... Figure 38 As shown, the first bit line BL1 can be connected to the first lower bonding pad LBP2a-1, and the second bit line BL2 is not connected to the second lower bonding pad LBP2a-2 but can be connected to the second lower connection pad LCP2a-2, or as... Figure 39 As shown, the first bit line BL1 is not connected to the first lower bonding pad LBP2a-1 but can be connected to the first lower connection pad LCP2a-1, and the second bit line BL2 can be connected to the second lower bonding pad LBP2a-2. The final superstructure can be determined during the final process of forming the first lower bonding pad LBP2a-1 and the second lower bonding pad LBP2a-2, as well as the first lower connection pad LCP2a-1 or the second lower connection pad LCP2a-2. Figure 38 The upper structure S2XYo shown is still as Figure 39 The upper structure S2XYp shown can reduce manufacturing costs.

[0187] Figure 40 A bottom view of the upper structure S2XYq included in a memory device according to an embodiment of the present invention is shown.

[0188] refer to Figure 40 ,and Figure 38Compared to the upper structure S2XYo shown, the upper structure S2XYq may further include a first lower line LLC1 connecting the second via V2 and the first portion P1 of the first line BL1, a second lower line LLC2 connecting the third via V3 and the second portion P2 of the first line BL1, a third lower line LLC3 connecting the ninth via V9 and the first portion P1 of the third line BL3, and a fourth lower line LLC4 connecting the tenth via V10 and the second portion P2 of the third line BL3. A fourth remaining via V4 may be disposed on the first lower line LLC1, and a fifth remaining via V5 may be disposed on the second lower line LLC2. A seventh remaining via V7 may be disposed on the third lower line LLC3, and an eighth remaining via V8 may be disposed on the fourth lower line LLC4.

[0189] Figure 41 A cross-sectional view of a memory device 10a according to an embodiment of the present invention is shown.

[0190] refer to Figure 41 The memory device 10a may include a first structure S1 to a third structure S3 stacked in the Z direction. The first structure S1 may be a cell-on-peri (COP) structure. That is, the first structure S1 may include a peripheral circuit PC and a first memory cell array MCA1 on the peripheral circuit PC, and the first memory cell array MCA1 may include a stacked structure having a stepped shape that ascends in the Z direction. For example, the first structure S1 may include... Figure 9A and Figure 9B The lower structure S1Xb shown in the figure Figure 10A and Figure 10B The lower structure S1Yb shown in the figure Figure 11A and Figure 11B The lower structure S1Xc shown in the figure Figure 12A and Figure 12B The lower structure S1Yc shown, or a combination thereof. The second structure S2 and the third structure S3 may each include a second memory cell array MCA2 and a third memory cell array MCA3, respectively. The second memory cell array MCA2 and the third memory cell array MCA3 may each include a stacked structure having a stepped shape descending in the Z direction. For example, the second structure S2 and the third structure S3 may each include Figure 5A and Figure 5B The upper structure S2Xa shown in the figure Figure 6A and Figure 6B The upper structure S2Ya shown in the figure Figure 7A and Figure 7B The upper structure S2Xb shown in the figure Figure 8A and Figure 8BThe upper structure S2Yb, or a combination thereof, is shown in the figure.

[0191] Figure 42 A cross-sectional view of a memory device 10b according to an embodiment of the present invention is shown.

[0192] refer to Figure 42 ,and Figure 41 In contrast, the second structure S2 and the third structure S3 of the memory device 10b can be reversed. That is, the second memory cell array MCA2 in the second structure S2 and the third memory cell array MCA3 in the third structure S3 can each include a stacked structure with a stepped shape that climbs in the Z direction.

[0193] Figure 43 A cross-sectional view of a memory device 10c according to an embodiment of the present invention is shown.

[0194] refer to Figure 43 The memory device 10c may include a first peripheral circuit PC1 disposed at the lower end of the memory device 10c, a second peripheral circuit PC2 disposed at the upper end of the memory device 10c, and a plurality of memory cell arrays (e.g., first memory cell array to fourth memory cell array) MCA1 to MCA4 stacked between the first peripheral circuit PC1 and the second peripheral circuit PC2 in the Z direction. For example, the memory device 10c may include a first structure S1 to a fifth structure S5 stacked in the Z direction, the second structure S2 to the fourth structure S4 may include the first memory cell array MCA1 to the third memory cell array MCA3, and the fifth structure S5 may include the fourth memory cell array MCA4 and the second peripheral circuit PC2. For example, the first structure S1 may include Figure 4 The lower structure S1a shown in the figure, and the second structure S2 to the fourth structure S4 may include Figure 5A and Figure 5B The upper structure S2Xa shown in the figure Figure 6A and Figure 6B The upper structure S2Ya shown in the figure Figure 7A and Figure 7B The upper structure S2Xb shown in the figure Figure 8A and Figure 8B The upper structure S2Yb shown, or a combination thereof. The fifth structure S5 may include, for example... Figure 9A and Figure 9B The lower structure S1Xb shown in the figure Figure 10A and Figure 10B The lower structure S1Yb shown in the figure Figure 11A and Figure 11B The lower structure S1Xc shown in the figure Figure 12A and Figure 12BThe lower structure S1Yc, or a combination thereof, is shown in the figure.

[0195] Figure 44 A cross-sectional view of a memory device 10d according to an embodiment of the present invention is shown.

[0196] refer to Figure 44 ,and Figure 43 In contrast, the memory device 10d may include a first structure S1' and third structures S3 to fifth structures S5 stacked in the Z direction. The first structure S1' may include a COP structure. That is, the first structure S1' may include a first peripheral circuit PC1 and a first memory cell array MCA1 on the first peripheral circuit PC1. For example, the first structure S1' may include... Figure 9A and Figure 9B The lower structure S1Xb shown in the figure Figure 10A and Figure 10B The lower structure S1Yb shown in the figure Figure 11A and Figure 11B The lower structure S1Xc shown in the figure Figure 12A and Figure 12B The lower structure S1Yc, or a combination thereof, is shown in the figure.

[0197] It should be understood that the above embodiments should be considered illustrative rather than restrictive. The scope of this disclosure should be interpreted based on the claims and should be interpreted without departing from the spirit and scope of the inventive concept.

Claims

1. A memory device, comprising: Substructure; as well as Multiple upper structures are stacked on the lower structure. The lower structure includes peripheral circuitry and an upper bonding pad, the upper bonding pad being connected to the peripheral circuitry and disposed on the top surface of the lower structure. Each of the plurality of upper structures has a bottom surface, and each of the plurality of upper structures includes a stacked structure having a plurality of gate layers stacked in a vertical direction, a plurality of channel structures each passing through the stacked structure in the vertical direction, a bit line disposed below the stacked structure and connected to the plurality of channel structures, a through-hole member passing through the stacked structure in the vertical direction, and a lower bonding pad disposed on the bottom surface and connected to the through-hole member. Each of the plurality of upper structures, except for the uppermost upper structure, also includes a top surface and an upper bonding pad disposed on the top surface and connected to the through member. Each of the plurality of upper structures includes a bit line comprising a first portion extending in a horizontal direction orthogonal to the vertical direction, a second portion extending in the horizontal direction, and a gap in the horizontal direction separating the first portion and the second portion of the bit line. In the plan view, the through-piece of each of the plurality of upper structures overlaps with the gap of the bit line. The lowest upper structure of the plurality of upper structures is stacked on the lower structure in the vertical direction, such that the lower bonding pad of the lowest upper structure contacts the upper bonding pad of the lower structure. The plurality of upper structures include a first upper structure and a second upper structure stacked in the vertical direction, and The lower bonding pad of the second upper structure contacts the upper bonding pad of the first upper structure. Wherein, the first and second portions of the bit lines of at least one of the plurality of upper structures are not connected to the lower bonding pads of the at least one upper structure.

2. The memory device of claim 1, wherein, The at least one upper structure further includes: a lower connection pad connecting the first portion of the bit line to the second portion of the bit line.

3. The memory device of claim 2, wherein, The bottom surface of the lower connecting pad of the at least one upper structure is disposed on the same plane as the bottom surface of the lower bonding pad of the at least one upper structure.

4. The memory device according to claim 2, wherein, The at least one upper structure includes: a first via connecting a lower bonding pad of the at least one upper structure to a through-hole of the at least one upper structure; a second via connecting a lower connection pad of the at least one upper structure to a first portion of a bit line of the at least one upper structure; and a third via connecting a lower connection pad of the at least one upper structure to a second portion of a bit line of the at least one upper structure.

5. The memory device according to claim 1, wherein, The at least one upper structure includes: a first lower line that connects the lower bonding pad of the at least one upper structure to a through-hole of the at least one upper structure; and a second lower line that connects a first portion of a bit line of the at least one upper structure to a second portion of a bit line of the at least one upper structure, and is disconnected from the lower bonding pad of the at least one upper structure.

6. The memory device according to claim 5, wherein, The bottom surface of the first lower line of the at least one upper structure is disposed on the same plane as the bottom surface of the second lower line of the at least one upper structure.

7. The memory device according to claim 1, wherein, The first and second portions of the bit lines of at least one of the plurality of upper structures, excluding the at least one upper structure, are connected to the lower bonding pads of the at least one other upper structure.

8. The memory device according to claim 7, wherein, The at least one other superstructure further includes: a first via connecting the lower bonding pad of the at least one other superstructure to a through-hole of the at least one other superstructure; a second via connecting the lower bonding pad of the at least one other superstructure to a first portion of a bit line of the at least one other superstructure; and a third via connecting the lower bonding pad of the at least one other superstructure to a second portion of a bit line of the at least one other superstructure.

9. The memory device according to claim 7, wherein, The at least one other upper structure further includes a first lower line that connects the lower bonding pad of the at least one other upper structure to the through-hole of the at least one other upper structure and a first and a second portion of the bit line of the at least one other upper structure.

10. The memory device according to claim 1, wherein, The lower structure further includes: a second stacked structure having a plurality of second gate layers stacked on the peripheral circuit in the vertical direction; a plurality of second channel structures each passing through the second stacked structure in the vertical direction; a second bit line disposed on the second stacked structure and connected to the plurality of second channel structures; and a second through-hole member passing through the second stacked structure and connecting the upper bonding pad of the lower structure to the peripheral circuit. The second bit line of the lower structure includes a first portion extending in the horizontal direction, a second portion extending in the horizontal direction, and a gap in the horizontal direction separating the first portion and the second portion of the second bit line of the lower structure. In the plan view, the gap between the second through member of the lower structure and the second position line of the lower structure overlaps.

11. The memory device according to claim 10, wherein, The first and second portions of the second bit line of the lower structure are not connected to the upper bonding pad of the lower structure.

12. The memory device according to claim 11, wherein, The lower structure also includes connecting a first portion of the second bit line of the lower structure to an upper connection pad of the second portion of the second bit line.

13. The memory device according to claim 12, wherein, The top surface of the upper connecting pad of the lower structure is disposed on the same plane as the top surface of the upper bonding pad of the lower structure.

14. The memory device according to claim 12, wherein, The lower structure further includes: a first via connecting the upper bonding pad of the lower structure to the second through-hole; a second via connecting the upper connecting pad of the lower structure to a first portion of the second bit line; and a third via connecting the upper connecting pad of the lower structure to a second portion of the second bit line.

15. The memory device according to claim 11, wherein, The lower structure further includes: a first upper line that connects the upper bonding pad of the lower structure to the second through-piece; and a second upper line that connects a first portion of the second bit line of the lower structure to a second portion of the second bit line and is disconnected from the upper bonding pad of the lower structure.

16. The memory device according to claim 15, wherein, The top surface of the first upper line of the lower structure is disposed on the same plane as the top surface of the second upper line of the lower structure.

17. The memory device according to claim 10, wherein, The first and second portions of the second bit line of the lower structure are connected to the upper bonding pad of the lower structure.

18. The memory device according to claim 17, wherein, The lower structure further includes: a first via connecting the upper bonding pad of the lower structure to the second through member; a second via connecting the upper bonding pad of the lower structure to a first portion of the second bit line; and a third via connecting the upper bonding pad of the lower structure to a second portion of the second bit line.

19. The memory device according to claim 17, wherein, The lower structure also includes a first upper line, which connects the upper bonding pad of the lower structure to the second through-piece of the lower structure and the first and second portions of the second bit line.

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