Semiconductor device with isolation structure

Abstract

The present disclosure relates to a semiconductor device with an isolation structure. A semiconductor device with an isolation structure having different dielectric constants and a method for manufacturing the same are disclosed. The semiconductor device includes a fin structure and a first pair of gate structures and a second pair of gate structures, the fin structure having a first fin portion disposed on a first device region and a second fin portion disposed on a second device region, the first pair of gate structures being disposed on the first fin portion, and the second pair of gate structures being disposed on the second fin portion. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device also includes a first isolation structure inserted between the first pair of gate structures and a second isolation structure inserted between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide filling layer. The second isolation structure includes a second nitride liner and a second oxide filling layer. The second nitride liner is thicker than the first nitride liner.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device having an isolation structure. Background Art

[0002] As semiconductor technology advances, people are demanding higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and the interconnect structure of semiconductor devices. This shrinkage increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate having a first device region and a second device region; a fin structure having a first fin portion arranged on the first device region and a second fin portion arranged on the second device region; a first pair of gate structures arranged on the first fin portion in the first device region; a second pair of gate structures arranged on the second fin portion in the second device region, wherein the second pair of gate structures are electrically isolated from the first pair of gate structures; a first isolation structure inserted between the first pair of gate structures, wherein the first isolation structure includes a first nitride liner and a first oxide filling layer; and a second isolation structure inserted between the second pair of gate structures, wherein the second isolation structure includes a second nitride liner and a second oxide filling layer, and wherein the second nitride liner is thicker than the first nitride liner.

[0004] According to another embodiment of the present disclosure, a semiconductor structure is provided, including: a substrate having a memory device region and a logic device region; a fin structure having a first fin portion arranged on the memory device region of the substrate and a second fin portion arranged on the logic device region of the substrate; a first pair of gate structures arranged on the first fin portion in the memory device region; a second pair of gate structures arranged on the second fin portion in the logic device region, wherein the second pair of gate structures is electrically isolated from the first pair of gate structures; a first isolation structure inserted between the first pair of gate structures, wherein the first isolation structure includes a first pair of nitride liners, a first oxide liners inserted between the first pair of nitride liners, and a first oxide filling layer; and a second isolation structure inserted between the second pair of gate structures, wherein the second isolation structure includes a second pair of nitride liners, a second oxide liners inserted between the second pair of nitride liners, and a second oxide filling layer, and wherein the second oxide liners are thicker than the first oxide liners.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a first gate structure and a second gate structure on a first fin structure and a second fin structure arranged on a substrate; forming a first isolation trench and a second isolation trench across the first gate structure and the second gate structure, respectively, wherein the first isolation trench divides the first gate structure into a first pair of gate structures electrically isolated from each other, and the second isolation structure divides the second gate structure into a second pair of gate structures electrically isolated from each other, and wherein forming the first isolation trench and the second isolation trench comprises: forming the first isolation trench to extend to a first distance in the substrate, and forming the second isolation trench to extend to a second distance in the substrate, wherein the second distance is equal to the first distance; and forming a first isolation structure and a second isolation structure in the first isolation trench and the second isolation trench, respectively, wherein forming the first isolation structure and the second isolation structure comprises: forming the first isolation structure having a first dielectric constant, and forming the second isolation structure having a second dielectric constant higher than the first dielectric constant. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1A An isometric view of a semiconductor device having an isolation structure in accordance with some embodiments is shown.

[0008] Figure 1B-1EA top view and a cross-sectional view of a semiconductor device having an isolation structure according to some embodiments are illustrated.

[0009] Figure 1F A cross-sectional view of an isolation structure of a semiconductor device according to some embodiments is shown.

[0010] Figure 2 is a flow chart of a method for manufacturing a semiconductor device having an isolation structure according to some embodiments.

[0011] Figures 3A-8D Cross-sectional views of a semiconductor device having an isolation structure at different stages of its fabrication process are shown in accordance with some embodiments.

[0012] Figures 9A-9D A top view and a cross-sectional view of a semiconductor device having an isolation structure according to some embodiments are illustrated.

[0013] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted to form, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature is formed to be in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0015] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0016] Note that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "an exemplary embodiment," etc. indicate that the described embodiment may include certain features, structures, or characteristics, but each embodiment may not necessarily include the certain features, structures, or characteristics. Furthermore, these phrases do not necessarily refer to the same embodiment. Furthermore, when certain features, structures, or characteristics are described in conjunction with an embodiment, those skilled in the art will realize these features, structures, or characteristics in conjunction with other embodiments within the scope of their knowledge, whether or not explicitly described.

[0017] It is to be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology in this specification is to be interpreted by those skilled in the relevant technical field based on the teachings herein.

[0018] As used herein, the term "etch selectivity" refers to the ratio of etching rates of two different materials under the same etching conditions.

[0019] As used herein, the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k refers to a dielectric constant greater than SiO 2 A dielectric constant of a dielectric constant (e.g., greater than 3.9).

[0020] As used herein, the term "low-k" refers to a low dielectric constant. In the field of semiconductor device structure and manufacturing process, low-k refers to a dielectric constant less than SiO 2 A dielectric constant of a dielectric constant (e.g., less than 3.9).

[0021] As used herein, the term "p-type" defines a structure, layer and / or region as being doped with a p-type dopant, such as boron.

[0022] As used herein, the term "n-type" defines a structure, layer, and / or region as being doped with an n-type dopant, such as phosphorus.

[0023] As used herein, the term "conductive" refers to electrically conductive structures, layers and / or regions.

[0024] In some embodiments, the terms "approximately" and "substantially" may indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. The terms "approximately" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art based on the teachings herein.

[0025] The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Double patterning or multi-patterning processes may combine photolithography and self-alignment processes, allowing the creation of patterns having, for example, smaller pitches than would otherwise be obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. The spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer is then used to pattern the fin structure.

[0026] The gate structure in a semiconductor device with finFETs can extend over two or more finFETs. For example, the gate structure can be formed as a long gate structure that extends across the active area (e.g., the fin area) of the finFET. Once the gate structure is formed, a patterning process can "cut" one or more long gate structures into shorter segments according to the desired structure. In other words, the patterning process can remove redundant gate portions of one or more long gate structures to form one or more isolation trenches (also called "metal cuts") between the finFETs and separate the long gate structures into shorter segments. This process is called a cut metal gate (CMG) process. Subsequently, the isolation trenches formed between the separated segments of the long gate structure can be filled with a dielectric material such as silicon nitride (SiN) to form an isolation structure that can electrically isolate the separated gate structure segments.

[0027] The isolation structure with the gate structure segment can form parasitic capacitance, which in turn generates undesirable parasitic capacitance in the semiconductor device. The greater the number of isolation structures formed by the CMG process, the higher the accumulation of parasitic capacitance in the semiconductor device. The high dielectric constant of the isolation structure due to the dielectric constant of the SiN filler in the insulating structure (e.g., about 6.5 to about 8) further exacerbates the parasitic capacitance. The parasitic capacitance can have an adverse effect on device performance, such as increasing the RC delay of the semiconductor device.

[0028] The present disclosure provides example isolation structures for reducing parasitic capacitance in semiconductor devices having finFETs, and example methods for fabricating the isolation structures. In some embodiments, the isolation structures may be fabricated by using a relatively low dielectric constant material, such as silicon dioxide (SiO 2 ) and a silicon dioxide-based material such as silicon oxycarbide (SiOC) to partially replace the SiN filler to reduce the dielectric constant of the isolation structure. The isolation structure can be formed by depositing a SiN liner in the isolation trench and then replacing it with a SiO 2 Or based on SiO 2The isolation trench is formed by filling the isolation trench with a material. 2 Based on SiO 2 The material has a dielectric constant equal to or less than about 3.9, so SiN and SiO are more 2 Or based on SiN and SiO 2 The double-layer dielectric stack of the material can reduce the dielectric constant of the isolation structure by about 30% to about 50%. In addition, the isolation structure can extend into the substrate of the semiconductor device and provide electrical isolation between the p-well region and the n-well region under the finFET. In some embodiments, the isolation structure can be formed to cut the fin structure of the finFET to electrically separate the fin structures from each other.

[0029] In some embodiments, isolation structures with different dielectric constants can be formed simultaneously in different device regions (e.g., a memory device region and a logic device region) of a semiconductor device. By varying the thickness of the SiN liner in the double-layer dielectric stack, the dielectric constant of the isolation structure can be different. The process of simultaneously forming isolation structures with different dielectric constants can eliminate CMG process-related variability associated with forming multiple isolation structures across a semiconductor device. Reducing process-related variability across semiconductor devices can reduce performance variability across finFETs and device manufacturing costs.

[0030] refer to Figures 1A-1F , a semiconductor device 100 having a memory device region 101 and a logic device region 102 according to some embodiments is described. Figure 1A An isometric view of a semiconductor device 100 according to some embodiments is shown. The semiconductor device 100 may be formed on a substrate 106. The substrate 106 may be a semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, the substrate 106 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, the substrate 106 may include an n-well region and a p-well region ( Figure 1A not shown).

[0031] refer to Figure 1A, the semiconductor device 100 may include isolation structures 103-104, fin structures 107-108 extending along the X-axis, gate structures 112A-112F extending along the Y-axis, a gate spacer 114, an etch stop layer (ESL) 116, an interlayer dielectric layer (ILD) 118, and a shallow trench isolation (STI) region 120. The fin structures 107-108 may be electrically isolated from each other. The ESL 116, the ILD layer 118, and the STI region 120 may include dielectric materials such as silicon oxide, silicon nitride, silicon germanium oxide, and combinations thereof. The gate structures 112A-112F may be electrically isolated from each other by the gate spacer 114, the ESL 116, and the ILD layer 118. The gate spacer 114 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, a low-k material, and combinations thereof.

[0032] The portions of the fin structures 107-108 in the memory device region 101 and the gate structures 112A-112C form finFETs of the memory device region 101. The finFETs in the memory device region 101 may be a memory device or a portion of a memory device. The portions of the fin structures 107-108 in the logic device region 102 and the gate structures 112D-112F form finFETs of the logic device region 102. The finFETs in the logic device region 102 may be a logic device or a portion of a logic device. The gate pitch GP1 and gate length GL1 of the gate structures 112A-112C are less than the corresponding gate pitch GP2 and gate length GL2 of the gate structures 112D-112F. The gate pitch is defined as the distance along the X-axis between adjacent gate structures having equal gate lengths and the gate length of one of the adjacent gate structures (e.g. Figure 1A 1-102). Although three gate structures are shown in each of device regions 101-102, each of device regions 101-102 may have any number of gate structures. Since gate pitch GP1 is less than gate pitch GP2, memory device region 101 may have more gate structures and, therefore, more finFETs per unit device area than logic device region 102. Therefore, memory device region 101 is a high-density device region having a denser patterned structure than logic device region 102, which is a low-density device region.

[0033] In some embodiments, in addition to the gate spacers 114, the ESL 116, and the ILD layer 118, the gate structures 112B-112C may be electrically isolated from each other by the isolation structure 103, and the gate structures 112E-112F may be electrically isolated from each other by the isolation structure 104 to provide independently controlled gate structures. The isolation structures 103-104 may be formed simultaneously in a CMG process with different dielectric constants from each other (described in further detail below) to cut the long gate structures formed on the fin structures 107-108 into (e.g., along the Y-axis) shorter gate structures, such as the gate structures 112B-112C and 112E-112F. The different dielectric constants of the isolation structures 103-104 are adjusted to reduce the parasitic capacitance of the semiconductor device 100. Although one isolation structure is shown in each of the device regions 101-102, each of the device regions 101-102 may have any number of isolation structures. In some embodiments, the semiconductor device 100 may further include an isolation structure 105 extending along the Z-axis and extending into the substrate 106 to cut the fin structures 107-108 and electrically isolate the portions of the fin structures 107-108 in the memory device region 101 from the portions of the fin structures 107-108 in the logic device region 102. Similar to the isolation structures 103 or 104, the isolation structure 105 may include SiN and SiO. 2 Or based on SiN and SiO 2 A double-layer dielectric stack of materials.

[0034] Figure 1B A top view of the semiconductor device 100 is shown without the ESL 116 and the ILD layer 118 so that the fin structures 107 - 108 are visible. Figure 1C-1E Shown along Figure 1B Cross-sectional view along lines AA, BB and CC.

[0035] refer to Figures 1A-1E, the fin structures 107-108 may include fin regions 107A-108A and epitaxial regions 107B-108B disposed on the respective fin regions 107A-108A. Portions of the fin regions 107A-108A under the epitaxial regions 107B-108B may be recessed within the STI region 120 compared to portions of the fin regions 107A-108A under the gate structures 112A-112F. The fin regions 107A-108A may include a material similar to the substrate 106 and may be formed by patterning and etching the substrate 106. In some embodiments, the fin regions 107A-108A may include a semiconductor material different from the substrate 106 and may be formed by patterning and etching an epitaxial layer grown on the substrate 106. In some embodiments, the fin regions 107A-108A may have a semiconductor material with a crystalline microstructure (e.g., a non-amorphous or non-polycrystalline microstructure).

[0036] The epitaxial regions 107B-108B are formed on portions of the respective fin regions 107A-108A that are not covered by the gate structures 112A-112F. The epitaxial regions 107B-108B may be source / drain (S / D) regions of finFETs of the semiconductor device 100 and may include epitaxially grown semiconductor materials that are similar to or different from each other. In some embodiments, the epitaxially grown semiconductor material may include a material that is the same as or different from that of the substrate 106. Depending on the conductivity type of the finFET, the epitaxial regions 107B-108B may include: (i) boron (B) doped SiGe, B doped Ge, or B doped germanium tin (GeSn) (for p-type finFETs); and (ii) carbon doped Si (Si:C), phosphorus doped Si (Si:P), or arsenic doped Si (Si:As) (for n-type finFETs). In addition, the epitaxial regions 107B-108B may include multiple layers with different dopant concentrations and / or different material compositions.

[0037] The gate structures 112A-112F are isolated from the epitaxial regions 107B-108B by gate spacers 114. The gate structures 112A-112F may be multi-layer structures. For simplicity, the different layers of the gate structures 112A-112F are not shown. Each of the gate structures 112A-112F may include an interface oxide (IO) layer, a high-k gate dielectric layer on the IO layer, a work function metal (WFM) layer on the high-k dielectric layer, and a gate metal fill layer on the WFM layer. The IO layer may include silicon oxide (SiO 2 ), silicon germanium oxide (SiGeO x ) or germanium oxide (GeO x The high-k gate dielectric layer may include a high-k dielectric material, such as hafnium oxide (HfO2 ), titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 3 ), Hafnium Silicate (HfSiO 4 )、ZrO 2 ) and zirconium silicate (ZrSiO 2 ). The WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), and combinations thereof. The gate metal filling layer may include a suitable conductive material, such as tungsten (W), titanium, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0038] refer to Figure 1B-1E , the isolation structures 103-104 may be formed with similar heights H1, but with different average widths along the X-axis. Since the gate length GL1 is less than the gate length GL2, the average width of the isolation structure 103 is less than the average width of the isolation structure 104. The average widths of the isolation structures 103-104 correspond to the respective gate lengths GL1-GL2, because the isolation structures 103-104 are formed by removing redundant gate portions between the gate structures 112B-112C and between the gate structures 112E-112F. In some embodiments, the average widths of the isolation structures 103-104 also depend on the thickness of the gate spacers 114 and the ESL 116, because portions of the gate spacers 114 and the ESL 116 adjacent to the redundant gate portions are removed to form the isolation structures 103-104, as described in further detail below. In some embodiments, the average width of the isolation structure 103 may be from about 20 nm to about 30 nm, and the average width of the isolation structure 104 may be from about 30 nm to about 40 nm. Therefore, isolation structures formed in high-density device regions (eg, isolation structures 103 in memory device region 101 ) are narrower along the X-axis than isolation structures formed in low-density device regions (eg, isolation structures 104 in logic device region 102 ).

[0039] In some embodiments, the height H1-H2 may be from about 150 nm to about 300 nm, and portions of the isolation structures 103-104 may extend into the substrate 106 by a distance D1-D2, such as Figure 1B-1E When the p-well and n-well regions are formed in the substrate 106, the portion of the isolation structures 103-104 in the substrate 106 provides electrical isolation between the p-well and n-well regions (eg, Figure 1D-1E). Therefore, if the height H1-H2 is shorter than about 150nm and / or the distance D1-D2 is shorter than about 5nm, there may be leakage between the p-well and n-well regions, which may have a negative impact on device performance. On the other hand, if the height H1-H2 is greater than about 300nm and / or the distance D1-D2 is greater than about 150nm, the process time (e.g., etching and dielectric filling time) for forming the isolation structure 103-104 increases, thereby increasing the device manufacturing cost. In some embodiments, the heights H1-H2 may be equal to or different from each other. In some embodiments, the distances D1-D2 may be equal to or different from each other. In some embodiments, the height H2 may be greater than the height H1, and the distance D2 may be greater than the distance D1.

[0040] In some embodiments, the isolation structure 103 may include a double-layer dielectric stack of a nitride liner 103A and an oxide filling layer 103B, and the isolation structure 104 may include a double-layer dielectric filler of a nitride liner 104A and an oxide filling layer 104B. The nitride liners 103A-104A may include SiN material, and the oxide filling layers 103B-104B may include SiO 2 Or based on SiO 2 The nitride liner 103A may be made of a material (e.g., silicon oxycarbide). The thickness T1 of the nitride liner 103A is less than the thickness T2 of the nitride liner 104A, and the range of thicknesses T1-T2 is each between about 4 nm and about 6 nm. Similarly, the average thickness of the oxide filling layer 103B along the X-axis is less than the average thickness of the oxide filling layer 104B. The average thickness of the oxide filling layer 103B may range from about 15 nm to about 25 nm, and the average thickness of the oxide filling layer 104B may range from about 25 nm to about 35 nm. In some embodiments, the thickness ratio between the nitride liner 103A and the oxide filling 103B and between the nitride liner 104A and the oxide filling 104B may be between about 1:4 and about 1:10.

[0041] Since the dielectric constant of the oxide filling layer 103B-104B is lower than that of the nitride liner 103A-104A (e.g., about 6.5 to about 8), and the volume occupied by the oxide filling layer 103B-104B in the isolation structure 103-104 is larger than the volume occupied by the nitride liner 103A-104A, the dielectric constant of each isolation structure 103-104 is closer to the dielectric constant of the oxide filling layer 103B-104B (e.g., about 4 to about 6). Therefore, compared with the isolation structure using only SiN filler, the effect of the isolation structure 103-104 on the parasitic capacitance is reduced. In some embodiments, since the thickness T1 of the nitride liner 103A is less than the thickness T2 of the nitride liner 104A, and the volume occupied by the oxide filling layer 103B is less than the volume occupied by the oxide filling layer 104B, the dielectric constant of the isolation structure 103 is lower than the dielectric constant of the isolation structure 104. The lower dielectric constant of the isolation structure 103 is achieved by the thinner nitride liner 103A because the performance of the devices in the memory device region 101 is more sensitive to parasitic capacitance than the performance of the devices in the logic device region 102.

[0042] In some embodiments, the thinner the nitride liner 103A-104A is, the lower the dielectric constant of the resulting isolation structure 103-104 is. In other words, the larger the volume occupied by the oxide fill layer 103B-104B at the expense of the nitride liner 103A-104A in the isolation structure 103-104, the lower the dielectric constant of the isolation structure 103-104 is. In some embodiments, the nitride liner 103A-104A has a minimum thickness to prevent oxygen from diffusing from the oxide fill layer 103B-104B into the gate structure layers 112B-112C and 112E-112F. In addition, during the subsequent formation of adjacent structures (e.g., the isolation structure 105), the nitride liner 103A-104A requires a minimum thickness to serve as an etch stop layer and protect the oxide fill layer 103B-104B. Therefore, the nitride liner 103A-104A having a thickness less than about 4 nm may not adequately block oxygen diffusion and / or may not fully function as an etch stop layer, which may result in an undesirable threshold voltage shift in the finFET. On the other hand, the nitride liner 103A-104A having a thickness greater than about 6 nm adequately blocks oxygen diffusion and / or fully functions as an etch stop layer, but simultaneously increases the dielectric constant of the isolation structure 103-104 and the parasitic capacitance of the semiconductor device 100 to exceed the threshold, which may increase the RC delay of the semiconductor device 100.

[0043] In some embodiments, in addition to the minimum thickness required for the nitride liners 103A-104A to effectively serve as an etch stop layer for the oxide fill layers 103B-104B, the nitride liners 103A-104A have a minimum film density and a minimum wet etch rate to serve as an effective etch stop layer. The wet etch rate can be defined as the etch rate of the material in diluted hydrofluoric acid (e.g., 1:50 diluted hydrofluoric acid). In some embodiments, the film density of the nitride liners 103A-104A can range from about 2.9 g / cm 3 To about 3.2g / cm 3 , and the wet etch rate can range from about 0.5 nm / min to about 3 nm / min. If the density of the nitride liner 103A-104A is less than about 2.9 g / cm 3 If the nitride liner 103A-104A has a low wet etching rate and / or a wet etching rate of less than about 0.5 nm / min, the nitride liner 103A-104A cannot be sufficiently used as an etch stop layer to protect the oxide fill layer 103B-104B from being etched during the subsequent formation of adjacent structures. During the deposition of the nitride liner 103A-104A, the film density of the nitride liner 103A-104A can be changed by adjusting the ratio of hydrogen atoms (H atoms) in the nitride liner 103A-104A.

[0044] refer to Figure 1F In some embodiments, the dielectric constant of the isolation structure 103 can be more accurately adjusted to a desired value by having a dielectric stack of liners 103C-103E and a filling layer 103F (rather than a double-layer dielectric stack of a nitride liner 103A and an oxide filling layer 103B). Similarly, the isolation structure 104 can have a dielectric stack of liners 104C-104E and a filling layer 104F, rather than a double-layer dielectric stack of a nitride liner 104A and an oxide filling layer 104B. In some embodiments, the liners 103C-103D and 104C-104D can include SiN, and the liner 103E inserted between the nitride liners 103C-103D and the liner 104E inserted between the nitride liners 104C-104D can include SiO 2 Or based on SiO 2 The filling layers 103F-104F disposed on the corresponding nitride liners 103E-104E may include SiO 2 Or based on SiO 2 Material.

[0045] Unless otherwise noted, the discussion of nitride liners 103A-104A may apply to the corresponding liners 103C-104C. In some embodiments, the thickness T5-T6, film density, and / or wet etch rate of the nitride liners 103D-104D may be equal to or less than the thickness, film density, and / or wet etch rate of the corresponding nitride liners 103C-104D. In some embodiments, the thickness T3-T4 of the oxide liners 103E-104E may be equal to or greater than the thickness of the corresponding nitride liners 103C-104D, depending on the desired dielectric constant of the isolation structures 103-104. In order to obtain a lower dielectric constant in the isolation structure 103 than the isolation structure 104, the nitride liners 103C-103D are thinner than the nitride liners 104C-104D.

[0046] Figure 2 is a flow chart of an exemplary method 200 for manufacturing a semiconductor device 100 according to some embodiments. For illustrative purposes, reference will be made to Figures 3A-8D describe Figure 2 The operations shown in . Figure 3A-8A is a top view of various stages in fabricating a semiconductor device 100 in accordance with some embodiments. Figure 3B-8B , 3C-8C and 3D-8D are steps of manufacturing the semiconductor device 100 according to some embodiments. Figure 3A-8A 2. The method 200 is a cross-sectional view of the corresponding lines DD, EE and FF of FIG. The operations may be performed in a different order or not performed, depending on the specific application. It should be noted that the method 200 may not produce a complete semiconductor device 100. Therefore, it is understood that additional processes may be provided before, during and after the method 200, and some other processes may only be briefly described herein. Figures 3A-8D In the Figures 1A-1F The elements in the same label are as described above.

[0047] In operation 205, a fin structure and a gate structure are formed in a first device region and a second device region of a semiconductor device. Figures 3A-3DAs shown, fin structures 107-108 having fin regions 107A-108A and epitaxial regions 107B-108B may be formed on substrate 106, and gate structures 112A, 112BC, 112D, and 112EF may be formed on fin regions 107A-108A. Gate structures 112A-112BC are formed in memory device region 101 of semiconductor device 100, and gate structures 112D-112EF are formed in logic device region 102 of semiconductor device 100. Gate structures 112BC and 112EF will be cut in subsequent processes to form gate structures 112B-112C and 112E-112F and isolation structures 103-104. The formation of the fin structures 107-108 may include the following sequential operations: (i) patterning the substrate 106 to form fin regions 107A-108A, (ii) forming a polysilicon gate structure (not shown) on portions of the fin regions 107A-108B that will have gate structures 112BD, 112CE, 112A, and 112F formed in subsequent processes, (iii) deep etching portions of the fin regions 107A-108A that are not covered by the polysilicon gate structure, (iv) forming epitaxial regions 107B-108B on the deeply etched fin regions 107A-108A, and (v) replacing the polysilicon gate structure with gate structures 112A, 112BC, 112D, and 112EF.

[0048] refer to Figure 2 In operation 210, a first isolation trench and a second isolation trench are formed across the first gate structure and the second gate structure in the first device region and the second device region, respectively. For example, the isolation trenches 103* and 104* can be formed across the gate structures 112BC and 112EF, respectively, as shown in FIG. Figures 4A-5D The formation of the isolation trenches 103*-104* may include the following sequential operations: (i) Figures 3A-3D The method further comprises depositing and patterning hard mask layers 423-424 on the structure of the gate structure 112BC to form an opening 424*, and (ii) etching the redundant gate portion 112* and the redundant dielectric portion of the gate structures 112BC and 112EF through the opening 424*. The redundant dielectric portion includes the gate spacer 114, the ESL 116, and the portion of the ILD layer 118 located on the sidewall of the redundant gate portion 112*.

[0049] In some embodiments, the hard mask layer 423 may include a metal nitride layer (eg, titanium nitride) or an oxide layer (eg, SiO 2), and the hard mask layer 424 may include a SiN layer. The SiN layer of the hard mask layer 424 may be deposited using a chemical vapor deposition (CVD) process, which is different from the atomic layer deposition (ALD) process used to form the SiN liners 103A-104A, as discussed in further detail below. In addition, due to the higher concentration of hydrogen atoms in the SiN layer of the hard mask layer 424, the film density of the SiN layer of the hard mask layer 424 is lower than the film density of the SiN liners 103A-104A. The higher concentration of hydrogen atoms is due to the presence of hydrogen-based gases (e.g., ammonia (NH 3 ) gas) is used as a nitrogen precursor when depositing the SiN layer. According to some embodiments, the hard mask layers 423-424 protect the underlying structure in a subsequent etching process to form the isolation trenches 103*-104*.

[0050] The hard mask layers 423-424 may be patterned using a photolithography process followed by a dry etching process to form the opening 424*. The dry etching process may include using fluoromethane (CH 3 F), a gas mixture of oxygen and argon. The opening 424* exposes the redundant gate portion 112* and the redundant dielectric portion, which are removed in a subsequent process to form the isolation trenches 103*-104*. Although the opening 424* is shown as having straight sidewalls, the opening 424* may have inclined sidewalls.

[0051] The etching process to remove the exposed structure through the opening 424* may include dry etching using an etchant having a higher etching selectivity to the metal material of the gate portion 112* than to the material of the redundant dielectric portion. The second etchant may include chlorine, methane (CH 4 ), boron chloride (BCL 3 The etching process is continued until the STI region 120 and the substrate 106 below the etched gate portion 112* and the dielectric portion are etched to form isolation trenches 103*-104*, such as Figures 5A-5D As shown. In some embodiments, in addition to removing gate portion 112*, redundant dielectric portions and underlying portions of STI region 120 and substrate 106 are also removed to ensure that the location of isolation trenches 103*-104* (e.g., corners and / or bottoms of isolation trenches 103*-104*) is difficult to etch without any gate material residue. Isolation trench 103* cuts gate structure 112BC into gate structures 112B-112C, and isolation trench 104* cuts gate structure 112EF into gate structures 112E-112F, as shown. Figure 5A shown.

[0052] The isolation trenches 103*-104* may be formed with similar heights H1, but with different average widths along the X-axis. Since the gate length GL1 is less than the gate length GL2, the average width of the isolation trenches 103* is less than the average width of the isolation trenches 104*. Since the isolation trenches 103*-104* are formed by removing the redundant gate portions 112*, the average widths of the isolation trenches 103*-104* correspond to the corresponding gate lengths GL1-GL2. In some embodiments, the average width of the isolation trenches 103* may range from about 20nm to about 30nm, and the average width of the isolation trenches 104* may range from about 30nm to about 40nm. Therefore, the isolation trenches formed in the high-density device region (e.g., the isolation trenches 103* in the memory device region 101) are narrower along the X-axis than the isolation trenches formed in the low-density device region (e.g., the isolation trenches 104* in the logic device region 102).

[0053] In some embodiments, height H1-H2 may range from about 150 nm to about 300 nm, and portions of trenches 103*-104* may extend into substrate 106 by a distance D1-D2, such as Figures 5B-5D As shown. If the height H1-H2 is shorter than about 150nm and / or the distance D1-D2 is shorter than about 5nm, the isolation structure 103-104 subsequently formed in the isolation trench 103*-104* may not effectively prevent leakage between the p-well and n-well regions in the substrate 106, resulting in poor device performance. On the other hand, if the height H1-H2 is greater than about 300nm and / or the distance D1-D2 is greater than about 150nm, the etching time increases, thereby increasing the device manufacturing cost. In some embodiments, the heights H1-H2 may be equal to or different from each other. In some embodiments, the distances D1-D2 may be equal to or different from each other. In some embodiments, the height H2 may be greater than the height H1, and the distance D2 may be greater than the distance D1.

[0054] refer to Figure 2 In operation 215, a nitride liner is deposited in the first isolation trench and the second isolation trench. Figures 6A-6D As shown, the nitride liner 626 may be substantially conformally deposited on Figures 5A-5D In some embodiments, the nitride liner 626 may be deposited to have a thickness ranging from about 4 nm to about 6 nm and a film density ranging from about 2.9 g / cm 3 To about 3.2g / cm 3, the wet etching rate is from about 0.5 nm / min to about 3 nm / min. In some embodiments, the nitride liner 626 may include SiN. In subsequent processes, the first liner portion of the nitride liner 626 deposited in the isolation trench 103* forms the nitride liner 103A, and the second liner portion of the nitride liner 626 deposited in the isolation trench 104* forms the nitride liner 104A. Unless otherwise specified, the above discussion of the nitride liners 103A and 104A applies to the corresponding first liner portion and the second liner portion.

[0055] The thickness T1 of the first liner portion is less than the thickness T2 of the second liner portion. This difference in thickness T1-T2 is caused by the deposition rate of the first liner portion being slower than the deposition rate of the second liner portion being deposited in the isolation trench 104*. This difference in deposition rate is caused by the linear relationship of the deposition rate with the trench width below 50nm. Therefore, since the isolation trench 103* is narrower than the isolation trench 104*, the first liner portion is deposited at a slower deposition rate than the second liner portion, which causes the first liner portion to be thinner than the second liner portion.

[0056] In some embodiments, the nitride liner 626 may be deposited at a temperature of about 400° C. to about 450° C., which is lower than other methods of depositing SiN layers. To deposit at such a low temperature, the deposition process may include: (i) using a plasma enhanced ALD (PEALD) process, (ii) using diiodosilane gas (SiH 2 I 2 ) and a mixture of nitrogen and hydrogen as a silicon precursor, (iii) supplying the silicon precursor into the deposition chamber at a flow rate of about 5 standard liters per minute (slm) to about 9 slm using a nitrogen carrier gas, (iv) supplying an RF power of about 600 W to about 800 W for a period of about 1 second to about 4 seconds, and (v) depositing at a pressure of about 10 Torr to about 20 Torr.

[0057] In some embodiments, the process of depositing the nitride liner 626 at a temperature of about 400° C. to about 450° C. may include: (i) using a PEALD process, (ii) using a dichlorosilane gas (SiH 2 Cl 2 ) as a silicon precursor, (iii) using NH 3 In some embodiments, the SiH2O2 precursor is used as a nitrogen precursor, (iv) using a nitrogen carrier gas to supply a silicon precursor into the deposition chamber at a flow rate of about 5 slm to about 9 slm, (v) supplying an RF power of about 600 W to about 800 W for a period of about 1 second to about 4 seconds, and (vi) depositing at a pressure of about 10 torr to about 20 torr. 2I 2 The nitride liner 626 film deposited using SiH 2 Cl 2 and NH 3 The nitride liner 626 film deposited using SiH as a precursor has a higher film density. 2 Cl 2 and NH 3 The lower film density of the nitride liner 626 deposited with the gas as the precursor may be due to the NH 3 Produced by a higher concentration of hydrogen atoms provided by the gas.

[0058] refer to Figure 2 In operation 220, an oxide fill layer is deposited on the nitride liner. Figures 7A-7D As shown, the oxide fill layer 728 may be deposited on Figures 6A-6D The isolation trenches 103*-104* are filled with an oxide filling layer 728. The oxide filling layer 728 may include SiO 2 Or based on SiO 2 In some embodiments, the oxide fill layer 728 may be deposited using a PEALD process at a temperature of about 200° C. to about 260° C. The deposition process may further include: (i) using bis(diacetamido)silane gas ((Et2n) 2 S H 2 ) as a silicon precursor, (ii) supplying the silicon precursor into a deposition chamber at a flow rate of about 1 slm to about 2 slm using an argon carrier gas, (iii) supplying oxygen plasma using an RF power of about 15 W to about 100 W for a period of time of about 0.5 minute to about 1 minute, and (vi) depositing at a pressure of about 2 Torr to about 5 Torr.

[0059] refer to Figure 2 In operation 225, the top surfaces of the nitride liner and the oxide filling layer are coplanar with the top surface of the gate structure. For example, the top surfaces of the nitride liner 626 and the oxide filling layer 728 can be coplanar with the top surfaces of the gate structures 112A and 112D to form the nitride liners 103A-104A and the oxide filling layers 103B-104B, as shown in FIG. Figures 8B-8D In some embodiments, Figures 7A-7D A chemical mechanical polishing (CMP) process is performed on the structure to form Figures 8A-8D structure.

[0060] In some embodiments, rather than performing operation 220 after operation 215, operation 220 may be performed after operation 215. Figures 6A-6DAn oxide liner is deposited on the structure, and then a second nitride liner (similar to the nitride liner 626) is deposited on the oxide liner, and then an oxide filling layer 728 is deposited on the second nitride liner. After the CMP process of operation 225 is performed on the stack, the stack of nitride liner 626, oxide liner, second nitride liner and oxide filling layer 728 can form a dielectric stack of the isolation structure 103-104, such as Figure 1F shown.

[0061] In some embodiments, rather than forming finFETs of semiconductor 100 on common fin structures 107 - 108 in device regions 101 - 102 , finFETs of semiconductor 100 may be formed on different fin structures in different device regions. Figures 9A-9D As shown, finFETs of semiconductor 100 may be formed on fin structures 107 *- 108 * in device region 101 , and finFETs of semiconductor 100 may be formed on fin structures 107 - 108 in device region 102 . Fig. 9A A top view of a semiconductor device 100 is shown in which finFETs are formed on different fin structures 107 *- 108 * and 107 - 108 in different device regions 101 - 102 . Figures 9B-9D Shown along Fig. 9A Unless otherwise noted, the discussion of fin structures 107 - 108 applies to fin structures 107 *- 108 *. Figures 9A-9D has Figures 1A-1F The elements in the same label are as described above. Figures 9A-9D FinFETs may be formed on different regions of the same substrate 106 using the operations of method 200 described above.

[0062] The present disclosure provides example isolation structures (e.g., isolation structures 103-104) for reducing parasitic capacitance in a semiconductor device having finFETs (e.g., semiconductor device 100), and example methods for fabricating these isolation structures. In some embodiments, the isolation structures may be fabricated by using a lower dielectric constant material (e.g., silicon dioxide (SiO 2 ) and SiO-based 2 The isolation structure can be formed by partially replacing the SiN filler with a material (such as silicon oxycarbide) to reduce the dielectric constant of the isolation structure. The isolation structure can be formed by first depositing a SiN liner (such as SiN liner 103A-104A) in the isolation trench, and then replacing the SiN filler with a SiO 2 Or based on SiO 2 The isolation trench is filled with a material (eg, oxide filling layer 103B-104B). 2Or based on SiO 2 The dielectric constant of the material is equal to or less than about 3.9, so SiN and SiO are more 2 , or SiN and SiO based 2 The double-layer dielectric filler of the material can reduce the dielectric constant of the isolation structure by about 30% to about 50%. In addition, the isolation structure can extend into the substrate of the semiconductor device and provide electrical isolation between the p-well region and the n-well region under the finFET. In some embodiments, the isolation structure (e.g., isolation structure 105) can be formed to cut the fin structure of the finFET to electrically separate the fin structures from each other.

[0063] In some embodiments, isolation structures (e.g., isolation structures 103-104) with different dielectric constants can be formed simultaneously in different device regions (e.g., memory device region 101 and logic device region 102) of a semiconductor device. By varying the thickness of the SiN liner in the double-layer dielectric fill layer, the dielectric constant of the isolation structure can be varied. The process of simultaneously forming isolation structures with different dielectric constants can eliminate CMG process-related variability associated with forming multiple isolation structures across a semiconductor device. Reducing process-related variability across semiconductor devices can reduce performance variability across finFETs and device manufacturing costs.

[0064] In some embodiments, a semiconductor device includes: a substrate having a first device region and a second device region; a fin structure having a first fin portion disposed on the first device region and a second fin portion disposed on the second device region; a first pair of gate structures disposed on the first fin portion in the first device region; and a second pair of gate structures disposed on the second fin portion in the second device region. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device also includes: a first isolation structure inserted between the first pair of gate structures; and a second isolation structure inserted between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide filling layer. The second isolation structure includes a second nitride liner and a second oxide filling layer. The second nitride liner is thicker than the first nitride liner.

[0065] In some embodiments, a semiconductor device includes: a substrate having a memory device region and a logic device region; a fin structure having a first fin portion disposed on the memory device region of the substrate and a second fin portion disposed on the logic device region of the substrate; a first pair of gate structures disposed on the first fin portion in the memory device region; a second pair of gate structures disposed on the second fin portion in the logic device region. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device also includes: a first isolation structure inserted between the first pair of gate structures; and a second isolation structure inserted between the second pair of gate structures. The first isolation structure includes a first pair of nitride liners, a first oxide liner inserted between the first pair of nitride liners, and a first oxide filling layer. The second isolation structure includes a second pair of nitride liners, a second oxide liner inserted between the second pair of nitride liners, and a second oxide filling layer. The second oxide liner is thicker than the first oxide liner.

[0066] In some embodiments, a method includes: forming a first gate structure and a second gate structure on a first fin structure and a second fin structure disposed on a substrate; forming a first isolation trench and a second isolation trench across the first gate structure and the second gate structure, respectively. The first isolation trench divides the first gate structure into a first pair of gate structures electrically isolated from each other, and the second isolation structure divides the second gate structure into a second pair of gate structures electrically isolated from each other. Forming the first isolation trench and the second isolation trench includes: forming the first isolation trench to extend to a first distance in the substrate, and forming the second isolation trench to extend to a second distance in the substrate. The second distance is substantially equal to the first distance. The method also includes forming a first isolation structure and a second isolation structure in the first isolation trench and the second isolation trench, respectively. Forming the first isolation structure and the second isolation structure includes: forming the first isolation structure having a first dielectric constant, and forming the second isolation structure having a second dielectric constant higher than the first dielectric constant.

[0067] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

[0068] Example 1. A semiconductor device, comprising: a substrate having a first device region and a second device region; a fin structure having a first fin portion arranged on the first device region and a second fin portion arranged on the second device region; a first pair of gate structures arranged on the first fin portion in the first device region; a second pair of gate structures arranged on the second fin portion in the second device region, wherein the second pair of gate structures are electrically isolated from the first pair of gate structures; a first isolation structure inserted between the first pair of gate structures, wherein the first isolation structure includes a first nitride liner and a first oxide filling layer; and a second isolation structure inserted between the second pair of gate structures, wherein the second isolation structure includes a second nitride liner and a second oxide filling layer, and wherein the second nitride liner is thicker than the first nitride liner.

[0069] Example 2. The semiconductor device of Example 1, wherein the first portion and the second portion of the first isolation structure and the second isolation structure are respectively embedded in the substrate.

[0070] Example 3. The semiconductor device according to Example 1, wherein the first portion and the second portion of the first isolation structure and the second isolation structure are respectively embedded in a shallow trench isolation region provided on the substrate.

[0071] Example 4. The semiconductor device of Example 1, wherein the first isolation structure extends into the substrate by a first distance, and the second isolation structure extends into the substrate by a second distance, the second distance being different from the first distance.

[0072] Example 5. The semiconductor device of Example 1, wherein the first nitride liner and the second nitride liner include a silicon nitride material, and the first oxide filling layer and the second oxide filling layer include a silicon oxide-based material.

[0073] Example 6. The semiconductor device of Example 1, wherein the dielectric constant of the first isolation structure is lower than the dielectric constant of the second isolation structure.

[0074] Example 7. The semiconductor device of Example 1, wherein an average width of the first oxide filling layer is smaller than an average width of the second oxide filling layer.

[0075] Example 8. The semiconductor device of Example 1, wherein an average width of the first isolation structure corresponds to a gate length of the first pair of gate structures, and an average width of the second isolation structure corresponds to a gate length of the second pair of gate structures.

[0076] Example 9. The semiconductor device of Example 1, wherein a gate pitch of the first pair of gate structures is smaller than a gate pitch of the second pair of gate structures.

[0077] Example 10. The semiconductor device of Example 1, wherein an average width of the first isolation structure is smaller than an average width of the second isolation structure.

[0078] Example 11. A semiconductor structure comprising: a substrate having a memory device region and a logic device region; a fin structure having a first fin portion arranged on the memory device region of the substrate and a second fin portion arranged on the logic device region of the substrate; a first pair of gate structures arranged on the first fin portion in the memory device region; a second pair of gate structures arranged on the second fin portion in the logic device region, wherein the second pair of gate structures is electrically isolated from the first pair of gate structures; a first isolation structure inserted between the first pair of gate structures, wherein the first isolation structure includes a first pair of nitride liners, a first oxide liner inserted between the first pair of nitride liners, and a first oxide filling layer; and a second isolation structure inserted between the second pair of gate structures, wherein the second isolation structure includes a second pair of nitride liners, a second oxide liner inserted between the second pair of nitride liners, and a second oxide filling layer, and wherein the second oxide liner is thicker than the first oxide liner.

[0079] Example 12. The semiconductor device of Example 11, wherein the second pair of nitride liners is thicker than the first pair of nitride liners.

[0080] Example 13. The semiconductor device of Example 11, wherein the first oxide layer liner is thicker than each nitride liner of the first pair of nitride liners.

[0081] Example 14. The semiconductor device of Example 11, wherein the first portion and the second portion of the first isolation structure and the second isolation structure are respectively embedded in the substrate.

[0082] Example 15. The semiconductor device of Example 11, wherein the dielectric constant of the first isolation structure is lower than the dielectric constant of the second isolation structure.

[0083] Example 16. A method for manufacturing a semiconductor device, comprising: forming a first gate structure and a second gate structure on a first fin structure and a second fin structure disposed on a substrate; forming a first isolation trench and a second isolation trench across the first gate structure and the second gate structure, respectively, wherein the first isolation trench divides the first gate structure into a first pair of gate structures electrically isolated from each other, and the second isolation structure divides the second gate structure into a second pair of gate structures electrically isolated from each other, and wherein forming the first isolation trench and the second isolation trench comprises: forming the first isolation trench to extend to a first distance in the substrate, and forming the second isolation trench to extend to a second distance in the substrate, wherein the second distance is equal to the first distance; and forming a first isolation structure and a second isolation structure in the first isolation trench and the second isolation trench, respectively, wherein forming the first isolation structure and the second isolation structure comprises: forming the first isolation structure having a first dielectric constant, and forming the second isolation structure having a second dielectric constant higher than the first dielectric constant.

[0084] Example 17. A method according to Example 16, wherein forming the first isolation structure and the second isolation structure includes depositing a nitride liner in the first isolation trench and the second isolation trench, wherein a first portion of the nitride liner is deposited in the first isolation trench at a first deposition rate, and a second portion of the nitride liner is deposited in the second isolation trench at a second deposition rate, and wherein the second deposition rate is faster than the first deposition rate.

[0085] Example 18. A method according to Example 16, wherein forming the first isolation structure and the second isolation structure includes depositing a nitride liner in the first isolation trench and the second isolation trench, wherein a first portion of the nitride liner is deposited in the first isolation trench with a first thickness, and a second portion of the nitride liner is deposited in the second isolation trench with a second thickness, and wherein the second thickness is greater than the first thickness.

[0086] Example 19. The method of Example 16, wherein forming the first isolation structure and the second isolation structure comprises: depositing a nitride liner in the first isolation trench and the second isolation trench; and depositing an oxide filling layer on the nitride liner.

[0087] Example 20. A method according to Example 16, wherein forming the first isolation structure and the second isolation structure includes: depositing a first nitride liner in the first isolation trench and the second isolation trench; depositing an oxide liner on the first nitride liner; depositing a second nitride liner on the oxide liner; and depositing an oxide filling layer on the second nitride liner.

Claims

1. A semiconductor device, comprising: A substrate having a first device region and a second device region; a first fin structure and a second fin structure, wherein each of the first fin structure and the second fin structure includes a first fin portion disposed on the first device region and a second fin portion disposed on the second device region; a first pair of gate structures disposed on the first fin structure and the first fin portion of the second fin structure in the first device region; a second pair of gate structures disposed on the first fin structure and the second fin portion of the second fin structure in the second device region, wherein the second pair of gate structures is electrically isolated from the first pair of gate structures; a first isolation structure inserted between the first pair of gate structures, wherein the first isolation structure comprises a first nitride liner and a first oxide filling layer; and A second isolation structure is inserted between the second pair of gate structures, wherein the second isolation structure includes a second nitride liner and a second oxide filling layer, and wherein the second nitride liner is thicker than the first nitride liner, and wherein the first isolation structure and the second isolation structure are parallel to each other in an extension direction and parallel to the first fin structure and the second fin structure.

2. The semiconductor device according to claim 1, wherein The first portion and the second portion of the first isolation structure and the second isolation structure are respectively embedded in the substrate.

3. The semiconductor device according to claim 1, wherein The first portion and the second portion of the first isolation structure and the second isolation structure are respectively embedded in a shallow trench isolation region disposed on the substrate.

4. The semiconductor device according to claim 1, wherein: The first isolation structure extends into the substrate a first distance, and the second isolation structure extends into the substrate a second distance, the second distance being different than the first distance.

5. The semiconductor device according to claim 1, wherein The first nitride liner and the second nitride liner include a silicon nitride material, and the first oxide filling layer and the second oxide filling layer include a silicon oxide-based material.

6. The semiconductor device according to claim 1, wherein The dielectric constant of the first isolation structure is lower than the dielectric constant of the second isolation structure.

7. The semiconductor device according to claim 1, wherein An average width of the first oxide filling layer is smaller than an average width of the second oxide filling layer.

8. The semiconductor device according to claim 1, wherein The average width of the first isolation structure corresponds to the gate length of the first pair of gate structures, and the average width of the second isolation structure corresponds to the gate length of the second pair of gate structures.

9. The semiconductor device according to claim 1, wherein: The gate pitch of the first pair of gate structures is smaller than the gate pitch of the second pair of gate structures.

10. The semiconductor device according to claim 1, wherein An average width of the first isolation structure is smaller than an average width of the second isolation structure.

11. A semiconductor device comprising: A substrate having a memory device region and a logic device region; a fin structure having a first fin portion disposed on the memory device region of the substrate and a second fin portion disposed on the logic device region of the substrate; a first pair of gate structures disposed on the first fin portion in the memory device region; a second pair of gate structures disposed on the second fin portion in the logic device region, wherein the second pair of gate structures are electrically isolated from the first pair of gate structures; a first isolation structure interposed between the first pair of gate structures, wherein the first isolation structure comprises a first pair of nitride liners, a first oxide liner interposed between the first pair of nitride liners, and a first oxide fill layer; and A second isolation structure is inserted between the second pair of gate structures, wherein the second isolation structure includes a second pair of nitride liners, a second oxide liner inserted between the second pair of nitride liners, and a second oxide fill layer, and wherein the second oxide liner is thicker than the first oxide liner.

12. The semiconductor device according to claim 11, wherein The second pair of nitride liners is thicker than the first pair of nitride liners.

13. The semiconductor device according to claim 11, wherein The first oxide liner is thicker than each nitride liner of the first pair of nitride liners.

14. The semiconductor device according to claim 11, wherein The first portion and the second portion of the first isolation structure and the second isolation structure are respectively embedded in the substrate.

15. The semiconductor device according to claim 11, wherein The dielectric constant of the first isolation structure is lower than the dielectric constant of the second isolation structure.

16. A method for manufacturing a semiconductor device, comprising: forming a first gate structure and a second gate structure on the first fin structure and the second fin structure disposed on the substrate; forming a first isolation trench and a second isolation trench across the first gate structure and the second gate structure, respectively, The first isolation trench and the second isolation trench are parallel to each other in an extension direction and are parallel to the first fin structure and the second fin structure. wherein the first isolation trench divides the first gate structure into a first pair of gate structures electrically isolated from each other, and the second isolation trench divides the second gate structure into a second pair of gate structures electrically isolated from each other, and Wherein, forming the first isolation trench and the second isolation trench comprises: forming the first isolation trench to extend to a first distance in the substrate, and forming the second isolation trench to extend to a second distance in the substrate, wherein the second distance is equal to the first distance; and A first isolation structure and a second isolation structure are formed in the first isolation trench and the second isolation trench respectively, wherein forming the first isolation structure and the second isolation structure includes: forming the first isolation structure having a first dielectric constant, and forming the second isolation structure having a second dielectric constant higher than the first dielectric constant.

17. The method according to claim 16, wherein: Forming the first isolation structure and the second isolation structure includes depositing a nitride liner in the first isolation trench and the second isolation trench, wherein a first portion of the nitride liner is deposited in the first isolation trench at a first deposition rate, and a second portion of the nitride liner is deposited in the second isolation trench at a second deposition rate, and wherein the second deposition rate is faster than the first deposition rate.

18. The method according to claim 16, wherein: Forming the first isolation structure and the second isolation structure includes depositing a nitride liner in the first isolation trench and the second isolation trench, wherein a first portion of the nitride liner is deposited in the first isolation trench with a first thickness, and a second portion of the nitride liner is deposited in the second isolation trench with a second thickness, and wherein the second thickness is greater than the first thickness.

19. The method according to claim 16, wherein: Forming the first isolation structure and the second isolation structure includes: depositing a nitride liner in the first isolation trench and the second isolation trench; and An oxide filling layer is deposited on the nitride liner.

20. The method according to claim 16, wherein: Forming the first isolation structure and the second isolation structure includes: depositing a first nitride liner in the first isolation trench and the second isolation trench; depositing an oxide liner on the first nitride liner; depositing a second nitride liner on the oxide liner; and An oxide filling layer is deposited on the second nitride liner.

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