Display device

Abstract

A display device is disclosed. The display device includes: a substrate including a sensor region; a display panel including a first pixel disposed in the sensor region; and a sensor disposed between the substrate and the display panel and superimposed on the sensor region. The sensor region includes a pixel region in which the first pixel is disposed and a transmissive region in which no first pixel is disposed. The transmissive region includes a first transmissive region. The pixel region includes a first pixel region located in a first direction of the first transmissive region and a second pixel region located in a second direction of the first transmissive region intersecting the first direction. The first pixel includes a first pixel circuit, some transistors of the first pixel circuit are disposed in the first pixel region, and other transistors of the first pixel circuit are disposed in the second pixel region.

Description

[0001] This application claims priority to and all benefits arising therefrom of Korean Patent Application No. 10-2020-0008342, filed on January 22, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] In general, this disclosure relates to a display device. More specifically, this disclosure relates to a display device that improves the recognition accuracy of a sensor disposed in a sensor region by increasing the area of ​​a transmissive region included in a sensor region. Background Technology

[0003] With the development of multimedia, the importance of display devices has gradually increased. Recently, various display devices, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, have been widely developed.

[0004] A display device may include: a display panel, which may include a sensor area; and a plurality of sensors, which may be stacked with the sensor area and located below the display panel. The sensor area may include a pixel area and a transmissive area. The display device can identify objects by using optical sensors and acquire images and videos by using a camera. Recently, the following developments have been made in front display technology: minimizing the size of the bezel on the front screen of the display device, rearranging sensors on the front screen, and displaying images on the entire front screen of the display device.

[0005] However, when the area of ​​the transmission region is set too narrow, the amount of light (or signal) incident through the transmission region may be insufficient, thus potentially degrading the recognition accuracy of the sensor located in the sensor area. Therefore, it is necessary to develop a new method to improve the display quality of the display panel. Summary of the Invention

[0006] This disclosure aims to provide a display device that improves the recognition accuracy of a sensor disposed in a sensor region by increasing the area of ​​the transmissive region included in the sensor region.

[0007] This disclosure is not limited, and other technologies not described above will be clearly understood by those skilled in the art through the following description.

[0008] A display device according to a disclosed embodiment for achieving the above-mentioned objective includes: a substrate including a sensor region; a display panel including a first pixel disposed in the sensor region; and a sensor disposed between the substrate and the display panel and stacked with the sensor region. The sensor region includes a plurality of pixel regions in which the first pixel is disposed and a plurality of transmissive regions in which no first pixel is disposed. The plurality of transmissive regions include the first transmissive region. The plurality of pixel regions include a first pixel region located in a first direction of the first transmissive region and a second pixel region located in a second direction of the first transmissive region intersecting the first direction. The first pixel includes a first pixel circuit, at least one transistor of the transistors in the first pixel circuit is disposed in the first pixel region, and other transistors of the transistors in the first pixel circuit are disposed in the second pixel region.

[0009] The first pixel circuit may include a first initialization transistor disposed in the second pixel region and connected between the first light-emitting element of the first pixel and the initialization power supply.

[0010] The display panel may include a first scan line, a first initialization line, and a first emission control line connected to a first pixel circuit. The first scan line, the first initialization line, and the first emission control line may pass through the first pixel area and bypass the transmissive area adjacent to the first pixel area.

[0011] The first pixel circuit may further include a first transistor, a second transistor, and a capacitor disposed in the first pixel region. The first transistor may control the amount of current flowing from the first power source through the first light-emitting element to the second power source in accordance with the voltage of the first node. The second transistor may be connected between the data line and the first electrode of the first transistor and may be turned on when a scan signal is supplied to the first scan line. The capacitor may be connected between the first power source and the first node.

[0012] The first pixel circuit may further include a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor disposed in the first pixel region. The third transistor may be connected between the first node and the second electrode of the first transistor and may be turned on when a scan signal is supplied to the first scan line. The fourth transistor may be connected between the first node and the initialization power supply and may be turned on when an initialization signal is supplied to the first initialization line. The fifth transistor may be connected between the first power supply and the first electrode of the first transistor and may be turned on when an emission control signal is supplied to the first emission control line. The sixth transistor may be connected between the second electrode of the first transistor and the first electrode of the first light-emitting element and may be turned on when an emission control signal is supplied to the first emission control line.

[0013] The pixel region may further include a third pixel region located in the direction opposite to the first direction of the first transmission region. A second pixel may also be disposed in the pixel region. The second pixel may include a second pixel circuit. At least a portion of the second pixel circuit may be disposed in the second pixel region, and other portions of the second pixel circuit may be disposed in the third pixel region.

[0014] The second pixel circuit may include a second initialization transistor, which is disposed in the third pixel region and connected between the second light-emitting element of the second pixel and the initialization power supply.

[0015] The display panel may include a second scan line and a second initialization line connected to the second pixel circuit, and the second scan line and the second initialization line may pass through the second pixel area and bypass the transmissive area adjacent to the second pixel area.

[0016] When the initialization signal is supplied to the second initialization line, the first initialization transistor can be turned on.

[0017] The initialization signal supplied to the second initialization line can be equal to the scan signal supplied to the first scan line.

[0018] The pixel region may also include a third pixel region located in a first direction of the first pixel region. The second pixel may also be disposed in the pixel region. The second pixel may include a second pixel circuit. At least a portion of the second pixel circuit may be disposed in the third pixel region, and other portions of the second pixel circuit may be disposed in the first pixel region.

[0019] The second pixel circuit may include a second initialization transistor, which is disposed in the first pixel region and connected between the second light-emitting element of the second pixel and the initialization power supply.

[0020] The display panel may include a connection pattern that electrically connects the anode electrode of the first light-emitting element and the first initialization transistor to each other without overlapping with the transmission region.

[0021] At least one transistor included in the first pixel circuit may include a substrate layer disposed on a substrate, a semiconductor pattern disposed on the substrate layer, a gate electrode disposed on the semiconductor pattern, and a first metal pattern and a second metal pattern disposed on the gate electrode and in contact with the semiconductor pattern, and a connection pattern is formed between the substrate layer and the gate electrode or on the same layer as the gate electrode.

[0022] The display panel may also include a display area in which display pixels are disposed, the display area may surround the sensor area, and the density of the first pixel disposed in the sensor area may be lower than the density of the display pixels disposed in the display area.

[0023] The size of the first pixel set in the sensor area can be smaller than the size of the display pixel set in the display area.

[0024] The transmittance of the sensor area can be greater than that of the display area.

[0025] A display device according to another disclosed embodiment for achieving the above-mentioned objective includes: a substrate including a sensor region; a display panel including a first pixel circuit and a second pixel circuit disposed in the sensor region; and a sensor disposed between the substrate and the display panel and stacked on top of the sensor region. The sensor region includes a transmissive region, at least one transistor of the transistors in the first pixel circuit is disposed adjacent to the transmissive region in a first direction, other transistors of the transistors in the first pixel circuit are disposed adjacent to the transmissive region in a second direction intersecting the first direction, and the second pixel circuit is disposed adjacent to the transmissive region in the second direction.

[0026] The display panel may further include a first light-emitting element, which is disposed adjacent to the transmission region in a first direction and connected to a first pixel circuit. The first pixel circuit may include an initialization transistor, which is disposed adjacent to the transmission region in a second direction and may be connected between the anode electrode of the first light-emitting element and an initialization power supply.

[0027] The display panel may also include a third pixel circuit, wherein at least one transistor of the transistors in the third pixel circuit may be disposed adjacent to the second pixel circuit in a first direction, and other transistors of the transistors in the third pixel circuit may be disposed adjacent to the transmissive region in the first direction.

[0028] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0029] According to the disclosed embodiments, a light-emitting element disposed in one pixel region of the sensor region can be connected to an initialization transistor disposed in another pixel region. Therefore, a display device can be provided that has a transmissive region with an increased area in the sensor region, thereby improving the recognition accuracy of the sensor disposed in the sensor region.

[0030] The effects of the embodiments are not limited to the details shown above, and many more effects are included in this specification. Attached Figure Description

[0031] The above and other features of the disclosure will become more apparent from the further detailed description of the disclosed embodiments with reference to the accompanying drawings, in which:

[0032] Figure 1This is a block diagram illustrating a schematic construction of a display device according to an embodiment;

[0033] Figure 2A It is shown Figure 1 The circuit diagram of an embodiment of the pixel is shown in the figure;

[0034] Figure 2B It is shown that it includes Figure 2A A cross-sectional view of an example of the first transistor in a pixel;

[0035] Figure 3A and Figure 3B This is a plan view of a display device according to a disclosed embodiment;

[0036] Figure 4 It is along Figure 3A A sectional view taken by line IV-IV';

[0037] Figure 5 This is a plan view showing the first display area according to an embodiment;

[0038] Figure 6 It is based on Figure 5 An enlarged view of an embodiment of region Q1;

[0039] Figure 7 It is based on Figure 5 An enlarged view of another embodiment of region Q1;

[0040] Figure 8 This is a schematic plan view of the second display area according to an embodiment;

[0041] Figure 9A It is based on Figure 8 An enlarged view of an embodiment of region Q2;

[0042] Figure 9B It is based on Figure 8 An enlarged view of another embodiment of region Q2;

[0043] Figure 10A It is based on Figure 8 An enlarged view of another embodiment of region Q2;

[0044] Figure 10B It is along Figure 10A A schematic cross-sectional view taken along line A-A'; and

[0045] Figure 11 It is based on Figure 8 An enlarged view of another embodiment of region Q2. Detailed Implementation

[0046] The advantages and features of this disclosure, as well as methods of implementing them, will become clear from the following detailed description of the embodiments and accompanying drawings. However, the disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. This disclosure is provided so that it will be thorough and complete, and that those skilled in the art will fully understand its scope. This disclosure is limited only by the scope of the claims.

[0047] The use of the term "on" another element or layer includes cases where the element or layer is directly disposed on the other element or layer, or cases where intermediate elements or layers may be present. Throughout this specification, the same reference numerals denote the same components.

[0048] Although terms like "first," "second," etc., are used to describe various components, it is self-evident that these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, it is self-evident that, within the spirit of the disclosed art, the "first component" mentioned below can be the "second component." Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0049] The disclosed embodiments will be described in detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are used for the same components.

[0050] Figure 1 This is a block diagram illustrating a schematic construction of a display device according to an embodiment.

[0051] Reference Figure 1 The display device 10 according to the embodiment may include a display panel 100, a scan driver 210, a data driver 220, a transmit driver 230, and a timing controller 240. The display panel 100 includes a plurality of pixels PXL. In addition, the display device 10 may include a plurality of scan lines SL1 to SLn (n is a natural number greater than 1), a plurality of data lines DL1 to DLm (m is a natural number greater than 1), and a plurality of transmit control lines EL1 to ELo (o is a natural number greater than 1) disposed on the display panel 100.

[0052] Based on a signal (not shown) input from an external source, the timing controller 240 can generate a scan drive control signal SCS, a data drive control signal DCS, and a transmit drive control signal ECS. The drive control signals SCS, DCS, and ECS generated by the timing controller 240 can be supplied to the scan driver 210, the data driver 220, and the transmit driver 230, respectively.

[0053] The scan drive control signal SCS can include a scan start pulse and a clock signal. The scan start pulse controls the output timing of the first scan signal, and the clock signal controls the output timing of the scan signals.

[0054] The data-driven control signal (DCS) can include a source start pulse and a clock signal. The source start pulse controls the start time of data sampling, and the clock signal is used to control the sampling operation.

[0055] The transmit drive control signal (ECS) can include a transmit start pulse and a clock signal. The transmit start pulse controls the output timing of the first transmit control signal, and the clock signal controls the output timing of the transmit control signal.

[0056] The scan driver 210 can output a scan signal in response to the scan drive control signal SCS. The scan driver 210 can supply the scan signal to scan lines SL1 to SLn. The scan signal can be applied to scan lines SL1 to SLn sequentially or simultaneously.

[0057] The data driver 220 can supply data signals to data lines DL1 to DLm in response to the data drive control signal DCS. The data signals supplied to data lines DL1 to DLm can be applied to pixels PXL of the pixel row selected by the scan signal. For this purpose, the data driver 220 can supply data signals to data lines DL1 to DLm synchronously with the scan signal.

[0058] The data driver 220 can apply a data signal corresponding to the image data provided from the outside to the data lines DL1 to DLm during the display period within a frame.

[0059] The transmit driver 230 can supply transmit control signals to transmit control lines EL1 to ELo in accordance with the transmit drive control signal ECS. The transmit control signals can be applied to the transmit control lines EL1 to ELo sequentially or simultaneously. The pixel PXL, which is supplied with transmit control signals through the transmit control lines EL1 to ELo, can emit light at a brightness corresponding to the data signal applied from the data driver 220.

[0060] The display panel 100 may include a plurality of pixels PXL connected to data lines DL1 to DLm, scan lines SL1 to SLn, and emission control lines EL1 to ELo. At least one or more scan lines may be connected to the pixels PXL corresponding to the circuit structure of the pixels PXL.

[0061] The PXL pixel can be connected to the first power supply ELVDD (see...). Figure 2A ) and the second power supply ELVSS (see Figure 2AThe pixel PXL can receive the drive power supply voltage. The first power supply voltage, supplied by the first power supply ELVDD, can be set to a voltage higher than the second power supply voltage supplied by the second power supply ELVSS. Additionally, the pixel PXL can also be connected to the initialization power supply Vint (see [link to initialization power supply]). Figure 2A It receives the initial power supply voltage.

[0062] When a scan signal is supplied through the corresponding scan line during a display period, each of the plurality of pixels PXL can receive a data signal from the corresponding data line. The pixel PXL receiving the data signal can control the amount of current flowing from the first power supply ELVDD through the light-emitting element (not shown) to the second power supply ELVSS in accordance with the data signal. When an emission control signal is applied from the corresponding emission control line, the light-emitting element can generate light with a predetermined brightness corresponding to the amount of current.

[0063] Figure 2A It is shown Figure 1 The circuit diagram of an embodiment of the pixel is shown in the figure.

[0064] Reference Figure 2A According to the disclosed embodiments, the pixel PXL may include a pixel circuit PC and a light-emitting element LD. The pixel circuit PC includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7, and a storage capacitor Cst.

[0065] According to the embodiment, the pixel PXL can be connected between the first scan line SLi, the second scan line SLi-1, the third scan line SLi+1, the data line DLj, the transmit control line ELi, the first power supply ELVDD, the second power supply ELVSS, and the initialization power supply Vint.

[0066] Each of the first transistor M1 to the seventh transistor M7 can be implemented as a P-type transistor, but is not limited thereto. For example, at least some of the first transistor M1 to the seventh transistor M7 can be implemented as N-type transistors.

[0067] The first electrode of the first transistor M1 can be connected to the first power supply ELVDD via the fifth transistor M5, and the second electrode of the first transistor M1 can be connected to the first electrode (e.g., the anode electrode) of the light-emitting element LD via the sixth transistor M6. Additionally, the gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via the light-emitting element LD, corresponding to the voltage of the first node N1.

[0068] The second transistor M2 (switching transistor) can be connected between the data line DLj and the first electrode of the first transistor M1. Additionally, the gate electrode of the second transistor M2 can be connected to the first scan line SLi. The second transistor M2 can be turned on when the first scan signal GW[i] is supplied to the first scan line SLi, thereby electrically connecting the data line DLj and the first electrode of the first transistor M1.

[0069] The third transistor M3 can be connected between the second electrode of the first transistor M1 and the first node N1. Additionally, the gate electrode of the third transistor M3 can be connected to the first scan line SLi. The third transistor M3 can be turned on when a scan signal with a gate on-voltage is supplied to the first scan line SLi, thereby electrically connecting the second electrode of the first transistor M1 and the first node N1. Therefore, when the third transistor M3 is turned on, the first transistor M1 can be connected in a diode configuration.

[0070] The fourth transistor M4 can be connected between the first node N1 and the initialization power supply Vint. Additionally, the gate electrode of the fourth transistor M4 can be connected to the second scan line SLi-1 (or the initialization line). The fourth transistor M4 is turned on when the second scan signal GI[i] (or the initialization signal) is supplied to the second scan line SLi-1 to supply the voltage of the initialization power supply Vint to the first node N1. That is, the fourth transistor M4 can be a gate initialization transistor that initializes the gate electrode of the first transistor M1. Here, the second scan signal GI[i] can be a signal with the same waveform as the first scan signal provided by the first scan line of the pixel in the previous row.

[0071] Figure 2A An embodiment is shown in which the second scan line SLi-1 is used as an initialization line to initialize the gate electrode (i.e., the first node N1) of the first transistor M1. However, the scope of the disclosed technology is not limited.

[0072] The fifth transistor M5 can be connected between the first power supply ELVDD and the first transistor M1. Additionally, the gate electrode of the fifth transistor M5 can be connected to the emitter control line ELi.

[0073] The sixth transistor M6 can be connected between the first transistor M1 and the light-emitting element LD. Additionally, the gate electrode of the sixth transistor M6 can be connected to the emission control line ELi.

[0074] The fifth transistor M5 and the sixth transistor M6 can be turned off when a gate-off voltage emitter control signal (e.g., a high-level voltage) is supplied to the emitter control line ELi, and can be turned on when a gate-on voltage emitter control signal (e.g., a low-level voltage) is supplied.

[0075] The seventh transistor M7 (or initialization transistor) can be connected between the initialization power supply Vint and the first electrode (anode electrode) of the light-emitting element LD. The gate electrode of the seventh transistor M7 can be connected to the third scan line SLi+1. The seventh transistor M7 can be turned on when the third scan signal GI[i+1] (e.g., a low-level voltage) with the gate on-state voltage is supplied to the third scan line SLi+1, so as to supply the voltage of the initialization power supply Vint (or the initialization power supply voltage) to the anode electrode of the light-emitting element LD. That is, the seventh transistor M7 can be an anode initialization transistor for initializing the anode electrode of the light-emitting element LD.

[0076] Here, the third scan line SLi+1 can be the same scan line as the second scan line of the pixel in the next row. That is, the gate electrode of the seventh transistor M7 can be connected to the second scan line of the pixel in the next row, and the third scan signal GI[i+1] provided to the gate electrode of the seventh transistor M7 can be the same as the second scan signal provided by the second scan line of the pixel in the next row. Therefore, the third scan signal GI[i+1] provided to the third scan line SLi+1 can be a signal with substantially the same waveform as the second scan signal GI[i] provided to the second scan line SLi-1, but is not limited thereto.

[0077] Additionally, the initialization power supply voltage Vint can be set to be lower than the data signal voltage. In other words, the initialization power supply voltage Vint can be set to be equal to or less than the minimum voltage of the data signal.

[0078] The seventh transistor M7 can be located in a different region than the regions of the first transistors M1 through M6. For example, the seventh transistor M7 can be located in a different pixel row (or a different pixel region) than the pixel rows of the first transistors M1 through M6. See below for further details. Figures 9A to 11 This will be described in detail.

[0079] The storage capacitor Cst can be connected between the first power supply ELVDD and the first node N1. The storage capacitor Cst can store a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

[0080] The first electrode (anode electrode) of the light-emitting element LD can be connected to the first transistor M1 via the sixth transistor M6, and the second electrode (cathode electrode) of the light-emitting element LD can be connected to the second power supply ELVSS. The light-emitting element LD produces light with a predetermined brightness corresponding to the amount of current supplied from the first transistor M1. The voltage value of the first power supply ELVDD can be set to be higher than the voltage value of the second power supply ELVSS, so that current can flow to the light-emitting element LD.

[0081] The light-emitting element (LD) can be, for example, an organic light-emitting diode (OLED). The LD can emit one of red, green, or blue light. However, disclosure is not limited.

[0082] Meanwhile, the structure of the pixel PXL is not limited to Figure 2A The embodiments shown are illustrated. For example, pixel circuits of various currently known structures can be applied to the pixel PXL.

[0083] Figure 2B It is shown that it includes Figure 2A A cross-sectional view of an example of the first transistor in a pixel.

[0084] Reference Figure 2A and Figure 2B The first transistor M1 (or pixel PXL) may include a substrate layer SUB, multiple insulating layers INS1, INS2, INS3 and INS4, a semiconductor pattern SC, and multiple conductive patterns GAT, BML, SDM1 and SDM2.

[0085] The substrate SUB can provide space for each construct in which the pixel PXL is disposed. The substrate SUB can be a rigid substrate or a flexible substrate, and the material or physical properties of the substrate SUB are not specifically limited.

[0086] Although not shown in the accompanying drawings, a buffer layer can also be provided on the substrate layer SUB. The buffer layer can prevent impurities from diffusing into the circuit elements.

[0087] The insulating layers INS1, INS2, INS3 and INS4 include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3 and a fourth insulating layer INS4, and the first insulating layer INS1, the second insulating layer INS2, the third insulating layer INS3 and the fourth insulating layer INS4 can be sequentially disposed on the substrate layer SUB.

[0088] Each of the insulating layers INS1, INS2, INS3, and INS4 may consist of a single layer or multiple layers and may include at least one inorganic insulating material and / or an organic insulating material. For example, each of the insulating layers INS1, INS2, INS3, and INS4 may include various types of currently known organic / inorganic insulating materials, including SiN. x and SiO x Furthermore, the construction material of each of the insulating layers INS1, INS2, INS3, and INS4 is not specifically limited. Additionally, insulating layers INS1, INS2, INS3, and INS4 may comprise different insulating materials, or at least some of the insulating layers INS1, INS2, INS3, and INS4 may comprise the same insulating material.

[0089] The conductive patterns GAT, BML, SDM1 and SDM2 may include a gate electrode GAT, a body electrode BML, a first metal pattern SDM1 and a second metal pattern SDM2.

[0090] Each of the gate electrode GAT, the body electrode BML, the first metal pattern SDM1, and the second metal pattern SDM2 may include, but is not limited to, at least one of the following metals: Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and alloys thereof.

[0091] The main electrode BML can be disposed on the substrate layer SUB. As described above, when the buffer layer is disposed on the substrate layer SUB, the main electrode BML can be disposed on the buffer layer.

[0092] A control signal can be transmitted to the body electrode BML, and the body electrode BML can, together with the gate electrode GAT, perform regulation of the channel region of the semiconductor pattern SC. For example, the same signal provided to the gate electrode GAT, the first metal pattern SDM1, and the second metal pattern SDM2 can be supplied to the body electrode BML. That is, the body electrode BML can be formed simultaneously with the gate electrode GAT, the first metal pattern SDM1, and the second metal pattern SDM2. As another example, the body electrode BML can receive the control signal via a separate control line. Additionally, according to an embodiment, the first transistor M1 may not include the body electrode BML.

[0093] A semiconductor pattern SC can be disposed on a first insulating layer INS1. For example, the semiconductor pattern SC can be disposed between the first insulating layer INS1 and the second insulating layer INS2. The semiconductor pattern SC may include: a first region in contact with a first transistor electrode ET1; a second region in contact with a second transistor electrode ET2; and a channel region located between the first region and the second region. One of the first region and the second region may be a source region, and the other may be a drain region.

[0094] The semiconductor pattern SC can be a semiconductor pattern formed from polycrystalline silicon, amorphous silicon, low-temperature polycrystalline silicon (LTPS), etc. The channel region of the semiconductor pattern SC can be an intrinsic semiconductor that is not doped with impurities, and the first region and the second region of the semiconductor pattern SC can be semiconductor patterns doped with predetermined impurities, respectively.

[0095] The semiconductor pattern SC can be configured to be superimposed on the body electrode BML, and the body electrode BML can be superimposed on at least one region of the semiconductor pattern SC.

[0096] The gate electrode GAT can be disposed on the second insulating layer INS2. That is, the gate electrode GAT can be disposed between the second insulating layer INS2 and the third insulating layer INS3. The gate electrode GAT can be stacked with at least one region of the semiconductor pattern SC. Figure 2B The diagram shows that the first transistor M1 includes only one gate electrode GAT, but the disclosure is not limited, and the first transistor M1 may include multiple gate electrodes. Additionally, the gate electrodes of transistors M2 to M7, other than the first transistor M1, may be disposed on a different layer than the layer on which the gate electrode GAT of the first transistor M1 is located.

[0097] The gate electrode GAT, the semiconductor pattern SC, the body electrode BML, the first transistor electrode ET1, and the second transistor electrode ET2 can constitute the first transistor M1.

[0098] The first metal pattern SDM1 and the second metal pattern SDM2 can be set on the third insulating layer INS3.

[0099] The first metal pattern SDM1 can contact a region of the semiconductor pattern SC through contact holes passing through the second insulating layer INS2 and the third insulating layer INS3, and can form the first transistor electrode ET1 of the first transistor M1.

[0100] The second metal pattern SDM2 can contact another area of ​​the semiconductor pattern SC through contact holes passing through the second insulating layer INS2 and the third insulating layer INS3, and can form the second transistor electrode ET2 of the first transistor M1.

[0101] Figure 3A and Figure 3B This is a plan view of a display device according to a disclosed embodiment. Specifically, Figure 3A and Figure 3B The front surface of the display device 10 is shown.

[0102] The entire display device 10 or at least some of the display device 10 may have flexible portions. For example, the display device 10 may have flexible portions throughout the entire area, or it may have flexible portions within a flexible area.

[0103] like Figure 3A As depicted, the display panel 100 may be disposed on the front surface of the display device 10. The display panel 100 may include a display area AA and a non-display area NA surrounding the display area AA.

[0104] The display area AA can be set with multiple pixels PXL (i.e., Figure 1The display area AA can be referred to as the effective area. In various embodiments of this disclosure, the display area AA can be positioned in a large screen to occupy most of the front surface of the display device 10.

[0105] The non-display area NA can be the area surrounding the display area AA, and can be set as follows: Figure 3A The non-display area NA is located at the edge of the front surface of the display device 10 shown in the figure. The non-display area NA can be referred to as an inactive area or a border area. The non-display area NA can broadly refer to the area remaining excluding the display area AA.

[0106] The non-display area NA may include drive elements, lines, and various dummy areas for applying drive signals to the display area AA. For example, in the non-display area NA, settings may be configured... Figure 1 The scan driver 210, data driver 220, transmit driver 230, timing controller 240, and various lines connected to the pixel PXL are shown to drive the pixel PXL set in the display area AA.

[0107] In another embodiment, the display area AA may be disposed on the entire front surface of the display device 10. When the display area AA is disposed on the entire front surface of the display device 10, the non-display area NA may not be disposed, or the non-display area NA may be disposed in a very small portion of the front surface. In such an embodiment, the display area AA may contact the side edge of the display device 10 or may be disposed at a distance of less than approximately 1 mm from the side edge.

[0108] Figure 3A An embodiment is shown in which the display area AA is disposed only on the front surface of the display device 10, but the disclosure is not limited. That is, in various embodiments, the display area AA may be disposed in at least one region of the side edge of the display device 10 or at least one region of its rear surface. At least a portion of the display areas AA disposed on multiple surfaces of the display device 10 may be connected to or separated from each other.

[0109] In various embodiments of this disclosure, the display device 10 may include a plurality of sensors (not shown) configured to be superimposed on the display area AA. The sensors may be disposed below pixels PXL and / or lines disposed in the display area AA and may be hidden relative to the front surface. When the sensors are disposed below pixels PXL and / or lines disposed in the display area AA and superimposed on the display area AA as described above, a wider display area AA can be ensured.

[0110] The area not overlapping with the sensor can be defined as the first display area AA1, and the area overlapping with the sensor can be defined as the second display area AA2 (or the sensor area). However, in various embodiments, the second display area AA2 can be configured to have a wider area than the area overlapping with the sensor. For example, as... Figure 3B As shown, the second display area AA2 can be widely formed on a portion of the display device 10 (e.g., one end of the display device 10). In such an embodiment, the distance from the upper edge of the display device 10 to the upper edge of the first display area AA1 can be between approximately 5 mm and approximately 8 mm. However, in other embodiments, this distance can be less than approximately 5 mm or greater than approximately 8 mm.

[0111] The second display area AA2 can be located inside the display area AA and can be surrounded by the first display area AA1. Figure 3A In the middle, the second display area AA2 has a roughly circular shape on the plane, but is not restricted. That is to say, as... Figure 3B As shown, the second display area AA2 can have various shapes such as polygons (such as quadrilaterals) and ellipses.

[0112] In addition, Figure 3A and Figure 3B In this embodiment, at least one second display area AA2 is disposed only at the upper end portion of the front surface of the display device 10, but the disclosure is not limited. That is, in various embodiments, multiple second display areas AA2 may be provided, and the multiple second display areas AA2 may be disposed adjacent to each other or dispersed in the display area AA. For example, when the display area AA is formed on the side edge and / or rear surface of the display device 10, a portion of the second display area AA2 may be disposed in the display area AA on the side edge and / or the display area AA on the rear surface.

[0113] The sensor configured to be superimposed on the second display area AA2 can be an optical sensor. Optical sensors can include, for example, fingerprint sensors, image sensors, cameras, flashlights, illuminance sensors, proximity sensors, RGB sensors, infrared sensors, etc. However, the sensor is not limited to optical sensors and can include various sensors such as ultrasonic sensors, microphones, environmental sensors (e.g., barometers, hygrometers, thermometers, radiation sensors, thermal sensors, etc.) and chemical sensors (gas sensors, dust sensors, odor sensors, etc.).

[0114] In an embodiment, such as Figure 3AAs shown, a second display area AA2 can be overlaid with a sensor. For example, one of the second display areas AA2 can be overlaid with a camera, another with a proximity sensor, and yet another with an illumination sensor.

[0115] However, in another embodiment, such as Figure 3B As shown, a second display area AA2 can be overlaid with multiple sensors. For example, one of the second display areas AA2 can be overlaid with a camera and a proximity sensor arranged side by side, and another can be overlaid with an illumination sensor.

[0116] The second display area AA2 can transmit signals input to the sensor (e.g., optical signals). To improve signal transmittance, pixels PXL can be arranged in the second display area AA2 at a lower density than in the first display area AA1. When pixels PXL are arranged at a low density, physical and / or optical openings can be formed between each pixel PXL, thus enabling more efficient signal transmission. That is, the transmittance of the second display area AA2 can be greater than that of the first display area AA1. The arrangement density of pixels PXL in the first display area AA1 and the second display area AA2 will be described in more detail later with reference to the accompanying drawings.

[0117] Figure 4 It is along Figure 3A A schematic cross-sectional view taken from line IV-IV'.

[0118] Reference Figure 4 The display device 10 may include a substrate 110, at least one sensor 120, a display panel 100, and a window 130. The substrate 110, sensor 120, display panel 100, and window 130 may be formed in a structure stacked in the vertical direction.

[0119] The substrate 110 can support the display panel 100 and the sensor 120. In embodiments, the substrate 110 can be a bracket, a bottom cover, etc., and can include plastic or metal materials. The substrate 110 can form the appearance of the rear surface of the display device 10 and can protect the internal components of the electronic device from external stress.

[0120] Sensor 120 may be mounted on substrate 110 using surface mount technology (SMT). Sensor 120 may be disposed between substrate 110 and display panel 100. Sensor 120 may be configured to overlap with at least one area of ​​display panel 100 (e.g., second display area AA2).

[0121] The display panel 100 can be a flat panel display panel or a flexible display panel. For example, the display panel 100 may include a rigid substrate layer formed of glass, plastic, etc., or a flexible substrate layer such as a plastic film. The display panel 100 can display images using a circuit element layer and a light-emitting element layer disposed on the substrate layer. See reference... Figure 2A As described, the pixel PXL may include pixel circuitry PC formed in the circuit element layer and light-emitting element LD formed in the light-emitting element layer. As mentioned above, the light-emitting element LD may be an organic light-emitting diode, but the light-emitting element LD is not limited to organic light-emitting diodes. For example, the light-emitting element LD may be an inorganic light-emitting element comprising inorganic light-emitting materials or a light-emitting element that emits light by changing the wavelength of the emitted light using quantum dots (quantum dot light-emitting element).

[0122] The display panel 100 may include a reference Figure 3A and Figure 3B The description includes a first display area AA1 and a second display area AA2 superimposed on the sensor 120. Pixel PXL can be set in the first display area AA1 and the second display area AA2.

[0123] The pixel configurations in each of the display areas AA1 and AA2 can be different from each other. In an embodiment, pixel PXL can be configured with different densities in the first display area AA1 and the second display area AA2. For example, pixel PXL can be configured with a first density in the first display area AA1, and pixel PXL can be configured with a second density in the second display area AA2. The second density can be set to be less than the first density.

[0124] In other words, the area where pixel PXL is set relative to the entire area of ​​the second display area AA2 can be smaller than the area where pixel PXL is set relative to the entire area of ​​the first display area AA1. Since pixel PXL is set at a relatively low density in the second display area AA2, the transmittance of the second display area AA2 can be greater than the transmittance of the first display area AA1.

[0125] Because the density of pixels PXL in the second display area AA2 is lower than that in the first display area AA1, the image displayed in the second display area AA2 will be visually perceived as darker (i.e., less bright) compared to the image displayed in the first display area AA1. To solve this problem, the pixels PXL set in the second display area AA2 can be controlled to emit light with a brighter brightness relative to the same image data.

[0126] Meanwhile, in another embodiment, the first display area AA1 and the second display area AA2 can have the same pixel density, but can instead be constructed to have different transmittances. For example, the pixel PXL disposed in the first display area AA1 can be made of a material with a first transmittance, and the pixel PXL disposed in the second display area AA2 can be made of a material with a second transmittance that is higher than the first transmittance.

[0127] Optionally, the circuit elements of pixel PXL disposed in the second display area AA2 and the lines connected to these circuit elements can be formed to be denser or have a narrower area than the circuit elements of pixel PXL disposed in the first display area AA1 and the lines connected to these circuit elements. That is, the size of pixel PXL disposed in the second display area AA2 can be formed to be smaller than the size of pixel PXL disposed in the first display area AA1. Therefore, the distances between circuit elements, between lines, and between circuit elements and lines in the second display area AA2 can be widened, resulting in improved transmittance of the second display area AA2.

[0128] The window 130 may be located at the outermost part of the display device 10. The window 130 may be made of glass or synthetic resin. The window 130 may be made of a translucent material. The window 130 may be configured to protect components located below the window 130.

[0129] Figure 5 This is a schematic plan view of the first display area according to an embodiment. Figure 6 It is based on Figure 5 An enlarged view of an embodiment of region Q1. Figure 7 It is based on Figure 5 An enlarged view of another embodiment of region Q1.

[0130] Reference Figures 5 to 7 The first display area AA1 may include a plurality of display pixel areas DPA. Depending on the resolution of the display device 10, a predetermined number of display pixel areas DPA may be arranged along a first direction X and a second direction Y. The first direction X and the second direction Y may be substantially perpendicular to each other.

[0131] Each display pixel area (DPA) can include, for example: Figure 6 The pixel PXL shown and as Figure 7 At least one of the pixels PXL' shown. Each of pixels PXL and PXL' may include multiple subpixels (or subpixel regions) that emit light of the same or different colors. For example, a subpixel may emit red light R, green light G, and / or blue light B. However, the disclosure is not limited, and subpixels included in the display pixel region DPA may emit light of various colors, as long as the subpixels can be combined to achieve white light.

[0132] Each subpixel may include a reference. Figure 2A The pixel PXL described includes the construction of the pixel circuit PC and the light-emitting element LD. For example, Figure 2A The pixel PXL can represent the circuitry of a subpixel.

[0133] In this embodiment, pixel PXL can be as follows: Figure 6 The diagram shows a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 arranged along a first direction X. The first sub-pixel SPX1, second sub-pixel SPX2, and third sub-pixel SPX3 can be arranged in a stripe pattern. For example, the first sub-pixel SPX1 (or the first sub-pixel area) can emit red light R, the second sub-pixel SPX2 (or the second sub-pixel area) can emit green light G, and the third sub-pixel SPX3 (or the third sub-pixel area) can emit blue light B.

[0134] In another embodiment, pixel PXL' can be as follows: Figure 7 The diagram shows a first sub-pixel SPX1, a second sub-pixel SPX2, a third sub-pixel SPX3, and a fourth sub-pixel SPX4 arranged along a first direction X. The first sub-pixel SPX1, second sub-pixel SPX2, third sub-pixel SPX3, and fourth sub-pixel SPX4 can be arranged in a Pentile pattern. For example, the first sub-pixel SPX1 can emit red light R, the second sub-pixel SPX2 can emit green light G, the third sub-pixel SPX3 can emit blue light B, and the fourth sub-pixel SPX4 (or a fourth sub-pixel area) can emit green light G.

[0135] At the same time, Figure 6 and Figure 7 In this embodiment, each sub-pixel has a rectangular shape, but the disclosure is not limited. That is, in various embodiments, each sub-pixel can have various shapes, such as squares, rhombuses, hexagons, and octagons. Furthermore, in... Figure 6 and Figure 7 In this embodiment, each sub-pixel has the same area as the others, but the disclosure is not limited thereto. That is, in various embodiments, a sub-pixel that emits light of any color (e.g., red light R and / or blue light B) may have a larger area than a sub-pixel that emits light of another color (e.g., green light G).

[0136] Figure 8 This is a schematic plan view of the second display area AA2 according to an embodiment.

[0137] Reference Figure 8The second display area AA2 may include a pixel area PA and a transmissive area TA. In an embodiment, the pixel area PA and the transmissive area TA may be arranged alternately along a first direction X and a second direction Y.

[0138] The pixel region PA may include a first pixel region PA1, a second pixel region PA2, and a third pixel region PA3, and the transmission region TA may include a first transmission region TA1, a second transmission region TA2, and a third transmission region TA3.

[0139] The first pixel region PA1 and the first transmissive region TA1 can be arranged alternately along the first direction X to form a first pixel row PXR1. The second pixel region PA2 and the second transmissive region TA2 can be arranged alternately along the first direction X to form a second pixel row PXR2. The third pixel region PA3 and the third transmissive region TA3 can be arranged alternately along the first direction X to form a third pixel row PXR3. The first pixel row PXR1, the second pixel row PXR2, and the third pixel row PXR3 can be arranged sequentially along the second direction Y. Therefore, the first pixel region PA1, the second pixel region PA2, and the third pixel region PA3 can be located in different pixel rows.

[0140] Furthermore, the second display area AA2 may include multiple pixel columns. For example, the second display area AA2 may include a first pixel column PXC1 and a second pixel column PXC2. The first pixel column PXC1 consists of a first pixel region PA1, a second transmissive region TA2, and a third pixel region PA3 arranged sequentially along the second direction Y. The second pixel column PXC2 is adjacent to the first pixel column PXC1 and consists of a first transmissive region TA1, a second pixel region PA2, and a third transmissive region TA3 arranged sequentially along the second direction Y. The first pixel column PXC1 and the second pixel column PXC2 may be arranged alternately along the first direction X. Therefore, the first pixel region PA1 included in the first pixel column PXC1 and the second pixel region PA2 included in the second pixel column PXC2 may be located in different pixel columns.

[0141] Each of the pixel regions PA1, PA2, and PA3 may include a reference. Figure 6 and Figure 7 The pixels PXL and PXL' (or subpixels SPX1, SPX2, SPX3, and SPX4) are described. Each of the pixel regions PA1, PA2, and PA3 may include multiple pixels PXL and PXL', but is not limited thereto. Each of the pixel regions PA1, PA2, and PA3 may include only one pixel.

[0142] Figure 9A It is based on Figure 8 An enlarged view of an embodiment of region Q2. Figure 9B It is based on Figure 8An enlarged view of another embodiment of region Q2.

[0143] In the following text, reference will be made to Figure 9A and Figure 9B The arrangement structure of pixels and signal lines in the second display area AA2 is described in detail.

[0144] Reference Figure 8 , Figure 9A and Figure 9B The second display area AA2 may include a first pixel area PA1, a second pixel area PA2, and a third pixel area PA3. As described above, the first pixel area PA1, the second pixel area PA2, and the third pixel area PA3 may be located in different pixel rows PXR1, PXR2, and PXR3.

[0145] First pixel PXL1, second pixel PXL2, and third pixel PXL3 can be disposed in the second display area AA2. Additionally, multiple signal lines SLp-1, SLp, ELp, SLq-1, SLq, ELq, SLr-1, SLr, and ELr, as well as the initialization power line VIL, which transmit drive signals, can be disposed in the second display area AA2. The drive signals are used to drive each of pixels PXL1, PXL2, and PXL3. The second display area AA2 may include a first transmissive area TA1, a second transmissive area TA2, and a third transmissive area TA3 arranged between the corresponding pixel areas PA1, PA2, and PA3.

[0146] Each of pixel regions PA1, PA2, and PA3 may include multiple sub-pixels (or sub-pixel regions) that emit light of the same or different colors. For example, the first pixel region PA1 may include a first sub-pixel SPX11 (or a first sub-pixel region), a second sub-pixel SPX12 (or a second sub-pixel region), a third sub-pixel SPX13 (or a third sub-pixel region), and a fourth sub-pixel SPX14 (or a fourth sub-pixel region) arranged along the first direction X. Additionally, the second pixel region PA2 may include a first sub-pixel SPX21, a second sub-pixel SPX22, a third sub-pixel SPX23, and a fourth sub-pixel SPX24 (or a first sub-pixel region, a second sub-pixel region, a third sub-pixel region, and a fourth sub-pixel region) arranged along the first direction X, and the third pixel region PA3 may include a first sub-pixel SPX31, a second sub-pixel SPX32, a third sub-pixel SPX33, and a fourth sub-pixel SPX34 (or a first sub-pixel region, a second sub-pixel region, a third sub-pixel region, and a fourth sub-pixel region) arranged along the first direction X.

[0147] The first sub-pixels SPX11 to SPX14 of the first pixel region PA1 can emit light of different colors. The first sub-pixels SPX11 to SPX14 can be arranged in a pentile pattern. For example, the first sub-pixel SPX11 can emit red light, the second sub-pixel SPX12 can emit green light, the third sub-pixel SPX13 can emit blue light, and the fourth sub-pixel SPX14 can emit green light. However, the disclosure is unrestricted, and the first sub-pixels SPX11 to SPX14 can emit various colors of light, as long as white light can be achieved through combinations of the first sub-pixels SPX11 to SPX14.

[0148] Similar to the first sub-pixels SPX11 to SPX14 in the first pixel region PA1, the first sub-pixels SPX21 to SPX24 in the second pixel region PA2 and the first sub-pixels SPX31 to SPX34 in the third pixel region PA3 can also emit light of different colors.

[0149] The construction of subpixels included in each of the pixel regions PA1, PA2 and PA3 is not limited, and may include only three subpixels that emit light of different colors, or may include white subpixels that emit white light.

[0150] At the same time, for ease of description, Figure 9A , Figure 9B and Figure 10A The diagram illustrates a structure in which each of pixel regions PA1, PA2, and PA3 comprises one pixel PXL1, PXL2, and PXL3, but the present disclosure is not limited. For example, each of pixel regions PA1, PA2, and PA3 may include multiple pixels. Reference will be made later. Figure 11 This will be described in detail.

[0151] like Figure 8 As shown, the first transmission region TA1 can be defined between the first pixel regions PA1 arranged along the first direction X, the second transmission region TA2 can be defined between the second pixel regions PA2 arranged along the first direction X, and the third transmission region TA3 can be defined between the third pixel regions PA3 arranged along the first direction X.

[0152] The multiple signal lines SLp-1, SLp, ELp, SLq-1, SLq, ELq, SLr-1, SLr, and ELr may include: initialization lines SLp-1, SLq-1, and SLr-1 providing initialization signals; scan lines SLp, SLq, and SLr providing scan signals; and transmit control lines ELp, ELq, and ELr providing transmit control signals. Each of the signal lines SLp-1, SLp, ELp, SLq-1, SLq, ELq, SLr-1, SLr, and ELr, as well as the initialization power line VIL, can be configured to pass through the corresponding pixel regions PA1, PA2, and PA3.

[0153] Initialization lines SLp-1, SLq-1, and SLr-1 can be related to the reference. Figure 2A The signal lines corresponding to the second scan line SLi-1 described herein, scan lines SLp, SLq, and SLr can be the same as the reference. Figure 2A The signal lines corresponding to the first scan line SLi described, and the transmit control lines ELp, ELq, and ELr can be the same as the reference. Figure 2A The described transmit control line ELi corresponds to the signal line. The initialization power line VIL can be connected to the initialization power Vint (i.e., Figure 2A This allows the initial power supply voltage to be transferred to each of pixels PXL1, PXL2, and PXL3.

[0154] Simultaneously, the gate electrode of the initialization transistor TINT can be connected to initialization lines SLp-1, SLq-1, and SLr-1. For example, the gate electrodes of initialization transistors TINT1 and TINT2, which are connected to the first light-emitting element LD1 (e.g., LD11 and LD12) of the first pixel PXL1, can be connected to the second initialization line SLq-1, which provides an initialization signal to the second pixel PXL2. Similarly, the gate electrode of initialization transistor TINT3, which is connected to the second light-emitting element LD2 of the second pixel PXL2, can be connected to the third initialization line SLr-1, which provides an initialization signal to the third pixel PXL3.

[0155] In an embodiment, signal lines SLp-1, SLp, ELp, SLq-1, SLq, ELq, SLr-1, SLr and ELr, as well as the initialization power line VIL, can be configured to bypass the transmission regions TA1, TA2 and TA3 located between the corresponding pixel regions PA1, PA2 and PA3.

[0156] For example, signal lines SLq-1, SLq, and ELq passing through the second pixel region PA2, as well as the initialization power line VIL, can be arranged adjacent to the first pixel region PA1 in an upward direction (e.g., the second direction Y) to bypass the second transmission region TA2 adjacent in the first direction X. In other words, the second transmission region TA2 can be a region formed by bypassing the signal lines SLq-1, SLq, and ELq and the initialization power line VIL arranged in the adjacent second pixel region PA2. However, the arrangement of the signal lines SLq-1, SLq, and ELq and the initialization power line VIL in the second pixel region PA2 is not limited, and can be arranged adjacent to the third pixel region PA3 in a downward direction (e.g., the direction opposite to the second direction Y) to bypass the second transmission region TA2.

[0157] In the first pixel region PA1, a first initialization line SLp-1, a first scan line SLp, a first emission control line ELp, and an initialization power line VIL can be provided, thus providing various signals to the first pixel PXL1. In addition, a first light-emitting element LD1 can be disposed in the first pixel region PA1, and the first light-emitting element LD1 emits light of different colors corresponding to each sub-pixel SPX11 to SPX14.

[0158] The first initialization line SLp-1 can be connected to the fourth transistor M4 located in the first pixel area PA1. Figure 2A The gate electrode (shown in the diagram) is used to provide the gate initialization signal. The first scan line SLp can be connected to the second transistor M2 (in the diagram). Figure 2A The gate electrode and the third transistor M3 (shown in) Figure 2A The gate electrode (shown in the diagram) is used to provide the scan signal. The first emitter control line ELp can be connected to the fifth transistor M5 (in the diagram). Figure 2A The gate electrode and the sixth transistor M6 (shown in) Figure 2A The gate electrode (shown in the figure) is used to provide the transmit control signal.

[0159] At the same time, the initialization transistor TINT of the first pixel PXL1 can be compared with the reference. Figure 2AThe seventh transistor M7 described has the same structure. The initialization transistor TINT can be located in a pixel region (e.g., a second pixel region PA2) that is different from the pixel region of the first light-emitting element LD1 located in the first pixel region PA1. Furthermore, the initialization transistor TINT can be located in a pixel region different from the pixel regions of the first transistors M1 to M6 located in the first pixel region PA1. For example, the first light-emitting element LD1 (or the first transistors M1 to M6) of the first pixel PXL1 can be located in the region where the first pixel row PXR1 and the first pixel column PXC1 intersect, and the initialization transistor TINT of the first pixel PXL1 can be located in the region where the second pixel row PXR2 and the second pixel column PXC2 intersect. That is, the initialization transistor TINT can be located in a pixel row and pixel column that are different from the pixel row and pixel column of the first light-emitting element LD1 (or the first transistors M1 to M6).

[0160] In other words, the first light-emitting element LD1 and the first transistor M1 to the sixth transistor M6 of the first pixel PXL1 can be positioned in the second direction Y relative to the second transmission region TA2, and the initialization transistor TINT for initializing the anode electrode of the first light-emitting element LD1 of the first pixel PXL1 can be set in at least one of the following ways: set in the direction opposite to the first direction X relative to the second transmission region TA2 and set in the first direction X relative to the second transmission region TA2.

[0161] The initialization transistor TINT may include a first initialization transistor TINT1 and a second initialization transistor TINT2. The first initialization transistor TINT1 and the second initialization transistor TINT2 may be located in the same sub-pixel. For example, the first initialization transistor TINT1 and the second initialization transistor TINT2 may be located in the fourth sub-pixel SPX24 of the second pixel region PA2. In another embodiment, the first initialization transistor TINT1 and the second initialization transistor TINT2 may be located in any one of the first sub-pixel SPX21, the second sub-pixel SPX22, and the third sub-pixel SPX23 of the second pixel region PA2. In yet another embodiment, the first initialization transistor TINT1 and the second initialization transistor TINT2 may be located in different sub-pixels.

[0162] For example, such as Figure 9BAs shown, the initialization transistor TINT connected to the first light-emitting element LD1 of the first pixel PXL1 can be respectively disposed in the first sub-pixels SPX21 to the fourth sub-pixels SPX24 of the second pixel region PA2. For example, the initialization transistor TINT connected to the first light-emitting element LD11 of the first pixel PXL1 can be disposed in the third sub-pixel SPX23 of the second pixel region PA2, and the initialization transistor TINT connected to the first light-emitting element LD12 of the first pixel PXL1 can be disposed in the fourth sub-pixel SPX24 of the second pixel region PA2.

[0163] Return to reference Figure 9A One electrode of the initialization transistor TINT, which is located in the second pixel area PA2, can be connected to the initialization power line VIL, while the other electrode can be connected to the first light-emitting element LD1 in the first pixel area PA1 via the connection line CNL. The connection line CNL includes a first connection line CNL1 and a second connection line CNL2.

[0164] The first initialization transistor TINT1 can be connected to the first light-emitting element LD11 in the first sub-pixel SPX11 of the first pixel region PA1 via the first connection line CNL1, and the second initialization transistor TINT2 can be connected to the first light-emitting element LD12 in the second sub-pixel SPX12 of the first pixel region PA1 via the second connection line CNL2.

[0165] The initialization transistor TINT can be turned on when the initialization signal of the gate conduction voltage is supplied to the second initialization line SLq-1 located in the second pixel area PA2, so as to supply the initialization power supply voltage of the initialization power line VIL to the first light-emitting element LD1 through the connection line CNL.

[0166] The initialization signal provided by the second initialization line SLq-1 of the second pixel region PA2 can be the same signal as the scan signal provided by the previous pixel row (e.g., the first pixel row PXR1). That is, the signal provided by the second initialization line SLq-1 can be substantially the same signal as the signal provided by the first scan line SLp of the first pixel region PA1.

[0167] The connecting line CNL can be a conductive pattern comprising a metallic material or a transparent conductive material. The connecting line CNL can be disposed on the same layer as a transistor configuration disposed in the first pixel region PA1 and the second pixel region PA2. That is, the connecting line CNL can be formed simultaneously with the transistor configuration.

[0168] Further reference Figure 2BIn one embodiment, the connection line CNL can be formed between the substrate layer SUB and the gate electrode GAT. For example, the connection line CNL can be formed on the same layer as the body electrode BML. In another embodiment, the connection line CNL can be formed on the same layer as the gate electrode GAT of the first transistor M1. When the connection line CNL is formed on the same layer as the body electrode BML or the gate electrode GAT, the connection line CNL can be highly efficient considering the design rules of the transistor. The arrangement of the connection line CNL is not limited; the connection line CNL can be formed on the same layer as the semiconductor pattern SC or the first metal pattern SDM1 and the second metal pattern SDM2, or it can be formed on a separate layer.

[0169] like Figure 9A As shown, the first connecting line CNL1 and the second connecting line CNL2, which are connected to different first light-emitting elements LD1, can be formed on the same layer. In this case, the first connecting line CNL1 and the second connecting line CNL2 may not overlap each other in the plane. However, this disclosure is not limited, and the first connecting line CNL1 and the second connecting line CNL2 may be formed on different layers. In this case, the first connecting line CNL1 and the second connecting line CNL2 may overlap each other in the plane. (See below for further details.) Figure 10A and Figure 10B This will be described.

[0170] Similar to the first pixel region PA1, the second pixel region PA2 can be equipped with a second initialization line SLq-1, a second scan line SLq, a second emission control line ELq, and an initialization power line VIL, thus providing various signals to the second pixel PXL2. Additionally, a second light-emitting element LD2 can be disposed in the second pixel region PA2, emitting light of a different color corresponding to each of the first sub-pixels SPX21 to the fourth sub-pixels SPX24 of the second pixel region PA2. As described above, the initialization transistor TINT disposed in the second pixel region PA2 can be connected to the first light-emitting element LD1 of the first pixel region PA1. However, the initialization transistor TINT disposed in the second pixel region PA2 may not be connected to the second light-emitting element LD2 of the second pixel region PA2.

[0171] Additionally, the second light-emitting element LD2 can be connected to an initialization transistor TINT located in a pixel region other than the second pixel region PA2. For example, the second light-emitting element LD2 can be connected to a third initialization transistor TINT3 located in the third pixel region PA3.

[0172] In other words, the initialization transistor TINT connected to the light-emitting element LD can be located in a region different from the region of other components of the pixel PXL (e.g., the first transistor M1 to the sixth transistor M6 and the light-emitting element LD).

[0173] As described above, when the initialization transistor TINT is located in a pixel region different from the pixel region of the first light-emitting element LD1, the area of ​​the transmission regions TA1, TA2, and TA3 can be expanded. For example, when the initialization transistor TINT of the first pixel PXL1 is located in the first pixel region PA1 instead of the second pixel region PA2, it may not be possible to adequately ensure bypass space for the signal lines SLq-1, SLq, and ELq used to provide the second transmission region TA2, as well as the initialization power line VIL. However, as Figure 9B As shown, when the initialization transistor TINT is set in a pixel region (e.g., the second pixel region PA2) that is different from the pixel region of the first light-emitting element LD1 set in the first pixel region PA1, the bypass space for the signal lines SLq-1, SLq and ELq and the initialization power line VIL used to provide the second transmission region TA2 can be sufficiently ensured, so that a large area of ​​the second transmission region TA2 can be formed.

[0174] When the areas of the transmission regions TA1, TA2, and TA3 are increased, the transmittance of the second display region AA2 can be improved. Therefore, more signals (e.g., optical signals) can pass through the second display region AA2 and be incident on the sensor 120 (i.e., Figure 4 It can also improve the recognition accuracy and reliability of sensor 120.

[0175] In the following description, other embodiments of the display device 10 will be described. In the following embodiments, the same construction as the embodiments described above will be indicated by the same reference numerals, and their descriptions will be omitted or simplified, with the differences being the main focus.

[0176] Figure 10A It is based on Figure 8 An enlarged view of another embodiment of region Q2. Figure 10B It is along Figure 10A A schematic cross-sectional view taken by line A-A'.

[0177] Figure 10A and Figure 10B Implementation examples and Figure 9A The difference in the embodiment is that the connecting lines to each light-emitting element are superimposed on each other on a plane.

[0178] Reference Figure 8 and Figure 10AThe second display area AA2' may include a first pixel area PA1, a second pixel area PA2, and a third pixel area PA3. The first pixel area PA1, the second pixel area PA2, and the third pixel area PA3 may be located in different pixel rows PXR1, PXR2, and PXR3, and the first pixel area PA1, the second pixel area PA2, and the third pixel area PA3 may be located in different pixel columns PXC1 and PXC2. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be located in the second display area AA2'. Furthermore, multiple signal lines SLp-1, SLp, ELp, SLq-1, SLq, ELq, SLr-1, SLr, and ELr, which transmit drive signals, and the initialization power line VIL may be located in the second display area AA2'. The drive signals are used to drive each of pixels PXL1, PXL2, and PXL3. The second display area AA2' may include a first transmission area TA1, a second transmission area TA2, and a third transmission area TA3 arranged between the corresponding pixel areas PA1, PA2, and PA3.

[0179] The first pixel PXL1 may include a first light-emitting element LD1 (e.g., LD11 and LD12) and an initialization transistor TINT connected thereto. The first light-emitting element LD1 may be disposed in each of the first sub-pixels SPX11 to the fourth sub-pixels SPX14 of the first pixel region PA1, and the first light-emitting element LD1 may emit light of different colors respectively. The initialization transistor TINT may be disposed in a pixel region different from the pixel region of the first light-emitting element LD1 disposed in the first pixel region PA1 (e.g., a second pixel region PA2).

[0180] The initialization transistor TINT can include a first initialization transistor TINT1 and a second initialization transistor TINT2. The first initialization transistor TINT1 and the second initialization transistor TINT2 can be located in the same sub-pixel. The first initialization transistor TINT1 and the second initialization transistor TINT2 can be connected to a first light-emitting element LD11 and LD12 via a connecting line CNLa. The connecting line CNLa can include a first connecting line CNL1 and a second connecting line CNL2. The first initialization transistor TINT1 can be connected via the first connecting line CNL1 to a first light-emitting element LD11 located in the first sub-pixel SPX11 of the first pixel region PA1, and the second initialization transistor TINT2 can be connected via the second connecting line CNL2 to another first light-emitting element LD12 located in the second sub-pixel SPX12 of the first pixel region PA1.

[0181] like Figure 10AAs shown, at least a portion of the first connecting line CNL1 and the second connecting line CNL2 can overlap each other on the plane.

[0182] Further reference Figure 2B and Figure 10B At least a portion of the first connection line CNL1 and the second connection line CNL2 can be stacked on top of each other in a plane and can be formed on different layers. Specifically, the first connection line CNL1 can be formed between the substrate layer SUB and the gate electrode GAT. For example, the first connection line CNL1 can be with... Figure 2B The main electrode BML is formed on the same layer. The second connecting line CNL2 can be formed on the second insulating layer INS2. For example, the second connecting line CNL2 can be... Figure 2B The gate electrode (GAT) is formed on the same layer.

[0183] When the first connection line CNL1 and the second connection line CNL2 can be electrically isolated from each other, the arrangement of the corresponding connection lines CNL1 and CNL2 is not limited thereto. For example, the first connection line CNL1 can be formed on the same layer as the gate electrode GAT, and the second connection line CNL2 can be formed on the same layer as the body electrode BML. In addition, the first connection line CNL1 and the second connection line CNL2 can be formed on the same layer as the semiconductor pattern SC or the first metal pattern SDM1 and the second metal pattern SDM2, and can also be formed on separate layers.

[0184] As described above, when the first connecting line CNL1 and the second connecting line CNL2 are superimposed on each other, the space provided between the second pixel region PA2 for providing the second transmission region TA2 can be further expanded. That is, it can provide a space larger than... Figure 9A The embodiment has a wide transmission region. Therefore, the area of ​​the transmission regions TA1, TA2, and TA3 can be increased, and the transmittance of the second display region AA2 can be further improved.

[0185] Figure 11 It is based on Figure 8 An enlarged view of another embodiment of region Q2.

[0186] Figure 11 The difference between this embodiment and the previous embodiment is that multiple sub-pixel rows are provided in a pixel region.

[0187] Reference Figure 8 and Figure 11The second display area AA2" may include a first pixel area PA1, a second pixel area PA2, and a third pixel area PA3. Each of the pixel areas PA1, PA2, and PA3 may include multiple sub-pixels (or sub-pixel areas) that emit light of the same or different colors. The second display area AA2" may include a first transmission area TA1, a second transmission area TA2, and a third transmission area TA3 arranged between the corresponding pixel areas PA1, PA2, and PA3.

[0188] The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be disposed in the second display area AA2". Each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include a first sub-pixel row PXL1a, PXL2a, and PXL3a (or a first sub-pixel region) and a second sub-pixel row PXL1b, PXL2b, and PXL3b (or a second sub-pixel region) arranged along the second direction Y. Each sub-pixel row may include a plurality of sub-pixels arranged along the first direction X.

[0189] In addition, multiple signal lines SLpa-1, SLpb-1, SLpa, SLpb, ELpa, ELpb, SLqa-1, SLqb-1, SLqa, SLqb, ELqa, ELqb, SLra-1, SLrb-1, SLra, SLrb, ELra and ELrb, as well as the initialization power line VIL, can be set in the second display area AA2”, and the drive signals are used to drive each of pixels PXL1, PXL2 and PXL3.

[0190] Multiple signal lines SLpa-1, SLpb-1, SLpa, SLpb, ELpa, ELpb, SLqa-1, SLqb-1, SLqa, SLqb, ELqa, ELqb, SLra-1, SLrb-1, SLra, SLrb, ELra, and ELrb may include: initialization lines SLpa-1, SLpb-1, SLqa-1, SLqb-1, SLra-1, and SLrb-1 providing initialization signals; scan lines SLpa, SLpb, SLqa, SLqb, SLra, and SLrb providing scan signals; and transmit lines ELpa, ELpb, ELqa, ELqb, ELra, and ELrb providing transmit control signals. Multiple signal lines SLpa-1, SLpb-1, SLpa, SLpb, ELpa, ELpb, SLqa-1, SLqb-1, SLqa, SLqb, ELqa, ELqb, SLra-1, SLrb-1, SLra, SLrb, ELra and ELrb, as well as the initialization power line VIL, can be configured to pass through each of the pixel regions PA1, PA2 and PA3.

[0191] For example, in the first pixel region PA1, first initialization lines SLpa-1 and SLpb-1, first scan lines SLpa and SLpb, first emission control lines ELpa and ELpb, and an initialization power line VIL can be provided, thus providing various signals to the first pixel PXL1. Additionally, first light-emitting elements LD1 (e.g., LD11, LD12, and LD13) emitting different colors of light can be provided in the first pixel region PA1.

[0192] The light-emitting elements disposed in the first sub-pixel rows PXL1a, PXL2a, and PXL3a (or the first sub-pixel region) can be connected to the initialization transistors disposed in the second sub-pixel rows PXL1b, PXL2b, and PXL3b (or the second sub-pixel region), respectively. For example, the first light-emitting element LD13 disposed in the first sub-pixel row PXL1a of the first pixel region PA1 can be connected to the fourth initialization transistor TINT4 disposed in the second sub-pixel row PXL1b of the first pixel region PA1. That is, some of the initialization transistors in the pixel circuits of the first sub-pixel rows PXL1a, PXL2a, and PXL3a can be disposed in the second sub-pixel rows PXL1b, PXL2b, and PXL3b (or the second sub-pixel region).

[0193] Light-emitting elements disposed in the second sub-pixel rows PXL1b, PXL2b, and PXL3b can be connected via connecting line CNLb to initialization transistors disposed in the first sub-pixel rows PXL1a, PXL2a, and PXL3a located in another pixel region. Connecting line CNLb may include a first connecting line CNL1 and a second connecting line CNL2. For example, a first light-emitting element LD11 disposed in the second sub-pixel row PXL1b of the first pixel region PA1 can be connected via the first connecting line CNL1 to a first initialization transistor TINT1 disposed in the first sub-pixel row PXL2a, and a first light-emitting element LD12 disposed in the second sub-pixel row PXL1b of the first pixel region PA1 can be connected via the second connecting line CNL2 to a second initialization transistor TINT2 disposed in the first sub-pixel row PXL2a of the second pixel region PA2.

[0194] Light-emitting elements and initialization transistors located in the same sub-pixel row may not be connected to each other. For example, the first light-emitting element LD11 located in the second sub-pixel row PXL1b of the first pixel region PA1 may not be connected to the fourth initialization transistor TINT4 located in the same sub-pixel row as the first light-emitting element LD11.

[0195] The first connecting line CNL1 and the second connecting line CNL2 can be superimposed on each other in the plane. In this case, as shown in the reference... Figure 10Aand Figure 10B The first connecting line CNL1 and the second connecting line CNL2 can be formed on different layers. Therefore, the area of ​​the transmission regions TA1, TA2, and TA3 can be further increased, and the transmittance of the second display region AA2” can be improved.

[0196] Figure 11 The diagram illustrates a structure in which two sub-pixel rows are arranged within a single pixel region, but is not limited to this configuration. According to an embodiment, three or more sub-pixel rows can be arranged along the second direction Y in each of pixel regions PA1, PA2, and PA3.

[0197] Although the disclosed embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that the embodiments may be implemented in other specific forms without changing the technical spirit and essential characteristics of this disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive.

Claims

1. A display device, the display device comprising: The substrate, including the sensor area; The display panel includes a first pixel disposed in the sensor area; as well as A sensor is disposed between the substrate and the display panel and superimposed on the sensor area. The sensor region includes: multiple pixel regions, with the first pixel disposed within the multiple pixel regions; and multiple transmission regions, with the first pixel not disposed within the multiple transmission regions. The plurality of transmission regions include a first transmission region. The plurality of pixel regions includes: a first pixel region positioned along a first direction of the first transmissive region; and a second pixel region positioned along a second direction of the first transmissive region intersecting with the first direction. The first pixel includes a first pixel circuit and a first light-emitting element. The first pixel circuit includes a first initialization transistor, which is connected between the first light-emitting element of the first pixel and the initialization power supply. The first light-emitting element is disposed in the first pixel region, and The first initialization transistor is disposed in the second pixel region.

2. The display device according to claim 1, wherein, The display panel includes a first scan line, a first initialization line, and a first emission control line connected to the first pixel circuit, and The first scan line, the first initialization line, and the first emission control line pass through the first pixel region and bypass the transmission region adjacent to the first pixel region.

3. The display device according to claim 2, wherein, The pixel region further includes a third pixel region, which is located in a direction opposite to the first direction of the first transmission region. A second pixel is also provided in the pixel area. The second pixel includes a second pixel circuit. At least a portion of the second pixel circuit is disposed in the second pixel region. The other parts of the second pixel circuit are disposed in the third pixel region, and The second pixel circuit includes a second initialization transistor, which is disposed in the third pixel region and connected between the second light-emitting element of the second pixel and the initialization power supply.

4. The display device according to claim 3, wherein, The display panel includes a second scan line and a second initialization line connected to the second pixel circuit, and The second scan line and the second initialization line pass through the second pixel region and bypass the transmission region adjacent to the second pixel region.

5. The display device according to claim 2, wherein, The pixel region further includes a third pixel region, which is positioned in the first direction of the first pixel region. A second pixel is also provided in the pixel area. The second pixel includes a second pixel circuit. At least a portion of the second pixel circuit is disposed in the third pixel region. Another part of the second pixel circuit is disposed in the first pixel region, and The second pixel circuit includes a second initialization transistor, which is disposed in the first pixel region and connected between the second light-emitting element of the second pixel and the initialization power supply.

6. The display device according to claim 1, wherein, The display panel includes a connection pattern that electrically connects the anode electrode of the first light-emitting element and the first initialization transistor to each other without overlapping with the transmissive region. Wherein, at least one transistor included in the transistors of the first pixel circuit includes: A substrate layer is disposed on the substrate; Semiconductor patterns are disposed on the substrate layer; A gate electrode is disposed on the semiconductor pattern; and A first metal pattern and a second metal pattern are disposed on the gate electrode and in contact with the semiconductor pattern, and The connection pattern is formed between the substrate layer and the gate electrode or on the same layer as the gate electrode.

7. The display device according to claim 1, wherein, The display panel also includes a display area, in which display pixels are provided. The display area surrounds the sensor area, and The density of the first pixel in the sensor area is lower than the density of the display pixels in the display area.

8. A display device, the display device comprising: The substrate, including the sensor area; The display panel includes a first pixel circuit disposed in the sensor area, a first light-emitting element connected to the first pixel circuit, and a second pixel circuit. as well as A sensor is disposed between the substrate and the display panel and superimposed on the sensor area. The sensor region includes a transmissive region, a first pixel region adjacent to the transmissive region in a first direction, and a second pixel region adjacent to the transmissive region in a second direction intersecting the first direction. The first pixel circuit includes an initialization transistor connected between the anode electrode of the first light-emitting element and an initialization power supply. The first light-emitting element is disposed in the first pixel region, and At least a portion of the initialization transistor and the second pixel circuit are disposed in the second pixel region.

9. The display device according to claim 8, wherein, The display panel also includes a third pixel circuit. At least one transistor in the third pixel circuit is disposed adjacent to the second pixel circuit in the first direction, and The other transistors in the transistors of the third pixel circuit are disposed adjacent to the transmission region in the first direction.

Images