Display device

Abstract

A display device according to an embodiment of the disclosure includes a substrate, a first conductive layer on the substrate, a first insulating layer on the first conductive layer, an active pattern on the first insulating layer, and the active pattern including a semiconductor material, a second insulating layer on the active pattern, and a second conductive layer on the second insulating layer, wherein the first insulating layer has a first opening exposing the first conductive layer, the second insulating layer has a second opening exposing the first conductive layer, a width of the first opening is different from a width of the second opening, and side surfaces of the first opening and the second opening are formed to a top surface of the first conductive layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0008722, filed on January 22, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices. Background Technology

[0004] Display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays include a display panel comprising a plurality of pixels capable of displaying images. Each pixel includes a pixel electrode for receiving data signals, and the pixel electrode is connected to at least one transistor to receive data signals.

[0005] To manufacture display devices, various suitable electrical devices and conductors, such as transistors, can be formed by stacking layers of various suitable materials on a substrate and patterning the layers using methods such as photolithography, which includes exposure using a photomask (e.g., exposure).

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background of this disclosure, and therefore, the above information may include information that does not constitute prior art that is normally known to those skilled in the art. Summary of the Invention

[0007] As the number of photomasks used in the manufacturing process of display devices increases, the manufacturing time and cost of display devices will also increase.

[0008] Various aspects of embodiments of this disclosure relate to reducing the number of photomasks used in the manufacturing process of a display device, thereby reducing the manufacturing time and cost of the display device, and also reducing damage to semiconductor layers in the manufacturing process.

[0009] Furthermore, aspects of the embodiments of this disclosure relate to a display device that reduces the area of ​​a pixel and achieves high resolution by reducing the number of openings for contact between different layers stacked on the substrate of the display device.

[0010] A display device according to an embodiment of the present disclosure includes: a substrate; a first conductive layer on the substrate; a first insulating layer on the first conductive layer; an active pattern on the first insulating layer, the active pattern comprising a semiconductor material; a second insulating layer on the active pattern; and a second conductive layer on the second insulating layer, wherein the first insulating layer has a first opening exposing the first conductive layer, the second insulating layer has a second opening exposing the first conductive layer, the first opening being different in width from the second opening, and side surfaces of the first opening and the second opening being formed onto a top surface of the first conductive layer.

[0011] The second conductive layer may include a first electrode, and the first electrode may be electrically connected to the first conductive layer through the second opening.

[0012] The second insulating layer may have a third opening that exposes the active pattern, and the first electrode may be electrically connected to the active pattern through the third opening.

[0013] The display device may further include a third insulating layer located on the active pattern and a third conductive layer located on the third insulating layer, and in the cross-sectional view, there may be no other conductive layer between the second conductive layer and the third conductive layer.

[0014] The side surface of the third insulating layer can be aligned with the side surface of the third conductive layer.

[0015] The first conductive layer may include a conductive pattern that overlaps with the active pattern, the second conductive layer may include a pixel electrode that is electrically connected to the conductive pattern through the second opening, and the display device may also include an emission layer and a common electrode located on the pixel electrode.

[0016] The first conductive layer may include a data line, and the second conductive layer may include a connection member electrically connected to the data line through the second opening.

[0017] The side surface of the active pattern can be aligned with the side surface of the first opening.

[0018] A display device according to an embodiment of the present disclosure includes: a substrate; a first conductive layer on the substrate; a first insulating layer on the first conductive layer; an active pattern on the first insulating layer, the active pattern comprising a semiconductor material; a second insulating layer on the active pattern; and a second conductive layer on the second insulating layer, wherein the first insulating layer has a first opening exposing the first conductive layer, the second insulating layer has a second opening exposing the first conductive layer, the first opening differs from the second opening in width, the first opening and the second opening are connected to each other to form an opening, and the opening is filled with a material of the second conductive layer.

[0019] The second conductive layer may include a first electrode, and the first electrode may be electrically connected to the first conductive layer through the opening.

[0020] The second insulating layer may have a third opening on the active pattern, and the first electrode may be electrically connected to the active pattern through the third opening.

[0021] The display device may further include a third insulating layer located on the active pattern and a third conductive layer located on the third insulating layer, and in the cross-sectional view, there may be no other conductive layer between the second conductive layer and the third conductive layer.

[0022] The side surface of the third insulating layer can be aligned with the side surface of the third conductive layer.

[0023] The first conductive layer may include a conductive pattern that overlaps with the active pattern, the second conductive layer may include a pixel electrode that is electrically connected to the conductive pattern through the opening, and the display device may also include an emitter layer and a common electrode located on the pixel electrode.

[0024] The first conductive layer may include a data line, and the second conductive layer may include a connection member electrically connected to the data line through the opening.

[0025] The side surface of the active pattern can be aligned with the side surface of the first opening.

[0026] A method for manufacturing a display device according to an embodiment of the present disclosure includes: forming a first conductive layer on a substrate; forming a first insulating layer and a semiconductor layer on the first conductive layer; forming a first mask pattern on the semiconductor layer including a first portion and a second portion having different thicknesses and having a first opening; patterning the first insulating layer and the semiconductor layer using the first mask pattern as a mask to form a second opening in the first insulating layer; removing the second portion of the first mask pattern to form a second mask pattern including a portion of the first portion and having a thickness less than the thickness of the first portion; patterning the semiconductor layer using the second mask pattern as a mask to form a semiconductor pattern; forming a second insulating layer and a second conductive layer on the semiconductor pattern; forming a third insulating layer on the second conductive layer; and forming a third mask pattern on the third insulating layer and patterning the third insulating layer using the third mask pattern as a mask to form a third opening overlapping the second opening.

[0027] The first opening may differ in width from the second opening, and in forming the third opening, the side surfaces of the first opening and the second opening may be formed onto the top surface of the first conductive layer.

[0028] The manufacturing method may further include: forming a third conductive layer on the third insulating layer, wherein the second opening may be different in width from the third opening, and in forming the third opening, the second opening and the third opening may be connected to each other to form an opening, and the opening may be filled with the material of the third conductive layer.

[0029] In forming the semiconductor pattern by patterning the semiconductor layer, the side surface of the semiconductor pattern can be aligned with the side surface of the second opening of the first insulating layer.

[0030] According to embodiments of this disclosure, the number of photomasks used in the manufacturing process of a display device can be reduced, thereby reducing the manufacturing time and cost of the display device, and also reducing damage to the semiconductor layer during the manufacturing process.

[0031] A display device with a reduced pixel area and high resolution can be provided by reducing the number of openings for contact between different layers stacked on the substrate of the display device. Attached Figure Description

[0032] The accompanying drawings, together with the description, illustrate exemplary embodiments of the invention. These drawings, together with the description, are used to better explain various aspects and principles of the invention.

[0033] Figure 1This is a circuit diagram of a pixel of a display device according to an embodiment of the present disclosure;

[0034] Figure 2 This is a layout diagram of a plurality of pixels of a display device according to an embodiment of the present disclosure;

[0035] Figure 3 It is intercepted along line IIIa-IIIb. Figure 2 Cross-sectional view of the display device shown;

[0036] Figure 4 It is intercepted along line IVa-IVb. Figure 2 Cross-sectional view of the display device shown;

[0037] Figure 5 and Figure 6 This is a cross-sectional view of the display device in the manufacturing process of the display device according to an embodiment of the present disclosure, and respectively along the and Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown in the figure;

[0038] Figure 7 and Figure 8 In separate Figure 5 and Figure 6 The cross-sectional view of the display device shown is a process following the manufacturing process of the display device, and is respectively along the process with... Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown in the figure;

[0039] Figure 9 and Figure 10 In separate Figure 7 and Figure 8 The cross-sectional view of the display device shown is a process following the manufacturing process of the display device, and is respectively along the process with Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown in the figure;

[0040] Figure 11 and Figure 12 In separate Figure 9 and Figure 10 The cross-sectional view of the display device shown is a process following the manufacturing process of the display device, and is respectively along the process with Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown in the figure;

[0041] Figure 13 and Figure 14 In separate Figure 11 and Figure 12The cross-sectional view of the display device shown is a process following the manufacturing process of the display device, and is respectively along the process with Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown in the figure;

[0042] Figure 15 and Figure 16 In separate Figure 13 and Figure 14 The cross-sectional view of the display device shown is a process following the manufacturing process of the display device, and is respectively along the process with Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown in the figure;

[0043] Figure 17 It is taken along line IIIa-IIIb as another example embodiment. Figure 2 Cross-sectional view of the display device shown;

[0044] Figure 18 It is taken along line IVa-IVb as another example embodiment. Figure 2 Cross-sectional view of the display device shown;

[0045] Figure 19 and Figure 20 In separate Figure 11 and Figure 12 Other example embodiments of the cross-sectional view of the display device in the process following the manufacturing process of the display device shown, and respectively along with the process of manufacturing the display device. Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown in the figure;

[0046] Figure 21 It is taken along line IIIa-IIIb as another example embodiment. Figure 2 Cross-sectional view of the display device shown;

[0047] Figure 22 It is taken along line IVa-IVb as another example embodiment. Figure 2 Cross-sectional view of the display device shown;

[0048] Figure 23 and Figure 24 In separate Figure 11 and Figure 12 Other example embodiments of the cross-sectional view of the display device in the process following the manufacturing process of the display device shown, and respectively along with the process of manufacturing the display device. Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown in the figure;

[0049] Figure 25 This is a layout diagram of a plurality of pixels of a display device according to an embodiment of the present disclosure;

[0050] Figure 26 It is a section taken along line XXVIa-XXVIb. Figure 25 Cross-sectional view of the display device shown;

[0051] Figure 27 It is a section taken along line XXVIIa-XXVIIb. Figure 25 Cross-sectional view of the display device shown;

[0052] Figure 28 and Figure 29 In separate Figure 5 and Figure 6 Other example embodiments of the cross-sectional view of the display device in the process following the manufacturing process of the display device shown, and respectively along with the process of manufacturing the display device. Figure 25 The cross-sectional view of the lines corresponding to lines XXVIa-XXVIb and XXVIIa-XXVIIb shown in the figure;

[0053] Figure 30 and Figure 31 In separate Figure 28 and Figure 29 Other example embodiments of the cross-sectional view of the display device in the process following the manufacturing process of the display device shown, and respectively along with the process of manufacturing the display device. Figure 25 The cross-sectional views of the lines XXVIa-XXVIb and XXVIIa-XXVIIb shown are shown; and

[0054] Figure 32 This is a cross-sectional view of a display device according to an embodiment of the present disclosure. Detailed Implementation

[0055] In the following description, the present disclosure will be described more fully with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated. As those skilled in the art will recognize, the described embodiments may be modified in a variety of suitable and different ways without departing from the spirit or scope of the present disclosure. As used herein, when describing embodiments of the present disclosure, the term "may" means "one or more embodiments of the present disclosure".

[0056] To clearly explain this disclosure, parts not directly related to this disclosure may be omitted, and throughout the specification, the same reference numerals refer to the same or similar constituent elements.

[0057] Additionally, for better understanding and ease of description, the dimensions and thicknesses of each configuration shown in the accompanying drawings may be exaggerated, but this disclosure is not limited thereto. In the drawings, the thicknesses of layers, films, panels, and regions, etc., may be exaggerated for clarity. In the drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description. As used herein, the terms “substantially,” “approximately,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent deviations in measurements or calculations that will be recognized by one of ordinary skill in the art.

[0058] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on said other element, or there may be intermediate elements present. In contrast, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in this specification, the terms "on" or "above" may indicate, for example, being positioned on or below an element, and do not necessarily indicate being positioned on the upper side of an element based on the direction of gravity. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are also intended to include the plural forms.

[0059] Furthermore, unless explicitly stated otherwise, the word “including” and variations such as “containing” and “comprising” will be understood to implicitly include the stated element, but not exclude any other element.

[0060] Throughout this specification, plan views represent views of a surface parallel to two intersecting directions (e.g., a first direction DR1 and a second direction DR2). For example, the surface may be parallel to a plane defined by the two directions. Cross-sectional views represent views of a surface cut in a direction perpendicular to the surface parallel to the first direction DR1 and the second direction DR2 (e.g., a third direction DR3). Additionally, unless otherwise stated, overlapping of two constituent elements means that the two constituent elements overlap in a third direction DR3 (e.g., a direction perpendicular to the upper surface of the substrate).

[0061] Now, referring to Figure 1 Examples describing the structure of a display device according to embodiments of the present disclosure.

[0062] Figure 1 This is a circuit diagram of a pixel PX of a display device according to an embodiment of the present disclosure.

[0063] The display device according to embodiments of the present disclosure includes a plurality of pixels PX as units capable of displaying images, and as follows Figure 1As shown, a pixel PX may include a pixel circuit unit and at least one light-emitting diode (LED) ED as a light-emitting element connected to the pixel circuit unit. The pixel circuit unit includes a plurality of transistors T1, T2, and T3 and a capacitor Cst. In this embodiment, an example in which one pixel PX includes a light-emitting diode (LED) ED is mainly described.

[0064] The multiple transistors T1, T2 and T3 include a first transistor T1, a second transistor T2 and a third transistor T3.

[0065] The gate electrode G1 of the first transistor T1 is connected to one terminal of the capacitor Cst, the source electrode S1 of the first transistor T1 is connected to a drive voltage line that can transmit the drive voltage ELVDD, and the drain electrode D1 of the first transistor T1 is connected to the anode of the light-emitting diode (LED) ED and to the other terminal of the capacitor Cst. The first transistor T1 can receive the data voltage DAT according to the switching operation of the second transistor T2, so as to supply drive current to the light-emitting diode (LED) ED according to the voltage stored in the capacitor Cst.

[0066] The gate electrode G1 of the first transistor T1 may face the conductive pattern 111, and the conductive pattern 111 may be electrically connected to the drain electrode D1 of the first transistor T1 and electrically connected to the anode of the light-emitting diode (LED) ED.

[0067] The gate electrode G2 of the second transistor T2 is connected to a first scan line that can transmit the first scan signal SC. The source electrode S2 of the second transistor T2 is connected to a data line that can transmit the data voltage DAT or a reference voltage. The drain electrode D2 of the second transistor T2 is connected to a terminal of the capacitor Cst and the gate electrode G1 of the first transistor T1. The second transistor T2 can be turned on according to the first scan signal SC to transmit the reference voltage or data voltage DAT to the gate electrode G1 of the first transistor T1 and to a terminal of the capacitor Cst.

[0068] The gate electrode G3 of the third transistor T3 is connected to the second scan line that can transmit the second scan signal SS; the source electrode S3 of the third transistor T3 is connected to the other terminal of the capacitor Cst, the drain electrode D1 of the first transistor T1, and the anode of the light-emitting diode (LED) ED; and the drain electrode D3 of the third transistor T3 is connected to the initialization voltage line that can transmit the initialization voltage INIT. The third transistor T3 can be turned on according to the second scan signal SS to transmit the initialization voltage INIT to the anode of the light-emitting diode (LED) ED and to the other terminal of the capacitor Cst, thereby initializing the voltage of the anode of the light-emitting diode (LED) ED.

[0069] One terminal of capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other terminal is connected to the source electrode S3 of the third transistor T3 and to the anode of the light-emitting diode (LED) ED. The cathode of the LED ED is connected to a common voltage line that can transmit the common voltage ELVSS.

[0070] A light-emitting diode (LED) can emit light according to a drive current formed by a first transistor T1 (e.g., flowing from or through the first transistor T1).

[0071] The structure of the pixel PX included in the display device according to the exemplary embodiments of this disclosure is not limited to... Figure 1 The circuit diagram shown is for reference only; however, various suitable pixel structures may be used depending on the type or variety of the display device.

[0072] Now, refer to Figures 2 to 4 Together with the above Figure 1 The structure of a display device according to embodiments of the present disclosure is described.

[0073] Figure 2 This is a layout diagram of a plurality of pixels of a display device according to an embodiment of the present disclosure. Figure 3 It is intercepted along line IIIa-IIIb. Figure 2 The cross-sectional view of the display device shown is as follows, and Figure 4 It is intercepted along line IVa-IVb. Figure 2 The cross-sectional view of the display device shown is shown.

[0074] The display device according to embodiments of the present disclosure may include a substrate 110. The substrate 110 may include (e.g.) an insulating material such as glass and plastic, and may be flexible.

[0075] A first conductive layer including a conductive pattern 111 and multiple signal lines and voltage lines can be disposed on a substrate 110. The multiple signal lines and voltage lines may include a common voltage line 170, multiple data lines 171a, 171b and 171c, a drive voltage line 172 and an initialization voltage line 173, etc.

[0076] The conductive pattern 111 can be disposed in each of pixels PX1, PX2, and PX3. The conductive pattern 111 may include (e.g., be) various suitable conductive metals and / or semiconductor materials having suitable conductivity properties (e.g., conductivity properties equivalent to those of conductive metals).

[0077] In the plan view, the common voltage line 170, multiple data lines 171a, 171b and 171c, drive voltage line 172 and initialization voltage line 173 can each extend substantially in the second direction DR2.

[0078] A buffer layer 120, which serves as an insulating layer, can be disposed on the first conductive layer.

[0079] The buffer layer 120 may include an opening 68a disposed on the conductive pattern 111 (e.g., exposing the conductive pattern 111), an opening disposed on the common voltage line 170 (e.g., exposing the common voltage line 170), an opening 64c disposed on each of the data lines 171a, 171b and 171c (e.g., exposing each of the data lines 171a, 171b and 171c), an opening 60c disposed on the drive voltage line 172 (e.g., exposing the drive voltage line 172), and an opening disposed on the initialization voltage line 173.

[0080] An active layer comprising multiple active patterns 130a, 130b, and 130c can be disposed on the buffer layer 120. The active patterns 130a, 130b, and 130c disposed in pixels PX1, PX2, and PX3 respectively may each include channel regions 134a, 134b, and 134c forming the respective channels of the plurality of transistors T1, T2, and T3, and respective conductive regions connected to the channel regions 134a, 134b, and 134c. Each conductive region of the active patterns 130a, 130b, and 130c may each include source regions 133a, 133b, and 133c and drain regions 135a, 135b, and 135c of transistors T1, T2, and T3.

[0081] Multiple active patterns 130a, 130b and 130c set in each of pixels PX1, PX2 and PX3 are separated from each other, but are not limited thereto.

[0082] The active layer may include (for example, be) a semiconductor material such as amorphous silicon, polycrystalline silicon, or oxide semiconductor, such as indium gallium zinc oxide (IGZO).

[0083] Insulating patterns 144 and 145 of the first insulating layer can be formed on the active layer. Insulating pattern 144 can be formed on channel regions 134a, 134b, and 134c, and overlaps with the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c. Insulating pattern 144 may substantially not overlap with the conductive regions of the active patterns 130a, 130b, and 130c. Insulating pattern 145 may not overlap with the active layer.

[0084] A second conductive layer may be provided on insulating patterns 144 and 145.

[0085] The second conductive layer may include a first scan line 151 capable of transmitting (e.g., capable of transmitting) the first scan signal SC, a second scan line 152 capable of transmitting (e.g., capable of transmitting) the second scan signal SS, a driving gate electrode 155, a first gate electrode 154a, a second gate electrode 154b, and a third gate electrode 154c, etc. Figure 1 The gate electrodes G1, G2, and G3 in the second conductive layer can correspond to the first gate electrode 154a, the second gate electrode 154b, and the third gate electrode 154c, respectively. The driving gate electrode 155 can be referred to as the first gate electrode.

[0086] Each of the first scan line 151 and the second scan line 152 may extend substantially in the first direction DR1, thereby intersecting with the common voltage line 170, data lines 171a, 171b and 171c, drive voltage line 172 and initialization voltage line 173.

[0087] The driving gate electrode 155 can be disposed corresponding to each of pixels PX1, PX2, and PX3. The driving gate electrode 155 disposed in each of pixels PX1, PX2, and PX3 may include a first gate electrode 154a protruding upward or downward and a protruding portion 155a protruding downward or upward. For example, the first gate electrode 154a may protrude in a direction opposite to the second direction DR2, and the protruding portion 155a may protrude in the second direction DR2. The first gate electrode 154a overlaps with and intersects with the channel region 134a of the active pattern 130a.

[0088] Multiple second gate electrodes 154b corresponding to multiple pixels PX1, PX2, and PX3 can be connected to each other to form an elongated shape extending in the second direction DR2, and can be electrically connected to the first scan line 151. The second gate electrodes 154b overlap with the channel region 134b of the active pattern 130b, and intersect with the active pattern 130b of each of pixels PX1, PX2, and PX3.

[0089] Multiple third gate electrodes 154c corresponding to multiple pixels PX1, PX2, and PX3 can be connected to each other to form an elongated shape extending in the second direction DR2, and can be electrically connected to the second scan line 152. The third gate electrodes 154c overlap with the channel region 134c of the active pattern 130c, and intersect with the active pattern 130c of each of pixels PX1, PX2, and PX3.

[0090] The edges of the first gate electrode 154a (e.g., side surfaces, such as side surfaces extending in the second direction DR2 and having a normal direction parallel to the first direction DR1), the edges of the second gate electrode 154b, and the edges of the third gate electrode 154c, which overlap with the active patterns 130a, 130b, and 130c respectively, can be aligned parallel (e.g., substantially parallel) to the respective edges (e.g., side surfaces) of the lower insulating pattern 144 and to the respective channel regions in the channel regions 134a, 134b, and 134c.

[0091] At least one selected from the first conductive layer and the second conductive layer may include (for example,) at least one selected from metals such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof. At least one selected from the first conductive layer and the second conductive layer may include a single layer or multiple layers. For example, the second conductive layer may have a multilayer structure including a lower layer and an upper layer, the lower layer including (for example,) titanium, and the upper layer including (for example,) copper.

[0092] A second insulating layer 160 may be disposed on the second conductive layer.

[0093] A third insulating layer 180 may be disposed on the second insulating layer 160.

[0094] The second insulating layer 160 and the third insulating layer 180 may include a plurality of openings 60a, 60d, 61a, 61b, 62, 63, 64a, 64d, 65, 66, 68b and 81.

[0095] Opening 68b may overlap with opening 68a of buffer layer 120. Opening 68b may be connected to opening 68a of buffer layer 120 to form an opening 68. The planar dimensions (e.g., width, diameter, or planar area) of opening 68b may be the same as or different from the planar dimensions (e.g., width, diameter, or planar area) of opening 68a.

[0096] Opening 81 may overlap with an opening of a buffer layer 120 disposed on the common voltage line 170 (e.g., exposing the common voltage line 170). Opening 81 may be connected to an opening of the buffer layer 120 disposed on the common voltage line 170 to form an opening (as indicated by reference numeral 81).

[0097] Opening 64d may overlap with opening 64c of buffer layer 120. Opening 64d may be connected to opening 64c of buffer layer 120 to form an opening 64b. The planar dimensions (e.g., width, diameter, or planar area) of opening 64d may be the same as or different from the planar dimensions (e.g., width, diameter, or planar area) of opening 64c.

[0098] Opening 60d may overlap with opening 60c of buffer layer 120. Opening 60d may be connected to opening 60c of buffer layer 120 to form an opening 60b. The planar dimensions (e.g., width, diameter, or planar area) of opening 60d may be the same as or different from the planar dimensions (e.g., width, diameter, or planar area) of opening 60c.

[0099] Opening 61b may overlap with an opening provided on initialization voltage line 173 (e.g., exposing initialization voltage line 173). Opening 61b may be connected to (or correspond to) an opening provided on initialization voltage line 173 to form an opening (indicated by reference numeral 61b).

[0100] An opening 60a may be disposed on the source region 133a of the active pattern 130a (e.g., exposing the source region 133a of the active pattern 130a). An opening 62 may be disposed on the drain region 135a of the active pattern 130a (e.g., exposing the drain region 135a of the active pattern 130a). An opening 61a may be disposed on the drain region 135c of the active pattern 130c (e.g., exposing the drain region 135c of the active pattern 130c). An opening 63 may be disposed on the source region 133c of the active pattern 130c (e.g., exposing the source region 133c of the active pattern 130c). An opening 66 may be disposed on the protrusion 155a of the drive gate electrode 155 (e.g., exposing the protrusion 155a of the drive gate electrode 155). An opening 65 may be provided on the drain region 135b of the active pattern 130b (e.g., exposing the drain region 135b of the active pattern 130b). An opening 64a may be provided on the source region 133b of the active pattern 130b (e.g., exposing the source region 133b of the active pattern 130b).

[0101] At least one selected from the buffer layer 120, the second insulating layer 160, and the third insulating layer 180 may include (for example,) silicon nitride (SiN). x ), silicon dioxide (SiO) xInorganic insulating materials such as silicon oxynitride (SiON) and / or organic insulating materials. For example, the third insulating layer 180 may include (e.g., is) an organic insulating material such as polyimide, acrylic polymer and / or siloxane polymer and may have a substantially flat top surface, and the second insulating layer 160 may include (e.g., is) an inorganic insulating material.

[0102] The second insulating layer 160 can be omitted.

[0103] A third conductive layer may be disposed on the third insulating layer 180.

[0104] The third conductive layer may include multiple pixel electrodes 191a, 191b and 191c and multiple connecting members 174, 175, 176, 178 and 191d.

[0105] Each of the plurality of pixel electrodes 191a, 191b, and 191c is electrically connected to the drain region 135a of the first transistor T1 through an opening 62 in the second insulating layer 160 and the third insulating layer 180 of each of pixels PX1, PX2, and PX3, thereby receiving voltage from the first transistor T1. Additionally, each of the plurality of pixel electrodes 191a, 191b, and 191c is electrically connected to the conductive pattern 111 through an opening 68 in the buffer layer 120, the second insulating layer 160, and the third insulating layer 180. Therefore, the drain region 135a of the first transistor T1 can be electrically connected to the conductive pattern 111.

[0106] Each of the pixel electrodes 191a, 191b, and 191c overlaps with the driving gate electrode 155 facing each of the pixel electrodes 191a, 191b, and 191c via the second insulating layer 160 and the third insulating layer 180 (e.g., each of the pixel electrodes 191a, 191b, and 191c can face the driving gate electrode 155 through the second insulating layer 160 and the third insulating layer 180) to form a capacitor Cst. For the connection between the pixel electrodes 191a, 191b, and 191c and the drain region 135a of the active pattern 130a, the driving gate electrode 155 may have an opening 55a overlapping the opening 62.

[0107] The connecting member 174 can be electrically connected to the source region 133a of the active pattern 130a through the opening 60a, and can be electrically connected to the driving voltage line 172 through the opening 60b in each of the pixels PX1, PX2 and PX3, and thus the source region 133a of the active pattern 130a and the driving voltage line 172 can be electrically connected to each other.

[0108] The connecting member 175 can be electrically connected to the drain region 135c of the active pattern 130c through the opening 61a, and can be electrically connected to the initialization voltage line 173 through the opening 61b in each of the pixels PX1, PX2 and PX3, and thus the drain region 135c of the active pattern 130c and the initialization voltage line 173 can be electrically connected to each other.

[0109] The connecting member 176 can be electrically connected to the source region 133b of the active pattern 130b through the opening 64a, and can be electrically connected to each of the data lines 171a, 171b and 171c through the opening 64b in each of the pixels PX1, PX2 and PX3. Therefore, the source region 133b of the active pattern 130b and each of the data lines 171a, 171b and 171c can be electrically connected to each other.

[0110] The connecting member 178 can be electrically connected to the drain region 135b of the active pattern 130b through the opening 65, and can be electrically connected to the protrusion 155a of the drive gate electrode 155 through the opening 66 in each of the pixels PX1, PX2 and PX3. Therefore, the drain region 135b of the active pattern 130b and the protrusion 155a of the drive gate electrode 155 can be electrically connected to each other.

[0111] The connecting member 191d can be electrically connected to the common voltage line 170 through the opening 81.

[0112] The third conductive layer may include (for example) a semi-permeable conductive material and / or a reflective conductive material.

[0113] In some embodiments, in a cross-sectional view (e.g., a section view), no other conductive layer is disposed between the second conductive layer and the third conductive layer.

[0114] The first transistor T1 includes a channel region 134a, a source region 133a, a drain region 135a, and a first gate electrode 154a. The source region 133a of the first transistor T1 is electrically connected to the drive voltage line 172, thereby receiving the drive voltage.

[0115] The conductive pattern 111 corresponding to the first transistor T1 overlaps with the channel region 134a between the first gate electrode 154a of the first transistor T1 and the substrate 110, preventing external light from reaching the channel region 134a, thereby reducing leakage current and characteristic degradation. The conductive pattern 111 is electrically connected to the drain region 135a of the first transistor T1 through pixel electrodes 191a, 191b and 191c.

[0116] The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 is electrically connected to each of the data lines 171a, 171b, and 171c, thereby receiving a data voltage or a reference voltage. The drain region 135b of the second transistor T2 can be electrically connected to the first gate electrode 154a via a drive gate electrode 155.

[0117] The third transistor T3 includes a channel region 134c, a source region 133c, a drain region 135c, and a third gate electrode 154c. The drain region 135c of the third transistor T3 can receive an initialization voltage from the initialization voltage line 173.

[0118] A fourth insulating layer 350 may be disposed on the third conductive layer. The fourth insulating layer 350 may have an opening 355 disposed on each of the pixel electrodes 191a, 191b and 191c respectively.

[0119] The fourth insulating layer 350 may include (for example, be) an organic insulating material such as polyacrylic resin and / or polyimide resin.

[0120] An emitting layer 370 may be disposed between the fourth insulating layer 350 and the third conductive layer. In some embodiments, the emitting layer 370 may be disposed on the third conductive layer and on the fourth insulating layer 350. The emitting layer 370 may include a portion disposed in an opening 355 of the fourth insulating layer 350. The emitting layer 370 may include (e.g., is) an organic light-emitting material and / or an inorganic light-emitting material. The emitting layer 370 may include a portion disposed on the fourth insulating layer 350, and at least a portion of the fourth insulating layer 350 may not be covered by the emitting layer 370.

[0121] The fourth insulating layer 350 and the emitting layer 370 may have an opening 82 provided on the connecting member 191d (e.g., exposing the connecting member 191d).

[0122] A common electrode 270 is disposed on the emitter layer 370. The common electrode 270 may be continuously formed above multiple pixels PX1, PX2 and PX3. The common electrode 270 contacts the connecting member 191d through the opening 82 to be electrically connected to the common voltage line 170, and the common electrode 270 can thus receive the common voltage.

[0123] The common electrode 270 may include (for example) a conductive transparent material.

[0124] Each of the pixel electrodes 191a, 191b, and 191c, together with the emitter layer 370 and the common electrode 270, forms a light-emitting diode (LED) ED, and one of the pixel electrodes (191a, 191b, and 191c) and the common electrode 270 becomes (e.g., constitutes) a cathode, and the other becomes (e.g., constitutes) an anode. An example in which the pixel electrodes 191a, 191b, and 191c become (e.g., constitute) the anode of the light-emitting diode (LED) ED has been described above.

[0125] In the plan view, the area where the fourth insulating layer 350 is provided, the opening 355, can define the light-emitting area of ​​each of the pixels PX1, PX2, and PX3.

[0126] Since the conductive pattern 111 is electrically connected to each corresponding pixel electrode 191a, 191b, and 191c and overlaps with the channel region 134a of the first transistor T1, the rate of change of current decreases in the saturation region of the voltage-current characteristic diagram of the first transistor T1, thereby expanding the range of the region in which the output current of the first transistor T1 is constant. Therefore, even if the source-drain voltage of the first transistor T1 changes, the output current of the first transistor T1 remains constant, thus improving the output saturation characteristics. Consequently, the brightness deviation between pixels caused by the output current of the first transistor T1 is reduced, thereby improving image quality.

[0127] According to this embodiment, the number of conductive and insulating layers constituting transistors T1, T2, and T3 and light-emitting diodes (LEDs) ED disposed on the substrate 110 can be minimized or reduced, thereby simplifying the structure of the display device.

[0128] Next, refer to Figures 5 to 16 Together with the above Figures 1 to 4 A method for manufacturing a display device according to embodiments of the present disclosure is described.

[0129] Figure 5 and Figure 6 This is a cross-sectional view of the display device in the manufacturing process of the display device according to an embodiment of the present disclosure, and respectively along the and Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown.

[0130] Reference Figure 5 and Figure 6A first conductive layer is formed by stacking and patterning various suitable conductive metals and / or semiconductor materials with suitable conductivity properties (e.g., conductivity equivalent to that of the conductive metals) on an insulating substrate 110, including a conductive pattern 111, a common voltage line 170, multiple data lines 171a, 171b and 171c, a drive voltage line 172 and an initialization voltage line 173, etc. The patterning method may utilize photolithography including exposure using a photomask.

[0131] Figure 7 and Figure 8 In separate Figure 5 and Figure 6 The manufacturing process of the display device shown is followed by (for example, immediately after) Figure 5 and Figure 6 The cross-sectional view of the display device in the manufacturing process of the display device shown is shown, and is respectively along the process of manufacturing the display device with respect to ... Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown.

[0132] Reference Figure 7 and Figure 8 An insulating material is stacked on a substrate 110 and a first conductive layer to form a buffer layer 120, and a semiconductor material, such as amorphous silicon, polycrystalline silicon, and / or oxide semiconductor, is stacked on the buffer layer 120 to form a semiconductor layer 130. Subsequently, a photosensitive material, such as a photoresist, is stacked on the semiconductor layer 130 to form a photosensitive material layer, and the photosensitive material layer is exposed (e.g., exposed to light) using a halftone photomask to form a mask pattern 50.

[0133] The mask pattern 50 may include a first portion 51 and a second portion 52 that is thinner than the first portion 51, and may have an opening 50H from which the photosensitive material layer is removed. The first portion 51 may be formed to correspond to the active patterns 130a, 130b and 130c described above.

[0134] Subsequently, the semiconductor layer 130 and the buffer layer 120 are etched using a mask pattern 50 with an opening 50H as a mask to form openings 60c, 64c and 68a of the buffer layer 120 corresponding to the openings 50H and the opening 130H of the semiconductor layer 130.

[0135] Figure 9 and Figure 10 In separate Figure 7 and Figure 8 The manufacturing process of the display device shown is followed by (for example, immediately after) Figure 7 and Figure 8 The cross-sectional view of the display device in the manufacturing process of the display device shown is shown, and is respectively along the process of manufacturing the display device with respect to ... Figure 2The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown.

[0136] Reference Figure 9 and Figure 10 The mask pattern 50 can be etched back or altified to remove the second portion 52 and form a mask pattern 51a that includes at least a portion or part of the first portion 51.

[0137] Next, the semiconductor layer 130 is patterned using mask pattern 51a as a mask to form multiple semiconductor patterns 131. The patterning method can utilize wet etching. An etchant with a sufficiently large etch selectivity ratio of the semiconductor layer 130 relative to the first conductive layer can be selected. Therefore, during the etching process of the semiconductor layer 130, almost no etching or damage to the first conductive layer occurs.

[0138] Figure 11 and Figure 12 In separate Figure 9 and Figure 10 The manufacturing process of the display device shown is followed by (for example, immediately after) Figure 9 and Figure 10 The cross-sectional view of the display device in the manufacturing process of the display device shown is shown, and is respectively along the process of manufacturing the display device with respect to ... Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown.

[0139] Reference Figure 11 and Figure 12 Together Figure 9 and Figure 10 The mask pattern 51a is removed from the semiconductor pattern 131. An insulating material is stacked on the substrate 110 to form an insulating material layer. A conductive material is stacked on the insulating material layer to form a conductive material layer. A mask pattern 52a, such as a photoresist, is formed on the conductive material layer. Next, the insulating material layer and the conductive material layer are patterned using the mask pattern 52a as a mask to form insulating patterns 144 and 145 and a lower second conductive layer. The lower second conductive layer includes a first scan line 151 including a second gate electrode 154b, a second scan line 152 including a third gate electrode 154c, and a drive gate electrode 155 including a protrusion 155a and the first gate electrode 154a. The patterning of the second conductive layer can be performed using wet etching, and the patterning of the insulating patterns 144 and 145 can be performed using dry etching.

[0140] During the dry etching used to pattern insulating patterns 144 and 145, the exposed semiconductor pattern 131 not covered by insulating pattern 144 may be doped with N-type (e.g., N-based) or P-type (e.g., P-based) impurities. Thus, active patterns 130a, 130b, and 130c can be formed, including source regions 133a, 133b, and 133c, drain regions 135a, 135b, and 135c, and channel regions 134a, 134b, and 134c overlapping with insulating pattern 144. After the dry etching of insulating patterns 144 and 145, a process can also be performed to dope N-type (e.g., N-based) or P-type (e.g., P-based) impurities into the semiconductor pattern 131 not covered by insulating pattern 144 to be exposed.

[0141] Figure 13 and Figure 14 In separate Figure 11 and Figure 12 The manufacturing process of the display device shown is followed by (for example, immediately after) Figure 11 and Figure 12 The cross-sectional view of the display device in the manufacturing process of the display device shown is shown, and is respectively along the process of manufacturing the display device with respect to ... Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown.

[0142] Reference Figure 13 and Figure 14 After removing the mask pattern 52a, an insulating material (e.g., an inorganic insulating material) is stacked on the substrate 110 to form a second insulating layer 160, and an insulating material (e.g., an organic insulating material) is stacked on the second insulating layer 160 to form a third insulating layer 180. Next, a mask pattern 53, such as a photoresist, is formed on the third insulating layer 180. Next, the third insulating layer 180 and the second insulating layer 160 are patterned using the mask pattern 53 as a mask to form a plurality of openings 60a, 60d, 61a, 61b, 62, 63, 64a, 64d, 65, 66, 68b, and 81 as described above. Here, the patterning method can utilize dry etching. In this case, since openings 60c, 64c, and 68a have already been formed in the buffer layer 120, it is not necessary to etch the buffer layer 120 when etching the third insulating layer 180 and the second insulating layer 160. Therefore, in the process of forming openings in the second insulating layer 160 and the third insulating layer 180, etching of active patterns 130a, 130b and 130c and corresponding damage to active patterns 130a, 130b and 130c can be prevented or reduced.

[0143] Figure 15 and Figure 16 In separate Figure 13 and Figure 14 The manufacturing process of the display device shown is followed by (for example, immediately after) Figure 13 and Figure 14 The cross-sectional view of the display device in the manufacturing process of the display device shown is shown, and is respectively along the process of manufacturing the display device with respect to ... Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown.

[0144] Reference Figure 15 and Figure 16 Conductive material is stacked on a third insulating layer 180 and the conductive material is patterned to form a third conductive layer, the third conductive layer including a plurality of pixel electrodes 191a, 191b and 191c and a plurality of connecting members 174, 175, 176, 178 and 191d.

[0145] like Figure 3 and Figure 4 As shown, a fourth insulating layer 350 is formed on the third conductive layer and the fourth insulating layer 350 is patterned to form an opening 355, and an emitter layer 370 and a common electrode 270 may be sequentially formed on the opening 355.

[0146] According to the manufacturing method of the display device in this embodiment, the process for forming transistors T1, T2, and T3 for pixels PX1, PX2, and PX3, as well as light-emitting diodes (LEDs) ED, requires a total of six photomasks. These six photomasks include a photomask for patterning a first conductive layer, a halftone photomask for forming openings in a buffer layer 120 and forming a semiconductor pattern 131, a photomask for patterning insulating patterns 144 and 145 and a second conductive layer, a photomask for forming openings in a second insulating layer 160 and a third insulating layer 180, a photomask for patterning a third conductive layer, and a photomask for forming openings 355 in a fourth insulating layer 350. Therefore, compared to related technologies, the manufacturing time and cost of the display device can be reduced by decreasing the number of photomasks used in the manufacturing process.

[0147] Furthermore, as described above, in the process of forming openings in the second insulating layer 160 and the third insulating layer 180, since openings 60c, 64c, and 68a are already formed in the buffer layer 120, it is not necessary to etch the buffer layer 120 when etching the third insulating layer 180 and the second insulating layer 160. Therefore, in the process of forming openings in the second insulating layer 160 and the third insulating layer 180, the etching of active patterns 130a, 130b, and 130c, as well as the corresponding damage to active patterns 130a, 130b, and 130c, can be prevented or reduced.

[0148] Furthermore, as described above, in the process of forming openings in the second insulating layer 160 and the third insulating layer 180, the buffer layer 120 does not need to be etched, thereby reducing the etching time. Therefore, the problem of the surface of the third insulating layer 180 becoming uneven or rough due to over-etching can be prevented or reduced.

[0149] Next, refer to Figure 17 and Figure 18 Together with the above Figures 2 to 4 A display device according to embodiments of the present disclosure is described.

[0150] Figure 17 It is taken along line IIIa-IIIb as another example embodiment. Figure 2 The cross-sectional view of the display device shown is as follows, and Figure 18 It is taken along line IVa-IVb as another example embodiment. Figure 2 The cross-sectional view of the display device shown is shown.

[0151] Reference Figure 17 and Figure 18 The display device according to this embodiment and the display device according to Figures 2 to 4 Most of the display devices in the embodiments are the same, but the size and / or shape of the openings selected from the openings of the second insulating layer 160 and the third insulating layer 180 that overlap with the openings of the buffer layer 120 may be different.

[0152] For example, the size (e.g., width, diameter, or planar area) of the opening 68b of the second insulating layer 160 and the third insulating layer 180 that overlaps with the opening 68a of the buffer layer 120 can be smaller than the size (e.g., width, diameter, or planar area) of the opening 68a, and in a plan view, the opening 68b can be disposed inside the opening 68a. For example, in a plan view, the opening 68a can overlap with the entire opening 68b. The openings 68b and 68a can be formed on the upper surface of the conductive pattern 111, respectively.

[0153] The size (e.g., width, diameter, or planar area) of the opening 60d of the second insulating layer 160 and the third insulating layer 180 that overlaps with the opening 60c of the buffer layer 120 can be smaller than the size (e.g., width, diameter, or planar area) of the opening 60c, and in a plan view, the opening 60d can be disposed inside the opening 60c. For example, in a plan view, the opening 60c can overlap with the entire opening 60d. The openings 60d and 60c can be formed on the upper surface of the drive voltage line 172, respectively.

[0154] The size (e.g., width, diameter, or planar area) of the opening 64d of the second insulating layer 160 and the third insulating layer 180 that overlaps with the opening 64c of the buffer layer 120 can be smaller than the size (e.g., width, diameter, or planar area) of the opening 64c, and in a plan view, the opening 64d can be disposed inside the opening 64c. For example, in a plan view, the opening 64c can overlap with the entire opening 64d. The openings 64d and 64c can be formed on the upper surfaces of the data lines 171a, 171b, and 171c, respectively.

[0155] Furthermore, the dimensions (e.g., width, diameter, or planar area) of the openings (e.g., one or more other openings) of the second insulating layer 160 and the third insulating layer 180 that overlap with the openings (e.g., corresponding openings) of the buffer layer 120 may be smaller than the dimensions (e.g., width, diameter, or planar area) of the openings of the buffer layer 120, and in a plan view, the openings of the second insulating layer 160 and the third insulating layer 180 may be disposed inside the openings of the buffer layer 120. For example, in a plan view, the openings of the buffer layer 120 may overlap with the entire openings of the second insulating layer 160 and the third insulating layer 180.

[0156] Now, refer to Figure 19 and Figure 20 Together Figure 17 and Figure 18 A method for manufacturing a display device according to embodiments of the present disclosure is described.

[0157] Figure 19 and Figure 20 In separate Figure 11 and Figure 12 The manufacturing process of the display device shown is followed by (for example, immediately after) Figure 11 and Figure 12 Other example embodiments of the cross-sectional view of the display device in the manufacturing process of the display device shown are shown, and are respectively along with the process of manufacturing the display device. Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown.

[0158] The manufacturing method of the display device according to the embodiments of the present disclosure and the method according to the present disclosure Figures 5 to 16 The manufacturing methods shown are mostly the same. However, as Figure 19 and Figure 20 Instead of as shown Figure 13 and Figure 14As shown, the mask pattern 53 can have different shapes. Therefore, the size (e.g., width, diameter, or planar area) of each opening in the second insulating layer 160 and the third insulating layer 180 at locations overlapping with the openings (e.g., corresponding openings) of the buffer layer 120 can be smaller than the size (e.g., width, diameter, or planar area) of the openings of the buffer layer 120, and in a plan view, the openings of the second insulating layer 160 and the third insulating layer 180 can be disposed inside the openings of the buffer layer 120. For example, in a plan view, the openings of the buffer layer 120 can overlap with all or a combination of the openings of the second insulating layer 160 and the third insulating layer 180.

[0159] Next, refer to Figure 21 and Figure 22 Together with the above Figures 2 to 4 A display device according to embodiments of the present disclosure is described.

[0160] Figure 21 It is taken along line IIIa-IIIb as another example embodiment. Figure 2 The cross-sectional view of the display device shown is as follows, and Figure 22 It is taken along line IVa-IVb as another example embodiment. Figure 2 The cross-sectional view of the display device shown is shown.

[0161] Reference Figure 21 and Figure 22 The display device according to this embodiment and the display device according to the above embodiment Figures 2 to 4 Most of the display devices in the embodiments shown are the same. However, the size and / or shape of the openings selected from the openings of the second insulating layer 160 and the third insulating layer 180 that overlap with the opening of the buffer layer 120 may be different.

[0162] For example, the size (e.g., width, diameter, or planar area) of the opening 68b of the second insulating layer 160 and the third insulating layer 180 that overlaps with the opening 68a of the buffer layer 120 can be larger than the size (e.g., width, diameter, or planar area) of the opening 68a, and in a plan view, the opening 68a can be disposed inside the opening 68b. For example, in a plan view, the opening 68b can overlap with the entire opening 68a. The edge (e.g., side surface) of the opening 68b can be formed to the top surface of the buffer layer 120. The side surface of the opening 68b and the top surface of the buffer layer 120 and the side surface of the opening 68a of the buffer layer 120 can together form a stepped shape. The openings 68a and 68b are connected to each other to form an opening 68, and the opening 68 can be filled with an extension of each of the pixel electrodes 191a, 191b, and 191c (e.g., the same material as the pixel electrodes 191a, 191b, and 191c).

[0163] The dimensions (e.g., width, diameter, or planar area) of the opening 60d of the second insulating layer 160 and the third insulating layer 180 that overlaps with the opening 60c of the buffer layer 120 may be larger than the dimensions (e.g., width, diameter, or planar area) of the opening 60c, and in a plan view, the opening 60c may be disposed inside the opening 60d. For example, in a plan view, the opening 60d may overlap the entire opening 60c. The edge (e.g., side surface) of the opening 60d may be formed to the top surface of the buffer layer 120. The side surfaces (e.g., side surfaces) of the opening 60d, the top surface of the buffer layer 120, and the side surfaces (e.g., side surfaces) of the opening 60c of the buffer layer 120 may together form a stepped shape. The openings 60c and 60d are connected to each other to form an opening 60b, and the opening 60b may be filled with an extension of the connecting member 174 (e.g., the same material as the connecting member 174).

[0164] The dimensions (e.g., width, diameter, or planar area) of the opening 64d of the second insulating layer 160 and the third insulating layer 180 that overlaps with the opening 64c of the buffer layer 120 may be larger than the dimensions (e.g., width, diameter, or planar area) of the opening 64c, and in a plan view, the opening 64c may be disposed inside the opening 64d. For example, in a plan view, the opening 64d may overlap the entire opening 64c. The edge (e.g., side surface) of the opening 64d may be formed to the top surface of the buffer layer 120. The side surfaces (e.g., side surfaces) of the opening 64d, the top surface of the buffer layer 120, and the side surfaces (e.g., side surfaces) of the opening 64c of the buffer layer 120 may together form a stepped shape. The openings 64c and 64d may be connected to each other to form an opening 64b, and the opening 64b may be filled with an extension of the connecting member 176 (e.g., the same material as the connecting member 176).

[0165] Additionally, the dimensions (e.g., width, diameter, or planar area) of the openings (e.g., one or more other openings) of the second insulating layer 160 and the third insulating layer 180 that overlap with the openings (e.g., corresponding openings) of the buffer layer 120 may be larger than the dimensions (e.g., width, diameter, or planar area) of the openings of the buffer layer 120, and in a plan view, the openings of the buffer layer 120 may be disposed inside the openings of the second insulating layer 160 and the third insulating layer 180. For example, in a plan view, the openings (or combined openings) of the second insulating layer 160 and the third insulating layer 180 may overlap with the entire opening of the buffer layer 120. In some embodiments, the side surfaces (or combined side surfaces) of the openings of the second insulating layer 160 and the third insulating layer 180, the top surface of the buffer layer 120, and the side surfaces of the openings of the buffer layer 120 may together form a stepped shape. The openings of the buffer layer 120 and the openings of the second insulating layer 160 and the third insulating layer 180 may be connected to each other to form an opening, and said opening may be filled with a material (e.g., the material of the third conductive layer).

[0166] Now, refer to Figure 23 and Figure 24 Together Figure 21 and Figure 22 A method for manufacturing a display device according to embodiments of the present disclosure is described.

[0167] Figure 23 and Figure 24 In separate Figure 11 and Figure 12 The manufacturing process of the display device shown is followed by (for example, immediately after) the manufacturing process of the display device shown. Figure 11 and Figure 12 Other example embodiments of the cross-sectional view of the display device in the manufacturing process of the display device shown are shown, and are respectively along with the process of manufacturing the display device. Figure 2 The cross-sectional view of the lines corresponding to lines IIIa-IIIb and IVa-IVb shown.

[0168] The method for manufacturing a display device according to embodiments of the present disclosure and the method according to the above... Figures 5 to 16 The manufacturing methods shown are mostly the same. However, as Figure 23 and Figure 24 As shown and with Figure 13 and Figure 14In contrast, the shape of the mask pattern 53 can be different. Therefore, the size (e.g., width, diameter, or planar area) of the openings of the second insulating layer 160 and the third insulating layer 180 at locations overlapping with the openings of the buffer layer 120 can be larger than the size (e.g., width, diameter, or planar area) of the openings of the buffer layer 120, and in a plan view, the openings of the second insulating layer 160 and the third insulating layer 180 can have edges (e.g., side surfaces) surrounding the openings of the buffer layer 120. For example, in a plan view, the openings of the second insulating layer 160 and the third insulating layer 180 can overlap the entire opening of the buffer layer 120.

[0169] Next, refer to Figures 25 to 27 Together with the above Figures 2 to 4 A display device according to embodiments of the present disclosure is described.

[0170] Figure 25 This is a layout diagram of a plurality of pixels of a display device according to an embodiment of the present disclosure. Figure 26 It is a section taken along line XXVIa-XXVIb. Figure 25 The cross-sectional view of the display device shown is as follows, and Figure 27 It is a section taken along line XXVIIa-XXVIIb. Figure 25 The cross-sectional view of the display device shown is shown.

[0171] Reference Figures 25 to 27 The display device according to this embodiment and the display device according to the above embodiment Figures 2 to 4 Most of the display devices in the embodiments shown are the same. However, the number of openings in each of pixels PX1, PX2, and PX3 (e.g., the openings associated with each of pixels PX1, PX2, and PX3) can be smaller.

[0172] More specifically, in the display device according to this embodiment, the part about "according to" can be omitted. Figures 2 to 4 The openings 60a, 62, 61a and 64a included in the display device of the embodiment shown.

[0173] Each of pixel electrodes 191a, 191b, and 191c can be electrically connected to the conductive pattern 111 and the drain region 135a of the first transistor T1 through an opening 68. For example, pixel electrodes 191a, 191b, and 191c can contact the top surface of the conductive pattern 111 and the side surface 132a on the drain region 135a side of the active pattern 130a through the opening 68 to be electrically connected to the conductive pattern 111 and the drain region 135a.

[0174] In some embodiments, the second insulating layer 160 is not disposed between the extension of the pixel electrode 191a disposed in the opening 68 and the side surface 132a on the drain region 135a side of the active pattern 130a.

[0175] In the plan view, the side surface 132a of the drain region 135a side of the active pattern 130a or the edge of the drain region 135a side of the active pattern 130a can be aligned with the side surface of the opening 68a of the buffer layer 120 or the edge of the opening 68a of the buffer layer 120.

[0176] The connecting member 174 can be electrically connected to the driving voltage line 172 and the source region 133a of the first transistor T1 through an opening 60b. For example, the connecting member 174 can contact the top surface of the driving voltage line 172 and the side surface 132b of the source region 133a side of the active pattern 130a through the opening 60b to be electrically connected to the driving voltage line 172 and the source region 133a.

[0177] In some embodiments, the second insulating layer 160 is not disposed between the extension of the connecting member 174 disposed in the opening 60b and the side surface 132b on the source region 133a side of the active pattern 130a.

[0178] In the plan view, the side surface 132b of the source region 133a side of the active pattern 130a or the edge of the source region 133a side of the active pattern 130a can be aligned with the side surface of the opening 60c of the buffer layer 120 or the edge of the opening 60c of the buffer layer 120.

[0179] The connection member 175 can be electrically connected to the initialization voltage line 173 and the drain region 135c of the third transistor T3 through an opening 61b. For example, the connection member 175 can contact the top surface of the initialization voltage line 173 and the side surface of the drain region 135c of the active pattern 130c through the opening 61b to be electrically connected to the initialization voltage line 173 and the drain region 135c.

[0180] In some embodiments, the second insulating layer 160 is not disposed between the extension of the connecting member 175 disposed in the opening 61b and the side surface on the drain region 135c side of the active pattern 130c.

[0181] In the plan view, the side surface of the drain region 135c of the active pattern 130c or the edge of the drain region 135c of the active pattern 130c may be aligned with the side surface of the opening 61b (e.g., the portion of the opening 61b located in the buffer layer 120) or the edge of the opening 61b.

[0182] The connecting member 176 can be electrically connected to the data lines 171a, 171b, and 171c and the source region 133b of the second transistor T2 through an opening 64b. For example, the connecting member 176 can contact the top surface of the data lines 171a, 171b, and 171c and the side surface 132c on the source region 133b side of the active pattern 130b through the opening 64b to be electrically connected to the data lines 171a, 171b, and 171c and the source region 133b.

[0183] The second insulating layer 160 may not be disposed between the extension of the connecting member 176 disposed in the opening 64b and the side surface 132c on the source region 133b side of the active pattern 130b.

[0184] In the plan view, the side surface 132c of the source region 133b of the active pattern 130b or the edge of the source region 133b of the active pattern 130b can be aligned with the side surface of the opening 64c or the edge of the opening 64c.

[0185] As described above, according to this embodiment, the number of openings for contact between different layers stacked on the substrate 110 of the display device can be reduced for each of pixels PX1, PX2 and PX3, so that the area of ​​one of pixels PX1, PX2 and PX3 can be reduced, and a display device with high resolution can be provided.

[0186] Now, refer to Figures 28 to 31 Together Figures 25 to 27 A method for manufacturing a display device according to embodiments of the present disclosure is described.

[0187] Figure 28 and Figure 29 In separate Figure 5 and Figure 6 The manufacturing process of the display device shown is followed by (for example, immediately after) Figure 5 and Figure 6 Other example embodiments of the cross-sectional view of the display device in the manufacturing process of the display device shown are shown, and are respectively along with the process of manufacturing the display device. Figure 25 The cross-sectional view of the lines corresponding to lines XXVIa-XXVIb and XXVIIa-XXVIIb shown in the figure. Figure 30 and Figure 31 In separate Figure 28 and Figure 29 The manufacturing process of the display device shown is followed by (for example, immediately after) Figure 28 and Figure 29 Other example embodiments of the cross-sectional view of the display device in the manufacturing process of the display device shown are shown, and are respectively along with the process of manufacturing the display device. Figure 25The cross-sectional view of the lines corresponding to lines XXVIa-XXVIb and XXVIIa-XXVIIb shown in the figure.

[0188] The method for manufacturing a display device according to embodiments of the present disclosure and the method according to the above... Figures 5 to 16 The manufacturing methods shown are largely the same. However, as Figures 28 to 31 As shown and with Figures 7 to 10 In contrast, the shape of mask pattern 50 and the shape of mask pattern 51a can be different.

[0189] First, refer to Figure 28 and Figure 29 According to this embodiment, the edge (e.g., side surface) of the first thick portion 51 of the mask pattern 50 can be adjacent to and aligned with the edges (e.g., side surfaces) of the openings 60c, 64c, and 68a of the buffer layer 120. Therefore, the edge (e.g., side surface) of the first thick portion 51 of the mask pattern 50 can form the side surface of the opening 50H. The semiconductor layer 130 and the buffer layer 120 are etched using the mask pattern 50 as a mask to form the openings 60c, 64c, and 68a of the buffer layer 120 corresponding to the opening 50H, and the opening 130H of the semiconductor layer 130.

[0190] Next, refer to Figure 30 and Figure 31 , will be respectively as Figure 28 and Figure 29 The mask pattern 50 shown is etched back or ashed to remove the second portion 52 and form a mask pattern 51a, which includes at least a portion or part of the first portion 51 and has a thickness less than that of the first portion 51. The edges (e.g., side surfaces) of the mask pattern 51a adjacent to the openings 60c, 64c, and 68a of the buffer layer 120 may be aligned with the edges (e.g., side surfaces) of the openings 60c, 64c, and 68a of the buffer layer 120.

[0191] The semiconductor layer 130 can be patterned using a mask pattern 51a to form a plurality of semiconductor patterns 131. The side surfaces 132a, 132b and 132c of the edges of the semiconductor patterns 131 can be aligned with the edges (e.g., side surfaces) of the openings 60c, 64c and 68a of the buffer layer 120.

[0192] Next, refer to Figure 32 Examples of cross-sectional structures of a display device according to embodiments of the present disclosure are described together with the accompanying drawings.

[0193] Figure 32 This is a cross-sectional view of a display device according to an embodiment of the present disclosure. The same description of the components described above may be omitted.

[0194] Reference Figure 32 On the substrate 110 of the display device according to an embodiment of the present disclosure, a first conductive layer including a conductive pattern 111, a buffer layer 120, an active pattern 134, a first insulating layer 140, a second conductive layer including a gate electrode 154, a second insulating layer 160, a third insulating layer 180, a third conductive layer including a plurality of pixel electrodes 191, a fourth insulating layer 350, an emission layer 370, and a common electrode 270 may be sequentially disposed.

[0195] The first insulating layer 140 may be similar to the insulating pattern 144 or insulating patterns 144 and 145 described above (e.g., composed of the same or similar material as the insulating pattern 144 (or 144 and 145) described above). However, unlike insulating pattern 144 or insulating patterns 144 and 145, the first insulating layer 140 may have a shape formed on the entire surface (e.g., above) of the substrate 110 and partially removed (e.g., to provide through-holes). In some embodiments, the same structure as insulating pattern 144 or insulating patterns 144 and 145 may be provided instead of the first insulating layer 140.

[0196] Pixel electrode 191 can be electrically connected to a conductive region (e.g., drain region) of active pattern 134 through openings 89 in the second insulating layer 160 and the third insulating layer 180. For example, pixel electrode 191 can be electrically connected to a conductive region (e.g., drain region) of active pattern 134 through opening 89 and through an opening in the first insulating layer 140 that overlaps with opening 89.

[0197] The emitting layer 370 may include (for example) a light-emitting material that emits a first color of light, which may be blue light.

[0198] An encapsulation layer 380 comprising multiple insulating layers 381, 382, ​​and 383 may be disposed on the common electrode 270. Insulating layers 381 and 383 may comprise (e.g., are) inorganic insulating materials, and insulating layer 382 disposed between insulating layers 381 and 383 may comprise (e.g., are) organic insulating materials.

[0199] A filler layer 390, including filler, may be provided on the encapsulation layer 380. A cover layer 400 including (for example,) an insulating material, a plurality of color conversion layers 430a and 430b, and a transmissive layer 430c may be provided on the filler layer 390.

[0200] The transmissive layer 430c allows incident light to pass through (e.g., transmits incident light). For example, the transmissive layer 430c can transmit a first color light, which can be blue light. The transmissive layer 430c may include (e.g., is) a polymeric material that transmits the first color light. The region where the transmissive layer 430c is disposed may correspond to a region emitting blue light, and the transmissive layer 430c allows the incident first color light to pass through intact without separately including semiconductor nanocrystals. For example, the transmissive layer 430c may not include semiconductor nanocrystals.

[0201] Color conversion layers 430a and 430b may include different semiconductor nanocrystals. For example, first-color light incident on color conversion layer 430a may be converted into second-color light for emission by the semiconductor nanocrystals included in color conversion layer 430a. First-color light incident on color conversion layer 430b may be converted into third-color light for emission by the semiconductor nanocrystals included in color conversion layer 430b.

[0202] Semiconductor nanocrystals may include (for example, are) at least one selected from phosphors and quantum dot materials that convert incident first color light into second or third color light.

[0203] The nucleus of a quantum dot can be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0204] Group II-VI compounds may be selected from the group consisting of: binary compounds selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; and compounds selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, C Ternary compounds selected from the group consisting of dHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and quaternary compounds selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0205] Group III-V compounds may be selected from the group consisting of: binary compounds selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof; ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InNP, InNAs, InNSb, InPAs, InPSb and mixtures thereof; and quaternary compounds selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0206] Group IV-VI compounds can be selected from the group consisting of: binary compounds selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; ternary compounds selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; and quaternary compounds selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. Group IV elements can be selected from the group consisting of Si, Ge and mixtures thereof. Group IV compounds can be binary compounds selected from the group consisting of SiC, SiGe and mixtures thereof.

[0207] In this configuration, binary, ternary, or quaternary compounds can exist in the particles at a uniform concentration, or they can exist in the same particle divided into states where the concentration distributions are partially different. Furthermore, the color conversion layer can have a core / shell structure where one quantum dot surrounds another. The interface between the core and shell can have a concentration gradient, such that the concentration of the element present in the shell gradually decreases towards its center.

[0208] In some embodiments, the quantum dot may have a core-shell structure comprising a core containing the aforementioned nanocrystals and a shell surrounding the core. The shell of the quantum dot serves as a protective layer to prevent or reduce chemical degradation of the core and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be monolayer or multilayer. The interface between the core and shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center. Examples of shells for quantum dots include metal or nonmetal oxides, semiconductor compounds, or combinations thereof.

[0209] For example, the metal or non-metal oxide can be a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4 and NiO, or a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4 and CoMn2O4, but this disclosure is not limited thereto.

[0210] In addition, the semiconductor compound may be CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, or AlSb, but this disclosure is not limited thereto.

[0211] Quantum dots can have a full width at half maximum (FWHM) of an emission wavelength spectrum equal to or less than about 45 nm, preferably equal to or less than about 40 nm, and more preferably equal to or less than about 30 nm. Within this range, color purity or color reproducibility can be improved. Furthermore, because light emitted through quantum dots is emitted in all directions, the viewing angle of light can be improved.

[0212] Furthermore, quantum dots are not limited to having shapes commonly used in the art fields related to this disclosure, and quantum dots can have shapes such as those of nanoparticles having spherical, pyramidal, multi-armed, or cubic shapes, or can be nanotubes, nanowires, nanofibers, planar nanoparticles, etc.

[0213] Quantum dots can emit light in a color that can be controlled by their particle size, and therefore can have a variety of suitable colors such as blue, red and green.

[0214] An insulating layer 440 may be provided on multiple color conversion layers 430a and 430b and a transmission layer 430c, and multiple color filters 450a, 450b and 450c and a light-shielding member 460 may be provided (for example, multiple color filters 450a, 450b and 450c and a light-shielding member 460 may be provided on the insulating layer 440).

[0215] Color filter 450a can represent (e.g., correspond to) a second color of light, color filter 450b can represent (e.g., correspond to) a third color of light, and color filter 450c can represent (e.g., correspond to) a first color of light.

[0216] The light-shielding member 460 can be disposed between adjacent color filters 450a, 450b and 450c.

[0217] A substrate 210 may be disposed on multiple color filters 450a, 450b, and 450c and a light-shielding member 460. For example, multiple color conversion layers 430a and 430b and multiple color filters 450a, 450b, and 450c may be disposed between substrate 110 and substrate 210.

[0218] According to another embodiment of this disclosure, the emitting layer 370 may include quantum dots to replace the plurality of color conversion layers 430a and 430b and the transmissive layer 430c. For example, a display device may include quantum dots in the emitting layer 370 to replace the plurality of color conversion layers 430a and 430b and the transmissive layer 430c.

[0219] While this disclosure has been described in conjunction with the disclosed embodiments, it will be understood that this disclosure is not limited to the disclosed embodiments. Rather, this disclosure is intended to cover various suitable modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

[0220] Description of reference numerals in the attached figures

[0221] 50, 51a, 52a, 53: Mask patterns

[0222] 110, 210: Base

[0223] 111: Conductive pattern

[0224] 120: Buffer layer

[0225] 130: Semiconductor layer

[0226] 130a, 130b, 130c, 134: Active patterns

[0227] 55a, 60a, 60b, 60c, 60d, 61a, 61b, 62, 63, 64a, 64b, 64c, 64d, 65, 66, 68, 68a, 68b, 81, 82, 89, 130H, 355: Open

[0228] 131: Semiconductor Pattern

[0229] 132a, 132b, 132c: Side surfaces

[0230] 133a, 133b, 133c: Source regions

[0231] 134a, 134b, 134c: Channel areas

[0232] 135a, 135b, 135c: Drain region

[0233] 140, 160, 180, 350, 381, 382, ​​440: Insulation layer

[0234] 144, 145: Insulation patterns

[0235] 151, 152: Scan lines

[0236] 154a, 154b, 154c: Gate electrodes

[0237] 155: Drive gate electrode

[0238] 170: Common voltage line

[0239] 171a, 171b, 171c: Data cables

[0240] 172: Drive voltage line

[0241] 173: Initialize voltage lines

[0242] 174, 175, 176, 178, 191d: Connecting components

[0243] 191, 191a, 191b, 191c: Pixel electrodes

[0244] 270: Common Electrode

[0245] 370: Launch Layer

[0246] 380: Encapsulation layer

Claims

1. A display device, wherein, The display device includes: Base; A first conductive layer is located on the substrate, and the first conductive layer includes conductive patterns, voltage lines and data lines that are separated from each other; A first insulating layer is located on the first conductive layer; The first active pattern and the second active pattern are located on the first insulating layer, and the first active pattern and the second active pattern include semiconductor materials; A second insulating layer is located on the first active pattern and the second active pattern; and A second conductive layer is located on the second insulating layer. The second conductive layer includes a pixel electrode, a first connecting member, and a second connecting member. The first insulating layer and the second insulating layer have a first opening that exposes the first conductive layer, and a second opening and a third opening that are spaced apart from each other. The pixel electrode contacts both the top surface of the conductive pattern in the first conductive layer and the first side surface of the first active pattern through the first opening, so as to be simultaneously electrically connected to the conductive pattern in the first conductive layer and the first active pattern. The first connecting member is electrically connected to the top surface of the voltage line and the second side surface of the first active pattern through the second opening, and The second connecting member is electrically connected to the top surface of the data line and the side surface of the second active pattern through the third opening.

2. The display device according to claim 1, wherein, The display device further includes: A third insulating layer is located on the first active pattern and the second active pattern; and The third conductive layer is located on the third insulating layer. In the cross-sectional view, there are no other conductive layers between the second conductive layer and the third conductive layer.

3. The display device according to claim 2, wherein, The side surface of the third insulating layer is aligned with the side surface of the third conductive layer.

4. The display device according to claim 1, wherein: The conductive pattern overlaps with the first active pattern. The display device also includes an emission layer and a common electrode located on the pixel electrode.

5. The display device according to claim 1, wherein, The second side surface of the first active pattern is aligned with the side surface of the second opening, and the side surface of the second active pattern is aligned with the side surface of the third opening.

6. The display device according to claim 1, wherein, The first side surface of the first active pattern is aligned with the side surface of the first opening.

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