Bipolar junction transistor having a bias structure between a base region and an emitter region

Abstract

This application is entitled "Bipolar Junction Transistor with Bias Structure Between Base Region and Emitter Region". In the described example, a bipolar junction transistor (100) includes a substrate. An emitter region (114), a base region (112), and a collector region (110) are each formed in the substrate (120). A gate-type structure (102) is formed on the substrate between the base region (112) and the emitter region (114). A contact (130) is coupled to the gate-type structure (102), and the contact is adapted to be coupled to a source of DC voltage (VCC).

Description

[0001] Related applications

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 62 / 957880, filed January 7, 2020, entitled “BJT WITH BIASED POLY PLATE BETWEENEMITTER AND BASE REGIONS”, which is incorporated herein by reference in its entirety. Technical Field

[0003] This specification relates to a bipolar junction transistor having a bias structure located between the base region and the emitter region. Background Technology

[0004] A bipolar junction transistor (BJT) uses two junctions between two semiconductor types (n-type and p-type), which are regions within a single-material crystal. BJTs are used for signal amplification, switching in digital circuits (e.g., high-voltage switches), in radio frequency amplifiers, or for switching large currents. In such applications, BJTs are expected to exhibit relatively high Hfe (high transistor beta value) and linearity of collector current to base-emitter voltage (Vbe). Summary of the Invention

[0005] In the described example, a bipolar junction transistor includes a substrate. An emitter region, a base region, and a collector region are all formed in the substrate. A gate-type structure is formed on the substrate and located between the base region and the emitter region. Contacts are coupled to the gate-type structure and are adapted to be coupled to a source of DC voltage.

[0006] Another described example relates to a method of forming a transistor. The method includes forming a collector region having a first type of majority carriers in a semiconductor substrate. The method also includes forming a base region having a second type of majority carriers and forming a gate-type structure over the base region. The method further includes etching the gate-type structure to expose an emitter region of the base region and a base contact region of the base region surrounding the gate-type structure. The method also includes implanting a first dopant into the emitter region to form an emitter region having the first type of majority carriers. The method further includes implanting a second dopant into the base contact region of the base region to form a base contact region having the second type of majority carriers. Contacts are formed on or above the base contact region, emitter contact region, collector contact region, and gate-type structure. A gate connection is coupled to the contacts of the gate-type structure and adapted to be coupled to a source of DC voltage.

[0007] Another described example provides a method for forming an integrated circuit. The method includes implanting a dopant having a first conductivity type into a semiconductor substrate to form a first doped region having the first conductivity type. The method further includes implanting a dopant having a second conductivity type into the first doped region to form a second doped region having the second conductivity type within the first doped region. The method further includes forming a polysilicon gate-type structure over the first doped region, between a region of the second doped region and a contact region of the first doped region. The method further includes forming a gate connection coupled to the polysilicon gate-type structure, wherein the gate connection is electrically isolated from the first and second doped regions. Attached Figure Description

[0008] Figure 1 This is a cross-sectional view of an example of a bipolar junction transistor.

[0009] Figure 2 An example of an electronic current vector for the region beneath the gate structure coupled to a first DC voltage is depicted.

[0010] Figure 3 An example of an electronic current vector for the region beneath the gate structure coupled to a second DC voltage is depicted.

[0011] Figure 4 It is a graph that plots the β value (BETA) of a bipolar junction transistor as a function of the collector current per area.

[0012] Figure 5 It is a graph that plots the n-factor values ​​of a bipolar junction transistor as a function of the collector current per area.

[0013] Figure 6 This is a cross-sectional view of a portion of a bipolar junction transistor.

[0014] Figure 7 yes Figure 6 The donor doping curve below the gate structure of the bipolar junction transistor.

[0015] Figure 8 It plots the collector current as a function of area for different DC bias values. Figure 6 A graph showing the β values ​​of a bipolar junction transistor.

[0016] Figure 9 It plots the collector current as a function of area for different DC bias values. Figure 6 A graph showing the n-factor values ​​of bipolar junction transistors.

[0017] Figure 10 This is a flowchart depicting an example method for fabricating a bipolar junction transistor.

[0018] Figures 11-21 It is based on Figure 10 A cross-sectional view of a transistor fabricated using the method described above. Detailed Implementation

[0019] Exemplary embodiments relate to bipolar junction transistors (BJTs). These BJTs can exhibit an improved β value relative to the collector current (Ic) ideality. The BJT has emitter and base contact regions separated from each other by a gate structure. For example, the gate structure is formed of polysilicon and coupled to a terminal for applying a direct current (DC) bias voltage. The DC bias voltage applied to the gate structure reduces the lateral current flowing between the emitter and base regions in the BJT. The gate structure can be formed without the need for a dedicated base mask, which can be used to add a high dose of low-energy implant to the base region to increase the surface dopant between the emitter and base contact regions. As a result, the BJTs described herein can be fabricated at a lower cost than other methods and exhibit comparable or improved performance.

[0020] Figure 1 A cross-sectional view of a transistor 100 including a gate-type structure 102 between emitter contact region 104 and base contact region 106 is depicted. For example, the gate-type structure 102 is called a gate-type structure because it is formed over a gate oxide layer (not shown) in conjunction with the formation of the gate in a CMOS process. As a further example, the gate-type structure 102 includes a polysilicon gate material that can be doped with N-type or P-type dopant (e.g., by implantation or as-deposited during structure formation). The gate oxide electrically isolates the gate material from the base region 112. The gate-type structure 102 also surrounds the emitter region 114. In operation, the gate-type structure 102 can be coupled to a source of DC bias voltage (VDC) via one or more electrical connections 134. This contrasts with other methods that may couple a gate structure to an emitter. As described herein, using separate connections to bias the gate-type structure 102 with a DC voltage electrically isolated from the emitter region 114 reduces the lateral current flowing in the transistor between the emitter and base contact regions. As a result, transistor 100 is able to exhibit an improved transistor β value (Hfe) relative to the collector current (Ic) and an improved Ic relative to the Vbe ideality.

[0021] As a further example, the transistor is a BJT including a collector region 110, a base region 112, and an emitter region 114 formed in a substrate, such as a semiconductor substrate or an epitaxial layer that can be grown or deposited on a semiconductor. In some examples, transistor 100 is a PNP transistor, wherein the collector region 110 and emitter region 114 are P-type semiconductors, and the base region 112 is an N-type semiconductor. For a PNP transistor, the collector region 110 and emitter region 114 can be fabricated by implanting acceptor dopant into a silicon semiconductor, and the base region 112 can be fabricated by implanting donor dopant into a silicon semiconductor.

[0022] In other examples, the transistor is an NPN transistor, where the collector region 110 and emitter region 114 are N-type semiconductors, and the base region 112 is a P-type semiconductor. For an NPN transistor, the collector region 110 and emitter region 114 can be fabricated by implanting donor dopant into the silicon semiconductor, and the base region 112 can be fabricated by implanting acceptor dopant into the silicon semiconductor.

[0023] As a further example, the transistor is implemented as a BJT including a collector region 110. For example, dopant is implanted into the collector region 110 to form a well region 120, and dopant is implanted into the well region 120 to form a collector contact region 122. The collector contact region 122 can be formed by source-drain implantation or other methods. A shallow trench isolation (STI) region 124 can be formed between the collector contact region 122 and the base contact region 106 to provide electrical isolation.

[0024] A corresponding metal layer is provided over each contact area to form a collector contact 126, a base contact 128, a gate contact 130, and an emitter contact 132. The gate contact is electrically isolated from the emitter and base contacts, for example, by an insulating material (not shown) formed over the exposed portion of the transistor 100. Each contact 126, 128, 130, and 132 can be coupled to a separate terminal of an IC chip, which includes the transistor 100 and / or other circuitry integrated within the IC chip. Figure 1In one example, gate connector 134 couples the gate contact 130 of gate-type structure 102 to a source of DC voltage (schematically shown as VDC). For example, the source of DC voltage is a terminal of the IC chip implementing transistor 100. In one example, the DC voltage terminal may be coupled to an external DC voltage (VDC), which may exist, for example, on another IC chip or other external circuitry. In another example, the DC voltage terminal may be coupled to a DC voltage (VDC) inside the IC chip implementing transistor 100. For example, the DC voltage VDC may be provided by a voltage regulator, a battery, or other circuitry configured to provide DC voltage to DC voltage terminal 136. The DC voltage VDC may be a positive DC voltage or a negative DC voltage. The magnitude of the DC voltage at DC voltage terminal 136 may vary depending on the type and configuration of transistor 100 and desired performance characteristics, such as the relationship between the transistor's beta value and Ic, and the relationship between Ic and Vbe ideality. As described herein, a minimum positive or negative value of the DC voltage can be determined to operate the transistor within desired operating parameters (e.g., to reduce the side current in transistor 100), thereby achieving the desired performance.

[0025] For ease of explanation, Figure 1 The entire semiconductor substrate, which is part of the wafer, is not shown, in which other devices may be integrated with the exemplary transistor 100. As an example, the collector region 110 may be fabricated within a well region formed in a substrate (such as a semiconductor substrate or epitaxial layer), and shallow trench isolation (STI) regions may be present to isolate the transistor 100 from other devices (not shown). The semiconductor material on which the exemplary transistor 100 is fabricated may be obtained from crystalline silicon grown from a seed, or the semiconductor material may also include an epitaxial layer grown or deposited on the semiconductor substrate.

[0026] Figure 2 and Figure 3 This is a cross-sectional view of a portion of transistor 200, including a base region 202 of the substrate located beneath a gate-type structure 204 between the emitter and base contact regions. For example, this transistor corresponds to transistor 100, and the gate-type structure 204 corresponds to... Figure 1 The gate structure 102. Figure 2 and Figure 3 Each of these figures further illustrates a vector of electronic current in the base region 202 of a transistor 200 having Vbe = 0.6V and Vce = 2.5V, for different bias voltages applied to the gate-type structure 204.

[0027] exist Figure 2 and Figure 3In one example, the gate structure 204 includes a gate oxide 206 formed over the base region 202. In some examples, the gate oxide 206 may include silicon dioxide (SiO2), such as a high-quality oxide thermally grown on a semiconductor on which the transistor 200 is fabricated. The gate structure 204 also includes a gate material 208 formed over the gate oxide 206. The gate material 208 may include polysilicon and may be doped with N-type or P-type dopants. For example, the polysilicon material may be formed using a complementary metal-oxide-semiconductor (CMOS) process. This CMOS process may be further used to form well regions in the base and collector regions.

[0028] Metal contacts 210 are formed over the gate material, and an additional oxide layer 212 may be formed over the gate structure 204 and other exposed portions of the transistor 200. For example, the metal contacts 210 may be silicide, which is deposited and annealed to form the contacts of the gate structure 204. Connectors 214 may be configured to couple the metal contacts 210 to a source of DC voltage, which... Figure 2 In the example, it is 0V and Figure 3 In the example, it is -1V.

[0029] The combination of gate oxide 206, gate material 208, and contact 210 defines a gate structure 204 disposed between the emitter region and the base contact region. When the gate structure 204 is biased by a suitable DC voltage source (VDC), this gate structure increases the hole concentration near the surface of the base region and provides an additional barrier for electrons injected laterally from the emitter region. This results in... Figure 2 Compared to the case shown where the bias is 0V, when the gate structure is as shown... Figure 3 As shown, when biased to -1V, the electron flow within transistor 200 is more vertical.

[0030] Figure 4 Chart 400 shows graphs 402, 404, 406, 408, 410, and 412, which are plots of the transistor β value applied to the gate structure (NPN bipolar junction transistor). Figure 1 Gate structure 102 or Figures 2-3The gate-type structure 204) is given multiple different DC bias voltages (VDC) as a function of the collector current (Ic) per area. Specifically, graph 402 shows the β value when VDC = 0V, graph 404 shows the β value when VDC = -0.5V, graph 406 shows the β value when VDC = -1V, graph 408 shows the β value when VDC = -2V, graph 410 shows the β value when VDC = +0.15V, and graph 412 shows the β value when VDC = +0.45V. Therefore, for an NPN transistor, graphs 404, 406, and 408 show that the relationship between the β value and Ic becomes more ideal when a negative DC bias is applied to the gate structure.

[0031] Figure 5 Chart 500 includes curves 502, 504, 506, 508, 510, and 512 of the NPN BJT as a function of Ic per unit area (representing the ideality of Ic). Similar to... Figure 4 The graph shows that, compared to 0 bias and positive DC bias as shown in graphs 502, 510 and 512, when a negative DC bias is applied to the gate structure as shown in graphs 504, 506 and 508, the Ic ideality factor exhibits good linearity.

[0032] Figure 6 This is a cross-sectional view of a portion of transistor 600. Figure 6 In the example, transistor 600 is a high-gain PNP BJT including a dedicated N-type base region 602 formed within a P-type collector region 604. For example, collector region 604 includes a P-type epitaxial (Pepi) layer in which N-type dopants are implanted to form base region 602. Transistor 600 also includes an N-well region 606 surrounding base contact region 608, which can be formed by implanting N-type surface dopants around the base contact region using a CMOS process. Emitter region 610 is formed (e.g., by implanting P-type surface dopants) in base region 602. Gate structure 612 is formed between base contact region 608 and emitter region 610. For example, gate structure 612 includes a polysilicon layer formed over gate oxide, and the polysilicon can be doped (e.g., doped with N-type or P-type dopants) or undoped, and can be formed by incorporating the gates of one or more field-effect transistors using a CMOS process. Metal contacts 614, 616, and 618 are formed over each of the emitter, base, and gate structures, respectively. An oxide layer 620 may be further formed over the metal and the exposed surface layer of the transistor 600. The oxide layer 620 (e.g., SiO2) electrically isolates the metal contacts 614, 616, and 618 and provides support for connections to the metal contacts 618 fabricated in vias formed through the oxide.

[0033] Figure 7 It is along in Figure 6 The vertical donor doping curve 700 is obtained from line 622 extending along the Y-axis direction below the gate structure 612 of the PNP transistor 600. (See graph 700.) Figure 7 As shown, the doping is low near the surface and increases through the N-base of base region 602, then decreases in collector region 604. By using a separate contact coupled to gate contact 618 and applying a bias to polysilicon gate structure 612, Hfe (transistor β value) can be increased relative to collector current (Ic) per unit area, thereby improving Hfe linearity and Ic ideality compared to BJTs without independently biased gate structures.

[0034] Figure 8 This is chart 800, which includes graphs 802, 804, 806, 808, 810, and 812 showing transistor β values ​​applied to the gate structure ( Figure 1 Gate structure 102 or Figure 6 The β values ​​of the gate structure 612 of the PNP bipolar junction transistor 600 are given as a function of the collector current (Ic) per area, with respect to various DC bias voltages (VDC). Specifically, graph 802 shows the β value when VDC = 0V, graph 804 shows the β value when VDC = -0.7V, graph 806 shows the β value when VDC = -0.8V, graph 808 shows the β value when VDC = -0.9V, graph 810 shows the β value when VDC = -1.5V, graph 812 shows the β value when VDC = -2.0V, and graph 814 shows the β value when VDC = -5.0V. Therefore, for the PNP transistor 600, graphs 810, 812, and 814 show that the relationship between the β value and Ic becomes more favorable when a sufficiently negative DC bias of -1.5V or less (more negative) is applied to the gate structure 612.

[0035] Figure 9 Chart 900 is a graph of NPN BJT n-factor values ​​(representing the ideality of Ic) as a function of Ic per unit area, including graphs 902, 904, 906, 908, 910, 912, and 914. Similar to... Figure 8 The graph shows that, compared to graphs 904, 906, and 908, the IC ideality factor exhibits good linearity when a negative DC bias of -1.5V or less is applied to the gate structure 612, as shown in graphs 910, 912, and 914. When IC ideality is the desired transistor parameter but the transistor β value is not a concern, a 0V bias can be applied to the gate structure, as shown in graph 902, which provides a reasonable ideality factor compared to a negative bias. However, as... Figure 8As shown, a 0V bias will result in a low transistor bias, which may be unsuitable for some applications. Therefore, the bias can be set for a given transistor based on its specific application requirements and desired operating parameters.

[0036] Given the previously described structural and functional features, the example method will refer to... Figure 10 To be better understood. Figure 10 This is a flowchart depicting an example method 1000 for fabricating transistors such as BJTs. Method 1000 can be used to fabricate any structure disclosed herein, including... Figure 1 Structure 100 Figure 2 and Figure 3 Structure 200 or Figure 6 The structure is 600. Although for illustrative purposes... Figure 10 The example methods are shown and described as executing sequentially, but the method is not limited to the order illustrated. The illustrations will be used to explain... Figures 11-21 To describe Figure 10 Method 1000 is used to illustrate an example of the structure that runs through Method 1000.

[0037] Method 1000 begins at 1002, where a dopant is implanted to form a collector region. For example, as... Figure 11 As shown, dopant 1102 is implanted into the semiconductor substrate or epitaxial layer 1100 to form a collector region having a first type of majority carriers, which can be N-type or P-type depending on the type of BJT being manufactured. At 1004, for example at... Figure 12 As shown, dopant 1110 is injected into collector region 1104 to form base region 1112 with a second type (P-type or N-type) majority carriers.

[0038] At position 1006, a gate oxide is formed on the semiconductor. For example, as... Figure 13 As shown at 1114, the gate oxide can be a layer of SiO2 thermally grown through thermal oxidation of a silicon semiconductor substrate or epitaxial layer 1100. At 1008, a gate-type structure is formed on the oxide. For example, as... Figure 14 As shown, the gate structure 1116 can be a layer of polysilicon material deposited over the oxide 1114, for example, formed in a CMOS process by chemical vapor deposition of silane. In some examples, polysilicon doping can also be performed during the deposition process, for example by adding phosphine, arsenic trihydrogenate, or diborane depending on the desired doping type (N-type and / or P-type).

[0039] At 1010, the gate material (e.g., polysilicon) and oxide are etched to form the exposed emitter region. For example, as... Figure 15As shown, the etching (at 1010) forms a gate-type structure 1120 surrounding the emitter region 1122 of the base region and exposes the base contact region 1123 in the base region 1112. Therefore, the gate structure (e.g., polysilicon and oxide) after the etching at 1010 can act as a hard mask for defining the emitter region and other regions for dopant implantation. At 1012, dopant is implanted to form the emitter region. For example, as... Figure 16 As shown, the gate structure 1120 is used as a mask for implanting dopant 1124 to form an emitter region 1126 with a first type of majority carriers (e.g., the same type as the collector region) within the base region 1112. At 1014, dopant is implanted to form a base contact region. For example, as... Figure 17 As shown, a dopant is implanted into the base contact region to form a base contact region 1130 with a majority carrier of the second type. Steps 1016 and 1018 form the collector region of the transistor. For example, as... Figure 18 As shown, dopant 1132 is injected into collector region 1104 to form well region 1134 having a first type of majority carriers, and dopant is injected into well region to form collector contact region 1136 having a first type of majority carriers, thereby contacting the collector region.

[0040] At 1020, metal is deposited and a contact is formed. For example, as... Figure 19 As shown, a metal layer 1140 is deposited over the semiconductor as part of the back end of line (BEOL) process. The metal 1140 can be annealed to form silicide. The metal layer 1140 can then be etched to form metal contacts, namely emitter contact 1142, base contact 1144, collector contact 1146, and gate contact 1148, as shown. Figure 20 As shown. Additional BEOL processing can be performed to form corresponding connectors (e.g., interconnecting wires) 1152, 1154, 1156, and 1158 isolated by dielectric layer 1160 (e.g., SiO2, silicate glass, silicon carbide, etc.), as... Figure 21 As shown.

[0041] In method 1000, prior to dopant implantation, a photoresist film is deposited and exposed to radiation through one or more photomasks, followed by baking and etching to define a pattern on the semiconductor for dopant implantation. However, for ease of explanation, such steps are not included. Figure 10 and Figures 11-21In method 1000, as described herein, the gate contact 1158 can be coupled to a source of DC bias voltage, such as a terminal. For example, this terminal can be coupled to a DC voltage generated by a circuit system located on the same IC die as the transistor or by a circuit system external to the IC. In operation, the DC bias voltage applied to the gate contact from the source of the DC bias voltage reduces the lateral current between the emitter and base regions. This DC bias voltage can be set according to the application requirements of the BJT and the desired operating characteristics (e.g., transistor β value and IC ideality and linearity).

[0042] In this application, the terms "coupled" or "coupled" refer to an indirect or direct connection. Therefore, if a first device is coupled to a second device, the connection can be either a direct connection or an indirect connection via other devices and connectors. For example, if device A generates a signal to control device B to perform an action, in the first example, device A is coupled to device B; or in the second example, if intermediate component C does not substantially alter the functional relationship between device A and device B, device A is coupled to device B via intermediate component C, such that device A controls device B via a control signal generated by device A.

[0043] The expression "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.

[0044] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are possible.

Claims

1. A bipolar junction transistor (BJT), comprising: Substrate; The emitter region is formed in the substrate; A base region is formed in the substrate and includes a base contact region; A collector region is formed in the substrate and includes a collector contact region, wherein the base contact region is disposed between the collector contact region and the emitter region; A gate-type structure is formed on the substrate between the base contact region and the emitter region; as well as Contacts coupled to the gate structure, the contacts being adapted to couple to a source of DC voltage.

2. The BJT of claim 1, further comprising a connector coupled to the contact and a DC voltage source terminal, the connector being adapted to provide the DC voltage to the gate structure through the contact.

3. The BJT according to claim 2, wherein the DC voltage source terminal is adapted to provide a negative DC voltage or a positive DC voltage.

4. The BJT according to claim 2, wherein the gate structure surrounds the emitter region.

5. The BJT according to claim 2, wherein the BJT is an NPN BJT or a PNP BJT.

6. The BJT of claim 1, further comprising a gate oxide layer located above the surface of the substrate between the base region and the emitter region, the gate-type structure being formed above the gate oxide layer.

7. The BJT of claim 6, further comprising a metal layer formed over the gate structure, the contacts being coupled to the metal layer.

8. The BJT according to claim 1, wherein the gate structure comprises polycrystalline silicon material.

9. The BJT of claim 2, wherein the connector is electrically isolated from the emitter region and the base region.

10. A method of forming a transistor, the method comprising: A collector region having a first type of majority carriers is formed in a semiconductor substrate; Formation of a base region with a second type of majority carriers; A gate material is formed above the base region; The gate material is etched to form a gate-type structure, thereby exposing the emitter region of the base region and the base contact region of the base region, the base contact region surrounding the gate-type structure, and the gate-type structure surrounding the emitter region; A first dopant is injected into the emitter region to form an emitter region having majority carriers of the first type; A second dopant is implanted into the base contact region of the base region to form a base contact region having the second type of majority carriers; Contacts are formed on or above the base contact region, the emitter region, the collector contact region, and the gate structure; A gate connector is formed, which is coupled to the contact of the gate structure and adapted to be coupled to a source of DC voltage.

11. The method of claim 10, wherein forming the gate structure further comprises: A gate oxide is formed over the semiconductor substrate; The gate material is formed on the gate oxide, and the gate material and the gate oxide are etched to form the gate structure.

12. The method of claim 11, wherein the gate material comprises polycrystalline silicon.

13. The method of claim 11, wherein the gate connection is isolated from the emitter region and the base region.

14. The method of claim 10, wherein the DC voltage source terminal is coupled to the gate structure via the gate connector.

15. The method of claim 14, wherein the DC voltage source terminal is adapted to provide a negative DC voltage or a positive DC voltage.

16. The method of claim 10, wherein the first type is N-type and the second type is P-type.

17. The method of claim 10, wherein the first type is type P and the second type is type N.

18. The method of claim 10, wherein forming the contact further comprises: Deposit metal over the exposed portion of the semiconductor substrate and the gate structure; and The semiconductor substrate is annealed to form silicide on or above the exposed portion of the semiconductor substrate and the gate structure.

19. A method for forming an integrated circuit, comprising: A dopant having a first conductivity type is implanted into a semiconductor substrate to form a first doped region having the first conductivity type; Dopants with different second conductivity types are implanted into the first doped region to form a second doped region having the second conductivity type in the first doped region; A polysilicon gate structure is formed above a first region of the second doped region, between a second region of the second doped region and a contact region of the second doped region. The contact region of the second doped region is located between the second region of the second doped region and the contact region of the first doped region. The contact region of the second doped region surrounds the gate structure. The second region of the second doped region is adapted to form an emitter region, and the contact region of the second doped region is adapted to form a base contact region. and A gate connector is formed coupled to the polysilicon gate structure, wherein the gate connector is electrically isolated from the first doped region and the second doped region.

20. The method of claim 19, wherein forming the polysilicon gate structure further comprises: A gate oxide is formed over the semiconductor substrate; A polysilicon material is formed on the gate oxide, and the polysilicon material and the gate oxide are etched to form the polysilicon gate structure surrounding the region of the second doped region; and A metal gate contact is formed on or above the polycrystalline silicon material, and the gate connector is coupled to the metal gate contact.

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