Vertical gate field effect transistor device and method of forming the same

Abstract

In some embodiments, the present disclosure relates to a vertical gate field effect transistor device having a semiconductor substrate including a front side and a back side. On the front side of the semiconductor substrate are a first source / drain region and a second source / drain region. The gate electrode is configured on the front side of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is configured above the front side of the semiconductor substrate and between the first source / drain region and the second source / drain region. The first vertical portion extends from the front side of the semiconductor substrate toward the back side of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the front side of the semiconductor substrate toward the back side of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by the channel region of the substrate.

Description

Technical Field

[0001] The embodiments of the present invention relate to a vertical gate field effect transistor device and a method for forming the same. Background Art

[0002] The integrated circuit (IC) manufacturing industry has experienced exponential growth over the past few decades. As integrated circuits have evolved, functional density (e.g., the number of interconnected devices per chip area) has increased while feature size has decreased. One advancement in the semiconductor industry's scaling down of semiconductor devices has been the development of fin field-effect transistors (finFETs). While finFETs have several advantages over traditional planar transistors (e.g., reduced power consumption, smaller feature size, reduced noise, etc.), this comes with the added bonus of their higher manufacturing costs. Therefore, alternative options and / or methods for replacing finFETs are being investigated to reduce manufacturing costs. Summary of the invention

[0003] In some embodiments, the present disclosure relates to a vertical gate field effect transistor device, comprising: a semiconductor substrate, comprising a front side and a back side; a first source / drain region and a second source / drain region, located on the front side of the semiconductor substrate; a gate electrode structure, configured on the front side of the semiconductor substrate and comprising: a horizontal portion, configured on the front side of the semiconductor substrate and between the first source / drain region and the second source / drain region; a first vertical portion, extending in a first direction from the front side of the semiconductor substrate toward the back side of the semiconductor substrate and contacting the horizontal portion of the gate electrode structure; and a second vertical portion, extending in the first direction from the front side of the semiconductor substrate toward the back side of the semiconductor substrate, contacting the horizontal portion of the gate electrode structure, and separated from the first vertical portion by a channel region of the semiconductor substrate.

[0004] In other embodiments, the present disclosure relates to a vertical gate field effect transistor device, comprising: a semiconductor substrate, comprising a front side and a back side; a first source / drain region, disposed in the semiconductor substrate; a second source / drain region, disposed in the semiconductor substrate and spaced apart from the first source / drain region; a gate electrode structure, configured above the first source / drain region and the second source / drain region and comprising: a horizontal portion, extending above the front side of the semiconductor substrate; a first vertical portion, extending from the front side of the semiconductor substrate to a first depth below the front side of the semiconductor substrate; and a second vertical portion, extending from the front side of the semiconductor substrate to a second depth below the front side of the semiconductor substrate; and an isolation structure, located in the semiconductor substrate and surrounding the gate electrode structure.

[0005] In some other embodiments, the present disclosure relates to a method for forming a vertical gate field effect transistor device, comprising: forming a first masking structure on a substrate, wherein the first masking structure comprises a first opening and a second opening, the first opening and the second opening extending parallel to each other; removing a portion of the substrate directly below the first opening and the second opening; removing the first masking structure; forming a gate dielectric layer on the substrate; forming a gate electrode material on the gate dielectric layer; removing an outer portion of the gate electrode material to form a gate electrode structure comprising a horizontal portion, a first vertical portion and a second vertical portion; forming a first source / drain region and a second source / drain region in the substrate; and forming an isolation structure located within the substrate and surrounding the first source / drain region, the second source / drain region and the gate electrode structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A to Figure 1C Various views of some embodiments of an integrated chip with a gate electrode structure including a first vertical portion and a second vertical portion connected by a horizontal portion are shown.

[0008] Figure 2A to Figure 2C Various views of some embodiments of an integrated chip having a gate electrode structure including a horizontal portion disposed over a vertical portion, wherein the vertical portion of the gate electrode structure is a continuously connected ring-like structure.

[0009] Figure 3Cross-sectional views of some embodiments of image sensors having a gate electrode structure including a first vertical portion and a second vertical portion connected by a horizontal portion are shown.

[0010] Figure 4 Cross-sectional views of some embodiments of image sensors having a gate electrode structure including a horizontal portion disposed over a vertical portion, wherein the vertical portion of the gate electrode structure is a continuously connected ring-like structure.

[0011] Figure 5 A circuit diagram of some embodiments of an image sensor including four transistors is shown.

[0012] FIG. 6A to FIG. 16C Shown is formed with Figure 1A to Figure 1C Various views of some embodiments of methods for integrating chips with gate electrode structures are shown.

[0013] Fig.17 Shown corresponding to FIG. 6A to FIG. 16C Flowcharts of some embodiments of the illustrated method.

[0014] FIG. 18A to FIG. 22C Shown is formed with Figure 2A to Figure 2C Various views of some embodiments of methods for integrating chips with gate electrode structures are shown.

[0015] Fig.23 Shown corresponding to FIG. 18A to FIG. 22C Flowcharts of some embodiments of the illustrated method. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0017] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0018] In some embodiments, a planar metal oxide semiconductor field effect transistor (MOSFET) includes a planar gate electrode disposed above a channel region of a substrate so that the planar gate electrode contacts the top surface of the channel region of the substrate. In other embodiments, in order to enhance control of the transistor and reduce space, a fin field effect transistor (finFET) is used in an electronic device instead of a planar MOSFET. A finFET includes a gate electrode overlying a fin protruding from a substrate and contacting the fin protruding from the substrate. The gate electrode of the finFET covers three surfaces of the channel region, which helps the finFET provide higher control and lower noise compared to a planar MOSFET. However, due to, for example, the formation of the fin, the finFET may have more processing steps, and therefore may have a higher production cost than a planar MOSFET. Therefore, when determining which type of transistor to use in an electronic device, the overall cost and performance requirements are considered. For example, in a complementary metal oxide semiconductor (CMOS) image sensor, low noise is an important factor in device reliability. However, in a four-transistor CMOS image sensor circuit, the cost of using finFETs in a CMOS image sensor is high.

[0019] Various embodiments of the present disclosure provide a vertical gate transistor having a gate electrode structure, the gate electrode structure comprising: a horizontal portion, arranged on the front side of a substrate; and a first vertical portion and a second vertical portion, extending from the horizontal portion toward the back side of the substrate. In some embodiments, a channel region of the substrate is arranged below the horizontal portion of the gate electrode structure and between the first vertical portion and the second vertical portion. Therefore, at least three surfaces of the channel region are surrounded by the gate electrode structure, thereby reducing noise and enhancing device control. Advantageously, compared to the process of forming a planar MOSFET, an additional masking structure and removal step are required to form the gate electrode structure. Therefore, a vertical gate transistor having a gate electrode structure including a horizontal portion and a first vertical portion and a second vertical portion can increase the reliability of electronic devices without significantly increasing manufacturing costs.

[0020] Figure 1A A cross-sectional view 100A of some embodiments of an integrated chip is shown that includes a gate electrode structure having a horizontal portion and a vertical portion.

[0021] The integrated chip in the cross-sectional view 100A includes a gate electrode structure 108, which is located within the dielectric structure 106 and is disposed on the front side 102f of the substrate 102. The dielectric structure 106 can be disposed on the substrate 102 and contact the substrate 102. The gate dielectric layer 110 separates the gate electrode structure 108 from the substrate 102 so that the gate electrode structure 108 does not contact the substrate 102. In some embodiments, the substrate 102 may include, for example, a semiconductor material having a first doping type (e.g., Si, Ge, SiGe, etc.). In other embodiments (not shown), the substrate 102 may include a doped well region located below the gate electrode structure 108 and having the first doping type.

[0022] In some embodiments, from the cross-sectional view 100A, the gate electrode structure 108 may include: a horizontal portion 108a disposed on the front side 102f of the substrate 102; a first vertical portion 108b directly below the horizontal portion 108a and extending from the front side 102f of the substrate 102 toward the back side 102b of the substrate 102; and a second vertical portion 108c directly below the horizontal portion 108a and extending from the front side 102f of the substrate 102 toward the back side 102b of the substrate 102. In some embodiments, the first vertical portion 108b and the second vertical portion 108c directly contact the horizontal portion 108a of the gate electrode structure 108. In addition, in some embodiments, the first vertical portion 108b and the second vertical portion 108c are completely and directly below the horizontal portion 108a of the gate electrode structure 108. From the cross-sectional view 100A, the gate dielectric layer 110 may be a continuously connected layer that separates the horizontal portion 108 a , the first vertical portion 108 b , and the second vertical portion 108 c of the gate electrode structure 108 from the substrate 102 .

[0023] In some embodiments, the sidewall spacer structure 112 surrounds the outermost sidewall of the gate electrode structure 108. The sidewall spacer structure 112 may include a dielectric material such as, for example, silicon nitride, silicon dioxide, silicon carbide, silicon oxynitride, etc. In some embodiments, the sidewall spacer structure 112 is disposed beside the gate dielectric layer 110 and does not directly overlie the gate dielectric layer 110, while in other embodiments, the sidewall spacer structure 112 may directly overlie the gate dielectric layer 110. In some embodiments, the sidewall spacer structure 112 may provide structural protection and / or electrical protection to the gate electrode structure 108.

[0024] In some embodiments, the trench isolation structure 104 is disposed within the substrate 102 and extends from the front side 102f of the substrate 102 toward the back side 102b of the substrate 102. In some embodiments, the trench isolation structure 104 includes a first doping type, while in other embodiments, the trench isolation structure 104 includes a second doping type different from the first doping type. In still other embodiments, the trench isolation structure 104 is undoped. In some embodiments, the trench isolation structure 104 is a shallow trench isolation (STI) structure or includes a shallow trench isolation (STI) structure and therefore does not extend through the substrate 102 to the back side 102b of the substrate 102. In some embodiments, the trench isolation structure 104 is directly below the sidewall spacer structure 112 in the cross-sectional view 100A. In other embodiments, the trench isolation structure 104 may be spaced apart from the gate electrode structure 108 and the gate dielectric layer 110 by, for example, the substrate 102. Furthermore, in some embodiments, the trench isolation structure 104 is disposed beside the outermost sidewalls of the first vertical portion 108 b and the second vertical portion 108 c of the gate electrode structure 108 .

[0025] In some embodiments, when the gate electrode structure 108 is “turned on,” a voltage or current is applied to the gate electrode structure 108 to push away majority charge carriers so that minority charge carriers remain in the channel region 114 of the substrate 102. For example, if the substrate 102 is p-type, when a positive voltage is applied to the gate electrode structure 108, positive charge carriers (e.g., holes) leave the gate electrode structure 108 and migrate toward the back side 102b of the substrate 102 so that negative charge carriers (e.g., electrons) remain in the channel region 114. The trench isolation structure 104 can prevent or mitigate current leakage through the channel region 114. Due to the first vertical portion 108b and the second vertical portion 108c, the channel region 114 is larger than if the gate electrode structure 108 only includes the horizontal portion 108a. Therefore, the gate electrode structure 108 including the horizontal portion 108a, the first vertical portion 108b and the second vertical portion 108c can reduce power consumption and noise, thereby enhancing the control and reliability of the overall device. In addition, it should be understood that Figure 1A Other changes in structure and / or materials are also within the scope of the present disclosure.

[0026] Figure 1B Show Figure 1A A top view 100B of some embodiments of an integrated chip including a gate electrode structure having a horizontal portion and a vertical portion. In some embodiments, the top view 100B corresponds to Figure 1A A top perspective view of the cross-sectional view 100A, which does not include Figure 1AIn some embodiments, Figure 1B The section line AA' corresponds to Figure 1A Cross-sectional view 100A.

[0027] In some embodiments, the trench isolation structure 104 is a continuously connected ring structure that completely surrounds the gate electrode structure 108. In some embodiments, the gate electrode structure 108 partially overlaps the trench isolation structure 104. In some embodiments, from the top view 100B, the first vertical portion 108b and the second vertical portion 108c of the gate electrode structure 108 are covered by the horizontal portion 108a of the gate electrode structure 108. Therefore, in the top view 100B, the first vertical portion 108b and the second vertical portion 108c shown with dotted lines are understood to be behind the horizontal portion 108a of the gate electrode structure 108.

[0028] In some embodiments, a first source / drain region 116 is disposed on the first side 108f of the gate electrode structure 108, and a second source / drain region 118 is disposed on the second side 108s of the gate electrode structure 108. The first source / drain region 116, the second source / drain region 118, and the gate electrode structure 108 are part of the vertical gate transistor 101. In some embodiments, the trench isolation structure 104 also surrounds the first source / drain region 116 and the second source / drain region 118. The first source / drain region 116 and the second source / drain region 118 have a channel region ( Figure 1A For example, in some embodiments, the channel region ( Figure 1A 114) is p-type, and the first source / drain region 116 and the second source / drain region 118 are n-type. Therefore, in some embodiments, when the vertical gate transistor 101 is "on", negative mobile charge carriers (e.g., electrons) can pass through the channel region ( Figure 1A The trench isolation structure 104 may extend from the first source / drain region 116 to the second source / drain region 118. The trench isolation structure 104 may also surround the first source / drain region 116 and the second source / drain region 118 to prevent leakage of current traveling between the first source / drain region 116 and the second source / drain region 118. It should be understood that other isolation structures are also within the scope of the present disclosure.

[0029] Figure 1C A cross-sectional view 100C showing some embodiments of an integrated chip including a chip corresponding to Figure 1B The vertical gate transistor 101 is shown by the cross section line CC′.

[0030] In some embodiments, from the perspective of the cross-sectional view 100C, the first vertical portion and the second vertical portion ( Figure 1A In addition, when the vertical gate transistor 101 is turned “on”, mobile charge carriers flow between the first source / drain region 116 and the second source / drain region 118 through the channel region 114. It should be understood that in Figure 1A In the cross-sectional view 100A of FIG. 1 , mobile charge carriers will travel in the direction of entering or leaving the page in the channel region 114. Figure 1A From the cross-sectional view 100A, due to the first vertical portion and the second vertical portion (108b, 108c) of the gate electrode structure 108, the channel region 114 is larger than Figure 1C Furthermore, although not shown, in some embodiments, a contact via is coupled to each of the first source / drain region 116 , the gate electrode structure 108 , and the second source / drain region 118 to operate the vertical gate transistor 101 .

[0031] Figure 2A A cross-sectional view 200A illustrates some alternative embodiments of an integrated chip having a vertical gate transistor including a gate electrode structure having a horizontal portion and a vertical portion.

[0032] In some embodiments, the gate electrode structure 108 is surrounded by a heavily doped region 204 of the substrate 102. In some embodiments, the heavily doped region 204 extends completely through the substrate 102, or in other words, extends from the front side 102f of the substrate 102 to the back side 102b of the substrate 102. In some embodiments, the heavily doped region 204 includes a first doping type and includes the same material as the substrate 102. In addition, in some embodiments, the heavily doped region 204 of the substrate 102 has a higher concentration of the first doping type than other portions of the substrate 102. The heavily doped region 204 is configured to prevent current from leaking from the vertical gate transistor during operation. It should be understood that other isolation structures other than the heavily doped region 204 (e.g., a shallow trench isolation structure or a backside deep trench isolation structure surrounding the gate electrode structure 108 of FIG. 2A) are also within the scope of the present disclosure.

[0033] In some embodiments, the trench isolation structure ( Figure 1A Compared to the heavily doped region 104, the heavily doped region 204 may be more effective in preventing current leakage during operation; however, in some embodiments, manufacturing the heavily doped region 204 may have advantages over manufacturing the trench isolation structure ( Figure 1A 104) High cost.

[0034] In some embodiments, the inner sidewall of the first vertical portion 108b of the gate electrode structure 108 and the inner sidewall of the second vertical portion 108c may be spaced apart from each other by a first distance d1. In some embodiments, the first distance d1 may be in a range of, for example, approximately 1 nanometer and approximately 1000 nanometers. In some embodiments, the first vertical portion 108b and the second vertical portion 108c of the gate electrode structure 108 may each have a bottom surface at a second distance d2 from the front side 102f of the substrate 102. In some embodiments, the second distance d2 may be in a range of, for example, approximately 1 nanometer and approximately 1 micrometer. In addition, in some embodiments, each of the first vertical portion 108b and the second vertical portion 108c has a width equal to a third distance d3. In some embodiments, the third distance d3 is in a range of, for example, approximately 10 nanometers and approximately 1 micrometer. In some embodiments, the horizontal portion 108a of the gate electrode structure 108 may have a height equal to a fourth distance d4 measured from the front side 102f of the substrate to the top surface of the horizontal portion 108a of the gate electrode structure 108. In some embodiments, the fourth distance d4 is in a range of, for example, approximately 20 nanometers and approximately 400 nanometers. In some embodiments, the measurement of the first distance d1 to the fourth distance d4 may include the gate dielectric layer 110. In some embodiments, the thickness of the gate dielectric layer 110 is in a range of, for example, approximately 1 nanometer and approximately 50 nanometers. It should be understood that other values ​​of the first distance d1 to the fourth distance d4 are also within the scope of the present disclosure.

[0035] Figure 2B Show Figure 1B A top view 200B of some embodiments of an integrated chip including a gate electrode structure having a horizontal portion and a vertical portion. In some embodiments, the top view 200B corresponds to Figure 2A A top perspective view of the cross-sectional view 200A, which does not include Figure 2A In some embodiments, Figure 2B The section line AA' corresponds to Figure 2A Cross-sectional view 200A.

[0036] like Figure 2BAs shown in the top view 200B of FIG. 1 , in some embodiments, the gate electrode structure 108 further includes a third vertical portion 108d and a fourth vertical portion 108e. The third vertical portion 108d may surround a portion of the first source / drain region 116, and may connect a first side of the first vertical portion 108b of the gate electrode structure 108 to a first side of the second vertical portion 108c of the gate electrode structure 108. The fourth vertical portion 108e may surround a portion of the second source / drain region 118, and may connect a second side of the first vertical portion 108b of the gate electrode structure 108 to a second side of the second vertical portion 108c of the gate electrode structure 108. Therefore, in some embodiments, the gate electrode structure 108 includes a vertical loop line portion that is continuously connected, and the vertical loop line portion includes the first vertical portion 108b to the fourth vertical portion 108e. In addition, the third vertical portion 108d and the fourth vertical portion 108e are surrounded by the heavily doped region 204.

[0037] Figure 2C A cross-sectional view 200C showing some embodiments of an integrated chip including a chip corresponding to Figure 2B The vertical gate transistor 101 is shown by the cross section line CC′.

[0038] In some embodiments, from the perspective of the cross-sectional view 200C, the first vertical portion and the second vertical portion ( Figure 2A Although the third vertical portion 108d and the fourth vertical portion 108e are spaced apart from the horizontal portion 108a of the gate electrode structure 108, the third vertical portion 108d and the fourth vertical portion 108e of the gate electrode structure 108 are electrically coupled to the horizontal portion 108a of the gate electrode structure 108. In addition, the gate dielectric layer 110 also separates the third vertical portion 108d and the fourth vertical portion 108e of the gate electrode structure 108 from the substrate 102. In some embodiments, although the gate dielectric layer 110 is not visible from the substrate 102, the gate dielectric layer 110 is not visible from the substrate 102. Figure 2C The angle of the cross-sectional view 200C is not visible, but the gate dielectric layer 110 that contacts the third vertical portion 108d of the gate electrode structure 108, the fourth vertical portion 108e of the gate electrode structure 108, and the horizontal portion 108a of the gate electrode structure 108 are the same, continuously connected layer.

[0039] In some embodiments, when the vertical gate transistor 101 is "turned on," the channel region 114 is formed below the horizontal portion 108a of the gate electrode structure 108, and mobile charge carriers may travel between the first source / drain region 116 and the second source / drain region 118. In addition, the first additional channel region 208 may be formed below the third vertical portion 108d of the gate electrode structure 108, and the second additional channel region 210 may be formed below the fourth vertical portion 108e of the gate electrode structure 108. In some embodiments, the heavily doped region 204 prevents mobile charge carriers from leaking from the vertical gate transistor 101 during operation. If the heavily doped region 204 does not extend below the third vertical portion 108d and the fourth vertical portion 108e of the gate electrode structure 108, leakage of mobile charge carriers in the first additional channel region 208 and the second additional channel region 210 may occur. In some embodiments, the heavily doped region 204 includes a first doping type that is the same as the first doping type of the substrate 102. In some embodiments, the heavily doped region 204 may have a higher dopant concentration than the substrate 102 , so that a channel region may not be formed in the heavily doped region 204 even when the vertical gate transistor 101 is “turned on”.

[0040] Furthermore, it should be understood that Figure 2A In the cross-sectional view 200A of FIG. 1 , mobile charge carriers will travel in the channel region 114 in a direction into or out of the page. Figure 2A From the cross-sectional view 200A, due to the first vertical portion and the second vertical portion (108b, 108c) of the gate electrode structure 108, the channel region 114 is larger than Figure 2C Furthermore, although not shown, in some embodiments, a contact via is coupled to each of the first source / drain region 116 , the gate electrode structure 108 , and the second source / drain region 118 to operate the vertical gate transistor 101 .

[0041] Figure 3 Show Figure 1C Some alternative embodiments of the integrated chip of the cross-sectional view 300, wherein the integrated chip of the cross-sectional view 300 is a complementary metal oxide semiconductor (CMOS) image sensor. Figure 3 The cross-sectional view 300 may correspond to Figure 1B Section line CC' corresponds to an alternative embodiment.

[0042] In some embodiments, the image sensor in the cross-sectional view 300 includes a vertical gate transistor 101 having a gate electrode structure 108. The gate electrode structure 108 may include a horizontal portion 108a located above the substrate 102, and a first vertical portion and a second vertical portion ( Figure 1AIn some embodiments, the gate electrode structure 108 may be or include a transfer gate electrode, wherein the gate electrode structure 108 overlies the photodiode 302 and the floating diffusion (FD) node 304. In some embodiments, the gate electrode structure 108 may be or include, for example, doped polysilicon and / or some other suitable conductive material (e.g., metal including copper, tungsten, aluminum, or other metals).

[0043] In some embodiments, the photodiode 302 and the FD node 304 may be separated from each other by the channel region 114. In some embodiments, the photodiode 302 may have a second doping type opposite to the first doping type of the substrate 102. The photodiode 302 and the substrate 102 may contact each other to form a photojunction. In other embodiments, the photodiode 302 may have a first region having a first doping type, and may have a second region having a second doping type, wherein the first region and the second region form a photojunction. The FD node 304 may have the same second doping type as the photodiode 302, and thus may have a doping type opposite to the substrate 102.

[0044] In some embodiments, the optical structure 308 is disposed on the back side 102b of the substrate 102, and the microlens 306 is disposed on the optical structure 308. In addition, in some embodiments, the trench isolation structure ( Figure 1C 104), in some embodiments, the CMOS image sensor includes a local backside trench isolation structure 310. The local backside trench isolation structure 310 may be formed during a backside patterning manufacturing step and may include a doped semiconductor material (e.g., doped polysilicon) or a dielectric material (e.g., silicon dioxide). In some embodiments, the optical structure 308 may include, for example, an anti-reflective layer and / or a color filter. The microlens 306 may be configured to focus light to the overlying photodiode 302. During operation, incident light illuminates the back side 102b of the substrate 102 through the microlens 306 and the optical structure 308, and the incident light travels to the photodiode 302. The photodiode 302 is configured to convert incident light (e.g., photons) into an electrical signal (i.e., generate electron-hole pairs from the incident light). When a voltage is applied to the gate electrode structure 108 to "turn on" the vertical gate transistor 101, the charge accumulated in the photodiode 302 is transferred from the photodiode 302 to the FD node 304 to output an electrical signal (eg, voltage, current) associated with the incident light. Figure 3 The image sensor in the image sensor converts the incident light into an electrical signal for processing. Since the gate electrode structure 108 also includes a first vertical portion and a second vertical portion ( Figure 1A 108b, 108c), the vertical gate transistor 101 and therefore the image sensor is more reliable.

[0045] Figure 4 Show Figure 2C Some alternative embodiments of the integrated chip of the cross-sectional view 400, wherein the integrated chip of the cross-sectional view 400 is a complementary metal oxide semiconductor (CMOS) image sensor. Figure 4 The cross-sectional view 400 may correspond to Figure 2B Section line CC' corresponds to an alternative embodiment.

[0046] As shown in the cross-sectional view 400, in some embodiments, the gate electrode structure 108 may be or include a transfer gate electrode in an image sensor. In some embodiments, the third vertical portion 108d of the gate electrode structure 108 may be disposed between the heavily doped region 204 and the photodiode 302. Furthermore, in some embodiments, the fourth vertical portion 108e of the gate electrode structure 108 may be disposed between the heavily doped region 204 and the FD node 304. The heavily doped region 204 may prevent accumulated charges traveling between the photodiode 302 and the FD node 304 from leaking through the channel region 114, the first additional channel region 208, and the second additional channel region 210 during operation of the vertical gate transistor 101 of the image sensor.

[0047] Figure 5 The invention shows a method including an image sensor (eg Figure 3 or Figure 4 Circuit diagram 500 of some embodiments of an image sensor).

[0048] like Figure 5 As shown, circuit diagram 500 may include photodiode 302 coupled to transfer transistor 501. In some embodiments, photodiode 302 acts as a source / drain region of transfer transistor 501. In other embodiments, photodiode 302 is coupled to the source / drain region of transfer transistor 501. Thus, transfer transistor 501 may be or include Figure 3 or Figure 4 The vertical gate transistor 101 is provided. The photodiode 302 accumulates charge (e.g., electrons) from incident light 502 on the photodiode 302. The transfer transistor 501 selectively transfers the charge from the photodiode 302 to the image sensor. The reset transistor 504 is electrically connected between the power supply 508 and the floating diffusion node ( Figure 3 304) to selectively clear floating diffusion nodes ( Figure 3 The source follower transistor 506 is electrically connected between the power supply 508 and the output 512 and is connected by a floating diffusion node ( Figure 3304) is gated to allow observation of the floating diffusion node ( Figure 3 The row select transistor 510 is electrically connected between the source follower transistor 506 and the output 512 to selectively output the floating diffusion node ( Figure 3 Thus, the reset transistor 504, the source follower transistor 506, and / or the row select transistor 510 may include the transistors 1A to 1B. Figure 1C or Figure 2A to Figure 2C The vertical gate transistor 101. It should be understood that Figure 5 Other configurations of circuit diagram 500 are also within the scope of the present disclosure.

[0049] FIG. 6A to FIG. 16C Various views 600A-1600C illustrate some embodiments of a method of forming a vertical gate transistor having a gate electrode structure including a first vertical portion and a second vertical portion. FIG. 6A to FIG. 16C is described with respect to one method, but it should be understood that FIG. 6A to FIG. 16C The structure disclosed in is not limited to this method, but can exist independently as a structure independent of this method.

[0050] like Fig. 6A As shown in the cross-sectional view 600A of , a substrate 102 is provided. The substrate 102 includes a front side 102f and a back side 102b, and may be, for example, a bulk monocrystalline silicon substrate, a semiconductor on insulator (SOI) substrate, or some other suitable semiconductor substrate (e.g., SiGe, Ge, etc.). In some embodiments, a trench isolation structure 104 is formed in the substrate and extends from the front side 102f of the substrate 102 toward the back side 102b of the substrate 102. In some embodiments, the trench isolation structure 104 may be or include a shallow trench isolation (STI) structure, because the trench isolation structure 104 does not extend completely from the front side 102f of the substrate 102 to the back side 102b of the substrate 102. In some embodiments, for example, the trench isolation structure 104 extends into the front side 102f of the substrate 102 to a depth of approximately 1500 angstroms. It should be understood that other values ​​are also within the scope of the present disclosure.

[0051] In some embodiments, the trench isolation structure 104 may be formed by a selective ion implantation process. For example, in some embodiments, due to the ion implantation process, the trench isolation structure 104 has a higher doping concentration than the substrate 102. In some other embodiments, the trench isolation structure 104 may be formed by, for example, photolithography, removal and / or deposition processes, so that the trench isolation structure 104 includes silicon dioxide or some other dielectric material.

[0052] It should be understood that other methods and structures are also within the scope of the present disclosure. For example, in some other embodiments, the FIG. 6A to FIG. 6C The trench isolation structure 104 is formed, and the backside isolation structure is formed after the patterning of the front side 102f of the substrate 102 is completed.

[0053] Figure 6B Shown with Fig. 6A The cross-sectional view 600A corresponds to the top view 600B of some embodiments. In some embodiments, the cross-sectional view 600A corresponds to Figure 6B Section line AA'.

[0054] As shown in the top view 600B, in some embodiments, the trench isolation structure 104 is a continuous ring structure. In such an embodiment, the trench isolation structure 104 can separate the inner region 102i of the substrate 102 from the outer region 102o of the substrate 102. In some embodiments, the inner region 102i of the substrate 102 and the inner periphery of the trench isolation structure 104 have an overall rectangular shape. In other embodiments, the inner region 102i of the substrate 102 and the inner periphery of the trench isolation structure 104 include an overall circular shape, an elliptical shape, or some other polygonal shape.

[0055] Figure 6C Shown with Figure 6B Section line CC' corresponds to cross-sectional view 600C of some embodiments.

[0056] like Fig. 7A As shown in the cross-sectional view 700A of FIG. 1 , in some embodiments, a doped well region 702 is formed between the trench isolation structures 104 . In some embodiments, the substrate 102 has a first doping type (e.g., p-type or n-type), and the doped well region 702 is formed to increase the concentration of the first doping type. The doped well region 702 can be formed using a photolithography process and an ion implantation process. In other embodiments, the substrate 102 includes the first doping type, and the doping concentration of the first doping type in the substrate 102 is sufficient. In such other embodiments, the formation of the doped well region 702 is omitted. It should be understood that other structures are also within the scope of the present disclosure.

[0057] Figure 7B Shown with Fig. 7A The cross-sectional view 700A corresponds to the top view 700B of some embodiments. In some embodiments, the cross-sectional view 700A corresponds to Figure 7B Section line AA'.

[0058] like Figure 7B As shown in the top view 700B of FIG. 1 , in some embodiments, the doped well region 702 is confined to the inner region ( Figure 6B 102i). In some embodiments, the trench isolation structure 104 continuously surrounds the doped well region 702. In some embodiments, the trench isolation structure 104 is doped to the same first doping type as the doped well region 702. In such an embodiment, the doping concentration of the trench isolation structure 104 is higher than the doping concentration of the doped well region 702. In other embodiments, the trench isolation structure 104 may not be doped, and thus the doped well region 702 may have a higher doping concentration than the trench isolation structure 104. In some embodiments, the doped well region 702 may directly contact the trench isolation structure 104, while in other embodiments, the doped well region 702 may be separated from the trench isolation structure 104 by the substrate 102.

[0059] Figure 7C Shown with Figure 7B Section line CC' corresponds to cross-sectional view 700C of some embodiments.

[0060] like Fig. 8A As shown in the cross-sectional view 800A of FIG. 1 , in some embodiments, a first masking structure 802 is formed on the front side 102f of the substrate 102. The first masking structure 802 may include a first opening 804 and a second opening 806. The first opening 804 and the second opening 806 may be disposed in the inner region ( 804f ) of the substrate 102 defined by the trench isolation structure 104. Figure 6B In some embodiments, the first opening 804 of the first masking structure 802 directly overlies the doped well region 702 and exposes the doped well region 702, and the second opening 806 of the first masking structure 802 directly overlies the doped well region 702 and exposes the doped well region 702. In other embodiments, the first opening 804 and the second opening 806 may directly overlie portions of the trench isolation structure 104 and the doped well region 702.

[0061] The first opening 804 and the second opening 806 may each have a width equal to the third distance d3. In some embodiments, the third distance d3 is in a range between, for example, approximately 10 nanometers and approximately 1 micrometer. The first opening 804 may be spaced apart from the second opening 806 by a first distance d1. In some embodiments, the first distance d1 may be in a range between, for example, approximately 1 nanometer and approximately 1000 nanometers. It should be understood that other values ​​are also within the scope of the present disclosure.

[0062] In some embodiments, the first masking structure 802 is formed by a photolithography process and a removal (eg, etching) process. In some embodiments, the first masking structure 802 includes a photoresist material, while in other embodiments, for example, the first masking structure 802 includes a hard mask material.

[0063] Figure 8B Shown with Fig. 8A The cross-sectional view 800A corresponds to the top view 800B of some embodiments. In some embodiments, the cross-sectional view 800A corresponds to Figure 8B Section line AA'.

[0064] As shown in the top view 800B, in some embodiments, the first opening 804 extends in the first direction to expose a portion of the doped well region 702. In addition, in some embodiments, the second opening 806 also extends in the first direction to expose a portion of the doped well region 702. In some embodiments, the first opening 804 is not connected to the second opening 806. In such an embodiment, the first opening 804 can be separated from the second opening 806 by a portion of the first masking structure 802 and separated by a first distance d1. In some embodiments, the first opening 804 and the second opening 806 can be substantially parallel to each other.

[0065] Figure 8C Shown with Figure 8B The cross-sectional view 800C of some embodiments corresponds to the section line CC'. In some embodiments, from the perspective of the cross-sectional view 800C, the first opening and / or the second opening ( Fig. 8A 804, 806) are not visible.

[0066] like Fig. 9AAs shown in the cross-sectional view 900A of FIG. 8 , in some embodiments, a first removal process is performed to remove a portion of the doped well region 702. After performing the first removal process, a first trench structure 902 and a second trench structure 904 are formed according to the first opening 804 and the second opening 806 of the first masking structure 802, respectively. In some embodiments, the first removal process includes a dry etchant. In some embodiments, the dry etchant is a substantially vertical etchant to remove a portion of the doped well region 702 in a second direction. The second direction may be substantially perpendicular to the first direction.

[0067] In some embodiments, the first trench structure 902 and the second trench structure 904 are formed to a depth equal to the second distance d2. The second distance d2 is measured from the front side 102f of the substrate 102. In some embodiments, the second distance d2 may be in a range between, for example, approximately 1 nanometer and approximately 1 micrometer. In some embodiments including a doped well region 702, the first trench structure 902 and the second trench structure 904 may be defined by the inner surface of the doped well region 702. Therefore, in some embodiments, the bottom surface of the first trench structure 902 and the bottom surface of the second trench structure 904 do not extend below the doped well region 702. In addition, in some embodiments, due to the substantially vertical etchant, the first trench structure 902 and the second trench structure 904 may have sidewalls that are inclined (i.e., not perpendicular to the back side 102b of the substrate 102). It should be understood that other structures and processing steps are also within the scope of the present disclosure.

[0068] Fig. 9B Shown with Fig. 9A The cross-sectional view 900A corresponds to the top view 900B of some embodiments. In some embodiments, the cross-sectional view 900A corresponds to Fig. 9B Section line AA'.

[0069] In some embodiments, the top view 900B appears to include Figure 8B However, it should be understood that the first trench structure 902 and the second trench structure 904 are directly below the first opening 804 and the second opening 806 of the first masking structure 802, respectively.

[0070] Fig. 9C Shown with Fig. 9B The cross-sectional view 900C of some embodiments corresponds to the section line CC'. In some embodiments, from the perspective of the cross-sectional view 900C, the first opening and / or the second opening ( Fig. 9A 804, 806) and thus the first trench structure and / or the second trench structure ( Fig. 9A 902, 904) are not visible.

[0071] like Fig. 10A As shown in the cross-sectional view 1000A of FIG. 1 , in some embodiments, a gate dielectric layer 110 is formed on the front side 102f of the substrate 102. In some embodiments, the gate dielectric layer 110 is formed by a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). In some embodiments, for example, the gate dielectric layer 110 may include silicon dioxide or a low-k dielectric material. In such an embodiment, the gate dielectric layer 110 may be deposited by a thermal oxidation process. The gate dielectric layer 110 may cover the inner surface of the first trench structure 902 and the inner surface of the second trench structure 904, but does not completely fill the first trench structure 902 and the second trench structure 904.

[0072] Fig. 10B Shown with Fig. 10A The cross-sectional view 1000A corresponds to the top view 1000B of some embodiments. In some embodiments, the cross-sectional view 1000A corresponds to Fig. 10B As shown in the top view 1000B, in some embodiments, the gate dielectric layer 110 completely covers the front side (102 of FIG. 10A) of the substrate. Fig. 10A 102f).

[0073] Fig. 10C Shown with Fig. 10B Section line CC' corresponds to cross-sectional view 1000C of some embodiments.

[0074] like Fig.11A As shown in the cross-sectional view 1100A of , in some embodiments, a gate material 1102 is formed on the gate dielectric layer 110 and in the first trench structure 902 and the second trench structure 904 over the front side 102f of the substrate 102. In some embodiments, the gate material 1102 includes a conductive material, such as polysilicon. In such an embodiment, the polysilicon may be doped. In such an embodiment, the gate material 1102 may be grown on the gate dielectric layer 110 in a furnace and / or an epitaxial chamber. In other embodiments, the gate material 1102 may include a conductive metal, such as (for example) copper, tungsten, aluminum, or other metals. In such other embodiments, the gate material 1102 may be formed by a deposition process (e.g., CVD, PVD, ALD, sputtering, etc.). It should be understood that other materials are also within the scope of the present disclosure.

[0075] In some embodiments, the gate material 1102 can have a height equal to a fourth distance d4 measured from the front side 102f of the substrate to a top surface of the gate material 1102. In some embodiments, the fourth distance d4 is in a range between, for example, approximately 20 nanometers and approximately 400 nanometers.

[0076] Fig. 11B Shown with Fig.11A The cross-sectional view 1100A corresponds to the top view 1100B of some embodiments. In some embodiments, the cross-sectional view 1100A corresponds to Fig. 11B As shown in the top view 1100B, in some embodiments, the gate material 1102 completely covers the substrate ( Fig. 10A The front side of 102) Fig. 10A 102f).

[0077] Fig. 11C Shown with Fig. 11B The cross-sectional line CC′ corresponds to the cross-sectional view 1100C of some embodiments. As shown in the cross-sectional view 1100C, from some angles, the gate material 1102 does not extend below the front side 102f of the substrate 102.

[0078] like Fig. 12A As shown in the cross-sectional view 1200A of FIG. 11A , in some embodiments, a second masking structure 1202 is formed on the gate material ( 1102 of FIG. 11A ), and a second removal process is performed to remove the gate material ( Fig.11A 1102) and forms the gate electrode structure 108. In some embodiments, the second masking structure 1202 is formed by a photolithography process and a removal process. For example, the second masking structure 1202 may include a photoresist material or a hard mask material. In addition, in some embodiments, the second removal process may include, for example, an etching process using a dry etchant.

[0079] In some embodiments, after the second removal process, the gate electrode structure 108 does not cover or does not completely cover the trench isolation structure 104. In some embodiments, the second removal process also removes the gate dielectric layer 110 that is not directly under the second masking structure 1202. In other embodiments, the second removal process removes the gate dielectric layer 110 that is not directly under the second masking structure 1202. In some embodiments, as shown in the cross-sectional view 1200A, the gate electrode structure 108 may include: a horizontal portion 108a, which is configured on the front side 102f of the substrate 102; a first vertical portion 108b, which protrudes from the horizontal portion 108a and extends toward the back side 102b of the substrate 102; and a second vertical portion 108c, which protrudes from the horizontal portion 108a and extends toward the back side 102b of the substrate 102. In some embodiments, both the first vertical portion 108b and the second vertical portion 108c are located in the doped well region 702 and are configured in the inner region ( Fig. 6A Therefore, the trench isolation structure 104 surrounds both the first vertical portion 108b and the second vertical portion 108c of the gate electrode structure 108. The first vertical portion 108b and the second vertical portion 108c of the gate electrode structure 108 can enhance the controllability of the channel region of the final device configured below the gate electrode structure 108.

[0080] Fig. 12B Shown with Fig. 12A The cross-sectional view 1200A corresponds to the top view 1200B of some embodiments. In some embodiments, the cross-sectional view 1200A corresponds to Fig. 12B In some embodiments, the second masking structure 1202 completely covers the gate electrode structure ( Fig. 12A 108) of the first vertical portion and the second vertical portion ( Fig. 12A 108b, 108c).

[0081] Fig. 12C Shown with Fig. 12B The cross-sectional view 1200C of some embodiments corresponds to the section line CC'. As shown in the cross-sectional view 1200C, in some embodiments, the horizontal portion 108a of the gate electrode structure 108 is visible, while the first vertical portion and the second vertical portion ( Fig. 12A 108b, 108c) are not visible.

[0082] like Fig.13AAs shown in the cross-sectional view 1300A of FIG. 1 , in some embodiments, a spacer layer 1302 is formed over the gate electrode structure 108 and over the front side 102f of the substrate 102. In some embodiments, the spacer layer 1302 includes a dielectric material such as, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoricsilicate glass (PSG), borophosphosilicate glass (BPSG), a low dielectric constant oxide (e.g., carbon-doped oxide, SiCOH), etc. In some embodiments, the gate dielectric layer 110 can separate the spacer layer 1302 from the substrate 102. In other embodiments, the spacer layer 1302 can directly contact the substrate 102. In some embodiments, the spacer layer 1302 can be formed by a deposition process (e.g., CVD, PVD, ALD, etc.).

[0083] Fig. 13B Shown with Fig.13A The cross-sectional view 1300A corresponds to the top view 1300B of some embodiments. In some embodiments, the cross-sectional view 1300A corresponds to Fig. 13B As shown in top view 1300B, in some embodiments, spacer layer 1302 completely covers substrate 102. In other embodiments, spacer layer 1302 can be selectively deposited on regions of substrate 102, for example, by photolithography, removal, and / or deposition processes.

[0084] Fig. 13C Shown with Fig. 13B Section line CC' corresponds to cross-sectional view 1300C of some embodiments.

[0085] like Fig.14A As shown in the cross-sectional view 1400A of FIG. 1400A , in some embodiments, a third removal process is performed to remove the spacer layer ( Fig.13A1302), thereby forming a sidewall spacer structure 112 on the outer sidewall of the horizontal portion 108a of the gate electrode structure 108. In some embodiments, the sidewall spacer structure 112 can protect the gate electrode structure 108 from damage by future processing steps. In some embodiments, as shown in the cross-sectional view 1400A, the third removal process does not remove the exposed portion of the gate dielectric layer 110. In other embodiments, the exposed portion of the gate dielectric layer 110 can be removed by the third removal process. In some embodiments, the sidewall spacer structure 112 directly overlies the gate dielectric layer 110. In other embodiments, the sidewall spacer structure 112 can directly contact the front side 102f of the substrate 102 or the trench isolation structure 104. In some embodiments, the third removal process can be or include a vertical etching process. It should be understood that other processes for forming the sidewall spacer structure 112 are also within the scope of the present disclosure.

[0086] Fig. 14B Shown with Fig.14A The cross-sectional view 1400A corresponds to the top view 1400B of some embodiments. In some embodiments, the cross-sectional view 1400A corresponds to Fig. 14B As shown in the top view 1400B, in some embodiments, the sidewall spacer structure 112 continuously surrounds the outer periphery of the horizontal portion 108a of the gate electrode structure 108. In some embodiments, the sidewall spacer structure 112 and / or the horizontal portion 108a of the gate electrode structure 108 may partially overlap the trench isolation structure 104. In some embodiments, the trench isolation structure 104 may be located below the gate dielectric layer 110, and therefore, for convenience, the trench isolation structure 104 is shown with a dotted line in the top view 1400B of FIG. 14.

[0087] Fig. 14C Shown with Fig. 14B Section line CC' corresponds to cross-sectional view 1400C of some embodiments.

[0088] FIG. 15A to FIG. 15C Various views 1500A-1500C respectively illustrate a method of forming first and second source / drain regions on the front side of a substrate.

[0089] In some embodiments, Fig.15A The cross-sectional view 1500A is shown after forming the first source / drain region and the second source / drain region. However, from the perspective of the cross-sectional view 1500A, the first source / drain region and the second source / drain region are not visible.

[0090] like Fig. 15BAs shown in the top view 1500B of FIG. 1500B, in some embodiments, a first source / drain region 116 is configured on the first side 108f of the gate electrode structure 108, and a second source / drain region 118 is configured on the second side 108s of the gate electrode structure 108. The first source / drain region 116 and the second source / drain region 118 may be formed in the inner region ( Figure 7B Because the first source / drain region 116 and the second source / drain region 118 are disposed below the gate dielectric layer 110, the first source / drain region 116 and the second source / drain region 118 are disposed below the gate dielectric layer 110. Fig. 15B The top view 1500B is shown with dotted lines.

[0091] like Fig. 15C As shown in the cross-sectional view 1500C of FIG. 1500A , in some embodiments, the first source / drain region 116 and the second source / drain region 118 are disposed in the substrate 102 and extend from the front side 102f of the substrate 102 toward the back side 102b of the substrate 102. In some embodiments, the bottom surfaces of the first source / drain region 116 and the second source / drain region 118 are disposed above the bottom surface of the trench isolation structure 104, so that the trench isolation structure 104 can effectively prevent current from leaking from the first source / drain region 116 and / or the second source / drain region 118. In some embodiments, the first source / drain region 116 and the second source / drain region 118 are formed by an ion implantation process, so that the first source / drain region 116 and the second source / drain region 118 include a second doping type opposite to the first doping type of the doped well region 702. The masking layer may be used to protect other features (e.g., gate electrode structure 108, substrate 102, trench isolation structure 104, etc.) from being doped by the ion implantation process. In some embodiments, gate dielectric layer 110 may remain on substrate 102 during the ion implantation process to form first source / drain region 116 and second source / drain region 118. In other embodiments, gate dielectric layer 110 disposed at least on first source / drain region 116 and second source / drain region 118 is removed before the ion implantation process. In some embodiments, first source / drain region 116 and / or second source / drain region 118 are partially located under gate electrode structure 108.

[0092] In some other embodiments, it should be understood that the first source / drain region 116 and / or the second source / drain region 118 may be formed in the substrate 102 in a previous step. For example, in some embodiments, Figure 3 The image sensor, photodiode ( Figure 3 302) and floating diffusion nodes ( Figure 3304) may be formed before the gate electrode structure 108 is formed. In some other embodiments, the photodiode ( Figure 3 302) and floating diffusion nodes ( Figure 3 304) can be formed after the gate electrode structure 108 is formed.

[0093] like Fig.16A As shown in the cross-sectional view 1600A of FIG. 1 , in some embodiments, a dielectric structure 106 is formed on the front side 102f of the substrate 102, and a contact via 1602 is formed in the dielectric structure 106 to contact the gate electrode structure 108. In some embodiments, the gate dielectric layer 110 may include, for example, nitride (e.g., silicon nitride, silicon oxynitride), carbide (e.g., silicon carbide), oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant oxide (e.g., carbon-doped oxide, SiCOH), etc. In addition, the contact via 1602 may include, for example, tungsten, copper, aluminum, or some other conductive material. The dielectric structure 106 and the contact via 1602 may be formed by various cycles of deposition (e.g., CVD, PVD, ALD, sputtering, etc.) processes, photolithography and / or removal (e.g., etching, chemical mechanical planarization (CMP), etc.) processes.

[0094] Fig. 16B Shown with Fig.16A The cross-sectional view 1600A corresponds to the top view 1600B of some embodiments. In some embodiments, the cross-sectional view 1600A corresponds to Fig. 16B Section line AA'.

[0095] As shown in the top view 1600B, the contact via 1602 may also be disposed above the first source / drain region 116 and the second source / drain region 118 and disposed in the dielectric structure 106. From the top view 1600B, in some embodiments, the contact via 1602 has a generally circular shape. In other embodiments, it should be understood that the contact via 1602 may have other shapes, such as, for example, a square shape, a rectangular shape, an elliptical shape, etc.

[0096] Fig. 16C Shown with Fig. 16B Section line CC' corresponds to cross-sectional view 1600C of some embodiments.

[0097] As shown in cross-sectional view 1600C, contact via 1602 contacts first source / drain region 116 and second source / drain region 118. Contact via 1602 contacting first source / drain region 116 may be coupled to a source terminal; contact via 1602 contacting gate electrode structure 108 may be coupled to a gate terminal; and contact via 1602 coupled to second source / drain region may be coupled to a drain terminal. In addition, first source / drain region 116 and second source / drain region 118 and gate electrode structure 108 may be a first vertical portion and a second vertical portion ( Fig.16A 108b, 108c) of the vertical gate transistor 101. Since the first vertical portion and the second vertical portion ( Fig.16A 108b, 108c), the vertical gate transistor 101 has lower noise and higher controllability than a transistor in which the gate electrode structure 108 only includes the horizontal portion 108a.

[0098] Fig.17 Shown to form corresponding to FIG. 6A to FIG. 16C The vertical gate transistor Fig.17 Flowcharts of some embodiments of the illustrated method.

[0099] Although method 1700 is shown and described as a series of actions or events below, it should be understood that the order of showing such actions or events should not be interpreted as limiting. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events except the actions or events shown and / or described herein. In addition, it may not be necessary for all the actions shown to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein can be carried out in one or more separate actions and / or stages.

[0100] In act 1702, a trench isolation structure is formed in a continuously connected ring on the front side of the substrate. The trench isolation structure separates an inner region of the substrate from an outer region of the substrate. Fig. 6A and 6B Some embodiments corresponding to act 1702 are shown in cross-sectional view 600A and top view 600B, respectively.

[0101] In act 1704, a first masking structure is formed on the substrate, the first masking structure including a first opening and a second opening. The first opening and the second opening are disposed on the inner region of the substrate. Fig. 8A and Figure 8B Some embodiments corresponding to act 1704 are shown in cross-sectional view 800A and top view 800B, respectively.

[0102] In act 1706 , a first removal process is performed to remove a portion of the inner region of the substrate to form a first trench structure and a second trench structure directly below the first opening and the second opening, respectively. Fig. 9A and Fig. 9B Some embodiments corresponding to act 1706 are shown in cross-sectional view 900A and top view 900B, respectively.

[0103] In act 1708, a gate dielectric layer is formed over the substrate. Fig. 10A A cross-sectional view 100A of some embodiments corresponding to act 1708 is shown.

[0104] In act 1710, a gate material is formed within the first trench structure and the second trench structure and over the substrate. Fig.11A A cross-sectional diagram 1100A of some embodiments corresponding to act 1710 is shown.

[0105] In action 1712, an outer portion of the gate material is removed to form a gate electrode structure disposed on the inner region of the substrate and within the first trench structure and the second trench structure. Fig. 12A Cross-sectional view 1200A of some embodiments corresponding to act 1712 is shown.

[0106] In action 1714, a first source / drain region and a second source / drain region are formed on the inner region of the substrate. A gate electrode structure is located between the first source / drain region and the second source / drain region. Fig. 15C Cross-sectional view 1500C of some embodiments corresponding to act 1714 is shown.

[0107] In action 1716 , a contact via is formed over the gate electrode structure, the first source / drain region, and the second source / drain region. Fig. 16C Cross-sectional view 1600C of some embodiments corresponding to act 1716 is shown.

[0108] FIG. 18A to FIG. 22C Various views 1800A to 2200C illustrate some embodiments of a method of forming a vertical gate transistor having a gate electrode structure including first to fourth vertical portions extending from a horizontal portion. FIG. 18A to FIG. 22C is described with respect to one method, but it should be understood that FIG. 18A to FIG. 22C The structure disclosed in is not limited to this method, but can exist independently as a structure independent of the method.

[0109] like Fig.18AAs shown in the cross-sectional view 1800A of FIG. 18 , in some embodiments, the doped well region 702 is formed within the front side 102f of the substrate 102. Therefore, in some embodiments, the doped well region 702 is formed in any type of trench isolation structure (e.g., Fig. 6A 104). In some embodiments, the substrate 102 has a first doping type (e.g., p-type or n-type), and the doped well region 702 is formed to increase the concentration of the first doping type. The doped well region 702 can be formed using photolithography and ion implantation processes. In other embodiments, the substrate 102 includes the first doping type, and the doping concentration of the first doping type in the substrate 102 is sufficient. In such other embodiments, the formation of the doped well region 702 is omitted.

[0110] Fig.18B Shown with Fig.18A The cross-sectional view 1800A corresponds to the top view 1800B of some embodiments. In some embodiments, the cross-sectional view 1800A corresponds to Fig.18B The section line AA'. Fig.18B As shown in top view 1800B, in some embodiments, the doped well region 702 does not completely cover the substrate 102.

[0111] Fig.18C Shown with Fig.18B Section line CC' corresponds to cross-sectional view 1800C of some embodiments.

[0112] like Fig.19A As shown in the cross-sectional view 1900A of FIG. 19 , in some embodiments, the first masking structure 802 is formed on the front side 102f of the substrate 102. From the cross-sectional view 1900A, the first masking structure 802 may include a first opening 804 and a second opening 806. In some embodiments, the first opening 804 of the first masking structure 802 directly overlies the doped well region 702 and exposes the doped well region 702, and the second opening 806 of the first masking structure 802 directly overlies the doped well region 702 and exposes the doped well region 702.

[0113] Fig.19B Shown with Fig.19A The cross-sectional view 1900A corresponds to the top view 1900B of some embodiments. In some embodiments, the cross-sectional view 1900A corresponds to Fig.19B Section line AA'.

[0114] As shown in the top view 1900B, in some embodiments, the first opening 804 extends in the first direction to expose a portion of the doped well region 702. In addition, in some embodiments, the second opening 806 also extends in the first direction to expose a portion of the doped well region 702. In some embodiments, the first opening 804 and the second opening 806 may be substantially parallel to each other. In addition, in some embodiments, the first masking structure 802 further includes a third opening 1902 and a fourth opening 1904. In some embodiments, the third opening 1902 and the fourth opening 1904 extend in a second direction different from the first direction. In some embodiments, the third opening 1902 and the fourth opening 1904 directly overlie a portion of the doped well region 702 and / or a portion of the substrate 102. In addition, the third opening 1902 connects a first side of the first opening 804 to a first side of the second opening 806, and the fourth opening 1904 connects a second side of the first opening 804 to a second side of the second opening 806. Thus, in some embodiments, the first masking structure 802 includes continuously connected openings including the first opening 804, the second opening 806, the third opening 1902, and the fourth opening 1904. In some embodiments, the continuously connected openings in the first masking structure 802 may separate the inner region 802i of the first masking structure 802 from the outer region 802o of the first masking structure 802. It should be understood that other structures are also within the scope of the present disclosure.

[0115] Fig.19C Shown with Fig.19B The cross-sectional view 1900C of some embodiments corresponds to the section line CC'. In some embodiments, from the perspective of the cross-sectional view 1900C, the first opening and / or the second opening ( Fig.19A However, in some embodiments, from the cross-sectional view 1900C, the third opening 1902 and the fourth opening 1904 of the first masking structure 802 are visible.

[0116] like Fig. 20A As shown in the cross-sectional view 2000A of FIG. 1 , in some embodiments, a first removal process is performed to remove a portion of the doped well region 702 and / or the substrate 102 according to the first masking structure 802. After the first removal process is performed, a first trench structure 902 and a second trench structure 904 are formed according to the first opening 804 and the second opening 806 of the first masking structure 802, respectively. Fig. 20A The first trench structure 902 and the second trench structure 904 may be formed by the same or similar method and may include Fig. 9A The first trench structure 902 and the second trench structure 904 have similar features (eg, measurement parameters). In addition, it should be understood that other processes are also within the scope of the present disclosure.

[0117] Fig. 20B Shown with Fig. 20A The cross-sectional view 2000A corresponds to the top view 2000B of some embodiments. In some embodiments, the cross-sectional view 2000A corresponds to Fig. 20B Section line AA'.

[0118] In some embodiments, the top view 2000B appears to include Fig. 20B 200B. However, it should be understood that the first trench structure 902 and the second trench structure 904 are respectively directly below the first opening 804 and the second opening 806 of the first masking structure 802. In addition, the third trench structure 2002 and the fourth trench structure 2004 may be respectively directly below the third opening 1902 and the fourth opening 1904. Therefore, the first removal process may form a continuously connected trench structure including the first trench structure 902, the second trench structure 904, the third trench structure 2002 and the fourth trench structure 2004.

[0119] Fig. 20C Shown with Fig. 20B The cross-sectional view 2000C of some embodiments corresponds to the section line CC'. In some embodiments, from the perspective of the cross-sectional view 2000C, the first opening and / or the second opening ( Fig. 20A 804, 806) and thus the first trench structure and / or the second trench structure ( Fig. 20A 902, 904) are not visible. In some embodiments, from the cross-sectional view 2000C, the third opening 1902 and the fourth opening 1904, and therefore the third trench structure 2002 and the fourth trench structure 2004 are visible. In some embodiments, the inner surface of the substrate 102 and the inner surface of the doped well region 702 define the third trench structure 2002 and the fourth trench structure 2004. In other embodiments, the inner surface of the substrate 102 or the inner surface of the doped well region 702 may define the third trench structure 2002 and the fourth trench structure 2004. In addition, in some embodiments, the third trench structure 2002 and the fourth trench structure 2004 have a width equal to the third distance d3, and the third trench structure 2002 and the fourth trench structure 2004 may each extend into the front side 102f of the substrate 102 to a depth equal to the second distance d2. It should be understood that other values ​​are also within the scope of the present disclosure.

[0120] FIG. 21A to FIG. 21CVarious views 2100A to 2100C of some embodiments of the vertical gate transistor 101 are shown after forming the gate dielectric layer 110, the gate electrode structure 108, the sidewall spacer structure 112, the dielectric structure 106, and the contact via 1602 over the substrate 102. It should be understood that in FIGS. 21A to 2100C, the gate dielectric layer 110, the gate electrode structure 108, the sidewall spacer structure 112, the dielectric structure 106, and the contact via 1602 are formed over the substrate 102. Fig. 21C The formation of the gate dielectric layer 110 may include the following steps: FIG. 10A to FIG. 10C The same or similar process as described in the gate dielectric layer 110 in FIG. FIG. 21A to FIG. 21C The formation of the gate electrode structure 108 may include the following steps: FIG. 11A to FIG. 12C The same or similar process as described in the gate electrode structure 108 in FIG. FIG. 21A to FIG. 21C The formation of the sidewall spacer structure 112 may include FIG. 13A to FIG. 14C The same or similar process as described in the sidewall spacer structure 112 in FIG. Further, it should be understood that FIG. 21A to FIG. 21C The formation of the dielectric structure 106 and the contact via 1602 may include the following steps: FIG. 16A to FIG. 16C The dielectric structure 106 and the contact via 1602 described in the same or similar process.

[0121] As in Fig. 21C As can be seen in the cross-sectional view 2100C of FIG. 2100, due to the third trench structure and the fourth trench structure ( Fig. 20C 2002, 2004), Fig. 21C The gate electrode structure 108 also includes a third vertical portion 108d and a fourth vertical portion 108e. The first source / drain region 116 may be disposed between the horizontal portion 108a of the gate electrode structure 108 and the third vertical portion 108d of the gate electrode structure 108. The second source / drain region 118 may be disposed between the horizontal portion 108a of the gate electrode structure 108 and the fourth vertical portion 108e of the gate electrode structure 108. In some embodiments, the first source / drain region 116 and the second source / drain region 118 may be separated from each other by a portion of the doped well region 702. It should be understood that other structures are also within the scope of the present disclosure.

[0122] like Fig.22AAs shown in the cross-sectional view 2200A of , in some embodiments, after the gate electrode structure 108 is formed, a heavily doped region 204 extending through the substrate 102 may be formed. In some embodiments, the heavily doped region 204 is formed from the back side 102b of the substrate 102 to the front side 102f of the substrate 102. In some embodiments, the heavily doped region 204 has a higher doping concentration than the substrate 102. Therefore, in some embodiments, the heavily doped region 204 has the same doping type as the substrate 102, but the doping concentration is higher than the substrate 102. In some embodiments, the heavily doped region 204 is formed by an ion implantation process. In such an embodiment, the heavily doped region 204 may include doped silicon. In other embodiments, the heavily doped region 204 may also be formed by a removal (e.g., etching) process and a deposition process. For example, in such other embodiments, the heavily doped region 204 may include doped polysilicon. It should be understood that other processing steps, materials and / or structures of the heavily doped region 204 are also within the scope of the present disclosure.

[0123] Fig. 22B Shown with Fig.22A The cross-sectional view 2200A corresponds to the rear view 2200B of some embodiments. In some embodiments, the cross-sectional view 2200A corresponds to Fig. 22B In some embodiments, from the rear view 2200B, the heavily doped region 204 is in a continuously connected ring shape. It should be understood that other structures are also within the scope of the present disclosure.

[0124] Fig. 22C Shown with Fig. 22B 2200C of some embodiments corresponding to the section line CC' of FIG. In some embodiments, the heavily doped region 204 surrounds the outer sidewalls of the third vertical portion 108d and the outer sidewalls of the fourth vertical portion 108e of the gate electrode structure 108. Therefore, when the vertical gate transistor 101 is "turned on", the heavily doped region 204 can prevent current leakage between the first source / drain region 116, the second source / drain region 118 and the gate electrode structure 108.

[0125] Fig.23 Shown to form corresponding to FIG. 18A to FIG. 22C The vertical gate transistor Fig.23 Flowcharts of some embodiments of the illustrated method.

[0126] Although method 2300 is shown and described as a series of actions or events below, it should be understood that the order in which these actions or events are shown should not be interpreted as limiting. For example, some actions can occur in different orders and / or occur simultaneously with other actions or events other than the actions or events shown and / or described herein. In addition, all the actions shown may not be needed to implement one or more aspects or embodiments described herein. In addition, one or more actions described herein can be performed in one or more separate actions and / or stages.

[0127] In act 2302, a first masking structure is formed over a substrate. An opening in the first masking structure completely separates an inner region from an outer region of the first masking structure. Fig.19A and Fig.19B Some embodiments corresponding to act 2302 are shown in cross-sectional view 1900A and top view 1900B, respectively.

[0128] In act 2304, a first removal process is performed to remove a portion of the substrate directly beneath the opening of the first masking structure, thereby forming a trench structure in the substrate. Fig. 20A and Fig. 20B Some embodiments corresponding to act 2304 are shown in cross-sectional view 2000A and top view 2000B, respectively.

[0129] In act 2306, a gate dielectric layer is formed over the substrate.

[0130] In action 2308, a gate electrode structure is formed within and over the trench structure.

[0131] In act 2310, a first source / drain region and a second source / drain region are formed on a substrate.

[0132] In action 2312, a contact via is formed over the gate electrode structure, the first source / drain region, and the second source / drain region. Fig.21A Cross-sectional view 2100A of some embodiments corresponding to act 2306 , act 2308 , act 2310 , and act 2312 is shown.

[0133] In act 2314, a heavily doped region is formed that continuously surrounds the gate electrode structure and extends from the back side of the substrate to the front side of the substrate. Fig.22A , Fig. 22B and Fig. 22C The cross-sectional view 2200A, the rear view 2200B, and the cross-sectional view 2200C of some embodiments corresponding to action 2314 are respectively shown.

[0134] Therefore, the present disclosure is directed to a method of forming a gate electrode structure comprising at least a horizontal portion, a first vertical portion, and a second vertical portion to reduce noise and thus increase reliability of a final transistor device.

[0135] Therefore, in some embodiments, the present disclosure relates to a device, comprising: a semiconductor substrate, comprising a front side and a back side; a first source / drain region and a second source / drain region, located on the front side of the semiconductor substrate; a gate electrode structure, configured on the front side of the semiconductor substrate and comprising: a horizontal portion, configured on the front side of the semiconductor substrate and between the first source / drain region and the second source / drain region; a first vertical portion, extending in a first direction from the front side of the semiconductor substrate toward the back side of the semiconductor substrate and contacting the horizontal portion of the gate electrode structure; and a second vertical portion, extending in the first direction from the front side of the semiconductor substrate toward the back side of the semiconductor substrate, contacting the horizontal portion of the gate electrode structure, and separated from the first vertical portion by a channel region of the semiconductor substrate.

[0136] In some embodiments, the first vertical portion extends from the first source / drain region to the second source / drain region in a second direction, wherein the second vertical portion extends from the first source / drain region to the second source / drain region in the second direction, and wherein the second direction is perpendicular to the first direction. In some embodiments, the gate electrode structure further comprises: a third vertical portion extending from the front side of the semiconductor substrate toward the back side of the semiconductor substrate, wherein a first side of the first vertical portion is connected to a first side of the second vertical portion through the third vertical portion; and a fourth vertical portion extending from the front side of the semiconductor substrate toward the back side of the semiconductor substrate, wherein a second side of the first vertical portion is connected to a second side of the second vertical portion through the fourth vertical portion. In some embodiments, the first vertical portion and the second vertical portion of the gate electrode structure are directly below the horizontal portion of the gate electrode structure, and wherein the third vertical portion and the fourth vertical portion of the gate electrode structure are not directly below the horizontal portion of the gate electrode structure. In some embodiments, the first source / drain region is configured between the horizontal portion of the gate electrode structure and the third vertical portion of the gate electrode structure, and wherein the second source / drain region is configured between the horizontal portion of the gate electrode structure and the fourth vertical portion of the gate electrode structure. In some embodiments, it also includes: an isolation structure that continuously surrounds the gate electrode structure and the first source / drain region and the second source / drain region. In some embodiments, the isolation structure is a shallow trench isolation structure extending from the front side of the semiconductor substrate to a depth between the front side of the semiconductor substrate and the back side of the semiconductor substrate. In some embodiments, the isolation structure is a heavily doped region extending from the back side of the semiconductor substrate to the front side of the semiconductor substrate.

[0137] In other embodiments, the present disclosure relates to a device, comprising: a semiconductor substrate, comprising a front side and a back side; a first source / drain region, disposed in the semiconductor substrate; a second source / drain region, disposed in the semiconductor substrate and spaced apart from the first source / drain region; a gate electrode structure, configured above the first source / drain region and the second source / drain region and comprising: a horizontal portion, extending above the front side of the semiconductor substrate; a first vertical portion, extending from the front side of the semiconductor substrate to a first depth below the front side of the semiconductor substrate; and a second vertical portion, extending from the front side of the semiconductor substrate to a second depth below the front side of the semiconductor substrate; and an isolation structure, located in the semiconductor substrate and surrounding the gate electrode structure.

[0138] In other embodiments, the first depth is approximately equal to the second depth. In other embodiments, the first vertical portion of the gate electrode structure and the second vertical portion of the gate electrode structure directly contact the bottom surface of the horizontal portion of the gate electrode structure and extend from the bottom surface of the horizontal portion of the gate electrode structure. In other embodiments, it also includes: a gate dielectric layer that separates the first vertical portion, the second vertical portion, and the horizontal portion of the gate electrode structure from the semiconductor substrate so that the first vertical portion, the second vertical portion, and the horizontal portion of the gate electrode structure do not directly contact the semiconductor substrate. In other embodiments, it also includes: a sidewall spacer structure that surrounds the outermost sidewall of the horizontal portion of the gate electrode structure, wherein the gate sidewall spacer structure is configured above the front side of the semiconductor substrate. In other embodiments, the channel region of the semiconductor substrate is configured below the horizontal portion of the gate electrode structure, configured between the first source / drain region and the second source / drain region, and includes a first concentration of a first doping type. In other embodiments, the isolation structure includes a second concentration of the first doping type, and wherein the second concentration is greater than the first concentration.

[0139] In some other embodiments, the present disclosure relates to a method, comprising: forming a first masking structure on a substrate, wherein the first masking structure includes a first opening and a second opening, and the first opening and the second opening extend parallel to each other; removing a portion of the substrate directly below the first opening and the second opening; removing the first masking structure; forming a gate dielectric layer on the substrate; forming a gate electrode material on the gate dielectric layer; removing an outer portion of the gate electrode material to form a gate electrode structure including a horizontal portion, a first vertical portion and a second vertical portion; forming a first source / drain region and a second source / drain region in the substrate; and forming an isolation structure located in the substrate and surrounding the first source / drain region, the second source / drain region and the gate electrode structure.

[0140] In some further embodiments, the first masking structure further includes: a third opening connecting the first side of the first opening to the first side of the second opening; and a fourth opening connecting the second side of the first opening to the second side of the second opening. In some further embodiments, the formation of the isolation structure is performed before the formation of the first masking structure. In some further embodiments, the formation of the isolation structure is performed after the formation of the gate electrode structure. In some further embodiments, the gate electrode structure surrounds the outermost wall of the first source / drain region and the outermost wall of the second source / drain region.

[0141] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A vertical gate field effect transistor device, comprising: A semiconductor substrate including a front side and a back side; a first source / drain region and a second source / drain region located on the front side of the semiconductor substrate; A gate electrode structure is disposed on the front side of the semiconductor substrate and comprises: a horizontal portion disposed on the front side of the semiconductor substrate and between the first source / drain region and the second source / drain region; a first vertical portion extending in a first direction from the front side of the semiconductor substrate toward the back side of the semiconductor substrate and contacting the horizontal portion of the gate electrode structure; a second vertical portion extending from the front side of the semiconductor substrate toward the back side of the semiconductor substrate in the first direction, contacting the horizontal portion of the gate electrode structure, and separated from the first vertical portion by a channel region of the semiconductor substrate; a third vertical portion extending from the front side of the semiconductor substrate toward the back side of the semiconductor substrate, wherein the first side of the first vertical portion is connected to the first side of the second vertical portion through the third vertical portion; and a fourth vertical portion extending from the front side of the semiconductor substrate toward the back side of the semiconductor substrate, wherein the second side of the first vertical portion is connected to the second side of the second vertical portion through the fourth vertical portion, Wherein the first vertical portion and the second vertical portion of the gate electrode structure are directly located below the horizontal portion of the gate electrode structure, and wherein the third vertical portion and the fourth vertical portion of the gate electrode structure are not directly located below the horizontal portion of the gate electrode structure.

2. The vertical gate field effect transistor device of claim 1 , wherein the first vertical portion extends from the first source / drain region to the second source / drain region in a second direction, wherein the second vertical portion extends from the first source / drain region to the second source / drain region in the second direction, and wherein the second direction is perpendicular to the first direction.

3. A vertical gate field effect transistor device according to claim 1, wherein the first source / drain region is configured between the horizontal portion of the gate electrode structure and the third vertical portion of the gate electrode structure, and wherein the second source / drain region is configured between the horizontal portion of the gate electrode structure and the fourth vertical portion of the gate electrode structure.

4. The vertical gate field effect transistor device according to claim 1, further comprising: The isolation structure continuously surrounds the gate electrode structure and the first source / drain region and the second source / drain region. 5 . The vertical gate field effect transistor device of claim 4 , wherein the isolation structure is a shallow trench isolation structure extending from the front side of the semiconductor substrate to a depth between the front side of the semiconductor substrate and the back side of the semiconductor substrate. 6 . The vertical gate field effect transistor device of claim 4 , wherein the isolation structure is a heavily doped region extending from the back side of the semiconductor substrate to the front side of the semiconductor substrate.

7. A vertical gate field effect transistor device, comprising: A semiconductor substrate including a front side and a back side; A first source / drain region is disposed in the semiconductor substrate; a second source / drain region disposed in the semiconductor substrate and spaced apart from the first source / drain region by a channel region in a first direction; a horizontal gate electrode portion extending above the channel region and disposed between the first source / drain region and the second source / drain region, the horizontal gate electrode portion comprising a first gate edge corresponding to the first source / drain region and a second gate edge corresponding to the second source / drain region; a first vertical gate electrode portion coupled to a lower portion of the horizontal gate electrode portion and extending from the front side of the semiconductor substrate to a first depth below the front side of the semiconductor substrate, wherein the first vertical gate electrode portion is spaced apart from the first gate edge in the first direction by the first source / drain region; as well as A second vertical gate electrode portion extends from the front side of the semiconductor substrate to a second depth below the front side of the semiconductor substrate. 8 . The vertical gate field effect transistor device of claim 7 , wherein the first depth is equal to the second depth.

9. The vertical gate field effect transistor device of claim 7, wherein the first vertical gate electrode portion and the second vertical gate electrode portion directly contact a bottom surface of the horizontal gate electrode portion and extend from the bottom surface of the horizontal gate electrode portion.

10. The vertical gate field effect transistor device according to claim 7, further comprising: A gate dielectric layer separates the first vertical gate electrode portion, the second gate electrode vertical portion, and the horizontal gate electrode portion from the semiconductor substrate so that the first vertical gate electrode portion, the second vertical gate electrode portion, and the horizontal gate electrode portion do not directly contact the semiconductor substrate.

11. The vertical gate field effect transistor device according to claim 7, further comprising: A sidewall spacer structure surrounds an outermost wall of the horizontal gate electrode portion, wherein the gate sidewall spacer structure is disposed over the front side of the semiconductor substrate.

12. A method for forming a vertical gate field effect transistor device, comprising: forming a first masking structure on the substrate, wherein the first masking structure comprises a first opening and a second opening, wherein the first opening and the second opening extend parallel to each other; removing a portion of the substrate directly below the first opening and the second opening; removing the first masking structure; forming a gate dielectric layer over the substrate; forming a gate electrode material over the gate dielectric layer; removing an outer portion of the gate electrode material to form a gate electrode structure including a horizontal portion, a first vertical portion, and a second vertical portion; forming a first source / drain region and a second source / drain region in the substrate; as well as An isolation structure is formed in the substrate and surrounds the first source / drain region, the second source / drain region and the gate electrode structure.

13. The method for forming a vertical gate field effect transistor device according to claim 12, wherein the first masking structure further comprises: a third opening connecting the first side of the first opening to the first side of the second opening; as well as A fourth opening connects the second side of the first opening to the second side of the second opening. 14 . The method for forming a vertical gate field effect transistor device according to claim 12 , wherein the formation of the isolation structure is performed before the formation of the first masking structure. 15 . The method for forming a vertical gate field effect transistor device according to claim 12 , wherein the formation of the isolation structure is performed after the formation of the gate electrode structure. 16 . The method for forming a vertical gate field effect transistor device according to claim 12 , wherein the gate electrode structure surrounds the outermost wall of the first source / drain region and the outermost wall of the second source / drain region.

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