Horizontal gate-all-around and FinFET device isolation

Abstract

The present application discloses horizontal all-around gate and FinFET device isolation. The embodiments described herein generally relate to methods and apparatus for horizontal all-around gate (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure including different materials arranged in an alternating stack formation can be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure can be oxidized to form a buried oxide layer adjacent to the substrate.

Description

[0001] This application is a divisional application with application date of May 11, 2016, application number of 201610309125.1, and title of “Horizontal full-ring gate and FinFET device isolation”. Technical Field

[0002] Embodiments of the present disclosure generally relate to semiconductor devices. More specifically, embodiments described herein relate to horizontal all-around gate device structures and fin field effect transistor device structures. Further embodiments relate to methods for forming horizontal all-around gate device structures and fin field effect transistor device structures. Background Art

[0003] As the feature size of transistor devices continues to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor device structures to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA device structure includes several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions.

[0004] However, challenges associated with the hGAA structure include the presence of parasitic devices at the bottom of the stacked lattice-matched channels. FinFET structures (which may present a different structure from the hGAA structure) also suffer from parasitic leakage and capacitance. Conventional approaches for mitigating the effects of parasitic devices include implanting dopants into the parasitic devices to suppress leakage of the device. However, the dose of dopants required to suppress leakage may hinder the epitaxial growth of the device structure on the parasitic devices. Dopants may harmfully diffuse into the channels of the intermediate structures during subsequent processing operations, which may lead to an undesirable increase in device variability. In addition, implantation may not be sufficient to reduce parasitic capacitance. Another conventional approach utilizes thermal oxidation of highly doped parasitic devices. However, the thermal oxidation process generally requires a temperature that exceeds the thermal budget of the stacked lattice-matched channels.

[0005] Therefore, there is a need in the art for improved methods for forming FinFET and hGAA device structures. Summary of the invention

[0006] In one embodiment, a method for forming a semiconductor device is provided. The method includes: forming a superlattice structure on a substrate. The superlattice structure may include a first material layer, a second material layer, and a third material layer. The superlattice structure may be patterned, and the superlattice structure and the substrate may be etched. At least one of the first material layer, the second material layer, or the third material layer may be oxidized to form a buried oxide layer. A liner deposition process may be performed to form a liner on the superlattice structure, and a shallow trench isolation process may be performed to deposit an oxide material layer on the substrate, and the substrate may be annealed.

[0007] In another embodiment, a method for forming a semiconductor device is provided. The method includes: forming a superlattice structure on a substrate. The superlattice structure may include a silicon material layer, a low germanium content silicon germanium material layer, and a high germanium content silicon germanium material layer. The superlattice structure may be patterned, and the superlattice structure and the substrate may be etched. At least one of the silicon material layer, the low germanium content silicon germanium material layer, and the high germanium content silicon germanium material layer may be oxidized to form a buried oxide layer. A liner deposition process may be performed to form a liner on the superlattice structure, and a shallow trench isolation process may be performed to deposit an oxide material layer on the substrate, and the substrate may be annealed.

[0008] In yet another embodiment, a method for forming a semiconductor device is provided. The method includes: forming a superlattice structure on a substrate. The superlattice structure may include a silicon material layer, a first silicon germanium material layer containing between about 20% and about 40% germanium, and a second silicon germanium material layer containing between about 50% and about 80% germanium. The silicon material layer, the first silicon germanium material layer, and the second silicon germanium material layer may be arranged in a stacked arrangement. The superlattice structure may be patterned, and the superlattice structure and the substrate may be etched. At least one of the first material layer, the first silicon germanium material layer, and the second silicon germanium material layer may be oxidized to form a buried oxide layer. A liner deposition process may be performed to form a liner on the superlattice structure, and a shallow trench isolation process may be performed to deposit an oxide material layer on the substrate, and the substrate may be annealed.

[0009] In yet another embodiment, a device structure is provided. The device structure may include a substrate having a superlattice structure formed on the substrate. The superlattice structure may include a silicon material layer, a first silicon germanium material layer including between about 20% and about 40% germanium, and a second silicon germanium material layer including between about 50% and about 80% germanium. The silicon material layer, the first silicon germanium material layer, and the second silicon germanium material layer may be arranged in a stacked arrangement.

[0010] In yet another embodiment, a device structure is provided. The device structure includes a superlattice structure, the superlattice structure including a silicon material layer, a first silicon germanium material layer including between about 20% and about 40% germanium, and a second silicon germanium material layer including between about 50% and about 80% germanium. The silicon material layer, the first silicon germanium material layer, and the second silicon germanium material layer can be arranged in a stacked arrangement.

[0011] In yet another embodiment, a device structure is provided. The device structure may include a substrate having a superlattice structure formed on the substrate. The superlattice structure may include one or more silicon material layers, one or more first silicon germanium material layers including between about 20% and about 40% germanium, and a buried oxide layer. The silicon material layers, the silicon germanium material layers, and the buried oxide layer may be arranged in a stacked arrangement.

[0012] In yet another embodiment, a device structure is provided. The device structure may include a superlattice, the superlattice including one or more silicon material layers, one or more first silicon germanium material layers including between about 20% and about 40% germanium, and a buried oxide layer. The silicon material layers, the silicon germanium material layers, and the buried oxide layer may be arranged in a stacked arrangement.

[0013] In yet another embodiment, a device structure is provided. The device structure may include a substrate having a superlattice structure formed on the substrate. The superlattice structure may include one or more silicon material layers, one or more silicon germanium material layers containing between about 20% and about 40% germanium, and a buried oxide layer. The silicon material layers, the silicon germanium material layers, and the buried oxide layer may be arranged in a stacked arrangement. A source / drain region may be formed on the substrate, and a metal gate structure may be formed above the superlattice structure.

[0014] In yet another embodiment, a device structure is provided. The device structure may include a substrate and a silicon germanium layer disposed on the substrate. The silicon germanium layer may include between about 20% and about 40% germanium, and a buried oxide layer may be disposed on the silicon germanium layer. A silicon layer or a silicon germanium layer including between about 20% and about 40% germanium may be disposed on the buried oxide layer, a source / drain region may be formed on the substrate, and a metal gate structure may be formed over the silicon layer or the silicon germanium layer.

[0015] In yet another embodiment, a device structure is provided. The device structure includes a substrate and a buried oxide layer disposed on and in contact with the substrate. A silicon layer or a silicon germanium layer including between about 20% and about 40% germanium may be disposed on the buried oxide layer. A source / drain region may be formed on the substrate, and a metal gate structure may be formed over the silicon layer or the silicon germanium layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Therefore, in order that the manner in which the features of the present disclosure set out above may be understood in detail, a more particular description of the present disclosure briefly summarized above may be made with reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show exemplary embodiments and therefore should not be considered to limit the scope of the present disclosure, which may allow other equally effective embodiments.

[0017] Figure 1 Operations of a method for forming a buried oxide material in a device structure are shown.

[0018] Figure 2 A schematic cross-sectional view showing a portion of a substrate having a superlattice structure formed thereon.

[0019] Figure 3 After performing patterning, etching and buried oxide layer formation processes Figure 2 Schematic cross-sectional view of a portion of a substrate and a superlattice structure.

[0020] Figure 4 After the liner formation process is performed Figure 3 Schematic cross-sectional view of a portion of a substrate and a superlattice structure.

[0021] Figure 5 After performing a shallow trench isolation (STI) process Figure 4 Schematic cross-sectional view of a portion of a substrate and a superlattice structure.

[0022] Figure 6 After the annealing process is performed Figure 5 Schematic cross-sectional view of a portion of a substrate and a superlattice structure.

[0023] Figure 7 After performing the STI recess process Figure 6 Schematic cross-sectional view of a portion of a substrate and a superlattice structure.

[0024] Figure 8 After forming the dummy gate structure Figure 7 Schematic cross-sectional view of a portion of a substrate and a superlattice structure.

[0025] Fig. 9 Shown rotated 90° Figure 8 Schematic cross-sectional view of a device depicting source and drain regions formed on a substrate adjacent to a superlattice structure.

[0026] Fig.10 A clustering tool is shown that may be utilized in accordance with one or more of the embodiments described herein.

[0027] Fig.11 Schematic cross-sectional views of device structures are shown that may be formed and / or implemented in a device according to embodiments described herein.

[0028] Fig.12 Shows the merged Fig.11 Schematic cross-sectional view of a device with a device structure.

[0029] To facilitate understanding, identical reference numerals have been used, where possible, to designate elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0030] Embodiments described herein generally relate to methods and apparatus for horizontal all-around gate (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure including different materials arranged in an alternating stack formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent to the substrate.

[0031] In one example, a superlattice structure may include one or more silicon-containing material layers and one or more silicon-germanium (SiGe)-containing material layers arranged in an alternating stacking arrangement. At least one of the SiGe layers may have a higher germanium content when compared to other SiGe layers in the superlattice structure. This SiGe layer with a higher germanium content may be oxidized to form a buried oxide layer, thereby providing improved device isolation in an hGAA or FinFET architecture. As a result, a substantially defect-free stacked channel structure may be achieved, which may provide a geometric benefit in terms of current density per square micron of surface area on a substrate. Therefore, current density may be increased, parasitic leakage and capacitance may be reduced, and power consumption of the device may be reduced.

[0032] Figure 1Operations of a method 100 for forming a buried oxide material in an hGAA or FinFET structure are shown. The method 100 may be part of a multi-operation manufacturing process for a semiconductor device (e.g., an hGAA or FinFET device). At operation 110, a superlattice structure may be formed on a substrate. As used herein, the term "superlattice" refers to a stack of material layers of lattice-closely matched materials, but the lattice-closely matched materials are sufficiently different in composition so that a selective removal process can be performed on the superlattice material. More generally, the composition of the various material layers in the stack may be unique to one or more of the material layers in the stack. In one example, the superlattice structure may include one or more layers of a silicon-containing material and a silicon-germanium-containing material. In one embodiment, the superlattice structure may include a first material layer and a second material layer. In another embodiment, the superlattice structure may include a first material layer, a second material layer, and a third material layer. In this embodiment, the second material layer and the third material layer may be formed of the same composite material and may have different material properties.

[0033] At operation 120, the superlattice structure may be patterned and etched. At operation 130, at least one of the first material layer, the second material layer, or the third material layer may be oxidized to form a buried oxide (BOX) layer. In one example, the second material layer and the third material layer are oxidized. In another example, the third material layer is oxidized.

[0034] At operation 140, a liner material may be formed on the sidewalls of the superlattice material. In one embodiment, the liner material may be deposited, for example, by chemical vapor deposition, atomic layer deposition, or an epitaxial deposition process. In another embodiment, the liner material may be formed (i.e., grown) by a suitable process such as a thermal oxidation or thermal nitridation process. The liner material is generally configured to repair portions of the superlattice structure that may have been damaged during a previous etching process. The liner material may also prevent or reduce oxidation of a material layer in the superlattice structure during subsequent processing operations.

[0035] In one embodiment, the liner material is an oxide material, a nitride material or an oxynitride material. For example, the liner material may be SiO 2 In some embodiments, the liner material may include a SiCN material, a SiOCN material, a SiBN material, a SiOBN material, and / or a SiOBCN material. In another embodiment, the liner material may include a SiCN material, a SiOCN material, a SiBN material, a SiOBN material, and / or a SiOBCN material. In another example, the liner material may include a phosphosilicate glass, a borosilicate glass, or a doped glass material. It is contemplated that various of the aforementioned liner materials may be doped in certain embodiments.

[0036] At operation 150, a shallow trench isolation (STI) material may be deposited on the substrate. In one embodiment, the STI material may be an oxide material such as SiO 2 Etc. Generally speaking, an oxide material may be formed over and around the superlattice material. In one embodiment, the oxide material is deposited by a flowable chemical vapor deposition (CVD) process.

[0037] At operation 160, an annealing process may be performed on the substrate. In one embodiment, the annealing process includes a steam annealing process. In another embodiment, the annealing process includes a steam annealing process and a dry annealing process. In yet another embodiment, the annealing process includes a dry annealing process (i.e., without steam). In general, the annealing process provides improved densification of the STI material, which may improve isolation of features formed on the substrate.

[0038] At operation 170, an STI recess process may be performed. Generally, the STI material may be etched to expose portions of the superlattice material. In one embodiment, the STI material may be recessed so that the STI material is coplanar with the BOX layer. STI planarization may also be performed prior to the STI recess process. Figure 2-7 A more detailed description of method 100 is provided in the description of Figure 2-7 The various stages of semiconductor device manufacturing are shown.

[0039] Figure 2 A schematic cross-sectional view of a portion of a substrate 202 having a superlattice structure 200 formed thereon is shown. In one embodiment, the substrate 202 may be a bulk semiconductor substrate. The term "bulk semiconductor substrate" refers to a substrate in which the entirety of the substrate is composed of semiconductor material. The bulk semiconductor substrate may include any semiconducting material and / or combination of semiconductor materials used to form a semiconductor structure. For example, the semiconducting layer may include one or more materials such as: crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon substrate, patterned or unpatterned substrate, doped silicon, germanium, gallium, arsenide or other suitable semiconductive materials. In some embodiments, the semiconductor material is silicon. In some embodiments, the semiconductor material can be a doped material such as n-type doped silicon (n-silicon) or p-type doped silicon (p-silicon).

[0040] The superlattice structure 200 includes a plurality of first layers 204 and a corresponding plurality of second layers 206 arranged alternately in a plurality of stacked pairs. In one embodiment, the plurality of first layers 204 may be formed of a silicon-containing material. In one embodiment, the plurality of second layers 206 may be formed of at least a silicon-containing material and a germanium-containing material. Therefore, the first material layers 204 and the second material layers 206 are different materials. In some embodiments, the plurality of first material layers 204 and the corresponding plurality of second material layers 206 may be lattice-matched materials and have sufficient compositional differences so that selective layer removal or selective oxidation may be performed subsequently.

[0041] In various embodiments, the plurality of first layers 204 may include a Group IV material, such as silicon. The plurality of second layers 206 may also include a Group IV material, such as silicon germanium (SiGe). In other embodiments, the plurality of first layers 204 and the plurality of second layers 206 may include Group III-V materials, such as indium phosphide (InP) and indium gallium phosphide (InGaP), respectively. In some embodiments, the plurality of first layers 204 and the plurality of second layers 206 may be a plurality of pairs of lattice-matched materials. In some embodiments, the plurality of first layers 204 and the corresponding plurality of second layers 206 may be any number of lattice-matched material pairs suitable for forming a superlattice on the superlattice structure 200. For example, the plurality of first material layers 204 and the corresponding plurality of second material layers 206 may include between about 2 pairs and about 5 pairs of lattice-matched materials.

[0042] Material layer 210 and material layer 208 may also be included in a plurality of second material layers. Alternatively, material layer 208 may be considered a third material layer. Material layers 210 and 208 may be formed of the same material as second material 206 (such as silicon germanium). However, it is contemplated that the compositional properties of material layers 210 and 208 may differ in Si:Ge molar ratio.

[0043] In one example, the plurality of first layers 204 and the material layer 210 may have a silicon:germanium molar ratio between about 1:1 and about 5:1. In one embodiment, the silicon germanium material of the plurality of first layers 204 and the material layer 210 may have a germanium content between about 10% and about 50%, such as a germanium content between about 20% and about 40%. The silicon content may be between about 30% and about 90%, such as between about 50% and about 80%, for example, about 70%. Alternatively, the plurality of first material layers 204 may be formed of pure silicon material. In another example, the material layer 208 has a silicon:germanium molar ratio between about 1:1 and about 1:5. In one embodiment, the silicon germanium material of the material layer 208 may have a germanium content between about 20% and about 100%, such as a germanium content between about 50% and about 80%. The silicon content may be between about 0% and about 80%, such as between about 20% and about 40%.

[0044] The plurality of first layers 204, the plurality of second layers 206, and the material layers 210, 208 may be deposited using an epitaxial chemical vapor deposition process. Suitable precursors for forming the plurality of first layers 204, the plurality of second layers 206, and the material layers 210, 208 include SiH 4 and GeH 4 , etc. In some embodiments, the plurality of first layers 204 and the plurality of second layers 206 can be deposited at a sufficiently low temperature (e.g., between about 300 degrees Celsius and about 750 degrees Celsius) to prevent intermixing of different atomic species. As a result, the interface between different atomic species can be controlled, which provides advantageous control of the structure during a selective etching or modification process (such as an oxidation process).

[0045] The material layers of the superlattice structure 200 may have controlled thicknesses to provide substantially defect-free crystalline profiles of various materials. In some embodiments, the layers of the superlattice structure 200 may have a thickness between about 3 nm and about 50 nm. For example, the plurality of first layers 204 may have a thickness 220 between about 3 nm and about 10 nm, such as between about 5 nm and 7 nm, for example, about 6 nm. The plurality of second layers 206 may have a thickness 218 between about 5 nm and about 15 nm, such as between about 7 nm and 10 nm, for example, about 8 nm. The material layer 210 may have a thickness 214 between about 5 nm and about 15 nm, such as between about 8 nm and 12 nm, for example, about 10 nm. The material layer 208 may have a thickness 216 between about 5 nm and about 15 nm, such as between about 8 nm and 12 nm, for example, about 10 nm.

[0046] During formation of the superlattice structure 200 on the substrate 202, various material layers may be deposited in certain sequences to fabricate one or more devices within the superlattice structure 200. In one embodiment, the material layer 210 may be disposed on the substrate 202, and the material layer 208 may be disposed on the material layer 210. In another embodiment, the material layer 210 may be optional, such that the material layer 208 is disposed on the substrate 202.

[0047] The plurality of second layers 206 and the plurality of first layers 204 may be deposited in an alternating arrangement to form a stacked structure. In this embodiment, one of the second layers 206 may be disposed on the material layer 208, and one of the first layers 204 may be disposed on the one of the second layers 206. A hard mask layer 212 may also be disposed on the superlattice structure 200. In one embodiment, the hard mask layer 212 is disposed on one of the first layers 204. The hard mask layer 212 may be any suitable hard mask material, such as a silicon nitride material, etc.

[0048] Figure 3After performing patterning, etching and oxidation processes Figure 2 Schematic cross-sectional view of a portion of a substrate 202 and a superlattice structure 200. In one embodiment, the substrate 202 and the superlattice structure 200 may be patterned using a photolithography process, such as an extreme ultraviolet patterning process. In another embodiment, the substrate 202 and the superlattice structure 200 may be patterned using a self-aligned double or quadruple patterning process. The patterning process may be configured to allow the superlattice structure 200 to be formed with a channel width 302 between about 5 nm and about 15 nm (e.g., between about 7 nm and about 10 nm) after an etching process.

[0049] An exemplary etching process that can be used to etch the substrate 202 and the superlattice structure 200 is reactive ion etching (RIE), etc. In one embodiment, the RIE process can be performed using chlorine-based, bromine-based, or fluorine-based chemicals to anisotropically etch the substrate 202 and the superlattice structure 200.

[0050] The superlattice structure 200 formed on the substrate 202 may also be subjected to an oxidation process. The oxidation process may selectively oxidize one or more of the various material layers of the superlattice structure 200. Suitable oxidation processes include decoupled plasma oxidation processes, remote plasma oxidation processes, ultraviolet ozone oxidation processes, and free radical oxidation processes. For example, the oxidation process may selectively oxidize the material layer 208. The oxidation process may be configured such that layers with relatively low germanium content (e.g., the material layer 210 and the plurality of second layers 206) are not oxidized during this oxidation process, while providing oxidation of layers with relatively high germanium content (such as the material layer 208). After the selective oxidation, the material layer 208 is converted into a buried oxide (BOX) layer 308. In one embodiment, oxidizing the material layer 208 to form the BOX layer 308 may also include: oxidizing the material layer 210 as a result of the material layer being adjacent to the material layer 208. However, in this embodiment, the plurality of second layers 206 may remain substantially unoxidized.

[0051] In one embodiment, a free radical oxidation process may be used to form the BOX layer 308. The free radical oxidation process generally exposes the desired material to oxygen radicals so as to selectively oxidize the desired material layer. The substrate 202 and the superlattice structure 200 may be set in a processing environment configured to perform a free radical oxidation process. The temperature of the free radical oxidation process may be between about 500° C. and about 900° C., such as between about 600° C. and about 800° C., for example, about 700° C. The free radical oxidation process may be performed at a pressure between about 1 mTorr and about 760 Torr (such as between 1 Torr and 100 Torr, for example, 7 Torr). The free radical oxidation process may be performed for an amount of time sufficient to oxidize the high germanium content material layer. In one embodiment, the free radical oxidation process may be performed for an amount of time between about 1 second and about 60 seconds (such as between about 10 seconds and about 30 seconds, for example, about 20 seconds).

[0052] The precursors provided to the processing environment during the free radical oxidation process include oxygen-containing precursors and hydrogen-containing precursors. In one embodiment, the precursors may be provided in a ratio of about 50:1 (0 2 :H 2 ) to about 150:1 (such as, between about 90:1 and about 110:1, for example, about 100:1) 2 and H 2 In this embodiment, the O can be provided at a flow rate between about 10 slm and about 100 slm, such as between about 15 slm and about 30 slm, for example, between about 19 slm and about 20 slm. 2 H can be provided at a flow rate between about 0.1 slm and 1.0 slm, such as 0.2 slm. 2 In the foregoing embodiments, the processing environment may be configured to perform a radical oxidation process on a 300 mm substrate.

[0053] The free radical oxidation process according to the aforementioned embodiment can oxidize about 1 nm of material per second. For example, if the material layer 208 has a channel width 302 of about 40 nm, the oxidation process can be performed for about 20 seconds. It is believed that the oxidation of the material layer 208 continues from the sidewalls of the material layer 208 inward. Therefore, the oxidation time (t) to form the BOX layer 308 (using appropriate processing parameters) can generally be defined as t=n / 2, where n is the channel width 302. By performing selective oxidation to form the BOX layer 308 before subsequent processing operations, processing efficiency can be achieved. For example, the amount of time used to completely oxidize the BOX layer 308 can be reduced. In addition, since there are fewer materials and structures to be selected from when compared to the oxidation process performed during the subsequent processing operation, improved oxidation selectivity can be achieved. In addition, the BOX layer formation process can be performed without the need for a capping layer as required in various conventional processes.

[0054] Figure 4 After the liner formation process is performed Figure 3 2 and a schematic cross-sectional view of a portion of a substrate 202 and a superlattice structure 200. During the etching process described previously, the sidewalls of the superlattice structure 200 may be damaged. A liner deposition process may be performed to deposit a liner material 402 on the sidewalls of the superlattice structure 200 and at least a portion of the substrate 202.

[0055] The liner material deposition process may include several different operations for making the liner material 402. For example, a thermal oxidation process may be performed to deposit an oxide material on the sidewalls of the superlattice structure 200 (including the BOX layer 308) and the substrate 202. Subsequently, a nitridation process (such as a decoupled plasma nitridation process) may be performed to incorporate nitrogen into the oxide material to form an oxynitride material. Subsequently, the oxynitride liner material 402 may be subjected to a post-nitridation annealing process to further incorporate nitrogen into the oxide material. The post-nitridation annealing process may also heal defects that may be present in the liner material 402.

[0056] In one embodiment, the width 404 of the liner material 402 may be approximately About Between, such as, about About Between, for example, about It is contemplated that the liner material 402 may be suitable for preventing oxidation of the unoxidized material layer of the superlattice structure 200 during a subsequent shallow trench isolation process.

[0057] Figure 5 After performing a shallow trench isolation (STI) process Figure 4Schematic cross-sectional view of a portion of a substrate 202 and a superlattice structure 200. The STI process is generally performed to electrically isolate at least one of the substrate 202 and / or the superlattice structure 200 from a well having a different conductivity type (e.g., n-type or p-type) and / or an adjacent transistor feature (not shown) on the substrate 202. In one embodiment, the STI process can be a flowable CVD deposition process configured to deposit a dielectric material layer 502 (such as a silicon oxide material or a silicon nitride material). The dielectric material layer 502 can be formed using a high density plasma CVD system, a plasma enhanced CVD system, and / or a sub-atmospheric CVD system, etc. Examples of CVD systems that may be suitable for forming the dielectric material layer 502 include ULTIMA HDP System and ETERNA systems, both of which are available from Applied Materials, Inc. of Santa Clara, Calif. It is contemplated that other appropriately configured CVD systems from other manufacturers may also be utilized.

[0058] Figure 6 After the annealing process is performed Figure 5 2 and a schematic cross-sectional view of a portion of a substrate 202 and a superlattice structure 200. An annealing process may be performed to densify the dielectric material layer 502, thereby forming a densified dielectric material layer 602.

[0059] In one embodiment, the annealing process includes a steam annealing process. The steam annealing process may be performed at a temperature between about 300 degrees Celsius and about 800 degrees Celsius, such as between about 500 degrees Celsius and about 600 degrees Celsius. The steam annealing process may be performed for an amount of time between about 15 minutes and about 180 minutes, for example, about 120 minutes. The steam annealing process may also further oxidize the densified dielectric material layer 602.

[0060] In another embodiment, the annealing process may also include a dry annealing process. The dry annealing process may be performed at a temperature between about 500 degrees Celsius and about 1000 degrees Celsius, such as between about 650 degrees Celsius and about 750 degrees Celsius. The dry annealing process may be performed for an amount of time between about 1 minute and about 60 minutes, for example, about 30 minutes. In yet another embodiment, both a steam annealing process and a dry annealing process may be utilized. In this embodiment, the dry annealing process may be performed after the steam annealing process.

[0061] After performing one or more annealing processes, the substrate 202 may be planarized. More specifically, the densified dielectric material layer 602 may be polished, etched, or otherwise altered so that the top surface of the densified material layer 602 is substantially coplanar with the hard mask layer 212. In one embodiment, the hard mask layer 212 may be used as a stop indicator for a chemical mechanical polishing process. After planarizing the densified dielectric material layer 602, the hard mask layer 212 may also be removed from the superlattice structure 200.

[0062] Figure 7 After performing the STI recess process Figure 6 2 and a schematic cross-sectional view of a portion of the substrate 202 and the superlattice structure 200. The STI recess process is generally an etching process configured to remove at least a portion of the densified dielectric material layer 602. In one embodiment, the top surface 702 of the densified dielectric material layer 602 may be removed so that the top surface 702 is substantially coplanar with the BOX layer 308 or with an interface between one of the plurality of second layers 206 and the BOX layer 308. The STI recess process may also remove a portion of the liner material 402. In one embodiment, the STI recess process may be a remote plasma assisted dry etching process that exposes various materials disposed on the substrate 202 to H 2 NF 3 and NH 3 Plasma byproducts. The STI process is an overall conformal removal process and may be selective to silicon oxide materials and may not readily etch silicon. For example, the removal rate of the BOX layer 308 may be less than the removal rate of the densified dielectric material layer 602. The presence of the liner material 402 may further reduce or prevent etching of the BOX layer 308 during the STI recess process. Thus, over-etching or undercutting of the BOX material 308 may be reduced or eliminated during etching of the densified dielectric material layer 602. In one embodiment, the BOX layer 308 may be removed by removing the liner material 402 from the densified dielectric material layer 602. The STI recess process may be performed using an etch process and appropriately configured apparatus available from Applied Materials, Inc. of Santa Clara, Calif. It is contemplated that other suitable etch processes and apparatus may also be utilized to perform the STI recess process.

[0063] After the STI recess process is performed, subsequent hGAA or FinFET processing operations may be performed. Advantageously, the BOX layer 308 is self-aligned to the bottom region of the superlattice structure 200. The self-aligned BOX formation process described herein advantageously improves transistor device performance and reduces transistor device variability by reducing or eliminating parasitic capacitance and leakage. In addition, by forming the BOX layer 308 before depositing the dielectric material layer 502 or by forming the BOX layer after depositing the dielectric material layer 502, processing flexibility and efficiency in the formation of the BOX layer may be achieved.

[0064] Subsequent processing operations for forming hGAA and FinFET device structures generally include gate structure formation and source / drain formation. Figure 8 A schematic cross-sectional view of a substrate 202 and a superlattice structure 200 having a dummy gate structure 802 formed thereon is shown. The dummy gate structure 802 may be formed of one or more materials suitable for use as a placeholder for subsequent replacement metal gate formation. In one embodiment, the dummy gate structure 802 may be formed of a silicon-containing material such as amorphous silicon.

[0065] Fig. 9 The cross-sectional line 9-9 is shown rotated 90 degrees. Figure 8 , which depicts source / drain regions 902 formed on substrate 202 adjacent to superlattice structure 200. Source / drain regions 902 are generally deposited on substrate 202 such that source / drain regions 902 are coupled to superlattice structure 200 (which acts as a channel) and facilitate the flow of electrons and holes therebetween.

[0066] The source / drain regions 902 may be formed of a suitable material, such as a silicon-containing material, a doped silicon material, a composite silicon material, or a non-silicon-containing material. For example, the source / drain regions 902 may be silicon, phosphorus-doped silicon, a silicon germanium material, or germanium. It is contemplated that the type of source / drain region material may be selected in response to the desired n-type or p-type characteristics of the source / drain regions 902. The source / drain regions 902 may be deposited by a suitable deposition technique, such as a CVD technique or an epitaxial deposition technique.

[0067] In some embodiments, such as hGGA integration schemes, the plurality of second layers 206 and the dummy gate structure 802 may be replaced by a metal gate structure 904. The plurality of second layers 206 and the dummy gate structure 802 may be removed by a selective etching process, and the plurality of second layers 206 and the dummy gate structure 802 may present substantially different compositional properties relative to other layers of the superlattice structure 200. In some embodiments, the dummy gate structure 802 may be removed by a first etching process that is selective to the material of the dummy gate structure 802, and the plurality of second layers 206 may be removed by a second etching process that is selective to the material of the second layer 206. Alternatively, the dummy gate structure 802 and the plurality of second layers 206 may be removed by a single etching process. Although not shown, in some embodiments, a spacer material may be disposed between the source / drain region 902 and the metal gate structure 904. In one embodiment, the deposition of the spacer material may be performed before the source / drain region 902 is deposited.

[0068] Subsequently, a metal gate structure 904 is deposited in the area previously occupied by the dummy gate structure 802 and the plurality of second layers 206. In general, the metal gate structure 904 can be deposited by an appropriately configured epitaxial process, an atomic layer deposition (ALD) process, or a CVD process. Materials that can be used as the metal gate structure 904 generally exhibit a k value greater than about 3.9. Examples of materials with suitably high k values ​​include hafnium dioxide, zirconium dioxide, titanium dioxide, titanium nitride, titanium aluminide, and the like. In certain embodiments, various other nitride materials may also be utilized. In one embodiment, the above materials may be used to replace portions of the metal gate structure 904 of the plurality of second layers.

[0069] The portion of the metal gate structure 904 that replaces the dummy gate structure 802 may be formed of a metal-containing material and / or a conductive material. For example, suitable materials include titanium-containing materials (such as TiN or TiAlC) and tantalum-containing materials (such as TaN). Other suitable materials include refractory materials such as tungsten, ruthenium, rhenium, and the like. In some embodiments, the material used to form the plurality of portions of the metal structure 904 that replaces the plurality of second layers 206 and the dummy gate structure 802 may be the same or different from the above-mentioned materials. The type of material selected for the metal gate structure 904 may be determined by the transistor type (i.e., NMOS / PMOS).

[0070] In one embodiment, if the BOX layer 308 has not been previously oxidized, an oxidation process may be performed during and / or after forming the source / drain regions 902. Thus, process flexibility in forming the BOX layer 308 may be improved, which may provide more efficient BOX layer formation and improved device performance depending on the desired integration scheme. It is contemplated that hGAA and FinFET processing sequences, among others, may benefit from implementing the above-described BOX layer formation scheme (i.e., a BOX layer 308 formed prior to depositing the dielectric material layer 502 or a BOX layer 308 formed after depositing the dielectric material layer 502).

[0071] Fig.10 A schematic plan view of a cluster tool 1080 suitable for performing one or more portions of the present disclosure is shown. In general, the cluster tool 1080 is a modular system that includes multiple chambers (e.g., process chambers 1090A-D, maintenance chambers 1091A-B, etc.) that perform various functions, including: substrate centering and orientation, degassing, annealing, deposition, and / or etching.

[0072] The cluster tool 1080 may include at least a semiconductor substrate processing chamber configured to perform at least a plurality of portions of the method 100, and may further include chambers such as ion implantation chambers, etching chambers, deposition chambers, and the like. The plurality of chambers of the cluster tool 1080 are mounted to a vacuum transfer chamber 1088 that houses a robot 1089 adapted to fetch substrates between chambers. The vacuum transfer chamber 1088 is typically maintained under vacuum conditions and provides an intermediate stage for fetching substrates from one chamber to another and / or to a load lock chamber 1084 positioned at the front end of the cluster tool 1080. A front-end environment 1083 is shown positioned to selectively communicate with the load lock chamber 1084. A pod loader 1085 disposed in the front-end environment 1083 is capable of linear and rotational movement (arrow 1082) to fetch substrate cassettes between the load lock chamber 1084 and the plurality of pods 1087.

[0073] The cluster tool 1080 also includes a controller 1081 that is programmed to execute various processing methods performed in the cluster tool 1080. For example, the controller 1081 can be configured to control the flow of various precursor gases and process gases from gas sources, and control processing parameters associated with material deposition or etching processes. The controller 1081 includes a programmable central processing unit (CPU) 1079 (the CPU 1079 operates in conjunction with a memory 1077 and mass storage devices), an input control unit, and a display unit (not shown), such as power supplies, clocks, caches, input / output (I / O) circuits, which are coupled to various components of the cluster tool 1080 to facilitate control of substrate processing. The controller 1081 may also include hardware to monitor substrate processing in the cluster tool 1080 through sensors. Other sensors that measure system parameters (such as substrate temperature, chamber atmospheric pressure, etc.) may also provide information to the controller 1081.

[0074] To facilitate control of the cluster tool 1080 described above, the CPU 1079 may be one of various forms of general purpose computer processors (such as a programmable logic controller (PLC)) that may be used in industrial settings to control various chambers and sub-processors. A memory 1077 is coupled to the CPU 1079 and is non-transitory and may be one or more of readily available memories, such as random access memory (RAM), read-only memory (ROM), a floppy disk drive, a hard disk, or any form of digital storage device, local or remote. Support circuits 1075 are coupled to the CPU 1079 to support the processor in a conventional manner. Deposition, etching, and other processes are typically stored as software routines in the memory 1077. The software routines may be stored and / or executed by a second CPU (not shown) that is remote from the hardware controlled by the CPU 1079.

[0075] The memory 1077 is in the form of a computer-readable storage medium containing instructions that, when executed by the CPU 1079, facilitate the operation of the cluster tool 1080. The instructions in the memory 1077 are in the form of a program product, such as a program that implements the method of the present disclosure. The program code may conform to any of a variety of different programming languages. In one example, the present disclosure may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The (multiple) programs of the program product define the functions of the embodiments (including the methods described herein). Illustrative computer-readable storage media include, but are not limited to: (i) non-writable storage media on which information is permanently stored (e.g., a read-only memory device within a computer (such as a CD-ROM disk that can be read by a CD-ROM drive), a flash memory, a ROM chip, or any type of solid-state non-ceremonial semiconductor memory); and (ii) a writable storage medium on which changeable information is stored (e.g., a floppy disk within a disk drive, or a hard disk, or any type of solid-state random access semiconductor memory). When carrying computer-readable instructions that indicate the functions of the methods described herein, such computer-readable storage media are embodiments of the present disclosure.

[0076] To practice embodiments of the present disclosure, at least one of the processor chambers of cluster tool 1080 (e.g., 1090A) may be configured to perform an etching process, a second processing chamber (e.g., 1090B) may be configured to perform a cleaning process, and a third processing chamber (e.g., 1090C) may be configured to perform an epitaxial deposition process. A cluster tool having the stated configuration advantageously prevents undesirable oxidation after etching the source / drain recesses and reduces or eliminates subsequent cleaning of the oxidized surfaces prior to epitaxial deposition. In some embodiments, at least one of the processing chambers of cluster tool 1080 (e.g., 1090A) may be configured to perform a selective etching process, and a second processing chamber (e.g., 1090B) may be configured to perform a deposition process (e.g., depositing a dielectric material). A cluster tool having the stated configuration advantageously prevents oxidation of the channel structure after exposure of the hGAA or FinFET channel.

[0077] Fig.11A cross-sectional view of a device structure 1100 that may be formed and / or implemented in a device according to embodiments described herein is schematically shown. The device structure 1100 may generally be viewed as an additional embodiment of the superlattice structure defined above. In one embodiment, the device structure 1100 may be formed on a substrate 202. In one embodiment, the device structure 1100 may include: a material layer 210 disposed on the substrate 202, a BOX layer 308 disposed on the material layer 210, and a single first layer 204 disposed on the BOX layer 308. In another embodiment, the device structure 1100 may include a BOX layer 308 disposed directly on the substrate 202 and a single first layer 204 disposed on the BOX layer 308. In this embodiment, there is no material layer 210 between the substrate 202 and the BOX layer 308.

[0078] Suitable materials for the single first layer 204 include silicon-containing materials, such as pure silicon or doped silicon materials. Other materials suitable for forming the single first layer 204 include silicon germanium materials. For example, the silicon germanium material may include between about 20% and about 40% silicon germanium and between about 60% and 80% silicon. It is contemplated that the device structure 1100 may be advantageously utilized in a FinFET integration scheme. Figure 1 as well as Figure 3-7 The device structure 1100 may also be processed according to the operations described in Figure 8-9 The device structure 1100 is implemented according to the disclosure without processing operations involving replacing the plurality of second layers 206 .

[0079] Fig.12 Shows the merged Fig.11 A schematic cross-sectional view of a device of a device structure 1100 is shown. As shown in the figure, according to the above Figure 8-9 The device structure 1100 is processed based on the disclosure of the present invention to form a device including source / drain 902 and metal gate structure 904. It is contemplated that the reference 1100 may be advantageously implemented for forming a FinFET type device. Fig.12 The described embodiments can also be advantageously implemented for forming hGAA type devices. Fig. 9 However, embodiments from both FinFET and hGAA schemes may be utilized individually or in combination to form a device structure that exhibits improved process flexibility when forming the BOX layer 308 and provides more efficient BOX layer formation and improved device performance.

[0080] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A method for forming a semiconductor device, the method The following steps are involved: A superlattice structure is formed on a substrate, wherein the superlattice structure comprises: a silicon-containing material layer; a first silicon germanium material layer having a first germanium content, wherein the silicon-containing material layer and the first silicon germanium material layer are disposed in an alternating stacked arrangement within the superlattice structure; and a second silicon germanium material layer, the second silicon germanium material layer having a second germanium content greater than the first germanium content of the first silicon germanium material layer, wherein the second silicon germanium material layer is disposed on the substrate; etching the superlattice structure; depositing a liner on the superlattice structure; After depositing the liner layer, depositing an oxide material layer on the substrate; and The second silicon germanium material layer is oxidized after depositing the oxide material layer to form a buried oxide layer, wherein the liner layer selectively prevents oxidation of the silicon-containing material layer and the first silicon germanium material layer. 2 . The method of claim 1 , wherein the first silicon germanium material layer comprises 70% silicon and 30% germanium, and the second silicon germanium material layer comprises 30% silicon and 70% germanium. The method of claim 1 , wherein the substrate comprises a silicon-containing material.

4. The method of claim 1, wherein the liner is deposited include: A chemical vapor deposition nitridation process is performed.

5. The method of claim 1, wherein the liner is deposited include: Perform an atomic layer deposition nitridation process.

6. The method of claim 1, wherein the oxide material layer is deposited include: A flowable chemical vapor deposition process is performed to deposit the oxide material layer.

7. The method of claim 1, wherein the oxidation include: The steam annealing process is performed at a temperature between 300°C and 800°C.

8. The method of claim 7, further comprising: include: A dry annealing process is performed after the steam annealing process, the dry annealing process being performed at a temperature between 500°C and 1000°C.

9. A method for forming a semiconductor device, the method The following steps are involved: A superlattice structure is formed on a substrate, wherein the superlattice structure comprises: Silicon material layer; a low germanium content silicon germanium material layer, wherein the silicon material layer and the low germanium content silicon germanium material layer are disposed in the superlattice structure in an alternating stacking arrangement; and A silicon germanium material layer with a high germanium content, wherein the silicon germanium material layer with a high germanium content is disposed on the substrate; etching the superlattice structure; depositing a nitride liner on the superlattice structure; After depositing the nitride liner, depositing an oxide material layer on the substrate; and The high germanium content silicon germanium material layer is oxidized after depositing the oxide material layer to form a buried oxide layer, wherein the nitride liner selectively prevents oxidation of the silicon material layer and the low germanium content silicon germanium material layer. 10 . The method of claim 9 , wherein the low germanium content silicon germanium material layer comprises 70% silicon and 30% germanium, and the high germanium content silicon germanium material layer comprises 30% silicon and 70% germanium.

11. The method according to claim 9, wherein the high germanium content silicon germanium material layer is oxidized include: performing a steam annealing process at a temperature between 300° C. and 800° C.; as well as After the steam annealing process, a dry annealing process is performed at a temperature between 500°C and 1000°C.

12. A method for forming a semiconductor device, the method The following steps are involved: A superlattice structure is formed on a substrate, wherein the superlattice structure comprises: Silicon material layer; A first silicon germanium material layer comprising 30% germanium; and a second silicon germanium material layer comprising 70% germanium, wherein the silicon material layer, the first silicon germanium material layer and the second silicon germanium material layer are arranged in a stacked arrangement, wherein the silicon material layer and the first silicon germanium material layer are arranged in an alternating stacked arrangement within the superlattice structure, and wherein the second silicon germanium material layer is arranged on the substrate; depositing a nitride liner on the superlattice structure; After depositing the nitride liner, depositing an oxide material layer on the substrate; and The second silicon germanium material layer is oxidized after depositing the oxide material layer to form a buried oxide layer, wherein the nitride liner selectively prevents oxidation of the silicon material layer and the first silicon germanium material layer.

13. The method according to claim 12, wherein the second silicon germanium material layer is oxidized include: The steam annealing process is performed at a temperature between 300°C and 800°C.

14. The method of claim 13, further comprising: The following steps are involved: After the steam annealing process, a dry annealing process is performed at a temperature between 500°C and 1000°C.

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