Capacitor array, memory cell array, method for forming capacitor array, and method for forming memory cell array

Abstract

A method of forming a capacitor array includes forming a plurality of horizontally spaced groups, the plurality of horizontally spaced groups individually including a plurality of horizontally spaced lower capacitor electrodes having a capacitor insulator thereon. Adjacent ones in the groups are horizontally spaced farther apart than adjacent ones in the lower capacitor electrodes within the group. A void space is located between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the group above the capacitor insulator and the lower capacitor electrode. The upper capacitor electrode material in the void space is connected to the upper capacitor electrode material in the adjacent group relative to each other. The upper capacitor electrode material does not fill the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent group relative to each other. A horizontally elongated conductive line is formed on top of the upper capacitor electrode material in the individual ones of the groups, the horizontally elongated conductive line being directly electrically coupled to the upper capacitor electrode material. Other methods are disclosed, including structures that do not rely on manufacturing methods.

Description

Technical Field

[0001] Embodiments disclosed herein relate to capacitor arrays, to memory cell arrays, to methods of forming capacitor arrays, and to methods of forming memory cell arrays. Background Art

[0002] Memory is a type of integrated circuit system and is used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read using digit lines (which may also be called bit lines, data lines, or sense lines) and access lines (which may also be called word lines). The digit lines conductively interconnect memory cells along the columns of the array, and the access lines conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of digit lines and access lines.

[0003] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for an extended period of time in the absence of power. Non-volatile memory is conventionally specified as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. Regardless, the memory cell is configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0004] A capacitor is a type of electronic component that can be used in a memory cell. A capacitor has two electrical conductors separated by an electrically insulating material. Energy as an electric field can be stored electrostatically within this material. Depending on the composition of the insulator material, the stored field will be either volatile or non-volatile. For example, a capacitor insulator material that only includes SiO2 will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor having a ferroelectric material as at least a portion of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and can thereby include programmable materials for capacitors and / or memory cells. The polarization state of a ferroelectric material can be changed by applying a suitable programming voltage and remains unchanged after the programming voltage is removed (at least for a period of time). Each polarization state has a different charge storage capacitance from one another, and the charge storage capacitance can ideally be used to write (i.e., store) and read a memory state without reversing the polarization state until it is desired to reverse this polarization state. Less desirable is that in a memory having a ferroelectric capacitor, the act of reading a memory state can reverse the polarization. Thus, upon determining the polarization state, rewriting of the memory cell is performed to place the memory cell in a pre-read state immediately following the determination of the polarization state. Regardless, memory cells incorporating ferroelectric capacitors are ideally non-volatile due to the bistable nature of the ferroelectric material forming part of the capacitor. Other programmable materials may be used as capacitor insulators to render the capacitor non-volatile.

[0005] Field effect transistors are another type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures (for example, a reversibly programmable charge storage region) as part of the gate construction between the gate insulator and the conductive gate. In any case, the gate insulator may be programmable, for example, ferroelectric.

[0006] Of course, capacitors and transistors may be used in integrated circuit systems other than memory circuitry. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagrammatic cross-sectional view of a portion of a construction in a process according to some embodiments of the present invention and is a cross-sectional view through Figure 3 Intercepted by line 1-1 in.

[0008] Figure 2 It passes through Figure 3 A view taken along line 2-2 in FIG.

[0009] Figure 3 It passes through Figure 1 and 2 A view taken along line 3-3 in FIG.

[0010] Figure 4 It passes through Figure 1 and 2 A view taken along line 4-4 in FIG.

[0011] Figure 5 In succession Figure 1 The processing steps after the processing steps shown Figure 1 A partial view of the structure and through Figure 6 Intercepted by line 5-5.

[0012] Figure 6 It passes through Figure 5 A view taken along line 6-6 in FIG.

[0013] Figure 7 In succession Figure 5 The processing steps after the processing steps shown Figure 5 The constructed view is through Figure 8 Intercepted by line 7-7 in.

[0014] Figure 8 It passes through Figure 7 A view taken along line 8-8 in FIG.

[0015] Fig. 9 In succession Figure 7 The processing steps after the processing steps shown Figure 7 The constructed view is through Fig.10 Intercepted by line 9-9 in.

[0016] Fig.11 It passes through Fig.10 A view taken along line 11-11 in FIG.

[0017] Fig.12 In succession Fig. 9 The processing steps after the processing steps shown Fig. 9 The constructed view is through Fig.13 Intercepted at line 12-12 in FIG.

[0018] Fig.13 It passes through Fig.12 A view taken along line 13-13 in FIG.

[0019] Fig.14 In succession Fig.12 The processing steps after the processing steps shown Fig.12 The constructed view is through Fig.15 Intercepted at line 14-14 in FIG.

[0020] Fig.15 It passes through Fig.14 A view taken along line 15-15 in FIG.

[0021] Fig.16 In succession Fig.14 The processing steps after the processing steps shown Fig.14 The constructed view is through Fig.17 The line 16-16 in FIG.

[0022] Fig.17 It passes through Fig.16 A view taken along line 17-17 in FIG.

[0023] Fig.18 In succession Fig.16 The processing steps after the processing steps shown Fig.16 The constructed view is through Fig.19 Intercepted at line 18-18 in FIG.

[0024] Fig.19 It passes through Fig.18 , 21 and the view taken along line 19-19 in 22 .

[0025] Fig. 20 It passes through Fig.18 , 19 , 21 and 22 are views taken along line 20-20.

[0026] Fig.21 It passes through Fig.19 and 20 A view taken along line 21-21 in FIG.

[0027] Fig. 22 It passes through Fig.19 and 20 A view taken along line 22-22 in FIG. DETAILED DESCRIPTION

[0028] Embodiments of the present invention include capacitor arrays, memory cell arrays, methods of forming capacitor arrays, and methods of forming memory cell arrays. Figures 1 to 22 Example method embodiments are described.

[0029] refer to Figures 1 to 4, such figures show a portion of a substrate construction 10 including a base substrate 11 including any one or more of conductive / conductor / conductive, semiconductive / semiconductor / semiconductive, and insulating / insulator / insulating (i.e., electrical in this context) materials. Various materials have been vertically formed above and within the base substrate 11. The materials may be Figures 1 to 4 Beside the depicted material, Figures 1 to 4 The material depicted is directed vertically inward or from Figures 1 to 4 The depicted material is vertically outward. For example, other partially or completely fabricated components of the integrated circuit system may be disposed on, around, or somewhere within the base substrate 11. Controls and / or other peripheral circuitry for operating components within the capacitor and / or memory cell array may also be fabricated and may or may not be completely or partially located within the array or sub-array. In addition, multiple sub-arrays may also be fabricated and operated independently, jointly, or otherwise relative to each other. As used in this document, a "sub-array" may also be considered an array.

[0030] Rows 14 and columns 16 of transistors 18 (which in one embodiment are vertical transistors) have been formed relative to or within substrate 11. Access lines 20 ( Figure 4 ) interconnects a plurality of transistors 18 along individual rows 14 in a row direction 24. In an exemplary embodiment, access lines 20 are individually shown, formed as a pair of lines running on opposite sides of a channel region 15 of an individual transistor 18, with a gate insulator 17 located between the channel region 15 and the conductive material of the access lines 20. Transistors 18 individually include lower source / drain regions 30 and upper source / drain regions 32. Digit lines 26 interconnect a plurality of transistors 18 along individual columns 16 in a column direction 28. Individual lower source / drain regions 30 are directly electrically coupled to individual digit lines 26. Dielectric material 12 (e.g., silicon dioxide and / or silicon nitride) is shown surrounding transistors 18 and digit lines 26.

[0031] A plurality of horizontally spaced groups 34, individually including a plurality of horizontally spaced lower capacitor electrodes 36, have been formed over the base substrate 11. In one embodiment, the individual lower capacitor electrodes 36 are directly over and electrically coupled to the individual upper source / drain regions 32 of the individual transistors 18. An example conductive material 38 (e.g., a metal material) is shown having a composition different from that of the upper source / drain regions 32 and the lower capacitor electrodes 36, and the example conductive material 38 may be considered to be a portion of one or both of the upper source / drain regions 32 and the lower capacitor electrodes 36. In one embodiment and as shown, the lower capacitor electrodes 36 in the individual groups 34 are arranged in horizontally elongated rows (e.g., row 14) in a row direction (e.g., 24) orthogonal to the column direction (e.g., 28). In one such embodiment and as shown, the lower capacitor electrodes 36 in the individual groups 34 are arranged in a 2D Bravais lattice, and in one such embodiment, the 2D Bravais lattice is rectangular or square. The depicted portions of groups 34 are individually shown as including sixteen lower capacitor electrodes 36, but fewer or most likely many more such lower capacitor electrodes will be located both horizontally and vertically within individual groups 34, as in FIG. Figure 1 and 2 Regardless and in one embodiment, the groups 34 are individually elongated horizontally, for example, as shown in the column direction 28. Figures 1 to 4 Only two example groups 34 are shown, but most likely many more such groups than two will be formed.

[0032] Adjacent groups 34 are horizontally spaced farther apart (eg, dimension D1) than adjacent lower capacitor electrodes 36 within groups 34 (eg, Figure 2 3 and 4). The material of the lower capacitor electrode 36 may include any existing or yet to be developed conductive material. In one embodiment and as shown, the lower capacitor electrode 36 is a pillar. Material 40 (e.g., silicon dioxide or polysilicon) (and in one embodiment, it is completely sacrificial) and material 44 (e.g., silicon nitride) are shown as being received around the lower capacitor electrode 36, with the example material 40 being located in the gaps between the individual groups 34. Another material 42 (e.g., silicon nitride) is shown as being received around the lower capacitor electrode 36 within the group 34. Material 42 may be used as a support structure to facilitate maintaining the lower capacitor electrode 36 in an upright manner during the fabrication of the capacitor and / or memory cell array, and is otherwise not important to the present invention (as is material 44). One or more additional layers (not shown) of support material 42 may be disposed between the top and bottom of the lower capacitor electrode 36 within the individual groups 34.

[0033] refer to Figure 5 and 6 , openings 46 have been formed through material 42 to provide access to sacrificial material 40 in group 34 below openings 46. The relative diameters of lower capacitor electrode 36, openings 46, and the spaces between the lower capacitor electrodes may be the same, larger, or smaller than one another. Figure 3 and 4 In comparison, Figure 6 and one Some other vertical cross-sectional views are compiled below materials 38, 44 and 40.

[0034] Figure 7 and 8 Subsequent processing is shown whereby sacrificial material 40 (not shown) has been removed (e.g., by isotropic wet etching selectively relative to lower capacitor electrodes 36 and materials 12, 42, and 44). This operation has formed void spaces 48 between adjacent groups 34, which in the depicted example embodiment are horizontally elongated in the column direction 28. In one embodiment, the minimum width of void spaces 48 in the row direction 24 (e.g., D1) is at least twice the maximum pitch (e.g., P) of lower capacitor electrodes 36 in the row direction 24. Void spaces 48 may be considered to include sidewalls 49 and a base 52.

[0035] refer to Figures 9 to 11 , a capacitor insulator 50 has been formed over the lower capacitor electrode 36. This capacitor insulator 50 may include any existing or yet to be developed insulator material (e.g., silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, etc.), and in one embodiment the capacitor insulator 50 is ferroelectric (e.g., any existing or yet to be developed ferroelectric material). In one embodiment and as shown, the capacitor insulator 50 extends laterally across the base 52 of the void space 48 and in one embodiment extends laterally across the base 52 entirely, and in one embodiment, the thickness of the capacitor insulator 50 is less than the horizontal thickness of the individual lower capacitor electrodes 36.

[0036] refer to Fig.12 and 13, an upper capacitor electrode material 58 (e.g., TiN) has been formed in the void spaces 48 and over the capacitor insulator 50 and lower capacitor electrodes 36 in the groups 34. The upper capacitor electrode material 58 in the void spaces 48 is connected to the upper capacitor material 58 in the adjacent groups 34 relative to each other and does not fill the void spaces 48. In one embodiment, the upper capacitor electrode material 58 has a thickness of no more than one-third of the minimum horizontal width (e.g., D1) of the void spaces 48 (in one such embodiment no more than one-quarter of this minimum horizontal width, and in one such embodiment no more than one-fifth of this minimum horizontal width). The upper capacitor electrode material 58 may fill (not shown) all of the space between the lower capacitor electrodes 36 surrounded by the capacitor insulator 50. In one embodiment and as shown, the upper capacitor electrode material 58 is along the sidewalls 49 of the void spaces 48.

[0037] refer to Fig.14 and 15 , at least a portion of upper capacitor electrode material 58 has been removed from void spaces 48 (e.g., by anisotropic etching) to disconnect upper capacitor electrode material 58 in adjacent groups 34 relative to each other. In one such embodiment, this removal occurs by anisotropic etching without a mask over groups 34 and void spaces 48 (e.g., although masking material [not shown] may cover other portions of the construction that do not include such groups and void spaces). In one embodiment, upper capacitor electrode material 58 is formed on that portion of capacitor insulator 50 that extends laterally across base 52 of void spaces 48 (e.g., Fig.13 In one such exemplary embodiment, the maskless anisotropic etch is performed from a central portion of the portion 70 of the capacitor insulator 50 extending laterally from the base 52 across the void space 48 (e.g., Fig.13 and 155. In one embodiment and as shown, the upper capacitor electrode material 58 is removed from the void space 48 above the central portion 72 in the individual groups 34. In one embodiment and as shown, the upper capacitor electrode material 58 is formed along the sidewalls 49 of the void space 48, wherein the maskless anisotropic etch leaves the portion of the upper capacitor electrode material 58 along the sidewalls 49 directly above the remaining opposite non-central portion of the portion 70 of the capacitor insulator extending laterally across the base 52 of the void space 48. Regardless, and in one embodiment and as shown, the action of removing material 58 from the void space 48 to disconnect it from being connected between adjacent groups 34 causes the upper capacitor electrode material 58 to form into an upper capacitor electrode 60 common to all capacitors within the individual groups 34. Such example capacitors 75 within the groups 34 individually include one of the lower capacitor electrodes 36 in the respective individual groups 34, the capacitor insulator 50, and the common upper capacitor electrode 60 (e.g., sixteen example capacitors 75 are shown within the individual groups 34). In one example embodiment and as shown, an array 90 of capacitors 75 has been formed.

[0038] refer to Fig.16 and 17 And in one embodiment, the remaining volume of void space 48 has been filled with insulating material 64 (e.g., silicon nitride and / or silicon dioxide). In one such embodiment, this operation can be performed by initially overfilling the remaining volume of void space 48 with insulating material 64 and then subsequently planarizing this insulating material 64 back to at least the vertical outermost surface of capacitor insulator 50.

[0039] refer to Figures 18 to 22 , a horizontally elongated conductive line 68 (e.g., comprising conductive material 66) has been formed on top of and electrically coupled directly to the upper capacitor electrode material 58 in the individual groups 34. In one embodiment and as shown, the horizontally elongated conductive line 68 is formed directly against the capacitor insulator 50 and directly against the upper capacitor electrode material 58 in the individual groups 34, as shown. In one embodiment and as shown, a portion of the horizontally elongated conductive line 68 is formed directly over the insulating material 64, and in one embodiment is formed directly against the insulating material 64.

[0040] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used with respect to the embodiments described above.

[0041] An embodiment of the present invention includes a method of forming an array (e.g., 90) of capacitors (e.g., 75) independent of whether the capacitors comprise a portion of a memory array and independent of whether the capacitors are formed relative to transistors that have been previously formed thereunder. This embodiment includes forming a plurality of horizontally spaced groups (e.g., 34) that individually include a plurality of horizontally spaced lower capacitor electrodes (e.g., 36) with a capacitor insulator (e.g., 50) thereover. Neighbors in a group are horizontally spaced farther apart (e.g., D1) than neighbors in the lower capacitor electrodes within the group (e.g., D2 and D3 considered individually). Void spaces (e.g., 48) are located between adjacent groups. Upper capacitor electrode material (e.g., 58) is formed in the void spaces and in the group over the capacitor insulator and the lower capacitor electrode. The upper capacitor electrode material in the void spaces is connected to the upper capacitor electrode material in the adjacent groups relative to each other. The upper capacitor electrode material does not fill the void spaces. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in adjacent groups relative to each other (e.g., at least partially removed from being connected in the void space). Horizontally elongated conductive lines (e.g., 68) are formed on top of the upper capacitor electrode material in the individual ones of the groups, the horizontally elongated conductive lines being directly electrically coupled to the upper capacitor electrode material. In one embodiment, a plurality of transistors (e.g., 18) are formed, wherein the transistors are individually directly electrically coupled to the individual ones of the lower capacitor electrodes, and in one such embodiment those transistors are vertical transistors. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0042] At least some method embodiments of the present invention may facilitate easier removal of upper capacitor electrode material 58 than would be the case with filled void spaces 48 .

[0043] Embodiments of the present invention encompass structures and / or devices that are independent of manufacturing methods. However, such structures and / or devices may have any of the properties described in the method embodiments as described herein. Likewise, the method embodiments described above may incorporate and form any of the properties described with respect to the structure and / or device embodiments.

[0044] Embodiments of the present invention include an array (e.g., 90) of capacitors (e.g., 75) that is independent of manufacturing methods. This array includes multiple horizontally spaced groups (e.g., 34), each of which includes multiple horizontally spaced lower capacitor electrodes (e.g., 36). Neighbors in a group are horizontally spaced farther apart (e.g., D1) than neighbors in the lower capacitor electrodes within the group (e.g., D2 and D3 considered individually). A capacitor insulator (e.g., 50) is above the lower capacitor electrodes. An upper capacitor electrode (e.g., 60) is common to all capacitors in the individual ones of the groups. The capacitors in the individual groups individually include one of the lower capacitor electrodes in the corresponding individual groups, a capacitor insulator, and a common upper capacitor electrode. A horizontally elongated conductive line (e.g., 68) is located on top of the upper capacitor electrode in the individual group and is directly electrically coupled to the upper capacitor electrode. In one embodiment, the array further includes an array of transistors (e.g., 18) below the capacitor array (e.g., Figures 19 to 21 92 in ), wherein the transistors are individually directly electrically coupled to individual ones of the lower capacitor electrodes. In one embodiment, the invention includes an array (e.g., 94) of memory cells (e.g., 95, and there would be sixteen of them in the depicted embodiment showing sixteen capacitors) that individually include one of the capacitors and one of the transistors. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0045] Embodiments of the present invention encompass an array (e.g., 94) of ferroelectric memory cells (e.g., 95) that individually include ferroelectric capacitors (e.g., 75) above transistors (e.g., 18). This array includes vertical rows (e.g., 14) and columns (e.g., 16) of transistors (e.g., 18). Access lines (e.g., 20) interconnect multiple transistors of the transistors along the individual ones of the rows in a row direction (e.g., 24), and digit lines (e.g., 26) interconnect multiple transistors of the transistors along the individual ones of the columns in a column direction (e.g., 28). The transistors individually include lower source / drain regions (e.g., 30) that are directly electrically coupled to individual ones of the digit lines. The transistors individually include upper source / drain regions (e.g., 32). Multiple horizontally spaced groups (e.g., 34) individually include multiple horizontally spaced lower capacitor electrodes (e.g., 36). Individuals of the lower capacitor electrodes are directly located above and electrically coupled to the individuals in the upper source / drain regions. Adjacents in a group are horizontally spaced apart from each other by a gap (e.g., spanning D1) that is larger than the horizontal spacing between adjacent lower capacitor electrodes within the group (e.g., D2 and D3 considered individually). The gap is horizontally elongated in the column direction. A ferroelectric capacitor insulator (e.g., 50) is above the lower capacitor electrode. An upper capacitor electrode (e.g., 60) is common to all capacitors in the individuals in the group. The capacitors in individual groups (e.g., 75) individually include one of the lower capacitor electrodes in the respective individual groups, a capacitor insulator, and a common upper capacitor electrode. A horizontally elongated conductive line (e.g., 68) is located on top of the upper capacitor electrode in the individual group and electrically coupled to the upper capacitor electrode. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0046] The above processing or construction may be considered to be relative to an array of components formed as or within a single stack or single layer of such components on or as part of an underlying base substrate (although a single stack / layer may have multiple levels). Controls and / or other peripheral circuitry for operating or accessing such components within the array may also be formed at any location as part of the completed construction, and in some embodiments may be below the array (e.g., CMOS below the array). Regardless, one or more additional such stacks / layers may be disposed or fabricated above and / or below the stacks / layers shown in the figures or described above. Furthermore, the array of components may be the same or different relative to each other in different stacks / layers. Intervening structures may be disposed between immediately vertically adjacent stacks / layers (e.g., additional circuitry and / or dielectric layers). Moreover, different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., above and below each other), or two or more stacks / layers may be fabricated at substantially the same time.

[0047] The assemblies and structures discussed above may be used in integrated circuits / circuitry systems and may be incorporated into electronic systems. For example, such electronic systems may be used in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic systems may be any of a wide range of systems (e.g., cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.).

[0048] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "on top", "bottom", "above", "below", "beneath", "under", "upward", and "downward" are generally referenced to vertical directions. "Horizontal" refers to a general direction along the main substrate surface (i.e., within 10 degrees) and relative to which the substrate can be processed during fabrication, and vertical is a direction generally orthogonal to horizontal. Reference to "completely horizontal" is a direction along the main substrate surface (i.e., no angle with the main substrate surface) and relative to which the substrate can be processed during fabrication. Furthermore, as used herein, "vertical" and "horizontal" are generally vertical directions relative to each other and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to directions that are at least 45° apart from a completely horizontal angle. Furthermore, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending" and the like with respect to a field effect transistor are referenced to the orientation of the channel length of the transistor, along which current flows between the source / drain regions in operation. For bipolar junction transistors, "vertically extending", "vertically extending", horizontally extending, and horizontally extending are referenced to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or at a deviation of no more than 10° from vertical.

[0049] Furthermore, "directly above," "directly below," and "directly below" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Also, "above" used without being preceded by "directly" requires only that some portion of the stated area / material / component that is above the other portion is vertically outward from the other portion (i.e., independent of whether there is any lateral overlap of the two stated areas / materials / components). Similarly, "below" and "beneath" used without being preceded by "directly" require only that some portion of the stated area / material / component that is below / beneath the other portion is vertically inward from the other portion (i.e., independent of whether there is any lateral overlap of the two stated areas / materials / components).

[0050] Any of the materials, regions, and structures described herein may be homogeneous or inhomogeneous, and in any case may be continuous or discontinuous over any material overlying such material. Where one or more exemplary compositions are provided for any material, the material may include, consist essentially of, or consist of such one or more compositions. Furthermore, unless otherwise stated, each material is formed using any suitable technique now known or yet to be developed, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0051] In addition, "thickness" itself (without a directional adjective in front) is defined as the average straight-line distance perpendicularly through a given material or region from the closest surface of the immediately adjacent material or immediately adjacent region of different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, the thickness refers to the average thickness (unless otherwise indicated), and this material or region will have a certain minimum thickness and a certain maximum thickness due to the variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different (for example, if such materials or regions are not homogeneous). If the two stated materials or regions do not directly abut against each other, "different compositions" only require that those parts of the two materials or regions that are closest to each other are chemically and / or physically different (if such materials or regions are not homogeneous). In this document, a material, region or structure "directly abuts" another when there is at least one physical touch contact of the stated materials, regions or structures relative to each other. In contrast, “over,” “on,” “adjacent,” “along,” and “against” without being preceded by “directly” encompasses “directly against” as well as configurations in which intervening materials, regions, or structures do not result in physical touching contact of the stated materials, regions, or structures relative to each other.

[0052] As used herein, region-material-components are "electrically coupled" with respect to one another if, in normal operation, electrical current is able to flow continuously from one region-material-component to another region-material-component and does so primarily through the movement of subatomic positive and / or negative charges (when such subatomic positive and / or negative charges are sufficiently generated). Another electronic component may be located between the region-material-components and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0053] The conductive / conductor / composition of any of the conductive materials herein may be a metallic material and / or a conductively doped semiconductive / semiconductor / semiconductive material. "Metallic material" is any one of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds, or any combination thereof.

[0054] As used herein, "selectivity" with respect to etching, etching, removing, removal, depositing, forming, and / or formation is such action that one stated material is acted upon at a volume ratio of at least 2:1 relative to another (further) stated material. Additionally, selectively depositing, selectively growing, or selectively forming is such that one material is deposited, grown, or formed relative to another or further stated material at a volume ratio of at least 2:1 within at least the first 75 angstroms of deposition, growth, or formation.

[0055] As used herein, "or" includes either or both unless otherwise indicated.

[0056] In this document, "row" and "column" are used for the convenience of distinguishing one set of features or orientation from another set of features or orientation, and along which the components have been or will be formed. "Row" and "column" are used synonymously with respect to any set of regions, components and / or features that are independent of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, just like columns. In addition, rows and columns can cross at 90° or at one or more other angles relative to each other.

[0057] in conclusion

[0058] In some embodiments, a method of forming a capacitor array includes forming a plurality of horizontally spaced groups, each of which individually includes a plurality of horizontally spaced lower capacitor electrodes having a capacitor insulator above them. Neighbors in the groups are horizontally spaced farther apart than neighbors in the lower capacitor electrodes within the group. A void space is located between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the group above the capacitor insulator and the lower capacitor electrode. The upper capacitor electrode material in the void space is connected to the upper capacitor electrode material in the adjacent group relative to each other. The upper capacitor electrode material does not fill the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent group relative to each other. A horizontally elongated conductive line is formed on top of the upper capacitor electrode material in the individual of the groups, the horizontally elongated conductive line being directly electrically coupled to the upper capacitor electrode material.

[0059] In some embodiments, a method of forming an array of ferroelectric memory cells that individually include ferroelectric capacitors above transistors includes forming vertical rows and columns of transistors relative to a substrate. Access lines interconnect multiple transistors of the transistors along the individual ones of the rows in a row direction. Digital lines interconnect multiple transistors of the transistors along the individual ones of the columns in a column direction. The transistors individually include lower source / drain regions that are directly electrically coupled to the individual ones of the digital lines. The transistors individually include upper source / drain regions. A plurality of horizontally spaced groups are formed, the plurality of horizontally spaced groups individually including a plurality of horizontally spaced lower capacitor electrodes having a ferroelectric capacitor insulator above. Individual ones of the lower capacitor electrodes are directly above and electrically coupled to the individual ones of the upper source / drain regions. Neighbors in the group are horizontally spaced farther apart than neighbors of the lower capacitor electrodes within the group. A void space is horizontally elongated in the column direction and is located between the adjacent groups. An upper capacitor electrode material is formed in the void space and in the group over the capacitor insulator and the lower capacitor electrode. The upper capacitor electrode material in the void space is connected to the upper capacitor electrode material in the adjacent group relative to each other. The upper capacitor electrode material does not fill the void space. At least a portion of the upper capacitor electrode material is removed from the void space to disconnect the upper capacitor electrode material in the adjacent group relative to each other. A horizontally elongated conductive line is formed on top of the upper capacitor electrode material in the individual ones of the groups, the horizontally elongated conductive line being directly electrically coupled to the upper capacitor electrode material.

[0060] In some embodiments, the capacitor array includes a plurality of horizontally spaced groups, each of which includes a plurality of horizontally spaced lower capacitor electrodes. Neighbors in the group are horizontally spaced farther apart than neighbors in the lower capacitor electrodes within the group. A capacitor insulator is above the lower capacitor electrodes. An upper capacitor electrode is common to all capacitors in the individuals of the groups. The capacitors in an individual group individually include one of the lower capacitor electrodes in the respective individual group, a capacitor insulator, and a common upper capacitor electrode. A horizontally elongated conductive line is on top of and electrically coupled directly to the upper capacitor electrode in the individual group.

[0061] In some embodiments, an array of ferroelectric memory cells individually includes ferroelectric capacitors above transistors. The array includes vertical rows and columns of transistors. Access lines interconnect multiple transistors of the transistors in a row direction along individual ones of the rows. Digital lines interconnect multiple transistors of the transistors in a column direction along individual ones of the columns. The transistors individually include lower source / drain regions that are directly electrically coupled to individual ones of the digital lines. The transistors individually include upper source / drain regions. Multiple horizontally spaced groups individually include multiple horizontally spaced lower capacitor electrodes. Individual ones of the lower capacitor electrodes are directly above and directly electrically coupled to individual ones of the upper source / drain regions. Neighbors in the group are horizontally spaced apart from each other by a gap that is larger than the horizontal spacing between neighbors of the lower capacitor electrodes within the group. The gap is horizontally elongated in the column direction. A ferroelectric capacitor insulator is above the lower capacitor electrode. The upper capacitor electrode is common to all capacitors in the individual ones of the group. The capacitors in individual groups individually include one of the lower capacitor electrodes in the respective individual groups, a capacitor insulator, and a common upper capacitor electrode. A horizontally elongated conductive line is on top of and directly electrically coupled to the upper capacitor electrode in the individual groups.

Claims

1. A method of forming a capacitor array, comprising: forming a plurality of horizontally spaced-apart groups, the plurality of horizontally spaced-apart groups individually comprising a plurality of horizontally spaced-apart lower capacitor electrodes having a capacitor insulator thereover, neighbors in the groups being horizontally spaced farther apart than neighbors in the lower capacitor electrodes within the group, an unfilled void space being located between the adjacent groups, the unfilled void space comprising at least a portion below a top portion of the lower capacitor electrodes; forming an upper capacitor electrode material in the portion of the void space below the top of the lower capacitor electrode and in the group over the capacitor insulator and the lower capacitor electrode, the upper capacitor electrode material in the void space being connected to the upper capacitor electrode material in the adjacent group relative to each other, the upper capacitor electrode material not filling the portion of the void space below the top of the lower capacitor electrode; removing at least a portion of the upper capacitor electrode material from the portion of the void space below the top of the lower capacitor electrode to disconnect the upper capacitor electrode materials in the adjacent groups relative to each other; and Horizontally elongated conductive lines are formed on top of the upper capacitor electrode material in individual ones of the groups, the horizontally elongated conductive lines being electrically coupled directly to the upper capacitor electrode material.

2. The method of claim 1, wherein the upper capacitor electrode material has a thickness of no more than one-third of a minimum horizontal width of the portion of the void space below the top of the lower capacitor electrode.

3. The method of claim 2, wherein the thickness is no more than one quarter of the minimum horizontal width. The method according to claim 3 , wherein the thickness is no more than one fifth of the minimum horizontal width.

5. The method of claim 1 , wherein the removing causes the upper capacitor electrode material to be formed into an upper capacitor electrode common to all capacitors within the individual groups; the capacitors within the individual groups individually comprising one of the lower capacitor electrodes in the respective individual groups, the capacitor insulator, and the common upper capacitor electrode. The method of claim 1 , wherein the lower capacitor electrode is a pillar.

7. The method according to claim 1, wherein: The portion of the void space below the top of the lower capacitor electrode is horizontally elongated in a column direction; The lower capacitor electrodes in the respective groups are arranged in horizontally elongated rows in a row direction orthogonal to the column direction; and The portion of the void space below the top portion of the lower capacitor electrode has a minimum width in the row direction that is at least twice as large as a maximum pitch of the lower capacitor electrodes in the row direction.

8. The method of claim 7, wherein the lower capacitor electrodes in the individual groups are arranged in a 2D Bravais lattice.

9. The method of claim 8, wherein the lattice is rectangular or square.

10. The method of claim 1, wherein the capacitor insulator is ferroelectric.

11. The method of claim 1 including forming the upper capacitor electrode material along sidewalls of the portion of the void space below the top of the lower capacitor electrode.

12. The method of claim 1 wherein the capacitor insulator extends entirely laterally across the base of the portion of the void space below the top of the lower capacitor electrode.

13. The method of claim 12, wherein the capacitor insulator has a thickness that is less than a horizontal thickness of individual ones of the lower capacitor electrodes.

14. The method of claim 1, wherein the removing comprises anisotropic etching without a mask over the groups and the void spaces.

15. The method according to claim 14, wherein: The capacitor insulator extends laterally across the base of the void space; forming the upper capacitor electrode material on top of the portion of the capacitor insulator extending laterally from the base across the void space; and The maskless anisotropic etch removes the upper capacitor electrode material from over a central portion of the portion of the capacitor insulator extending laterally from the substrate across the void space.

16. The method of claim 15 , comprising forming the upper capacitor electrode material along sidewalls of the void space, the maskless anisotropic etching leaving the portions of the upper capacitor electrode material along the sidewalls of the void space directly above remaining opposed non-central portions of the portion of the capacitor insulator extending laterally across the base of the void space.

17. The method of claim 1, comprising forming a plurality of transistors individually electrically coupled directly to individual ones of the lower capacitor electrodes. The method of claim 17 , wherein the transistor is a vertical transistor.

19. The method of claim 1 including forming the horizontally elongated conductive lines directly against the capacitor insulator and directly against the upper capacitor electrode material in the individual groups.

20. A method of forming a capacitor array, comprising: forming a plurality of horizontally spaced-apart groups, the plurality of horizontally spaced-apart groups individually comprising a plurality of horizontally spaced-apart lower capacitor electrodes having a capacitor insulator thereover, neighbors in the groups being horizontally spaced farther apart than neighbors in the lower capacitor electrodes within the group, void spaces being located between the adjacent groups; forming an upper capacitor electrode material in the void space and in the group over the capacitor insulator and the lower capacitor electrode, the upper capacitor electrode material in the void space being connected to the upper capacitor electrode material in the adjacent group relative to each other, the upper capacitor electrode material not filling the void space; removing at least a portion of the upper capacitor electrode material from the void space to disconnect the upper capacitor electrode materials in the adjacent groups relative to each other; forming a horizontally elongated conductive line on top of the upper capacitor electrode material in individual ones of the groups, the horizontally elongated conductive line being directly electrically coupled to the upper capacitor electrode material; and The remaining volume of the void space after the removing is filled with an insulating material prior to forming the horizontally elongated conductive lines.

21. The method of claim 20, wherein the filling comprises initially overfilling the remaining volume of the void space with the insulating material, followed by subsequently planarizing the insulating material back to at least the vertically outermost surface of the capacitor insulator.

22. The method of claim 20, comprising forming a portion of the horizontally elongated conductive line directly above the insulating material.

23. The method of claim 22, comprising forming the horizontally elongated conductive lines directly against the capacitor insulator, directly against the upper capacitor electrode material in the individual groups, and directly against the insulating material.

24. A method of forming an array of ferroelectric memory cells individually including ferroelectric capacitors above transistors, comprising: forming vertical rows and columns of transistors relative to a substrate, access lines interconnecting a plurality of the transistors in a row direction along individual ones of the rows, digit lines interconnecting a plurality of the transistors in a column direction along individual ones of the columns, the transistors individually including lower source / drain regions directly electrically coupled to individual ones of the digit lines, the transistors individually including upper source / drain regions; forming a plurality of horizontally spaced-apart groups, the plurality of horizontally spaced-apart groups individually comprising a plurality of horizontally spaced-apart lower capacitor electrodes having a ferroelectric capacitor insulator thereover, individual ones of the lower capacitor electrodes being directly above and electrically coupled to individual ones of the upper source / drain regions, adjacent ones of the groups being horizontally spaced farther apart than adjacent ones of the lower capacitor electrodes within the group, unfilled void spaces being elongated horizontally in the column direction between the adjacent groups, the unfilled void spaces comprising at least a portion below tops of the lower capacitor electrodes; forming an upper capacitor electrode material in the portion of the void space below the top of the lower capacitor electrode and in the group over the capacitor insulator and the lower capacitor electrode, the upper capacitor electrode material in the void space being connected to the upper capacitor electrode material in the adjacent group relative to each other, the upper capacitor electrode material not filling the portion of the void space below the top of the lower capacitor electrode; removing at least a portion of the upper capacitor electrode material from the portion of the void space below the top of the lower capacitor electrode to disconnect the upper capacitor electrode materials in the adjacent groups relative to each other; and Horizontally elongated conductive lines are formed on top of the upper capacitor electrode material in individual ones of the groups, the horizontally elongated conductive lines being electrically coupled directly to the upper capacitor electrode material.

25. A capacitor array comprising: a plurality of horizontally spaced groups, individually comprising horizontally spaced lower capacitor electrodes, individual ones of the groups comprising rows and columns of the horizontally spaced lower capacitor electrodes, each of the rows and columns comprising a plurality of horizontally spaced lower capacitor electrodes, neighbors in the groups being horizontally spaced farther apart than neighbors of the lower capacitor electrodes within the groups; a capacitor insulator positioned over the lower capacitor electrode; an upper capacitor electrode that is common to all capacitors in an individual group; the capacitors in the individual groups individually comprising one of the lower capacitor electrodes in the respective individual group, the capacitor insulator, and the common upper capacitor electrode; and A horizontally elongated conductive line on top of and directly electrically coupled to the upper capacitor electrodes in the individual groups, the horizontally elongated conductive line horizontally spanning a plurality of rows and a plurality of columns.

26. The capacitor array of claim 25, further comprising an array of transistors beneath the capacitor array, the transistors individually directly electrically coupled to individual ones of the lower capacitor electrodes.

27. The capacitor array of claim 26, wherein the transistors are vertical transistors.

28. The capacitor array of claim 26, comprising an array of memory cells individually comprising one of the capacitors and one of the transistors.

29. The capacitor array of claim 25 comprising a plurality of horizontally spaced apart support structures, neighbors of the support structures being horizontally spaced farther apart than neighbors of the lower capacitor electrodes within the group.

30. The capacitor array of claim 29 comprising a plurality of openings formed through individual ones of the support structures.

31. The capacitor array of claim 30 wherein the capacitor insulator extends through individual ones of the openings.

32. The capacitor array of claim 30 wherein the common upper capacitor electrode extends through individual ones of the openings.

33. The capacitor array of claim 30 wherein the capacitor insulator and the common upper capacitor electrode extend through respective ones of the openings.

34. The capacitor array of claim 30, wherein individual ones of the openings are circumferentially surrounded by a plurality of the lower capacitor electrodes.

35. The capacitor array of claim 34 wherein for each individual opening, the plurality is four.

36. The capacitor array of claim 35, wherein the four are equidistantly spaced circumferentially relative to each other around a circumference of the respective openings.

37. A capacitor array according to claim 25, comprising a plurality of horizontally spaced support structures, wherein the horizontally elongated conductive lines individually have relative lateral edges in a vertical cross-section, and the relative lateral edges in the vertical cross-section are laterally located outside the relative lateral edges of the individual support structures in the vertical cross-section.

38. A capacitor array according to claim 25, comprising a plurality of horizontally spaced support structures, wherein the horizontally elongated conductive lines individually have relative lateral edges in a vertical cross-section, and the relative lateral edges in the vertical cross-section are laterally located outside the relative lateral edges of the common upper capacitor electrode in the corresponding individual groups.

39. The capacitor array of claim 25, comprising: a plurality of horizontally spaced apart support structures, the horizontally elongated conductive lines individually having opposing lateral edges in vertical cross-section, the opposing lateral edges in the vertical cross-section being laterally outward of opposing lateral edges of individual ones of the support structures in the vertical cross-section; as well as The opposing lateral edges of the horizontally elongated conductive lines in the vertical cross-section are laterally outside of opposing lateral edges of the common upper capacitor electrode in respective individual groups.

40. An array of ferroelectric memory cells individually including ferroelectric capacitors above transistors, comprising: vertical rows and columns of transistors, access lines interconnecting a plurality of the transistors in a row direction along individual ones of the rows of the vertical transistors, digit lines interconnecting a plurality of the transistors in a column direction along individual ones of the columns of the vertical transistors, the transistors individually including lower source / drain regions directly electrically coupled to individual ones of the digit lines, the transistors individually including upper source / drain regions; a plurality of horizontally spaced groups, individually comprising horizontally spaced lower capacitor electrodes, individual ones of the lower capacitor electrodes being directly above and directly electrically coupled to individual ones of the upper source / drain regions, individual ones of the groups comprising lower capacitor electrode rows and lower capacitor electrode columns of the horizontally spaced lower capacitor electrodes, each of the lower capacitor electrode rows and the lower capacitor electrode columns comprising a plurality of the horizontally spaced lower capacitor electrodes, Neighbors in the group are horizontally spaced apart from each other by a gap that is larger than a horizontal spacing between neighbors in the lower capacitor electrodes within the group, the gap being horizontally elongated in the column direction; a ferroelectric capacitor insulator positioned over the lower capacitor electrode; an upper capacitor electrode that is common to all capacitors in an individual group; the capacitors in the individual groups individually comprising one of the lower capacitor electrodes in the respective individual group, the capacitor insulator, and the common upper capacitor electrode; and A horizontally elongated conductive line on top of and directly electrically coupled to the upper capacitor electrodes in the individual groups, the horizontally elongated conductive line horizontally spanning a plurality of the lower capacitor electrode rows and a plurality of the lower capacitor electrode columns.

41. A capacitor array according to claim 40, comprising a plurality of horizontally spaced support structures, wherein the horizontally elongated conductive lines individually have relative lateral edges in a vertical cross-section, and the relative lateral edges in the vertical cross-section are laterally located outside the relative lateral edges of the individual support structures in the vertical cross-section.

42. A capacitor array according to claim 40, comprising a plurality of horizontally spaced support structures, wherein the horizontally elongated conductive lines individually have relative lateral edges in a vertical cross-section, and the relative lateral edges in the vertical cross-section are laterally located outside the relative lateral edges of the common upper capacitor electrode in the corresponding individual groups.

43. The capacitor array of claim 40, comprising: a plurality of horizontally spaced apart support structures, the horizontally elongated conductive lines individually having opposing lateral edges in vertical cross-section that are laterally outward of opposing lateral edges of individual ones of the support structures in the vertical cross-section; as well as The opposing lateral edges of the horizontally elongated conductive lines in the vertical cross-section are laterally outside of opposing lateral edges of the common upper capacitor electrode in respective individual groups.

44. The capacitor array of claim 40, comprising: a plurality of horizontally spaced apart support structures, adjacent ones of the support structures being horizontally spaced farther apart than adjacent ones of the lower capacitor electrodes within the group; a plurality of openings formed through respective ones of the support structures; the capacitor insulator and the common upper capacitor electrode extending through respective ones of the openings; as well as Individual ones of the openings are circumferentially surrounded by a plurality of the lower capacitor electrodes, the plurality of the lower capacitor electrodes being circumferentially equally spaced relative to one another along the circumferential direction of the individual openings.

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