Data processing apparatus and data processing method

Abstract

The present disclosure relates to predicting results of instructions after a flush. An apparatus is described comprising processing circuitry to speculatively execute an earlier instruction and a later instruction by generating a prediction of a result of the earlier instruction and a prediction of a result of the later instruction, wherein the prediction of the result of the earlier instruction causes a first control flow path to be executed. The apparatus further comprises storage circuitry to store the result of the later instruction in response to the later instruction completing, and flush circuitry to generate a flush in response to the prediction of the result of the earlier instruction being incorrect. When the later instruction is re-executed in a second control flow path after the flush, the processing circuitry is adapted to generate the prediction of the result of the later instruction as the result stored in the storage circuitry during execution of the first control flow path.

Description

Technical Field

[0001] This technology relates to the field of data processing. More specifically, this technology relates to speculative execution of instructions. Background Technology

[0002] In data processing systems, instructions can be executed speculatively. For example, control flow path changing instructions determine which sequence of instructions (the control flow path) will be executed next. A specific example of a control flow path changing instruction is a branch instruction.

[0003] In such a system, the execution of a control flow path change instruction may involve predicting the outcome of the control flow path change instruction before the instruction is executed. This allows the data processing system to speculatively execute subsequent instructions on the control flow path indicated by the predicted outcome of the control flow path change instruction.

[0004] This speculative execution of instructions allows later instructions to be executed much faster than could be possible if the data processing system were forced to wait until the result of an earlier instruction was known, thus improving the performance of the data processing system. If the prediction of the result of an instruction that changed the control flow path is later determined to be incorrect, the later instruction executed from the incorrect control flow path is flushed out of the data processing system's pipeline, and the data processing system subsequently executes the instruction on the correct control flow path. Summary of the Invention

[0005] As one example, the present technology provides an apparatus comprising: processing circuitry to speculatively execute an earlier instruction and a later instruction by generating a prediction of the result of an earlier instruction and a prediction of the result of a later instruction, wherein the prediction of the result of the earlier instruction causes a first control flow path to be executed; storage circuitry to store the result of the later instruction in response to completion of the later instruction; and flushing circuitry to generate a flush in response to an incorrect prediction of the result of the earlier instruction, wherein when the later instruction is re-executed in a second control flow path after a flush, the processing circuitry is adapted to generate the prediction of the result of the later instruction as the result stored in the storage circuitry during the execution of the first control flow path.

[0006] In another example, the present technology provides a method comprising: speculatively executing an earlier instruction and a later instruction by generating a prediction of the result of an earlier instruction and a prediction of the result of a later instruction, wherein the prediction of the result of the earlier instruction causes a first control flow path to be executed; storing the result of the later instruction in response to completion of the later instruction; generating a flush in response to an incorrect prediction of the result of the earlier instruction; and generating the prediction of the result of the later instruction as the result stored during the execution of the first control flow path when the later instruction is re-executed in a second control flow path after the flush.

[0007] In another example, the present technology provides an apparatus comprising: means for speculatively executing an earlier instruction and a later instruction by generating a prediction of the result of an earlier instruction and a prediction of the result of a later instruction, wherein the prediction of the result of the earlier instruction causes a first control flow path to be executed; means for storing the result of a later instruction in response to completion of a later instruction; means for generating a flush in response to an incorrect prediction of the result of the earlier instruction; and means for generating a prediction of the result of a later instruction as the result stored during execution of the first control flow path when the later instruction is re-executed in a second control flow path after a flush.

[0008] Further aspects, features, and advantages of this technology will become clear from the following description of the examples, which is read in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 The figure illustrates a data processing apparatus according to the present technology; Figure 2 The diagram illustrates the convergence control flow path in the instruction stream; Figure 3 The illustration shows a replay predictor; Figure 4 The illustration shows the use of a replay predictor with a base predictor; Figure 5A , Figure 5B and Figure 5C An example of an instruction flow with a converging control flow path is illustrated; Figure 6 The illustration shows an example of how a replay predictor can be used; and Figure 7 This is a flowchart illustrating a method for using a replay predictor to predict the outcome of subsequent instructions. Detailed Implementation

[0010] In data processing systems, the results of earlier instructions can be predicted, allowing subsequent instructions to be retrieved and speculatively executed based on that prediction. For example, the result of an earlier instruction can indicate the control flow path that the processing circuitry should follow, and the processing circuitry can speculatively execute instructions on that control flow path in response to the prediction of that result. Speculative execution of instructions in this way allows instructions on predicted control flow paths to be executed earlier than if speculative execution were not allowed, providing significant performance benefits.

[0011] However, if the prediction of the result of an earlier instruction is subsequently determined to be incorrect, the execution of any subsequent instructions (e.g., instructions on the predicted control flow path) is canceled or reversed to avoid damage or safety issues that could arise from executing and completing incorrect instructions. This could involve, for example, flushing the processing circuitry to prevent the completion of any instructions that occurred after the earlier instruction and instead executing instructions on the correct control flow path. However, there is a significant performance cost associated with performing the flush, and the time spent executing the erroneous instructions is wasted. This is especially true if the correct control path also includes some of the same reversed instructions. Therefore, it would be advantageous to be able to improve the performance of the processing circuitry when re-executing instructions.

[0012] In some examples of this technology, an apparatus is provided comprising processing circuitry to speculatively execute an earlier instruction and a later instruction by generating a prediction of the result of an earlier instruction and a prediction of the result of a later instruction, wherein the prediction of the result of the earlier instruction causes a first control flow path to be executed; storage circuitry to store the result of a later instruction in response to completion of the later instruction; and flushing circuitry to generate a flush in response to an incorrect prediction of the result of the earlier instruction, wherein when the later instruction is re-executed in a second control flow path following the flush, the processing circuitry is adapted to generate the prediction of the result of the later instruction as the result stored in the storage circuitry during the execution of the first control flow path.

[0013] By storing the results of subsequent instructions in a memory circuit and using the stored results as predictions when re-executing subsequent instructions, this technique allows for a reduction in the time and processing power required to re-execute subsequent instructions. This results in increased device efficiency and improved performance. Specifically, the prediction of subsequent instructions can be determined more quickly, allowing subsequent instructions to be fetched and executed speculatively. Furthermore, basing the prediction of subsequent instructions on the actual execution results allows for more accurate predictions, reducing the likelihood of generating another flush, and thus improving device performance.

[0014] The storage circuit can be any form of storage circuit; for example, it can be a dedicated storage circuit or a region within the system memory.

[0015] In some examples, the first control flow path and the second control flow path each include subsequent instructions.

[0016] This technology is particularly advantageous in situations where subsequent instructions do not directly follow the results of earlier instructions, but rather follow both an incorrect control flow path (the first control flow path) and a correct control flow path (the second control flow path). In such cases, the same (subsequent) instructions will be re-executed after flushing, even if their results are unlikely to have changed. Therefore, by using the results of previous executions of subsequent instructions as a prediction, the storage circuitry employing this technology is particularly advantageous in reducing power consumption and increasing the speed of re-execution of subsequent instructions in such situations.

[0017] In some examples, earlier instructions are earlier than later instructions in the predetermined program sequence, and the processing circuitry completes the execution of the later instructions before the flushing is finished.

[0018] This out-of-order execution of earlier and later instructions allows instructions to be executed in an order constrained by, for example, the availability of input data or execution units, rather than by their original order in the program (the predetermined program order). Completing later instructions before flushing means that the result of later instructions is known and can be stored before the flush is complete.

[0019] In some examples, later instructions and earlier instructions are issued out of order relative to the program sequence.

[0020] In this example, the later instruction is executed before the earlier instruction, so that the result of the later instruction is known before the flush (triggered by an incorrect prediction of the earlier instruction) is completed. This technique is particularly advantageous in this situation because the result of the later instruction is known—and therefore can be stored—before the instruction is flushed from the processing circuitry.

[0021] Alternatively, earlier and later instructions may be executed sequentially, but later instructions are executed faster than earlier instructions, so that their results can be known before the flush is complete. This technique is also useful in this case because, similarly, the results of later instructions are known—and therefore can be stored—before the instructions are flushed from the processing circuitry.

[0022] In some examples, the storage circuit stores a validity indicator indicating whether a subsequent instruction has been completed in the first control flow path; and when the validity indicator indicates that the subsequent instruction has been previously completed, the processing circuit generates a prediction of the result of the subsequent instruction as the result stored in the storage circuit during the execution of the first control flow path.

[0023] In this way, the processing circuitry can use a validity indicator to determine whether an accurate prediction of the result of a subsequent instruction has been stored in the storage circuitry. This reduces the likelihood of making an incorrect prediction by decreasing the probability of generating another flush, and thus improves the performance of the device.

[0024] In some examples, the processing circuit executes multiple iterations of earlier instructions and multiple iterations of later instructions; the storage circuit stores multiple results of later instructions, each corresponding to one of the multiple iterations of later instructions; and for each iteration of a later instruction, when that iteration of the later instruction is re-executed in a second control flow path after flushing, the processing circuit is adapted to generate a prediction of the result of that iteration of the later instruction as the result stored in the storage circuit for that iteration during the execution of the first control flow path.

[0025] The storage circuitry stores the results of each of multiple iterations of the same subsequent instruction, thus allowing the accurate prediction of the result of any particular iteration of a subsequent instruction. This makes the technique applicable regardless of how many iterations of the subsequent instruction were executed before the flush was generated. For example, this may be useful in cases where the earlier and later instructions are instructions within each "for," "while," or "do" loop that is iterated multiple times. Therefore, the storage circuitry of this technique, capable of storing the results of multiple iterations of the same instruction, is useful.

[0026] In some examples, the device includes pointer storage circuitry to store a pointer indicating which of the multiple results of a subsequent instruction corresponds to the current iteration of that subsequent instruction.

[0027] This pointer allows the processing circuitry to determine which of several results corresponds to the current iteration of a later instruction, ensuring that the result of that iteration is correctly predicted and / or stored in the correct location within the storage circuitry. This improves the accuracy of predictions made using this technique.

[0028] In some examples, the pointer is advanced after each prediction of a later instruction; and after a flush, the pointer is returned to the state it held when the earlier instruction was predicted.

[0029] This allows the pointer to correctly identify the result corresponding to the current iteration of a later instruction, so that the corresponding result can be retrieved or stored in the correct location.

[0030] In some examples, the processing circuitry speculatively executes multiple subsequent instructions by generating predictions of multiple results, each corresponding to one of multiple subsequent instructions; and the storage circuitry stores multiple results, each of which is stored in response to the completion of the corresponding one of the multiple subsequent instructions.

[0031] This technique can still be applied to generate predictions for instructions that are re-executed after flushing, even when multiple subsequent instructions are executed on an incorrect control flow path (the first control flow path).

[0032] In some examples, the storage circuitry stores the result of multiple subsequent instructions as a circular bit vector.

[0033] A circular bit vector is a specific, compact, and efficient way to store the results of multiple subsequent instructions in a memory circuit, requiring minimal circuit area. Each bit in the bit vector can correspond to one of the results of multiple subsequent instructions.

[0034] In some examples, the storage circuitry stores multiple validity indicators as another cyclic bit vector, where each of the multiple validity indicators indicates whether the corresponding one of a plurality of subsequent instructions has been completed in the previous control flow path.

[0035] As mentioned above, the use of validity indicators reduces the likelihood of making incorrect predictions and thus improves the performance of the device. Furthermore, as mentioned above, storing data elements such as validity indicators as cyclic bit vectors is particularly compact and efficient, where each bit of the bit vector corresponds to one of the validity indicators.

[0036] In some examples, the device includes another prediction circuitry to generate another prediction of the result of a subsequent instruction; and a prediction selection circuitry to select either the prediction of the result of the subsequent instruction or another prediction of the result of the subsequent instruction as the selected prediction.

[0037] By providing a selection circuit to choose between a prediction of the result of a subsequent instruction and another prediction generated by another prediction circuit, this technique can be used with existing prediction circuits such as branch predictors and value predictors. This allows the technique to be more easily integrated into existing systems and provides the additional advantage that the prediction (another prediction) can still be available even when the result stored in the memory circuit is unavailable (e.g., if the subsequent instruction has not been executed previously, meaning no result is stored in the memory circuit of this technique) or inaccurate.

[0038] In some examples, the storage circuit stores a validity indicator indicating whether a subsequent instruction has been previously completed; when the validity indicator indicates that a subsequent instruction has been previously completed, the processing circuit generates a prediction of the result of the subsequent instruction as the result stored in the storage circuit during the execution of the first control flow path; and unless the validity indicator indicates that a subsequent instruction has been previously completed, the prediction selection circuit selects another prediction of the result of the subsequent instruction as the selected prediction.

[0039] As mentioned above, the use of a validity indicator reduces the likelihood of making incorrect predictions and thus improves the performance of the device. In this case, the validity indicator is also used to determine which of the two predictions should be used as the prediction result for the later instruction. Specifically, the result stored in the memory circuit will generally be the most accurate prediction because it corresponds to the actual (most recent) execution of the later instruction. Therefore, by selecting this result unless the validity indicator indicates that the later instruction has not yet been completed, the accuracy of the generated prediction can be improved, and the possibility of generating another flush can be reduced.

[0040] In some examples, the preceding instruction is a control flow path change instruction; and the result of the preceding instruction causes execution to proceed along either the first or the second control flow path.

[0041] In these examples, a control flow path change instruction refers to an instruction that can modify the flow of instructions to be executed by the processing circuitry. For such an instruction, the result of the control flow path change instruction (as described above, to be stored in the memory circuitry) is an indication of the control flow path to be followed by subsequent instructions. The processing circuitry responds to the prediction of the result of the control flow path change instruction by predictively acquiring and executing instructions from the predicted control flow path. Therefore, in cases where the earlier instruction is a control flow path change instruction, this technique can be applied to generate a prediction of the result upon re-execution of such an instruction.

[0042] In some examples, the preceding instruction is a branch instruction; and the result of the preceding instruction determines whether the branch is taken.

[0043] Earlier instructions could be branch instructions that, when taken, identify a specific control flow path to be followed by the circuit being processed, and identify a different control flow path when the branch is not taken. The result of the branch instruction thus indicates whether the branch was taken—for example, the result could be "taken" or "not taken," and subsequent instructions (e.g., later instructions) could be speculatively taken and executed based on predictions of whether the branch was taken.

[0044] In some examples, the subsequent instruction is a control flow path change instruction; and the result of the subsequent instruction causes execution to proceed along the third or fourth control flow path.

[0045] In these examples, the result that the processing circuitry needs to predict—and the result that needs to be stored in the memory circuitry—is whether execution should proceed via the third or fourth control flow path. This technique can therefore be used to predict the result (which control flow path) of a later instruction when it is re-executed.

[0046] In some examples, the subsequent instruction determines the data value; and the prediction of the result of the subsequent instruction will predict the value of that data value.

[0047] For example, the subsequent instruction could be a load instruction to load a data value from memory, or an arithmetic instruction to calculate the value using arithmetic instructions. The storage circuitry of this technology can therefore store the data value calculated or retrieved by the instruction, and use this stored value as a prediction if the instruction is re-executed.

[0048] In some examples, an earlier instruction determines a data value; the prediction of the result of the earlier instruction will predict the value of that data value; and the first control flow path and the second control flow path are the same.

[0049] As described above, examples of such instructions may include load instructions that load data values ​​from memory, or arithmetic instructions that calculate values ​​using arithmetic instructions. In such examples, since the result of the instruction does not change the control flow path of subsequent instructions, the first and second control flow paths can be considered the same. Thus, subsequent instructions are executed regardless of the result of earlier instructions, making this a particularly advantageous situation for applying the present technology.

[0050] Specific embodiments will now be described with reference to the accompanying drawings.

[0051] Figure 1 An example of a data processing apparatus 100 having a processing pipeline comprising several pipeline stages is illustrated. The data processing apparatus 100 is an example of a processing circuit that speculatively executes earlier and later instructions by generating predictions of the results of earlier instructions and predictions of the results of later instructions. The pipeline includes a base predictor 102 and a replay predictor 104 for predicting the results of instructions processed by the data processing apparatus 100. The base predictor 102 and the replay predictor 104 are each prediction circuits for predicting the results of instructions, allowing subsequent instructions to be executed based on these predictions. The base predictor 102 is a standard predictor and can predict the results of instructions, for example, based on a recorded history. The replay predictor 104, which will be discussed in more detail below, makes predictions based on the results of previously executed versions of the same instruction stored in memory. The outputs of the base predictor 102 and the replay predictor 104 are fed into a selection circuit 106, which selects between the predictions generated by the two predictors. The base predictor 102 is an example of another prediction circuit, and the selection circuit 106 is an example of a prediction selection circuit. Note that each of the base predictor 102 and the replay predictor 104 can be a branch predictor for predicting the result of a branch instruction, or a value predictor for predicting the data value determined by the instruction.

[0052] The pipeline also includes a fetch unit 108, which fetches instructions from instruction cache 110 or other memory structures 112, 114. The fetch stage 108 fetches the instruction identified by the fetch address, and the decode stage 116 decodes the fetched instruction to generate control signals for subsequent stages of the pipeline. The instruction fetched by the fetch unit 108 may be subject to a prediction provided by the select circuit 106. Specifically, if the prediction provided by the select circuit 106 predicts that a branch will occur, the fetched instruction will be at the location indicated by that branch.

[0053] The renaming phase 118 performs register renaming to map the architecture register designator recognized by the instruction to the physical register designator that identifies the register provided in the hardware. The issuing phase 120 includes an issuing queue that queues instructions awaiting execution until the operands required to process these instructions are available in the register, and includes selection circuitry to select instructions for execution phase 122. Execution phase 122 executes the instructions to implement the corresponding processing operations, and the results of the executed instructions are written back to the register.

[0054] Execution phase 122 may include several execution units, such as a branch unit 124 for evaluating whether a branch instruction has been correctly predicted, an ALU (Arithmetic Logic Unit) 126 for performing arithmetic or logical operations, an FPU (Floating Point Unit) 128 for performing operations using floating-point operands, and a load / store unit 130 for performing load operations to load data from the memory system into registers or performing store operations to store data from registers into the memory system. In this example, the memory system includes a first-level instruction cache 110, a first-level data cache 132, a second-level cache 112 shared between data and instructions, and main memory 114, but it will be understood that this is only one example of a possible memory hierarchy, and other implementations may have additional levels of caches or different arrangements. Access to memory can be controlled using a Memory Management Unit (MMU) for controlling address translation and / or memory protection. It will be understood that... Figure 1 The pipeline shown is just one example, and other examples may have different sets of pipeline stages or execution units. For example, an ordered processor may not have a renaming stage 118.

[0055] A flushing circuit 134 is also provided. The flushing circuit 134 generates a flush in response to certain triggers—such as an incorrect prediction made by one of the base predictor 102 and the replay predictor 104. The flush removes all incomplete instructions from the pipeline. The flushing circuit 134 is an example of a flushing circuit that generates a flush in response to an incorrect prediction of the result of an earlier instruction.

[0056] As described above, a replay predictor 104 can be provided to generate predictions of the results of instructions. Specifically, the replay predictor 104 stores the results of previous executions of instructions performed prior to flushing of the pipeline. The stored values ​​can then be provided via selection circuit 106 to acquisition circuit 108 as predictions of the results of the same instruction when it is re-executed after flushing.

[0057] As described above, prediction circuits 102 and 104 can make predictions about specific instructions before they are executed by execution unit 122. Specifically, the outcome of an instruction can be predicted to determine which of several control flow paths to follow after the execution of that instruction. This allows acquisition circuit 108 to acquire the next set of instructions.

[0058] Figure 2 An example of instruction flow 200 is shown—for example, Figure 2 The sequence of instructions described indicates a predetermined program order, which could be, for example, the order of instructions compiled by a compiler, or the order provided by a programmer. Specifically, Figure 2 An earlier instruction (instruction A) 202 is shown, which determines whether to follow a first control flow path (path 1) or a second control flow path (path 2) based on its result. If the first control flow path is followed, the first set of instructions (path 1 instructions) 204 is executed, followed by the later instruction (instruction B) 208. If the second control flow path is followed, the second set of instructions (path 2 instructions) 206 is executed, followed by the later instruction (instruction B) 208. Figure 2 In the example shown, the first and second control flow paths converge, where the later instruction (instruction B) 208 is executed on both control flow paths—that is, the first and second control flow paths each include the later instruction 208. The earlier instruction 202 in this example is thus a control flow path modification instruction, used to cause a particular control flow path to be followed. The later instruction 208 could also be a control flow path modification instruction. Alternatively, the later instruction 208 could be any other type of instruction for which a prediction can be generated—for example, it could be an instruction for predicting data values.

[0059] In some examples, the earlier instruction 202 is a branch instruction where one of the two paths is the "take" path and the other of the two paths is the "not take" path.

[0060] By predicting the result of the first instruction 202 in advance—for example, using the base predictor 102—the acquisition circuit 108 is able to acquire subsequent instructions based on that prediction (e.g., the prediction of the result of the earlier instruction causes the first control flow path to be followed). This allows subsequent instructions to be executed faster compared to not predicting the result of later instructions (202), resulting in performance improvements.

[0061] In the event that the result of an earlier instruction 202 is incorrectly predicted, leading to the execution of an instruction on an incorrect control flow path, a flushing circuit 134 is configured to trigger a flush to remove the incorrectly executed instruction from the processing pipeline 2. The correct set of instructions based on the correct result of the first instruction 202 can then be executed. In this case, if a later instruction 208, which is on both the first and second control flow paths, has been executed (e.g., completed) before the flushing is complete, this means that the same instruction will be re-executed after the flushing occurs. Furthermore, it can be expected that the second execution of this instruction will give the same result as the first execution of the instruction. This is a waste of processing resources, leading to increased power consumption and reduced performance. This technology aims to overcome this reduction in performance and efficiency by using a replay predictor 104 to store the result of the later instruction 208 and using the stored result to predict its result during the second execution of the instruction.

[0062] Figure 3 An example of the replay predictor 104 is shown in more detail. The replay predictor 104 includes a plurality of prediction units 301a, 301b, ..., 301n, each corresponding to one of a plurality of subsequent instructions. For example, the first prediction unit 301a may correspond to the above reference. Figure 2 The following instruction (instruction B) is described.

[0063] The first prediction unit 301a includes a prediction storage circuit 302a, which is arranged to store the result of a subsequent instruction executed on an incorrect control path—the prediction storage circuit 302a is an example of a storage circuit that stores the result of a subsequent instruction in response to its completion. This result can then be read from the prediction storage 302a when the subsequent instruction is re-executed after a flush, in order to generate a prediction of the result of an instruction that is more accurate than that generated using the basic prediction circuit.

[0064] Multiple iterations of a subsequent instruction can be executed before the flushing is complete, for example, within a loop. Therefore, the predictive storage circuit 302a in these examples is adapted to store multiple results of a subsequent instruction, each corresponding to one of the iterations. Figure 3 In the example, the predictive storage circuit 302a stores multiple results of subsequent instructions as a first cyclic bit vector 304a. Figure 2The predictive memory circuit 302a also stores a second cyclic bit vector 306a to store multiple validity values ​​(validity indicators / validity bits), each corresponding to one of the iterations of a subsequent instruction. In this example, each result is stored as a single bit, and each validity value is stored as a single bit (e.g., stored as "1" or "0"). This allows the results of multiple iterations of a subsequent instruction to be stored in the predictive memory circuit 302a in a compact and efficient manner, reducing the circuit area required to implement the predictive memory circuit 302a. For example, if the subsequent instruction is a branch instruction and the result is therefore take or not take, then a value of 0 can be stored when the result is not take and a value of 1 can be stored when the result is take. Each bit position in the cyclic bit vector 304a corresponds to a specific iteration of the instruction.

[0065] The validity vector 306a allows for storing a validity bit for each iteration of a subsequent instruction, indicating whether the corresponding iteration of the subsequent instruction has been completed. For example, a value of 1 stored in a given bit position of the validity vector indicates that the corresponding iteration of the subsequent instruction has been completed and the corresponding result has been stored, while a value of 0 indicates that the corresponding iteration of the subsequent instruction has not yet been completed.

[0066] To identify which iteration of a subsequent instruction is the current iteration, a pointer storage circuit 308a is provided to store a pointer that indicates which bit position of the prediction vector and validity vector corresponds to the current iteration of a subsequent instruction.

[0067] As described above, after the flush is generated by the flush circuit 134, subsequent instructions may need to be re-executed (e.g., if it is on both an incorrect and correct control flow path). When a subsequent instruction is re-executed, a prediction of the result of the subsequent instruction is generated so that subsequent instructions can be executed speculatively. To generate a prediction of the result of a given iteration of the subsequent instruction, the output of the pointer storage circuit 308a and the output of the prediction storage 302a can then be fed into the multiplexer 310a to allow the validity value 311a and the prediction 309a corresponding to the current iteration to be output.

[0068] A program counter store 312a is also provided to store the program counter value corresponding to a subsequent instruction. To obtain a prediction from the replay predictor 104 for a specific instruction, a program counter value 314 corresponding to the program counter of the instruction to be executed is input to the replay predictor 104. In each prediction unit 301, a comparison circuit 315 compares this value with the stored program counter value 312, and the result of this comparison becomes a selection signal for a pair of multiplexers 316, 318, which receive a validity value 311 and a prediction 309 as input from each prediction unit 301. The validity value 311 and the prediction value 309 corresponding to the current instruction—the instruction whose stored program counter value 312 equals the input program counter value 314—are then selected by the multiplexers 316, 318. If the selected validity value 320 indicates that the prediction is valid, the selected prediction 322 can then be used to predict the result of another instruction.

[0069] like Figure 3 The replay prediction circuit 104 shown allows for the rapid generation of accurate predictions of subsequent instructions and enables predictions to be made based on the actual execution results of the instruction from an incorrect control flow path.

[0070] Figure 4 This illustrates how replay predictor 104 can be implemented simultaneously with base predictor 102. Base predictor 102 is an example of another predictive circuit that generates another prediction of the result of a subsequent instruction, and can be a normal predictive circuit provided in data processing device 100. For example, base predictor 102—like replay predictor 104—can be configured to predict the result of a branch instruction, or a value prediction circuit for predicting the data value to be computed by the instruction. Base predictor 102 can generate predictions based on stored historical data, such as using a pattern history table.

[0071] During the execution of instructions by the data processing device 100, each of the replay predictor 104 and the base predictor 102 can generate a prediction. The replay predictor 104 outputs a prediction 322 and a validity value 320 as described above, and the base predictor 102 outputs another prediction 406. The prediction 322 from the replay predictor 104 and the other prediction 406 from the base predictor 102 are fed into a multiplexer 402, which selects a chosen prediction 408 from the two input predictions.

[0072] A selection circuit 106 is also provided to generate a prediction selection signal 410. The prediction selection signal 410 and the validity value 320 are input into an AND gate 404, and the output of the AND gate 404 is provided as the selection signal 412 for the multiplexer 402. Thus, if no valid prediction is stored in the replay predictor for the current instruction, the prediction from the base predictor is selected because the validity value 0 is output by the replay predictor.

[0073] The selection circuit 106 thus allows the replay predictor 104 and the base predictor 102 to be implemented simultaneously. In such a system, the base predictor 102 is typically relied upon to generate predictions. However, in some cases, the replay predictor 104 can "overturn" the base predictor 102 by generating predictions through instruction-based rewind execution. This allows the replay predictor 104 to be implemented in existing systems without conflicting with existing prediction circuitry.

[0074] Figure 5A , Figure 5B and Figure 5C An example of how this technique can benefit instruction flows is shown. Figure 5A In the middle, the earlier instruction 502 (which is Figure 2 An example of an earlier instruction (e.g., 502) is an "if" instruction with unpredictable conditions. This could mean that resolving (executing) an earlier instruction 502 would take a long time (e.g., many processor cycles). Consequently, if a later instruction 504 (which is...) Figure 2 If a later instruction (e.g., 502) can be executed faster than an earlier instruction (e.g., 502), then the later instruction can be resolved before the earlier instruction is resolved.

[0075] It should be noted that while the later instruction 504 follows the earlier instruction 502 in the program sequence, since the later instruction 504 does not depend on the result of the earlier instruction 502, it can be executed regardless of the result of the earlier instruction 502. That is, the later instruction 504 should be considered to be on any control path following the earlier instruction 502. For example, the earlier instruction 502 could be a branch instruction, where two control flow paths (the taken path and the untaken path) converge to allow the later instruction 504 to be executed. Alternatively, the earlier instruction 502 could be a data value instruction for generating data values—such as an arithmetic instruction—for which a prediction of the data value is made. In this case, the earlier instruction is not a control flow path modification instruction, and therefore only one control path can be followed after the earlier instruction 502.

[0076] Figure 5B Another example of the instruction flow implementing this technique is illustrated. Figure 5B In the example, the earlier instruction 506 ( Figure 2 Examples of earlier instruction 202) and later instruction 508 ( Figure 2 The example of the later instruction 208 is the instruction within the "for" loop 510. In this example, if the later instruction 508 can be executed quickly, it can be executed multiple times before the result of the earlier instruction 506 is known. Therefore, in this case, it is useful to store the results of multiple iterations of the later instruction 508 in the prediction storage circuit 302 of the replay predictor 104. This can be achieved using, as referenced... Figure 3 The prediction storage circuit 302 is used to implement this, which can compactly store multiple results of subsequent instructions into a first circular bit vector 304.

[0077] Figure 5C Another example of an instruction flow that can implement this technique is illustrated. Figure 3 The example shown illustrates the relationship with Figure 5B The "for" loop 510 is similar to the "for" loop 512, except that it includes additional instructions 514. Therefore, Figure 5C The instruction stream depicted includes an earlier instruction 506 and two subsequent instructions 508 and 514. In this example, both subsequent instructions 508 and 514 are resolved before the result of the earlier instruction 506 is known, making it advantageous to store the results of the two subsequent instructions 508 and 514 in the replay predictor 104. This is achieved using multiple prediction units 301 of the replay predictor 104—specifically, the result of one of the subsequent instructions 508 is stored in the prediction storage circuit 302 of the first prediction unit 301a, and the result of the other subsequent instruction 514 is stored in the prediction storage circuit of the second prediction unit 301b. Thus, the replay predictor 104 is used to predict the results of multiple subsequent instructions 508 and 514.

[0078] Figure 6 According to the schematic diagram of this technology Figure 2 The execution of earlier instruction 202 and later instruction 208. In these examples, the instructions are executed sequentially, meaning that earlier instruction 202 is fetched in the first processing cycle. In the next processing cycle, earlier instruction 202 is decoded, and later instruction 208 is fetched. However, in this example, earlier instruction 202 takes a relatively long time to execute, causing its execution to not complete until many cycles later. Meanwhile, the execution of later instruction 208, in the processing cycle after the decoding of earlier instruction 208, involves a more rapid prediction based on the result of earlier instruction 202. This means that the result of later instruction 208 is known before the result of earlier instruction 202 is known.

[0079] Given that instruction 208 was obtained based on a prediction of the result of the earlier instruction 202, if it is subsequently determined that the earlier instruction 202 was mispredicted, then instruction 208 is flushed from the processing circuit. However, as referenced... Figure 2 As stated, instruction 208 will be re-executed after flushing.

[0080] Therefore, during the initial execution of subsequent instruction 208 (or an incorrect control flow path), the result of the subsequent instruction is stored in the replay predictor 104. Figure 6 In the example, it was later determined that the earlier instruction 202 was mispredicted, resulting in a flush. This means that the later instruction 208 needs to be re-executed, as shown in the figure. However, since the result of the previous execution of the later instruction 208 is stored in the replay predictor, this result can be reused when predicting the result of the later instruction 208 during re-execution. This allows for a more accurate prediction of the later instruction 208 compared to what the basic predictor circuit can generate, as it depends on the actual execution result of the same instruction. This thus leads to improvements in system performance and efficiency by significantly reducing the likelihood of subsequent flushes.

[0081] Although Figure 2 and Figure 6 In the example, the earlier instruction 202 and the later instruction 208 are executed sequentially, but this technique is also applicable to cases where instructions are executed out of order relative to the predetermined program order (e.g., the later instruction 208 is issued before the earlier instruction 202).

[0082] Figure 7 This is a flowchart illustrating an example method based on this technology. Figure 7The method involves obtaining an earlier instruction (instruction A) in step 702. Processing circuit 100 then predicts the result of instruction A 704 and uses this prediction to speculatively obtain instruction B 706. As described above, in this case, instruction B is obtained regardless of the result or prediction of instruction A, because instruction B is on both the correct and incorrect control flow paths. Once instruction B is obtained, its result is predicted 708. Instruction B is then speculatively executed 710. Instruction A is also speculatively executed; the processing circuit may be configured for out-of-order execution of instructions, allowing instruction B to be speculatively executed before instruction A is executed. Or it may simply be that the execution of instruction B completes faster than the execution of instruction A. In either case, the result of instruction B is known before the execution of instruction A is complete, and therefore the result of instruction B is stored in the replay predictor in step 712. Once the execution of instruction A has completed 714, processing circuit 100 can determine whether the prediction of instruction A is correct 716. If the prediction of instruction A is correct, processing can continue 718. However, if the prediction result of instruction A is ultimately incorrect, processing pipeline 100 is flushed 720. As a result, instruction B needs to be re-acquired 722 and re-predicted 724. However, since the result of the previous execution of instruction B is stored in the replay predictor, the stored result of the first execution can be used to generate a prediction of instruction B during re-execution. Once instruction B is predicted, it can be executed 726 and processing can continue 718.

[0083] As shown, a replay predictor can be used to store the results of subsequent instructions executed on an incorrect control flow path after a misprediction of an earlier instruction. Following a flush, by basing predictions on the stored results, the results of subsequent instructions can be predicted more quickly and accurately during re-execution of those instructions after the flush.

[0084] In this application, the term "configured as" is used to mean that the elements of the device are configured to perform defined operations. In this context, "configuration" refers to the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform that function. "Configured as" does not mean that the elements of the device need to be changed in any way in order to provide the defined operations.

[0085] While illustrative embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to these specific embodiments, and various changes and modifications may be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. A data processing apparatus, comprising: Processing circuitry is configured to speculatively execute the earlier instruction and the later instruction by generating a prediction of the result of the earlier instruction and a prediction of the result of the later instruction, wherein the prediction of the result of the earlier instruction causes a first control flow path to be executed. A storage circuit for storing the result of the subsequent instruction in response to its completion; as well as A flushing circuit is used to generate a flush in response to an incorrect prediction of the result of the earlier instruction. When the subsequent instruction is re-executed in the second control flow path after the flushing, the processing circuitry is adapted to generate a prediction of the result of the subsequent instruction as a result stored in the storage circuitry during the execution of the first control flow path. The earlier instruction is earlier than the later instruction in the predetermined program sequence. The processing circuit executes the later instruction before the flushing is completed, and the later instruction and the earlier instruction are issued out of order relative to the program sequence.

2. The apparatus of claim 1, wherein: The first control flow path and the second control flow path each include the subsequent instruction.

3. The apparatus of claim 1, wherein: The storage circuit stores a validity indicator indicating whether the subsequent instruction was completed in the first control flow path; and When the validity indicator indicates that the subsequent instruction has been previously completed, the processing circuit generates a prediction of the result of the subsequent instruction as a result stored in the storage circuit during the execution of the first control flow path.

4. The apparatus of claim 1, wherein: The processing circuit executes multiple iterations of the earlier instruction and multiple iterations of the later instruction; The storage circuit stores multiple results of the subsequent instruction, each result corresponding to one of multiple iterations of the subsequent instruction; and For each iteration of the subsequent instruction, when that iteration of the subsequent instruction is re-executed in the second control flow path after the flush, the processing circuitry is adapted to generate a prediction of the result of that iteration of the subsequent instruction as a result stored in the storage circuitry for that iteration during the execution of the first control flow path.

5. The apparatus of claim 4, comprising: A pointer storage circuit is used to store a pointer indicating which of the plurality of results of the subsequent instruction corresponds to the current iteration of the subsequent instruction.

6. The apparatus of claim 5, wherein: The pointer is advanced after each prediction of the subsequent instruction; and After the flushing, the pointer is returned to the state it occupied when the earlier instruction was predicted.

7. The apparatus of claim 1, wherein: The processing circuit speculatively executes multiple subsequent instructions by generating predictions of multiple results, each prediction corresponding to one of the multiple subsequent instructions; and The storage circuit stores the plurality of results, each of which is stored in response to the completion of a corresponding one of the plurality of subsequent instructions.

8. The apparatus of claim 7, wherein: The storage circuit stores the results of the multiple subsequent instructions as a circular bit vector.

9. The apparatus of claim 8, wherein: The storage circuit stores a plurality of validity indicators as another cyclic bit vector, wherein each of the plurality of validity indicators indicates whether a corresponding one of the plurality of subsequent instructions was completed in a previous control flow path.

10. The apparatus of claim 1, comprising: Another prediction circuit is used to generate another prediction of the result of the subsequent instruction; as well as A prediction selection circuit is used to select either a prediction of the result of the subsequent instruction or another prediction of the result of the subsequent instruction as the selected prediction.

11. The apparatus of claim 10, wherein: The storage circuit stores a validity indicator indicating whether the subsequent instruction has been previously completed; When the validity indicator indicates that the subsequent instruction has been previously completed, the processing circuit generates a prediction of the result of the subsequent instruction as a result stored in the storage circuit during the execution of the first control flow path; and Unless the validity indicator indicates that the subsequent instruction has been previously completed, the prediction selection circuit selects another prediction of the result of the subsequent instruction as the selected prediction.

12. The apparatus of claim 1, wherein: The earlier instruction was a control flow path change instruction; and The result of the earlier instruction causes execution to proceed along either the first control flow path or the second control flow path.

13. The apparatus of claim 12, wherein: The earlier instruction was a branch instruction; and The result of the earlier instruction determines whether the branch is taken.

14. The apparatus of claim 1, wherein: The subsequent instruction is a control flow path change instruction; and The result of the subsequent instruction causes execution to proceed along either the third or fourth control flow path.

15. The apparatus of claim 1, wherein: The subsequent instruction determines the data value; and The prediction of the result of the subsequent instruction will predict the value of the data value.

16. The apparatus of claim 1, wherein: The earlier instruction determined the data value; The prediction of the result of the earlier instruction will predict the value of the data value; and The first control flow path and the second control flow path are the same.

17. A data processing method, comprising: The earlier and later instructions are executed speculatively by generating predictions of the results of earlier instructions and predictions of the results of later instructions, wherein the prediction of the results of the earlier instructions causes the first control flow path to be executed. The result of the subsequent instruction is stored in response to its completion. A scour is generated in response to an incorrect prediction of the result of the earlier instruction; and When the subsequent instruction is re-executed in the second control flow path after the flushing, the prediction of the result of the subsequent instruction is generated as the result stored during the execution of the first control flow path. The earlier instruction is earlier than the later instruction in the predetermined program sequence, the later instruction is executed before the flushing is completed, and the later instruction and the earlier instruction are issued out of order relative to the program sequence.

18. A data processing apparatus, comprising: A means for speculatively executing the earlier instruction and the later instruction by generating a prediction of the result of the earlier instruction and a prediction of the result of the later instruction, wherein the prediction of the result of the earlier instruction causes a first control flow path to be executed. A means for storing the result of a subsequent instruction in response to its completion; A means for generating a flush in response to an incorrect prediction of the result of the earlier instruction; as well as A means for generating a prediction of the result of the subsequent instruction as a result stored during the execution of the first control flow path when the subsequent instruction is re-executed in the second control flow path after the flushing. The earlier instruction is earlier than the later instruction in the predetermined program sequence, the later instruction is executed before the flushing is completed, and the later instruction and the earlier instruction are issued out of order relative to the program sequence.

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