Method for manufacturing chip package

CN113178396BActive Publication Date: 2024-12-27TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
View PDF 2 Cites 0 Cited by

Patent Information

Application Number
CN202110319418.9
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2015-09-30
Filing Date
2016-08-17
Publication Date
2024-12-27
Estimated Expiration
2036-08-17

Smart Images

  • Figure CN113178396B_ABST
    Figure CN113178396B_ABST
Patent Text Reader

Abstract

Embodiments of the present invention relate to methods for manufacturing chip packages. In one embodiment, a method for forming a chip package includes: placing at least one first die over a carrier, the at least one first die having a plurality of first contact pads facing away from the carrier; forming at least one conductive pillar over at least one peripheral contact pad of the plurality of first contact pads; placing at least one second die over the at least one first die and laterally adjacent to the at least one conductive pillar, the at least one second die having a plurality of second contact pads facing away from the carrier; encapsulating the at least one first die, the at least one second die, and the at least one conductive pillar in a molding compound; and forming a redistribution layer over the molding compound, the redistribution layer being electrically connected to the plurality of second contact pads and the at least one conductive pillar.
Need to check novelty before this filing date? Find Prior Art

Citation Information

Patent Citations

  • Packaging methods and structures for semiconductor devices

    CN103000593A

  • Chip Stacked Structure and the Forming Method

    US20090302448A1