Fin field-effect transistor devices with contact plugs including recessed profiles

Abstract

This disclosure relates to a fin field-effect transistor device having a contact plug including a recessed profile. A method of forming a semiconductor device includes: forming a gate structure over a fin protruding above a substrate; forming a source / drain region over the fin on the opposite side of the gate structure; sequentially forming a first dielectric layer and a second dielectric layer over the source / drain region; performing a first etching process to form an opening in the first and second dielectric layers, wherein the opening exposes underlying conductive features; after performing the first etching process, performing a second etching process to widen the opening near the lower portion of the substrate; and forming a contact plug in the opening after the second etching process.

Description

Technical Field

[0001] This disclosure relates to a fin field-effect transistor device having a contact plug including a re-entrant profile. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration density stems from the continuous reduction in the minimum feature size, which allows more components to be integrated into a given area.

[0003] FinFET devices have become increasingly common in integrated circuits. A FinFET device has a three-dimensional structure comprising semiconductor fins protruding from a substrate. A gate structure, configured to control the flow of charge carriers within the conductive channels of the FinFET device, surrounds the semiconductor fins. For example, in a tri-gate FinFET device, the gate structure surrounds three sides of the semiconductor fin, thereby forming conductive channels on the three sides of the semiconductor fin. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a gate structure over a fin protruding above a substrate; forming a source / drain region over the fin on the opposite side of the gate structure; sequentially forming a first dielectric layer and a second dielectric layer over the source / drain region; performing a first etching process to form an opening in the first dielectric layer and the second dielectric layer, wherein the opening exposes underlying conductive features; performing a second etching process after performing the first etching process to enlarge the opening to a lower portion approaching the substrate; and forming a contact plug in the opening after the second etching process.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a gate over a fin protruding above a substrate; forming a source / drain region over the fin adjacent to a gate structure; forming a first dielectric layer over the source / drain region and surrounding the gate; forming a second dielectric layer over the first dielectric layer; forming an opening extending into the first and second dielectric layers using a first etching process, wherein the opening exposes underlying conductive features; increasing the volume of the opening in the first dielectric layer using a second etching process; forming a sacrificial layer along the sidewalls of the opening; forming a spacer layer along the sacrificial layer; filling the opening with a conductive material; and removing the sacrificial layer after filling the opening, wherein after removing the sacrificial layer, an air gap is formed between the first and second dielectric layers and the conductive material.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a fin protruding above a substrate; a gate structure located above the fin; a source / drain region located on the opposite side of the gate structure; a dielectric layer located above the source / drain region; and a contact plug extending through the dielectric layer and electrically coupled to an underlying conductive feature, wherein the upper portion of the contact plug has a straight sidewall profile, and the lower portion of the contact plug has a curved sidewall profile. Attached Figure Description

[0007] When with attachment Figure 1 When reading this document, the following detailed description will best help you understand all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 A perspective view of a FinFET device according to some embodiments is shown.

[0009] Figure 2-7 , Figure 8A , Figure 9-13 and Figures 14A-14C Various cross-sectional views of a FinFET device at different manufacturing stages according to one embodiment are shown.

[0010] Figure 8B and Figure 8C It shows Figure 8A Cross-sectional views of two embodiments of the FinFET device.

[0011] Figure 15 A cross-sectional view of a FinFET device according to another embodiment is shown.

[0012] Figure 16 A cross-sectional view of a FinFET device according to yet another embodiment is shown.

[0013] Figure 17 A flowchart of a method for forming a semiconductor device according to some embodiments is shown. Detailed Implementation

[0014] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact.

[0015] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are also intended to include different orientations of the device being used or operated. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise specified, the same figures in different figures refer to the same or similar components formed using the same or similar materials (one or more) by the same or similar methods.

[0016] The embodiments disclosed herein are discussed in the context of forming FinFET devices, and particularly in the context of forming FinFET devices with contact plugs having recessed profiles. Although FinFET devices are used as examples to discuss the disclosed embodiments, the disclosed methods can also be used for other types of devices, such as planar devices.

[0017] In some embodiments, a first dielectric layer and a second dielectric layer are formed over the source / drain regions of a FinFET device. An opening is formed in the first and second dielectric layers using a first etching process (e.g., an anisotropic etching process) to expose an underlying conductive feature, which may be the source / drain region, a via connecting to the gate structure of the FinFET device, or a via connecting to the source / drain region. Next, a second etching process (e.g., an isotropic etching process) is performed to widen the lower portion of the opening, such that the lower portion of the opening has a curved sidewall profile, while the upper portion of the opening has a linear sidewall profile. Next, a contact plug (also referred to as a via) is formed in the opening by: forming a sacrificial layer along the sidewalls of the opening; forming a spacer layer over the sacrificial layer; filling the opening with a conductive material; and removing the sacrificial layer after filling the opening. After removing the sacrificial layer, an air gap is formed between the spacer layer and the first and second dielectric layers. The air gap can be sealed by forming another dielectric layer over the second dielectric layer. The enlarged lower portion of the opening expands the lower portion of the formed contact plug, thereby reducing the resistance of the contact plug. Furthermore, the air gap advantageously reduces capacitance by lowering the average dielectric constant (K value) of the dielectric material surrounding the contact plug.

[0018] Figure 1 An example of a FinFET 30 is shown in perspective. The FinFET 30 includes a substrate 50 and a fin 64 protruding above the substrate 50. An isolation region 62 is formed on the opposite side of the fin 64, with the fin 64 protruding above the isolation region 62. A gate dielectric 66 runs along the sidewalls of the fin 64 and lies above its top surface, and a gate electrode 68 lies above the gate dielectric 66. A source / drain region 80 is located in the fin 64 and on the opposite side of the gate dielectric 66 and the gate electrode 68. Figure 1 The reference cross sections used in the following figures are further illustrated. Cross section BB extends along the longitudinal axis of the gate electrode 68 of the FinFET 30. Cross section AA is perpendicular to cross section BB and runs along the longitudinal axis of the fin 64 in the direction of current, for example, between the source / drain regions 80. Cross section CC is parallel to cross section BB and crosses the source / drain regions 80. These reference cross sections are referenced in the following figures for clarity.

[0019] Figure 2-7 , Figure 8A , Figure 9-13 and Figures 14A-14C This is a cross-sectional view of a FinFET device 100 at different manufacturing stages according to some embodiments. The FinFET device 100 is similar to... Figure 1 It is a FinFET 30, but with multiple fins and multiple gate structures. Figure 2-5A cross-sectional view of the FinFET device 100 along section BB is shown. Figure 6-7 , Figure 8A , Figure 9-13 and Figure 14A A cross-sectional view of the FinFET device 100 along section AA is shown. Figure 8B and Figure 8C An embodiment cross-sectional view of a FinFET device 100 along section CC is shown. Figure 14B and Figure 14C Cross-sectional views of the FinFET device 100 along sections CC and BB are shown respectively. Throughout this discussion, unless otherwise specified, figures with the same number but different letters (e.g., Figure 14A and Figure 14B () refers to different cross-sectional views of the same device at the same manufacturing stage.

[0020] Figure 2 A cross-sectional view of substrate 50 is shown. Substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., using p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX), a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0021] refer to Figure 3 Patterning is achieved using techniques such as photolithography and etching. Figure 2 The substrate 50 is shown. For example, a mask layer, such as a pad oxide layer 52 and an overlying pad nitride layer 56, is formed on the substrate 50. The pad oxide layer 52 may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer 52 may serve as an adhesive layer between the substrate 50 and the overlying pad nitride layer 56. In some embodiments, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof, and may be formed using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0022] The mask layer can be patterned using photolithography. Generally, photolithography utilizes a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove portions of the photoresist. The remaining photoresist protects the underlying material (e.g., the mask layer in this example) from subsequent processing steps (e.g., etching). In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58, such as... Figure 3 As shown.

[0023] The exposed portion of the substrate 50 is then patterned using a patterning mask 58 to form trenches 61, thereby defining semiconductor fins 64 (e.g., 64A and 64B) between adjacent trenches 61, such as... Figure 3 As shown. In some embodiments, the semiconductor fin 64 is formed by etching trenches in the substrate 50 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching process can be anisotropic. In some embodiments, the trenches 61 can be stripes that are parallel to each other and closely spaced from each other (viewed from top). In some embodiments, the trenches 61 can be continuous and surround the semiconductor fin 64. The semiconductor fin 64 may also be referred to as fin 64 hereinafter.

[0024] Fin 64 can be patterned using any suitable method. For example, fin 64 can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with smaller pitches than those otherwise achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0025] Figure 4An insulating material is formed between adjacent semiconductor fins 64 to form an isolation region 62. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to transform it into another material (e.g., an oxide), or a combination thereof. Other insulating materials and / or other formation processes can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. A planarization process (e.g., chemical mechanical polishing (CMP)) can remove any excess insulating material and form a coplanar (not shown) top surface of the isolation region 62 and the top surface of the semiconductor fin 64. A patterned mask 58 (see...) Figure 3 This can also be removed using the planarization process.

[0026] In some embodiments, the isolation region 62 includes a liner, such as a liner oxide (not shown), located at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the liner oxide is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the liner oxide can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, but other suitable methods can also be used to form the liner oxide.

[0027] Next, isolation region 62 is recessed to form shallow trench isolation (STI) region 62. The isolation region 62 is recessed such that the upper portion of semiconductor fin 64 protrudes between adjacent STI regions 62. The top surface of STI region 62 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of STI region 62 can be formed as flat, convex, and / or concave by appropriate etching. An acceptable etching process (e.g., an etching process selective for the material of isolation region 62) can be used to recess isolation region 62. For example, dry etching or wet etching using dilute hydrofluoric acid (dHF) can be performed to recess isolation region 62.

[0028] Figures 2 to 4 An embodiment of forming fin 64 is shown, but the fin can be formed in a variety of different processes. For example, the top portion of substrate 50 can be replaced with a suitable material, such as an epitaxial material suitable for the type of semiconductor device to be formed (e.g., N-type or P-type). Subsequently, substrate 50 with epitaxial material on top is patterned to form semiconductor fin 64 including the epitaxial material.

[0029] As another example, a dielectric layer can be formed above the top surface of the substrate; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form fins.

[0030] In yet another example, a dielectric layer can be formed above the top surface of the substrate; trenches can be etched through the dielectric layer; a heteroepitaxial structure can be epitaxially grown in the trenches using a material different from the substrate; and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form a fin.

[0031] In embodiments where one or more epitaxial materials or structures (e.g., heteroepitaxial or homoepitaxial structures) are grown, the grown material or structure may be doped in situ during growth, which avoids prior and subsequent implantation, but in-situ doping and implantation doping can be used together. Furthermore, it may be advantageous to epitaxially grow a material different from the material in the PMOS region in the NMOS region. In various embodiments, fin 64 may comprise silicon-germanium (Si... x Ge 1-x (where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0032] Figure 5 A dummy gate structure 75 is shown formed on a semiconductor fin 64. In some embodiments, the dummy gate structure 75 includes a gate dielectric 66 and a gate electrode 68. A mask 70 may be formed on the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fin 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, or a multilayer thereof, and may be deposited or thermally grown.

[0033] A gate layer is formed on top of a dielectric layer, and a mask layer is formed on top of the gate layer. The gate layer may be deposited on top of the dielectric layer and then planarized, for example, by CMP. The mask layer may be deposited on top of the gate layer. The gate layer may be formed of, for example, polysilicon, but other materials may also be used. The mask layer may be formed of, for example, silicon nitride.

[0034] After these layers (e.g., dielectric layer, gate layer, and mask layer) are formed, the mask layer can be patterned using acceptable photolithography and etching techniques to form mask 70. The pattern of mask 70 can then be transferred to the gate layer and dielectric layer using acceptable etching techniques to form gate electrode 68 and gate dielectric 66, respectively. Gate electrode 68 and gate dielectric 66 cover corresponding channel regions of semiconductor fin 64. Gate electrode 68 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the corresponding semiconductor fin 64.

[0035] exist Figure 5 In the example, the gate dielectric 66 is shown formed over the fin 64 (e.g., over the top surface and sidewalls of the fin 64) and over the STI region 62. In other embodiments, the gate dielectric 66 may be formed by thermal oxidation of, for example, the material of the fin 64, and thus may be formed over the fin 64 but not over the STI region 62. These and other variations are intended to be fully included within the scope of this disclosure.

[0036] Figure 6-7 , Figure 8A , Figure 9-13 and Figure 14A A cross-sectional view of the FinFET device 100 is shown, further processed along section AA (along the longitudinal axis of fin 64). Note that in Figure 6-7 , Figure 8A and Figure 9 In this embodiment, three dummy gate structures 75 (e.g., 75A, 75B, and 75C) are formed on the fin 64. Those skilled in the art will recognize that more or fewer than three gate structures may be formed on the fin 64, and these and other variations are intended to be included within the scope of this disclosure.

[0037] like Figure 6 As shown, a lightly doped drain (LDD) region 65 is formed in fin 64. LDD region 65 can be formed by a plasma doping process. The plasma doping process may include forming and patterning a mask (e.g., a photoresist) to cover the region of the FinFET to be protected from the plasma doping process. The plasma doping process can implant N-type or P-type impurities into fin 64 to form LDD region 65. For example, P-type impurities (e.g., boron) can be implanted into fin 64 to form LDD region 65 for P-type devices. As another example, N-type impurities (e.g., phosphorus) can be implanted into fin 64 to form LDD region 65 for N-type devices. In some embodiments, LDD region 65 is adjacent to the channel region of FinFET device 100. A portion of LDD region 65 may extend below gate electrode 68 and into the channel region of FinFET device 100. Figure 6A non-limiting example of LDD region 65 is shown. Other configurations, shapes, and formation methods of LDD region 65 are also possible and are fully intended to be included within the scope of this disclosure. For example, LDD region 65 may be formed after the gate spacer body 87 is formed. In some embodiments, LDD region 65 is omitted. For simplicity, LDD region 65 is not shown in the following figures, and it is understood that LDD region 65 may be formed in fin 64.

[0038] Still referencing Figure 6 After forming the LDD region 65, a gate spacer 87 is formed around the dummy gate structure 75. The gate spacer 87 may include a first gate spacer 72 and a second gate spacer 86. For example, the first gate spacer 72 may be a gate sealing spacer and is formed on the opposite side of the gate electrode 68 and the opposite side of the gate dielectric 66. The second gate spacer 86 is formed on the first gate spacer 72. The first gate spacer 72 may be formed of a nitride (e.g., silicon nitride, silicon oxide, silicon carbonitride, etc., or combinations thereof) and may be formed using, for example, thermal oxidation, CVD, or other suitable deposition processes. The second gate spacer 86 may be formed of silicon nitride, silicon carbonitride, combinations thereof, or the like using suitable deposition methods.

[0039] In this embodiment, a gate spacer 87 is formed by first conformally depositing a first gate spacer layer on the FinFET device 100, and then conformally depositing a second gate spacer layer on the deposited first gate spacer layer. Next, an anisotropic etching process, such as a dry etching process, is performed to remove a first portion of the second gate spacer layer disposed on the upper surface of the FinFET device 100 (e.g., the upper surface of mask 70), while retaining a second portion of the second gate spacer layer disposed along the sidewalls of the gate structure. The remaining second portion of the second gate spacer layer after the anisotropic etching process forms a second gate spacer 86. The anisotropic etching process also removes a portion of the first gate spacer layer disposed outside the sidewalls of the second gate spacer 86, and the remaining portion of the first gate spacer layer forms a first gate spacer 72.

[0040] like Figure 6 The shape and formation method of the gate spacer 87 shown are merely non-limiting examples, and other shapes and formation methods are possible. These and other variations are intended to be included within the scope of this disclosure.

[0041] Next, as Figure 7As shown, a groove 88 is formed in a fin 64 adjacent to a dummy gate structure 75, for example, between and / or near adjacent dummy gate structures 75. In some embodiments, the groove 88 is formed by an anisotropic etching process, for example, using the dummy gate structure 75 and the gate spacer 87 as an etching mask, but any other suitable etching process may also be used.

[0042] Next, as Figure 8A As shown, the source / drain region 80 is formed in the groove 88. The source / drain region 80 is formed by epitaxially growing materials in the groove 88 using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or combinations thereof.

[0043] like Figure 8A As shown, the epitaxial source / drain region 80 may have a surface that protrudes from the corresponding surface of the fin 64 (e.g., protrudes above the non-recessed upper surface 64U of the fin 64) and may have facets. The source / drain regions 80 of adjacent fins 64 may merge to form a continuous epitaxial source / drain region 80 (see [reference]). Figure 8B In some embodiments, the source / drain regions 80 of adjacent fins 64 are not merged together and remain separate source / drain regions 80 (see [link]). Figure 8C In some embodiments, the resulting FinFET is an n-type FinFET, and the source / drain region 80 includes silicon carbide (SiC), silicon-phosphorus (SiP), phosphorus-doped silicon-carbon (SiCP), etc. In some embodiments, the resulting FinFET is a p-type FinFET, and the source / drain region 80 includes SiGe and p-type impurities, such as boron or indium.

[0044] The epitaxial source / drain region 80 can be formed by implanting dopants, followed by an annealing process. The implantation process may include forming and patterning a mask (e.g., a photoresist) to cover the areas of the FinFET device 100 to be protected from the implantation process. The impurity (e.g., dopant) concentration of the source / drain region 80 can be approximately 1E19 cm⁻¹. -3 Up to approximately 1E21cm -3 Within the range. P-type impurities (e.g., boron or indium) can be implanted into the source / drain region 80 of the P-type transistor. N-type impurities (e.g., phosphorus or arsenide) can be implanted into the source / drain region 80 of the N-type transistor. In some embodiments, the epitaxial source / drain region can be doped in situ during growth.

[0045] Next, as Figure 9 As shown, in Figure 8A A contact etch stop layer (CESL) 89 is formed on the structure shown. The CESL 89 acts as an etch stop layer in subsequent etch processes and may include suitable materials such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, etc., and may be formed by suitable formation methods (e.g., CVD, PVD, combinations thereof, etc.).

[0046] Next, a first interlayer dielectric (ILD) 90 is formed over CESL 89 and dummy gate structures 75 (e.g., 75A, 75B, and 75C). In some embodiments, the first ILD 90 is formed of a dielectric material (e.g., silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.) and can be deposited by any suitable method (e.g., CVD, PECVD, or FCVD). A planarization process (e.g., CMP) can be performed to remove the mask 70 and the portion of CESL 89 disposed above the gate electrode 68. After the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate electrode 68.

[0047] Next, in Figure 10 In this embodiment, a gate-last process (sometimes referred to as a gate replacement process) is performed to replace gate electrode 68 and gate dielectric 66 with an active gate (also referred to as a replacement gate or metal gate) and (one or more) active gate dielectric materials, respectively. Therefore, in the gate-last process, gate electrode 68 and gate dielectric 66 may be referred to as a dummy gate electrode and a dummy gate dielectric, respectively. In some embodiments, the active gate is a metal gate.

[0048] refer to Figure 10 Virtual gate structures 75A, 75B, and 75C (see...) Figure 9 The gates 68 and 97B are replaced by replacement gate structures 97A, 97B, and 97C, respectively. According to some embodiments, to form the replacement gate structure 97 (e.g., 97A, 97B, or 97C), the gate electrode 68 and the gate dielectric 66 located directly beneath the gate electrode 68 are removed in one or more etching steps to form a groove (not shown) between the gate spacers 87. Each groove exposes a channel region of the corresponding fin 64. During dummy gate removal, the gate dielectric 66 can be used as an etch stop layer when etching the gate electrode 68. The gate dielectric 66 can then be removed after the gate electrode 68 has been removed.

[0049] Next, a gate dielectric layer 94, a barrier layer 96, a work function layer 98, and a gate electrode 99 are formed in the recess of the replacement gate structure 97. The gate dielectric layer 94 is conformally deposited in the recess, for example, on the top surface and sidewalls of the fin 64, on the sidewalls of the gate spacer 87, and on the top surface of the first ILD 90 (not shown). According to some embodiments, the gate dielectric layer 94 comprises silicon oxide, silicon nitride, or a multilayer thereof. In other embodiments, the gate dielectric layer 94 comprises a high-k dielectric material, and in these embodiments, the k value of the gate dielectric layer 94 may be greater than about 7.0, and may comprise metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the gate dielectric layer 94 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0050] Next, a barrier layer 96 is conformally formed over the gate dielectric layer 94. The barrier layer 96 may comprise a conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, etc., may be used alternatively. The barrier layer 96 may be formed using a CVD process such as PECVD. However, other alternative processes such as sputtering, metal-organic chemical vapor deposition (MOCVD), or ALD may be used.

[0051] Next, in some embodiments, a work function layer 98 (e.g., a P-type work function layer or an N-type work function layer) may be formed in a recess above the barrier layer 96 and is formed prior to the formation of the gate electrode 99. Exemplary P-type work function metals that may be included in the gate structure for a P-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable P-type work function materials, or combinations thereof. Exemplary N-type work function metals that may be included in the gate structure for an N-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer; therefore, the material of the work function layer is selected to adjust its work function value in order to achieve a target threshold voltage Vt in the device to be formed. One or more work function layers may be deposited by CVD, physical vapor deposition (PVD), and / or other suitable processes.

[0052] Next, a seed layer (not shown) is conformally formed on the work function layer 98. The seed layer may include copper, titanium, tantalum, titanium nitride, tantalum nitride, or combinations thereof, and may be deposited by ALD, sputtering, PVD, or the like. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. For example, the seed layer includes a titanium layer and a copper layer on top of the titanium layer.

[0053] Next, a gate electrode 99 is deposited on top of the seed layer and fills the remaining portion of the trench. The gate electrode 99 can be made of a material including metals, such as Cu, Al, W, combinations thereof, or multiples thereof, and can be formed, for example, by electroplating, electroless plating, or other suitable methods. After forming the gate electrode 99, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer 94, barrier layer 96, work function layer 98, seed layer, and gate electrode 99 located above the top surface of the first ILD 90. The resulting remaining portions of the gate dielectric layer 94, barrier layer 96, work function layer 98, seed layer, and gate electrode 99 thus form the replacement gate structure 97 of the obtained FinFET device 100.

[0054] Next reference Figure 11 A second ILD 92 is formed on top of the first ILD 90. An opening 93 is formed through the second ILD 92 and the first ILD 90 to expose the source / drain region 80.

[0055] In some embodiments, the second ILD 92 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 92 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. In some embodiments, the second ILD 92 and the first ILD 90 are formed of the same material. In some embodiments, the second ILD 92 and the first ILD 90 are formed of different materials.

[0056] In some embodiments, photolithography and etching are used to form Figure 11 The opening 93 is in the middle. An etching process etches through CESL89 to expose the source / drain region 80. In some embodiments, Figure 11 The opening 93 is formed using an anisotropic etching process (e.g., anisotropic plasma etching). In an embodiment, the anisotropic plasma etching process uses a gas source comprising CF4, C4F6, C4F8, or combinations thereof. Following the anisotropic etching process, Figure 11 The sidewalls of the opening 93 have a straight profile; for example, each sidewall of the opening 93 extends along a corresponding straight line (e.g., an inclined straight line).

[0057] Next, in Figure 12 In this process, an isotropic etching process, such as an isotropic plasma etching process, is performed to expand the lower portion of the opening 93. In an embodiment, the isotropic plasma etching process uses a gas source comprising Cl2, HBr, or a combination thereof. As an example, the bias power (or bias voltage) of the plasma etching tool can be adjusted (e.g., reduced) to achieve isotropic plasma etching. In some embodiments, the first ILD 90 and the second ILD 92 are formed of the same or similar materials (e.g., the first ILD 90 is silicon oxide formed by PECVD, and the second ILD 92 is silicon oxide formed by FCVD), and the gas source of the isotropic etching process has high etch selectivity (e.g., a higher etch rate) for the first and second ILDs 90 / 92 compared to the source / drain region 80. In some embodiments, during the isotropic etching process, the etching gas in the upper part of the opening 93 tends to diffuse out of the opening 93, while the etching gas in the lower part of the opening 93 is retained and removes (e.g., etches) a portion of the first ILD 90, such that the lower part of the opening 93 (e.g., the portion within the first ILD 90) is enlarged by the isotropic etching process, while the upper part of the opening 93 (e.g., the portion in the second ILD 92) remains substantially unchanged. Therefore, after the isotropic etching process, the upper part of the opening 93 has a straight sidewall profile, while the lower part of the opening 93 has a curved sidewall profile; for example, the sidewalls of the lower part of each opening 93 are curved. Although the isotropic plasma etching process is used as an example, other suitable isotropic etching processes, such as wet etching processes, can also be used.

[0058] Isotropic etching processes increase the volume of the lower part of opening 93. For example... Figure 12 As shown, each opening 93 has a first width A on the upper surface of the second ILD 92 and a second width B at the bottom of the opening 93, wherein B is greater than A. In some embodiments, the second width B is a value between approximately 1 nm and approximately 5 nm greater than the first width A (e.g., 5 nm ≥ A ≥ 1 nm), for example, approximately 1 nm. The angle α between straight lines R1 and R2 is between approximately 87 degrees and approximately 91 degrees, for example, approximately 87 degrees, wherein straight line R1 extends along a straight sidewall (e.g., a sloping straight sidewall) at the upper part of the opening 93, and straight line R2 is parallel to the main upper surface of the substrate 50.

[0059] Next, in Figure 13In the first ILD 90, a sacrificial layer 121 is formed (e.g., conformally) in the opening 93 along the sidewalls of the first ILD 90 and the second ILD 92. Next, a spacer layer 123 is formed (e.g., conformally) over and along the sacrificial layer 121. Then, a silicide region 95 is formed over the source / drain region 80 at the bottom of the opening 93, and a conductive material 125 is formed to fill the opening 93. Details are as follows.

[0060] In an embodiment, the sacrificial layer 121 is a semiconductor layer, such as a silicon layer, and is formed by a suitable deposition process such as ALD, CVD, PECVD, etc. In some embodiments, the deposited sacrificial layer 121 extends conformally along the sidewalls and bottom of the opening 93 and along the upper surface of the second ILD 92. Next, an etching process (e.g., an anisotropic etching process) is performed to remove a portion of the sacrificial layer 121 from the bottom of the opening 93 to expose the underlying source / drain region 80. The etching process may also remove a portion of the sacrificial layer 121 from the upper surface of the second ILD 92. After the etching process, the sacrificial layer 121 is disposed along the sidewalls of the opening 93. In a subsequent process, the sacrificial layer 121 is removed to form an air gap between the first ILD / second ILD 90 / 92 and the spacer layer 123. Although silicon is used as an example of the sacrificial layer 121, any other suitable material (e.g., a material that can be selectively removed by a subsequent etching process) may be used as the sacrificial layer 121.

[0061] Next, a spacer layer 123 is formed (e.g., conformally) in the opening 93 and over the sacrificial layer 121. In an embodiment, the spacer layer 123 is a dielectric layer, such as a silicon nitride layer, and is formed by a suitable deposition process such as ALD, CVD, PECVD, etc. The spacer layer 123 is formed using a material different from that of the sacrificial layer 121 to provide etch selectivity, such that in a subsequent etch process to remove the sacrificial layer 121, the sacrificial layer 121 is removed with substantially no impact on the spacer layer 123.

[0062] In some embodiments, the deposited spacer layer 123 extends conformally along the sidewalls and bottom of the opening 93 and along the upper surface of the second ILD 92. Next, another etching process (e.g., an anisotropic etching process) is performed to remove a portion of the spacer layer 123 from the bottom of the opening 93 to expose the underlying source / drain region 80. Another etching process may also remove a portion of the spacer layer 123 from the upper surface of the second ILD 92. After this other etching process, the spacer layer 123 is disposed on the sacrificial layer 121 along the sidewalls of the opening 93.

[0063] Next, a silicide region 95 (optional) is formed in the opening 93, above the source / drain region 80. In some embodiments, the silicide region 95 is formed by first depositing a metal (e.g., nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof) capable of reacting with a semiconductor material (e.g., silicon, germanium) to form a silicide or germanide region on the exposed portion of the epitaxial source / drain region 80, and then performing a thermal annealing process to form the silicide region 95. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although region 95 is referred to as a silicide region, region 95 can also be a germanide region or a silicon-germanide region (e.g., a region comprising both silicides and germanides).

[0064] Next, a barrier layer (not shown) is formed (e.g., conformally) in the opening 93. The barrier layer may include a conductive material, such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, etc. may be used alternatively. The barrier layer may be formed using ALD, CVD, PECVD, MOCVD, etc.

[0065] Next, a conductive material 125 is formed in the opening 93 to fill it. The conductive material 125 can be made of a metallic material, such as Cu, Al, W, or combinations thereof, or multiples thereof, and can be formed by, for example, electroplating, electroless plating, or other suitable methods. A planarization process such as CMP can be performed to remove excess portions of the layers (e.g., 121, 123, the barrier layer, and 125) disposed above the upper surface of the second ILD 92. Note that the conductive material 125 also has an enlarged lower portion due to the enlarged lower portion of the opening 93, which advantageously reduces the resistance of the formed contact plug. For example, the conductive material 125 in each opening 93 has an upper portion including a straight sidewall profile and a lower portion including a curved sidewall profile, and the lower portion is wider than the upper portion.

[0066] Next, in Figure 14AIn this embodiment, a selective etching process is performed to remove the sacrificial layer 121. In one embodiment, the sacrificial layer 121 is a silicon layer, and the chemicals used in the selective etching process include hydrogen (H2) and nitrogen fluoride (NF3). In another embodiment, a chemical comprising ammonium hydroxide (NH4OH) is used to selectively remove the sacrificial layer 121. Note that the selective etching process for removing the sacrificial layer 121 differs from the etching process for forming the openings 93. After the selective etching process, an air gap 124 is formed between the first ILD / second ILD 90 / 92 and the spacer layer 123. The air gap 124 advantageously reduces the capacitance of the formed device because it lowers the average dielectric constant (K value) of the dielectric material (e.g., the first ILD 90 and the second ILD 92) surrounding the formed contact plug. Thus, the air gap 124, spacer layer 123, barrier layer, and conductive material 125 in each opening 93 form a contact plug 104 with a recessed profile. Figure 14A The contact plug 104 is electrically coupled to the source / drain region 80, and is therefore also called the source / drain contact plug.

[0067] Next, an impurity (e.g., Ge) is implanted into the top portion of the second ILD 92 via an implantation process to (at least partially) seal the air gap 124, and subsequently, a dielectric layer 111 is formed on the second ILD 92. In some embodiments, the implantation process implants a suitable impurity (e.g., germanium) into the top portion of the second ILD 92. The implantation process causes the top portion of the second ILD 92 to expand (e.g., extend), thereby sealing (e.g., completely or partially sealing) the air gap 124. Figure 14A As shown, a portion 92S (caused by the expansion of the top portion of the second ILD 92) seals the air gap 124, and this portion 92S may include impurities (e.g., Ge). Conductive features 113 (e.g., conductive lines) are formed in the dielectric layer 111. The conductive features 113 in the dielectric layer 111 and / or the dielectric layer 111 can further seal the air gap 124. As will be readily understood by those skilled in the art, in Figure 14A After the initial process, additional processes can be used to manufacture the FinFET device 100, but the details will not be repeated here.

[0068] Figure 14B It shows Figure 14A The FinFET device 100 is located along the cross section CC. Figure 14C It shows Figure 14A The FinFET device 100 is located along the cross section BB.

[0069] Figure 15A cross-sectional view of a FinFET device 100A according to another embodiment is shown. FinFET device 100A is similar to FinFET device 100, but has a contact plug 104 (also referred to as a via-to-contact plug) formed in dielectric layers 111 / 112 disposed on a second ILD 92. In other words, the source / drain region 80 is first electrically coupled to the contact plug 102 (which may or may not have a recessed profile), and then the via-to-contact plug 104 is formed on and electrically coupled to the lower contact plug 102. Figure 15 In the example, the contact plug 102 does not have a recessed profile. In other embodiments, Figure 15 The contact plug 102 in the middle can be replaced by a contact plug with a concave profile (e.g., contact plug 104).

[0070] exist Figure 15 In the first ILD 90 and the second ILD 92, contact plugs 102 (also referred to as contacts) are formed. Each of the contacts 102 includes a barrier layer 101, a seed layer 103, and a conductive material 105, and is electrically coupled to an underlying conductive feature (e.g., a source / drain region 80). The materials and formation methods of the barrier layer 101, seed layer 103, and conductive material 105 may be the same as or similar to those discussed above for the barrier layer 96, seed layer, and gate electrode 99 of the replacement gate structure 97, and therefore details are not repeated. The contact plug 104 may use materials similar to those discussed above for the barrier layer 96, seed layer, and gate electrode 99 of the replacement gate structure 97. Figure 11-14A The same or similar processing steps are formed as shown. For example... Figure 15 As shown, impurities (e.g., germanium) can be injected into the top portion of dielectric layer 112 to cause it to expand, thereby sealing (e.g., completely or partially sealing) the corresponding air gap 124 of portion 112S of dielectric layer 112.

[0071] Figure 16 A cross-sectional view of a FinFET device 100B according to another embodiment is shown. The FinFET device 100B is similar to the FinFET device 100, but has a contact plug 104 with a recessed profile (also referred to as a via-to-gate plug) formed in the dielectric layers 111 / 112 and the first ILD / second ILD 90 / 92 and electrically coupled to the alternative gate structure 97.

[0072] Variations of the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. For example, through-hole to contact plug 104 (with a recessed profile) and lower contact plug 102 (e.g., see...). Figure 15 The combination of these can be used to replace the contact plug 102, which is used alone as an electrical connection contact, for example... Figure 16The contact plug 102 in the middle.

[0073] Figure 17 A flowchart of a method 1000 for forming a semiconductor device according to some embodiments is shown. It should be understood that... Figure 17 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 17 The various steps are shown.

[0074] Reference Figure 17 In step 1010, a gate structure is formed over a fin protruding above the substrate. In step 1020, a source / drain region is formed over the fin on the opposite side of the gate structure. In step 1030, a first dielectric layer and a second dielectric layer are sequentially formed over the source / drain region. In step 1040, a first etching process is performed to form an opening in the first and second dielectric layers, wherein the opening exposes the underlying conductive features. In step 1050, after performing the first etching process, a second etching process is performed to enlarge the opening near the lower portion of the substrate. In step 1060, a contact plug is formed in the opening after the second etching process.

[0075] The embodiments can achieve advantages. For example, the disclosed cleaning method allows the contact plug to be formed with an enlarged lower portion, thereby reducing the resistance of the formed contact plug. In addition, the air gap of the contact plug helps to prevent or reduce metal diffusion and can further reduce the average dielectric constant (k value) of the formed device.

[0076] According to an embodiment, a method of forming a semiconductor device includes: forming a gate structure over a fin protruding above a substrate; forming a source / drain region over the fin on the opposite side of the gate structure; sequentially forming a first dielectric layer and a second dielectric layer over the source / drain region; performing a first etching process to form an opening in the first dielectric layer and the second dielectric layer, wherein the opening exposes underlying conductive features; after performing the first etching process, performing a second etching process to enlarge the lower portion of the opening near the substrate; and forming a contact plug in the opening after the second etching process. In an embodiment, the first etching process is an anisotropic etching process. In an embodiment, the second etching process is an isotropic etching process. In an embodiment, the opening has a straight sidewall profile after the first etching process and before the second etching process, wherein after the second etching process, the lower portion of the opening has a curved sidewall profile, and the upper portion of the opening away from the substrate has a straight profile. In one embodiment, after the second etching process, the lower portion of the opening has a first width, and the upper portion of the opening away from the substrate has a second width, wherein the first width is greater than the second width. In one embodiment, the first etching process is an anisotropic plasma etching process performed using a gas source including CF4, C4F6, or C4F8. In one embodiment, the second etching process is an isotropic plasma etching process performed using a gas source including Cl2 or HBr. In one embodiment, forming the contact plug includes: forming a sacrificial layer lining the sidewalls of the opening; forming a spacer layer over the sacrificial layer; filling the opening with a conductive material; and removing the sacrificial layer after filling the opening, wherein after removing the sacrificial layer, an air gap is formed between the first dielectric layer and the second dielectric layer and the spacer layer. In one embodiment, the sacrificial layer is formed along the sidewalls of the opening, and there is no sacrificial layer at the bottom of the opening. In one embodiment, the method further includes: after removing the sacrificial layer, forming a third dielectric layer over the second dielectric layer, the third dielectric layer sealing the air gap. In one embodiment, the spacer layer is formed using a nitride, and the sacrificial layer is formed using a semiconductor material. In another embodiment, the nitride is silicon nitride, and the semiconductor material is silicon.

[0077] According to an embodiment, a method of forming a semiconductor device includes: forming a gate over a fin protruding above a substrate; forming a source / drain region over the fin adjacent to the gate structure; forming a first dielectric layer over the source / drain region and surrounding the gate; forming a second dielectric layer over the first dielectric layer; forming an opening extending into the first and second dielectric layers using a first etching process, wherein the opening exposes underlying conductive features; increasing the volume of the opening in the first dielectric layer using a second etching process; forming a sacrificial layer along the sidewalls of the opening; forming a spacer layer along the sacrificial layer; filling the opening with a conductive material; and removing the sacrificial layer after filling the opening, wherein after removing the sacrificial layer, an air gap is formed between the first and second dielectric layers and the conductive material. In an embodiment, the method further includes sealing the air gap by forming a third dielectric layer over the second dielectric layer. In an embodiment, the first etching process is an anisotropic etching process, and the second etching process is an isotropic etching process. In an embodiment, the second etching process is performed using an etchant selective for the material of the first dielectric layer.

[0078] According to an embodiment, a semiconductor device includes: a fin protruding above a substrate; a gate structure located above the fin; a source / drain region located on the opposite side of the gate structure; a dielectric layer located above the source / drain region; and a contact plug extending through the dielectric layer and electrically coupled to an underlying conductive feature, wherein the upper portion of the contact plug has a straight sidewall profile, and the lower portion of the contact plug has a curved sidewall profile. In an embodiment, the width of the lower portion of the contact plug near the substrate is greater than the width of the upper portion of the contact plug away from the substrate. In an embodiment, the contact plug includes: a conductive material; a spacer layer surrounding the conductive material; and an air gap located between the spacer layer and the dielectric layer. In an embodiment, the underlying conductive feature is one of the source / drain regions, the gate structure, or a via connected to the gate structure or connected to one of the source / drain regions.

[0079] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same objectives and / or realize the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

[0080] Example 1. A method of forming a semiconductor device, the method comprising: forming a gate structure over a fin protruding above a substrate; forming a source / drain region over the fin on the opposite side of the gate structure; sequentially forming a first dielectric layer and a second dielectric layer over the source / drain region; performing a first etching process to form an opening in the first dielectric layer and the second dielectric layer, wherein the opening exposes underlying conductive features; after performing the first etching process, performing a second etching process to enlarge the opening to a lower portion protruding from the substrate; and after the second etching process, forming a contact plug in the opening.

[0081] Example 2. The method according to Example 1, wherein the first etching process is an anisotropic etching process.

[0082] Example 3. The method according to Example 2, wherein the second etching process is an isotropic etching process.

[0083] Example 4. The method according to Example 3, wherein, after the first etching process and before the second etching process, the opening has a straight sidewall profile, wherein, after the second etching process, the lower portion of the opening has a curved sidewall profile, and the upper portion of the opening away from the substrate has a straight profile.

[0084] Example 5. The method according to Example 4, wherein, after the second etching process, the lower portion of the opening has a first width, and the upper portion of the opening away from the substrate has a second width, wherein the first width is greater than the second width.

[0085] Example 6. The method according to Example 1, wherein the first etching process is an anisotropic plasma etching process performed using a gas source including CF4, C4F6 or C4F8.

[0086] Example 7. The method according to Example 6, wherein the second etching process is an isotropic plasma etching process performed using a gas source including Cl2 or HBr.

[0087] Example 8. The method according to Example 1, wherein forming the contact plug includes: forming a sacrificial layer lining the sidewall of the opening; forming a spacer layer on the sacrificial layer; filling the opening with a conductive material; and removing the sacrificial layer after filling the opening, wherein after removing the sacrificial layer, an air gap is formed between the first dielectric layer and the second dielectric layer and the spacer layer.

[0088] Example 9. The method according to Example 8, wherein the sacrificial layer is formed along the sidewall of the opening, and the bottom of the opening does not have the sacrificial layer.

[0089] Example 10. The method according to Example 9 further includes: after removing the sacrificial layer, forming a third dielectric layer on top of the second dielectric layer, the third dielectric layer sealing the air gap.

[0090] Example 11. The method according to Example 8, wherein the spacer layer is formed using a nitride and the sacrificial layer is formed using a semiconductor material.

[0091] Example 12. The method according to Example 11, wherein the nitride is silicon nitride and the semiconductor material is silicon.

[0092] Example 13. A method of forming a semiconductor device, the method comprising: forming a gate over a fin protruding above a substrate; forming a source / drain region over the fin adjacent to the gate structure; forming a first dielectric layer over the source / drain region and surrounding the gate; forming a second dielectric layer over the first dielectric layer; forming an opening extending into the first and second dielectric layers using a first etching process, wherein the opening exposes underlying conductive features; increasing the volume of the opening in the first dielectric layer using a second etching process; forming a sacrificial layer along the sidewalls of the opening; forming a spacer layer along the sacrificial layer; filling the opening with a conductive material; and removing the sacrificial layer after filling the opening, wherein after removing the sacrificial layer, an air gap is formed between the first and second dielectric layers and the conductive material.

[0093] Example 14. The method according to Example 13 further includes: sealing the air gap by forming a third dielectric layer over the second dielectric layer.

[0094] Example 15. The method according to Example 13, wherein the first etching process is an anisotropic etching process and the second etching process is an isotropic etching process.

[0095] Example 16. The method according to Example 15, wherein the second etching process is performed using an etchant that is selective for the material of the first dielectric layer.

[0096] Example 17. A semiconductor device comprising: a fin protruding above a substrate; a gate structure located above the fin; a source / drain region located on the opposite side of the gate structure; a dielectric layer located above the source / drain region; and a contact plug extending through the dielectric layer and electrically coupled to an underlying conductive feature, wherein an upper portion of the contact plug has a straight sidewall profile and a lower portion of the contact plug has a curved sidewall profile.

[0097] Example 18. The semiconductor device according to Example 17, wherein the width of the lower portion of the contact plug near the substrate is greater than the width of the upper portion of the contact plug away from the substrate.

[0098] Example 19. The semiconductor device according to Example 17, wherein the contact plug comprises: a conductive material; a spacer layer surrounding the conductive material; and an air gap located between the spacer layer and the dielectric layer.

[0099] Example 20. A semiconductor device according to Example 17, wherein the underlying conductive feature is one of the source / drain regions, the gate structure, or a via connected to the gate structure or connected to one of the source / drain regions.

Claims

1. A method for forming a semiconductor device, the method comprising: A gate structure is formed on a fin that protrudes above the substrate; On the opposite side of the gate structure, a source / drain region is formed on the fin; A first dielectric layer and a second dielectric layer are sequentially formed on the source / drain region; A first etching process is performed to form openings in the first dielectric layer and the second dielectric layer, wherein the openings expose underlying conductive features; After performing the first etching process, a second etching process is performed to enlarge the opening near the lower portion of the substrate; and After the second etching process, a contact plug is formed in the opening, wherein forming the contact plug includes: A sacrificial layer is formed as a lining on the sidewalls of the opening; The opening is filled with a conductive material; After filling the opening, the sacrificial layer is removed, wherein after removing the sacrificial layer, an air gap is formed between the first dielectric layer and the second dielectric layer and the conductive material; and After the sacrificial layer is removed, an implantation process is performed on the second dielectric layer, wherein the implantation process causes the upper part of the second dielectric layer to expand to seal the air gap.

2. The method according to claim 1, wherein, The first etching process is an anisotropic etching process.

3. The method according to claim 2, wherein, The second etching process is an isotropic etching process.

4. The method according to claim 3, wherein, After the first etching process and before the second etching process, the opening has a straight sidewall profile, wherein after the second etching process, the lower portion of the opening has a curved sidewall profile, and the upper portion of the opening away from the substrate has a straight profile.

5. The method according to claim 4, wherein, After the second etching process, the lower part of the opening has a first width, and the upper part of the opening away from the substrate has a second width, wherein the first width is greater than the second width.

6. The method according to claim 1, wherein, The first etching process is an anisotropic plasma etching process performed using a gas source including CF4, C4F6, or C4F8.

7. The method according to claim 6, wherein, The second etching process is an isotropic plasma etching process performed using a gas source including Cl2 or HBr.

8. The method according to claim 1, wherein, The sacrificial layer is formed along the sidewall of the opening, and there is no sacrificial layer at the bottom of the opening.

9. The method according to claim 8, further comprising: After the sacrificial layer is removed, a third dielectric layer is formed on top of the second dielectric layer, and the third dielectric layer seals the air gap.

10. The method according to claim 1, further comprising: After forming a sacrificial layer lining the sidewalls of the opening, a spacer layer is formed on top of the sacrificial layer. After the sacrificial layer is removed, the air gap is formed between the first dielectric layer, the second dielectric layer, and the spacer layer. The spacer layer is formed using nitrides, and the sacrificial layer is formed using semiconductor materials.

11. The method according to claim 10, wherein, The nitride is silicon nitride, and the semiconductor material is silicon.

12. A method of forming a semiconductor device, the method comprising: A gate is formed on a fin that protrudes above the substrate; The adjacent gate structure forms a source / drain region on the fin; A first dielectric layer is formed above the source / drain region and around the gate; A second dielectric layer is formed on top of the first dielectric layer; An opening extending into the first dielectric layer and the second dielectric layer is formed using a first etching process, wherein the opening exposes the underlying conductive features; The volume of the opening in the first dielectric layer is increased using a second etching process; A sacrificial layer is formed along the sidewall of the opening; A spacer layer is formed along the sacrificial layer; The opening is filled with a conductive material; After filling the opening, the sacrificial layer is removed, wherein after removing the sacrificial layer, an air gap is formed between the first dielectric layer and the second dielectric layer and the conductive material; and The upper part of the second dielectric layer is expanded by performing an injection process to at least partially seal the air gap.

13. The method of claim 12, further comprising: The air gap is sealed by forming a third dielectric layer on top of the second dielectric layer.

14. The method according to claim 12, wherein, The first etching process is an anisotropic etching process, and the second etching process is an isotropic etching process.

15. The method according to claim 14, wherein, The second etching process is performed using an etchant that is selective for the material of the first dielectric layer.

16. A semiconductor device, comprising: Fins protruding above the substrate; A gate structure located on the fin; The source / drain regions are located on opposite sides of the gate structure; A dielectric layer located above the source / drain regions; as well as A contact plug extending through the dielectric layer and electrically coupled to an underlying conductive feature, wherein a sealed gap exists between the dielectric layer and the conductive feature, and wherein the upper portion of the contact plug has a straight sidewall profile and the lower portion of the contact plug has a curved sidewall profile.

17. The semiconductor device according to claim 16, wherein, The width of the lower portion of the contact plug near the substrate is greater than the width of the upper portion of the contact plug away from the substrate.

18. The semiconductor device according to claim 16, wherein, The contact plug includes: Conductive materials; The spacer layer surrounding the conductive material; and The air gap located between the spacer layer and the dielectric layer.

19. The semiconductor device according to claim 16, wherein, The underlying conductive feature is one of the source / drain regions, the gate structure, or a via, wherein the via is connected to the gate structure or to one of the source / drain regions.

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