Semiconductor device and method

Abstract

The present application discloses a semiconductor device and method. An embodiment method includes: forming a gate stack above a channel region; growing a source / drain region adjacent to the channel region; depositing a first ILD layer above the source / drain region and the gate stack; forming a source / drain contact through the first ILD layer; forming a gate contact through the first ILD layer, the gate contact being in physical contact with the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being located at a first interface between the source / drain contact and the first ILD layer, and the second sidewall being located at a second interface between the gate contact and the first ILD layer; forming a first conductive feature, the first conductive feature being in physical contact with a first sidewall and a first top surface of the source / drain contact; and forming a second conductive feature, the second conductive feature being in physical contact with a second sidewall and a second top surface of the gate contact.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of materials on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other issues arise that should be addressed. Summary of the invention

[0004] According to one aspect of the present disclosure, a structure for manufacturing a semiconductor device is provided, comprising: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first interlayer dielectric ILD layer located above the source / drain region and the gate stack; a first intermetallic dielectric IMD layer located above the first ILD layer; a first conductive feature extending through the first IMD layer; a second conductive feature extending through the first IMD layer; a source / drain contact extending through the first ILD layer and partially extending into the first conductive feature, the source / drain contact being in physical contact with the source / drain region and the first conductive feature; and a gate contact extending through the first ILD layer and partially extending into the second conductive feature, the gate contact being in physical contact with the gate stack and the second conductive feature.

[0005] According to another aspect of the present disclosure, a structure for manufacturing a semiconductor device is provided, comprising: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first interlayer dielectric ILD layer located above the source / drain region and the gate stack; a first intermetallic dielectric IMD layer located above the first ILD layer; a first conductive feature extending through the first IMD layer and partially extending into the first ILD layer; a second conductive feature extending through the first IMD layer and partially extending into the first ILD layer; a source / drain contact partially extending into the first ILD layer, the source / drain contact being in physical contact with the source / drain region and the first conductive feature; and a gate contact partially extending into the first ILD layer, the gate contact being in physical contact with the gate stack and the second conductive feature.

[0006] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a gate stack over a channel region of a substrate; growing a source / drain region adjacent to the channel region; depositing a first interlayer dielectric ILD layer over the source / drain region and the gate stack; forming a source / drain contact through the first ILD layer, the source / drain contact being in physical contact with the source / drain region; forming a gate contact through the first ILD layer, the gate contact being in physical contact with the gate stack; recessing the first ILD layer to expose a first sidewall of the source / drain contact and a second sidewall of the gate contact; forming a first conductive feature, the first conductive feature being in physical contact with the first sidewall and a first top surface of the source / drain contact; and forming a second conductive feature, the second conductive feature being in physical contact with the second sidewall and a second top surface of the gate contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a FinFET in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 and Figure 3 is a three-dimensional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Figure 4A , Figure 4B, Figure 4C , Figure 4D , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A and Figure 7B is a cross-sectional view of other intermediate stages in the fabrication of a FinFET according to some embodiments.

[0011] Figure 8 , Fig. 9 and Fig.10 is a cross-sectional view of other intermediate stages in the fabrication of a FinFET according to some embodiments.

[0012] Fig.11 is a cross-sectional view of a FinFET according to some other embodiments.

[0013] Fig.12 is a cross-sectional view of a FinFET according to some other embodiments.

[0014] Fig.13 is a cross-sectional view of a FinFET according to some other embodiments.

[0015] Fig.14 is a cross-sectional view of a FinFET according to some other embodiments.

[0016] Fig.15 is a cross-sectional view of a FinFET according to some other embodiments.

[0017] Fig.16 and Fig.17 is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments.

[0018] Fig.18 is a cross-sectional view of a FinFET according to some other embodiments.

[0019] Fig.19 is a cross-sectional view of a FinFET according to some other embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0022] According to some embodiments, a gate contact and / or source / drain contact is formed with a larger interface, the larger interface having an overlying conductive feature. Specifically, the interface has a larger surface area. During the process, the surface area of ​​the interface can be increased by exposing the sidewalls, convex top surface, or concave top surface of the contact. The overlying conductive feature is formed as a solid contact exposed surface. Such an interface has a larger surface area than a planar interface. Optionally, the interface can also be doped. When the contact and the overlying conductive feature are formed of different conductive materials, doping the interface can reduce the work function difference between the material of the contact and the material of the overlying conductive feature. Increasing the surface area of ​​the interface and reducing the work function difference can help reduce the resistance of the contact, thereby improving the performance of the FinFET

[0023] Figure 1 An example of a simplified fin field effect transistor (FinFET) in a three-dimensional view according to some embodiments is shown. For clarity of illustration, some other features of the FinFET (described below) are omitted. The FinFET shown can be electrically coupled in a manner to function as, for example, one transistor or multiple transistors, for example, four transistors.

[0024] The FinFET includes a fin 52 extending from a substrate 50. A shallow trench isolation (STI) region 56 is disposed above the substrate 50, and the fin 52 is above and protrudes between adjacent STI regions 56. Although the STI regions 56 are described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer to a semiconductor substrate alone or to a semiconductor substrate including an isolation region. In addition, although the fin 52 is shown as a single continuous material of the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 52 refers to a portion extending between adjacent STI regions 56.

[0025] The gate structure 80 is located above the channel region of the fin 52. The gate structure 80 includes a gate dielectric 82 and a gate electrode 84. The gate dielectric 82 is along the sidewalls of the fin 52 and above the top surface of the fin 52, and the gate electrode 84 is above the gate dielectric 82. The source / drain region 70 is disposed on the opposite side of the fin 52 relative to the gate dielectric 82 and the gate electrode 84. The gate spacer 66 separates the source / drain region 70 from the gate structure 80. In embodiments where multiple transistors are formed, the source / drain region 70 can be shared between the respective transistors. In embodiments where one transistor is formed from multiple fins 52, adjacent source / drain regions 70 can be electrically coupled, for example, by merging the source / drain regions 70 by epitaxial growth, or by coupling the source / drain regions 70 to the same source / drain contact. One or more interlayer dielectric (ILD) layers (discussed further below) are located above the source / drain regions 70 and / or the gate electrode 84, and contacts to the source / drain regions 70 and the gate electrode 84 are formed through the one or more interlayer dielectric (ILD) layers (discussed further below).

[0026] Figure 1 Several reference cross sections are further shown. Cross section AA is along the longitudinal axis of the fin 52 and in the direction of current flow, for example, between the source / drain regions 70 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the gate electrode 84. Cross section CC is perpendicular to cross section AA and extends through the source / drain regions 70 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0027] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0028] Figure 2 and Figure 3 is a three-dimensional view of another intermediate stage in the fabrication of a FinFET according to some embodiments. Figure 2 and Figure 3 Shown with Figure 1 A similar view showing two gate structures.

[0029] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, for example, a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (for example, doped with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, for example, a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. For example, the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates may also be used, for example, a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0030] Substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type FinFET). Region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type FinFET). Region 50N can be physically separated from region 50, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between region 50N and region 50P.

[0031] Fin 52 is formed to extend from substrate 50. Fin 52 is a semiconductor strip. In some embodiments, fin 52 may be formed in substrate 50 by etching trenches in substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), etc. Etching may be anisotropic.

[0032] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-alignment process, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the spacers (or other masks) may remain on the fins 52.

[0033] STI regions 56 are formed over the substrate 50 and between adjacent fins 52. As an example of forming the STI regions 56, an insulating material is formed over the intermediate structure. The insulating material may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by the following processes: high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., deposition and post-curing of a material based on chemical vapor deposition (CVD) in a remote plasma system to convert it into another material (e.g., oxide)), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material is formed so that excess insulating material covers the fins 52. Although the STI regions 56 are shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material such as the above-described filling material may be formed over the liner. A removal process is applied to the insulating material to remove excess insulating material above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like may be utilized. The planarization process exposes the fin 52 so that the top surfaces of the fin 52 and the insulating material are coplanar after the planarization process is completed. In an embodiment in which the mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that after the planarization process is completed, the top surfaces of the mask or the fin 52 are coplanar with the insulating material, respectively. The insulating material is then recessed, and the remainder of the insulating material forms an STI region 56. The insulating material is recessed so that the upper portions of the fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56. The exposed portion of the fin 52 includes a portion that will be the channel region of the resulting FinFET.

[0034] In addition, the top surface of STI region 56 may have a flat surface, a convex surface, a concave surface (e.g., a groove), or a combination thereof as shown. The top surface of STI region 56 may be formed to be flat, convex, and / or concave by appropriate etching. STI region 56 may be recessed using an acceptable etching process (e.g., an etching process that is selective to the material of the insulating material (e.g., etches the material of the insulating material at a faster rate than the material of fin 52)). For example, oxide removal using an acid such as dilute hydrofluoric acid (dHF) may be employed.

[0035] The above process is only one example of how the fin 52 can be formed. In some embodiments, the fin 52 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin 52. In addition, in some embodiments, a heteroepitaxial structure can be used for the fin 52. For example, after the insulating material of the STI region 56 is coplanar with the fin 52, the fin 52 can be recessed, and a material different from the fin 52 can be epitaxially grown on the recessed fin 52. In such an embodiment, the fin 52 includes a recessed material, and an epitaxially grown material arranged on the recessed material. In another embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer. A heteroepitaxial structure may then be epitaxially grown in the trench using a different material than substrate 50, and the dielectric layer may be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form fins 52. In some embodiments where a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid prior and subsequent implants, but both in situ and implant doping may be used together.

[0036] In addition, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SiGe). x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to: indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0037] Furthermore, appropriate wells may be formed in fin 52 and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

[0038] In embodiments with different well types, a photoresist or other mask may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, e.g., a PMOS region. The photoresist may be formed using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N (e.g., an NMOS region). The n-type impurity may be phosphorus, arsenic, antimony, etc., and may be implanted to a depth equal to or less than 10 μm in this region. 18 cm -3 (For example, at about 10 16 cm -3 To about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0039] After the implantation of region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, for example, an NMOS region. The photoresist may be formed by using a spin coating technique, and the photoresist may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P (for example, a PMOS region). The p-type impurity may be boron, boron fluoride, indium, etc., and may be implanted to a depth of 10 or less in the region. 18 cm -3 (For example, at about 10 16 cm -3 To about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0040] After implantation of regions 50N and 50P, annealing may be performed to repair implantation damage and activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may avoid implantation, but in-situ doping and implantation doping may be used together.

[0041] exist Figure 3 In the embodiment of the present invention, a dummy dielectric 60 is formed on the fin 52, and a dummy gate 62 is formed on the dummy dielectric 60. The dummy dielectric 60 and the dummy gate 62 may be collectively referred to as a “dummy gate stack”, and each dummy gate stack includes the dummy dielectric 60 and the dummy gate 62. The dummy gate stack extends along the sidewall of the fin 52.

[0042] As an example of forming a dummy dielectric 60 and a dummy gate 62, a dummy dielectric layer is formed on the fin 52. For example, the dummy dielectric layer can be silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed on the dummy dielectric layer, and a mask layer is formed on the dummy gate layer. The dummy gate layer can be deposited on the dummy dielectric layer and then planarized (e.g., by CMP). The mask layer can be deposited on the dummy gate layer. The dummy gate layer can be a conductive material or a non-conductive material, and can be selected from the group including the following items: amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polycrystalline SiGe), metal nitride, metal silicide, metal oxide and metal. The dummy gate layer can be deposited by the following process: physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit selected materials. The dummy gate layer can be made of other materials with high etching selectivity relative to the etching of the STI region 56. For example, the mask layer may include silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer and a single mask layer are formed across region 50N and region 50P. The mask layer is then patterned using acceptable photolithography and etching techniques to form mask 64. The pattern of mask 64 is then transferred to the dummy gate layer by acceptable etching techniques to form dummy gate 62. The pattern of mask 64 may optionally be further transferred to a dummy dielectric layer to form dummy dielectric 60. Dummy gate 62 covers the corresponding channel region 58 of fin 52 (see Figure 4A and Figure 4B). The pattern of mask 64 can be used to physically separate each dummy gate 62 from adjacent dummy gates. Dummy gates 62 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fin 52 (within process limitations). Although dummy dielectric 60 is shown as covering STI region 56, it should be understood that dummy dielectric 60 can be formed in other ways. In some embodiments, such as when the dummy dielectric layer is thermally grown, dummy dielectric layer 60 is formed to cover only fin 52.

[0043] FIG. 4A to FIG. 7B is a cross-sectional view of other intermediate stages in the fabrication of a FinFET according to some embodiments. Figure 4A , Figure 5A , Fig. 6A and Fig. 7A It is along Figure 1 A cross-sectional view is shown with reference to cross section AA in which two gate structures are shown. Figure 4B , Figure 5B , Figure 6B and Figure 7B It is along Figure 1 Reference section BB in FIG. 1 shows a cross-sectional view except that only two fins are shown. Figure 4C and Figure 4D It is along Figure 1 Reference section CC in FIG. 1 shows a cross-sectional view, except that only two fins are shown. FIG. 4A to FIG. 7B Features in either region 50N or region 50P are shown. For example, FIG. 4A to FIG. 7B The structure shown is applicable to both region 50N and region 50P. Differences in the structures of region 50N and region 50P, if any, are described herein.

[0044] exist Figure 4A and Figure 4B In the embodiment of the present invention, a gate spacer 66 is formed on the exposed surface of the dummy gate 62, the mask 64 and / or the fin 52. The gate spacer 66 can be formed by forming an insulating material and then etching the insulating material. The insulating material of the gate spacer 66 can be silicon nitride, silicon carbonitride, silicon carbon nitride oxide, a combination thereof, etc., and can be formed by thermal oxidation, deposition, a combination thereof, etc. In some embodiments, the gate spacer 66 is formed of a multilayer insulating material and includes a plurality of layers. For example, the gate spacer 66 may include a multilayer silicon carbonitride, may include a multilayer silicon carbon nitride oxide, or may include a silicon oxide layer disposed between two layers of silicon nitride. The etching of the gate spacer 66 may be anisotropic. After etching, the gate spacer 66 may have a straight sidewall or a curved sidewall.

[0045] Prior to or during formation of gate spacers 66, implantation for lightly doped source / drain (LDD) regions (not explicitly shown) may be performed. In embodiments having different device types, similar to the implantation discussed, a mask (e.g., photoresist) may be formed over region 50N, leaving region 50P exposed, and an appropriate type (e.g., p-type) of impurity may be implanted into exposed fins 52 in region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over region 50P, leaving region 50N exposed, and an appropriate type (e.g., n-type) of impurity may be implanted into exposed fins 52 in region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a value ranging from about 10 15 cm -3 to about 10 19 cm -3 Annealing can be used to repair implant damage and activate the implanted impurities.

[0046] However, epitaxial source / drain regions 70 are formed in the fins 52. The epitaxial source / drain regions 70 are formed in the fins 52 so that each dummy gate 62 is disposed between a corresponding adjacent pair of epitaxial source / drain regions 70. In some embodiments, the epitaxial source / drain regions 70 may extend into a portion of the fins 52 below the top surface of the SIT region 56. In some embodiments, gate spacers 66 are used to separate the epitaxial source / drain regions 70 from the dummy gates 62 by an appropriate lateral distance so that the epitaxial source / drain regions 70 do not short-circuit a subsequently formed gate of the resulting FinFET. The epitaxial source / drain regions 70 may exert stress in the channel region 58 of the fins 52, thereby improving performance.

[0047] The epitaxial source / drain regions 70 in the region 50N (e.g., NMOS region) may be formed by masking the region 50P (e.g., PMOS region) and etching the source / drain regions of the fin 52 in the region 50N to form recesses in the fin 52. The epitaxial source / drain regions 70 in the region 50N are then epitaxially grown in the recesses. The epitaxial source / drain regions 70 may include any acceptable material (e.g., suitable for n-type FinFETs). For example, if the fin 52 is silicon, the epitaxial source / drain regions 70 in the region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 70 in the region 50N may have surfaces that protrude from the corresponding surfaces of the fin 52 and may have facets.

[0048] The epitaxial source / drain regions 70 in the region 50P (e.g., the PMOS region) can be formed by masking the region 50N (e.g., the NMOS region) and etching the source / drain regions of the fin 52 in the region 50P to form recesses in the fin 52. The epitaxial source / drain regions 70 in the region 50P are then epitaxially grown in the recesses. The epitaxial source / drain regions 70 can include any acceptable material (e.g., suitable for p-type FinFETs). For example, if the fin 52 is silicon, the epitaxial source / drain regions 70 in the region 50P can include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 70 in the region 50P can also have surfaces that protrude from the corresponding surfaces of the fin 52 and can have small facets.

[0049] The epitaxial source / drain regions 70 and / or fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have a dopant concentration of about 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 70 may be doped in situ during growth.

[0050] As a result of the epitaxial process used to form epitaxial source / drain regions 70, the upper surface of epitaxial source / drain regions 70 has facets that extend laterally outward beyond the sidewalls of fins 52. In some embodiments, these facets allow adjacent epitaxial source / drain regions 70 of the same FinFET to merge, such as Figure 4C For example, when a transistor is formed from multiple fins 52, a merged epitaxial source / drain region 70 may be formed. In other embodiments, adjacent epitaxial source / drain regions 70 remain separated after the epitaxial process is completed, such as Figure 4D As shown. For example, when a transistor is formed from a single fin 52 or when a transistor is formed from multiple fins 52, an unmerged epitaxial source / drain region 70 may be formed. In the illustrated embodiment, the gate spacer 66 is formed to cover the portion of the sidewall of the fin 52 that extends over the STI region 56, thereby blocking epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacer 66 may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region 56.

[0051] Note that the above disclosure generally describes the process of forming spacers, LDD regions, and source / drain regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, steps in different sequences may be used, spacers may be formed and removed, and the like. In some embodiments, gate spacers 66 may be formed after epitaxial source / drain regions 70. In addition, different structures and steps may be used to form n-type and p-type devices. In some embodiments, during the formation of epitaxial source / drain regions 70 in region 50N, dummy spacers may be formed in region 50N. The dummy spacers in region 50N may then be removed. Then during the formation of epitaxial source / drain regions 70 in region 50P, dummy spacers may be formed in region 50P. The dummy spacers in region 50P may then be removed. Gate spacers 66 may then be formed after epitaxial source / drain regions 70 have been formed in both region 50N and region 50P.

[0052] exist Figure 5A and Figure 5B In the embodiment, CESL 72 is deposited over epitaxial source / drain regions 70, gate spacers 66, mask 64 (if present) or dummy gate 62, and STI regions 56. CESL 72 is formed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc. In an embodiment, CESL 72 is formed of silicon nitride.

[0053] Then, a first ILD layer 74 is deposited over the CESL 72. The first ILD layer 74 is formed of a dielectric material having a different etch rate than the material of the CESL 72, and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include an oxide (e.g., silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.; a nitride, such as silicon nitride; etc. Other insulating materials formed by any acceptable process may be used. After formation, the first ILD layer 74 may be planarized, such as by CMP.

[0054] exist Fig. 6A and Figure 6BIn the process, a planarization process such as CMP may be performed to make the top surface of the first ILD layer 74 flush with the top surface of the mask 64 (if present) or the dummy gate 62. The planarization process may remove the mask 64 on the dummy gate 62, and the portion of the gate spacer 66 along the sidewall of the mask 64. The planarization process may also remove the portion of the CESL 72 above the dummy gate 62 and the gate spacer 66. After the planarization process, the top surfaces of the dummy gate 62, the gate spacer 66, the CESL 72, and the first ILD layer 74 are coplanar. Therefore, the top surface of the dummy gate 62 is exposed through the first ILD layer 74. In some embodiments, the mask 64 may remain in the case where the planarization process makes the top surface of the first ILD layer 74 flush with the top surface of the mask 64.

[0055] exist Fig. 7A and Figure 7BIn the embodiment of the present invention, the dummy gate 62 and optionally the dummy dielectric 60 are removed and replaced by a gate structure 80. The gate structure 80 includes a gate dielectric 82 and a gate electrode 84. As an example of forming the gate structure 80, the dummy gate 62 and the mask 64 (if present) are removed in one or more etching steps to form a groove. The portion of the dummy dielectric 60 in the groove may also be removed. In some embodiments, only the dummy gate 62 is removed, and the dummy dielectric 60 is retained and exposed by the groove. In some embodiments, the dummy dielectric 60 is removed from the groove in a first die area (e.g., a core logic area) and is retained in the groove in a second die area (e.g., an input / output area). In some embodiments, the dummy gate 62 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etches the dummy gate 62 without etching the first ILD layer 74, the CESL 72, or the gate spacer 66. Each groove exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 70. During removal, the dummy dielectric 60 can be used as an etch stop layer when etching the dummy gate 62. The dummy dielectric 60 can then be optionally removed after removing the dummy gate 62. After removal, a gate dielectric 82 is conformally deposited in the groove, for example, on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate electrode 66. The gate dielectric 82 can also be formed on the top surface of the first ILD layer 74. According to some embodiments, the gate dielectric 82 includes silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric 82 includes a high-k dielectric material, and in these embodiments, the gate dielectric 82 can have a k value greater than about 7.0 and can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric 82 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In an embodiment in which a portion of the dummy dielectric 60 remains in the groove, the gate dielectric 82 includes the material of the dummy dielectric 60 (e.g., silicon oxide). The gate electrodes 84 are deposited on the gate dielectric 82 respectively and fill the rest of the groove. The gate electrode 84 may include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, a combination thereof, or multiple layers thereof. For example, although a single-layer gate electrode 84 is shown, each gate electrode 84 may include any number of liner layers, any number of work function adjustment layers, and filling materials. After filling the gate electrode 84, a planarization process such as CMP may be performed to remove the material of the gate electrode 84 and the excess portion of the gate dielectric 82, which is above the top surface of the first ILD layer 74.The material of the gate electrode 84 and the remainder of the gate dielectric 82 form the gate structure 80 of the resulting FinFET. The gate structure 80 may also be referred to as a “gate stack” or a “metal gate.” The gate structure 80 may extend along the sidewalls of the channel region 58 of the fin 52 .

[0056] The formation of gate structure 80 in region 50N and region 50P may occur simultaneously, such that gate dielectric 82 in each region is formed of the same material, and gate electrode 84 in each region is formed of the same material. In some embodiments, gate structure 80 in each region may be formed by different processes, such that gate dielectric 82 in each region may be a different material, and gate electrode 84 in each region may be a different material. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0057] Figures 8 to 10 is a cross-sectional view of other intermediate stages in the fabrication of a FinFET according to some embodiments. Figures 8 to 10 It is along Figure 1 Reference section AA shows a cross-sectional view except that four gate structures are shown. Figures 8 to 10 A first region 50A (wherein a gate contact will be formed) and a second region 50B (wherein a source / drain contact will be formed) are shown. Regions 50A and 50B are treated simultaneously and discussed together. Regions 50A and 50B are portions of different cross-sections in which contacts are formed, which can avoid shorting of the contacts. It should be understood that the gate contact and the source / drain contact can be formed in the same cross-section of the transistor. One fin 52 is shown in each of regions 50A and 50B, but it should be understood that each of regions 50A and 50B can include fins 52 from both regions 50N and 50P of substrate 50, for example, the first region 50A and the second region 50B can each include an n-type device and a p-type device.

[0058] exist Figure 8In the embodiment of the present invention, a second ILD layer 90 is deposited on top of the first ILD layer 74. The second ILD layer 90 is formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include an oxide (e.g., silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.; a nitride, such as silicon nitride; etc. Other insulating materials formed by any acceptable method may be used. After formation, the second ILD layer 90 may be planarized, for example, by CMP. In some embodiments, an etch stop layer is formed between the first ILD layer 74 and the second ILD layer 90. The etch stop layer may include a dielectric material having a different etch rate from that of the material of the second ILD layer 90, such as silicon nitride, silicon oxide, silicon oxynitride, etc. In some embodiments, before forming the second ILD layer 90 , a gate mask (not shown) may be formed over the gate dielectric 82 and the gate electrode 84 , which may protect the gate dielectric 82 and the gate electrode 84 during contact formation.

[0059] After forming the second ILD layer 90, source / drain contacts 92 and gate contacts 94 extending through the second ILD layer 90 are formed. Openings for source / drain contacts 92 are formed through the ILD layers 74, 90, and openings for gate contacts 94 are formed through the second ILD layer 90. The openings can be formed using acceptable photolithography and etching techniques. A liner (e.g., a diffusion barrier, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD layer 90. The remaining liner and conductive material form source / drain contacts 92 and gate contacts 94 in the opening. In some embodiments, the source / drain contacts 92 and the gate contacts 94 are formed of the same conductive material. Source / drain contacts 92 are connected (e.g., physically and electrically coupled) to epitaxial source / drain regions 70, and gate contact 94 is connected to gate electrode 84. Gate contact 94 may pass through a gate mask (if present) over gate electrode 84. Source / drain contacts 92 and gate contact 94 may be formed in different processes, or may be formed in the same process.

[0060] exist Fig. 9In the embodiment, the second ILD layer 90 is recessed to form a groove 98. The groove 98 exposes a portion of the surface located at the interface of the second ILD layer 90 and the contacts 92, 94, for example, a portion of the sidewalls of the contacts 92, 94. In this embodiment, the exposed portion of the contacts 92, 94 has a substantially vertical sidewall and a substantially flat top surface. In other words, the sidewall can be substantially perpendicular to the main surface of the substrate 50, and the top surface can be substantially parallel to the main surface of the substrate 50. The groove can be made by an acceptable etching process, for example, an etching process that is selective to the material of the second ILD layer 90. In the embodiment in which the second ILD layer 90 is an oxide, a chemical oxide removal can be performed. For example, HF and NH 3 A mixture of NF 3 and NH 3 The second ILD layer 90 is etched by wet or dry etching (without plasma) for a duration ranging from about 7 seconds to about 60 seconds, which can form the groove 98 to a depth D of at least about 2 nm. 1 , for example, in the range of about 2 nm to about 15 nm. Depth D 1 The second ILD layer 90 may be recessed at a height of about 4% to about 25% of the original height of the second ILD layer 90. Such an etching process may produce a high etching selectivity between the dielectric material of the second ILD layer 90 and the conductive material of the contacts 92, 94. For example, such an etching process may selectively etch the dielectric material of the second ILD layer 90 at a rate up to 15 times that of the conductive material of the contacts 92, 94. Recessing the second ILD layer 90 using a highly selective etching process may cause the exposed portions of the contacts 92, 94 to have substantially vertical sidewalls and substantially flat top surfaces. Recessing the second ILD layer 90 increases the exposed surface area of ​​the contacts 92, 94 by an amount in the range of about 100% to about 700%.

[0061] Optionally, one or more implants may be performed to modify the exposed surfaces of the second ILD layer 90, the source / drain contacts 92, and the gate contact 94. As a result, a doped region 90M of the second ILD layer 90, a doped region 92M of the source / drain contacts 92, and a doped region 94M of the gate contact 94 are formed. The remaining undoped regions of the features where the implants are performed may be referred to as "main regions." For example, the second ILD layer 90, the source / drain contacts 92, and the gate contact 94 may be implanted with one or more impurities, such as boron, phosphorus, etc. The doped region 92M of the source / drain contact 92 may be implanted to have a doping concentration of approximately 10 18 cm -3 to about 10 21 cm -3 The impurity concentration of the gate contact 94 may be implanted to have an impurity concentration of about 1018 cm -3 to about 10 21 cm -3 The implantation may be performed at a low energy, for example, an energy in the range of about 0.5 keV to about 3 keV, so that the impurities do not pass through the second ILD layer 90 and are not implanted into the following features. Implanting impurities into the second ILD layer 90 may increase the volume of the second ILD layer 90, thereby expanding it. Therefore, the second ILD layer 90 may have a reduced density after the implantation. In some embodiments, after the implantation, the density of the second ILD layer 90 is less than the density of the first ILD layer 74. As discussed further below, the subsequently formed interconnect may be formed of a conductive material different from the contacts 92, 94. Forming the doped regions 92M, 94M may help reduce the work function difference between the contacts 92, 94 and the subsequently formed interconnect.

[0062] Annealing may be performed after the implantation. For example, the annealing may be performed at a temperature ranging from about 700° C. to about 1200° C. The annealing activates the impurities implanted into the second ILD layer 90 , the source / drain contacts 92 , and the gate contact 94 .

[0063] exist Fig.10 In the embodiment of the present invention, an intermetallic dielectric (IMD) layer 102 is formed in the recess 98 and on the exposed surfaces of the source / drain contacts 92 and the gate contacts 94. Conductive features 104 are formed in the IMD layer 102 and connected to the source / drain contacts 92 and the gate contacts 94. A first subset 104A of the conductive features is connected to the source / drain contacts 92, and a second subset 104B of the conductive features is connected to the gate contacts 94. The IMD layer 102 and the conductive features 104 can be part of an interconnect structure. For example, the conductive features 104 can include conductive vias and conductive lines that are part of a metallization pattern (e.g., an interconnect) of the interconnect structure. The metallization pattern interconnects the resulting FinFETs to form an integrated circuit. The interconnect structure (including the IMD layer 102 and the conductive features 104) can be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

[0064] The IMD layer 102 may be formed of any suitable dielectric material, such as an oxide (e.g., silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; a nitride, such as silicon nitride; etc. The IMD layer 102 may be formed by any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), etc., or a combination thereof. The IMD layer 102 may be a layer formed of a low-k dielectric material having a k value less than about 3.9. The IMD layer 102 may be a layer formed of an ultra-low-k (ELK) dielectric material having a k value less than 2.5. In some embodiments, an etch stop layer is formed between the IMD layer 102 and the second ILD layer 90. The etch stop layer may include a dielectric material having an etch rate different from that of the material of the IMD layer 102, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0065] Conductive feature 104 may include a diffusion barrier layer, and a conductive material on the conductive barrier layer. As an example of forming conductive feature 104, an opening formed in IMD layer 102 exposes the conductive features below, such as source / drain contacts 92 and gate contacts 94. Acceptable photolithography and etching techniques may be used to form the opening. The diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc., and may be formed in the opening by a deposition process such as atomic layer deposition (ALD), etc. The conductive material may include copper, aluminum, tungsten, silver, and combinations thereof, etc., and may be formed on the diffusion barrier layer in the opening by an electrochemical plating process, CVD, ALD, PVD, etc., or a combination thereof. In an embodiment, the conductive material is copper, and the diffusion barrier layer is a thin barrier layer that prevents copper from diffusing into IMD layer 102. After forming the diffusion barrier layer and the conductive material, the excess diffusion barrier layer and the conductive layer material may be removed by a planarization process such as a chemical mechanical polishing (CMP) process. The remaining portion of the diffusion barrier layer and the conductive material forms conductive feature 104.

[0066] The conductive feature 104 contacts the exposed surfaces of the contacts 92, 94 extending above the second ILD layer 90. In other words, the conductive feature 104A contacts the top surface and sidewalls of the source / drain contact 92, and the conductive feature 104B contacts the top surface and sidewalls of the gate contact 94. As a result of the recessed second ILD layer 90, the contacts 92, 94 extend through the second ILD layer 90 and partially extend into the conductive feature 104 by a distance D 1. The source / drain contact 92 also extends through the first ILD layer 74. Therefore, the conductive features 104 each physically contact multiple surfaces of one of the contacts 92, 94. The surface area of ​​the interface between the contacts 92, 94 and the conductive feature 104 can be increased as a result. For example, the surface area of ​​each interface can be increased by an amount in the range of about 100% to about 700%. Increasing the surface area of ​​the interface between the contacts 92, 94 and the conductive feature 104 can help reduce the resistance of the contacts. Because the contacts 92, 94 extend through the second ILD layer 90 and partially extend into the conductive feature 104, the final height of the contacts 92, 94 is greater than the final height of the second ILD layer 90. Specifically, the top surface of the second ILD layer 90 is arranged to be closer to the substrate 50 than the top surface of the contacts 92, 94.

[0067] Conductive feature 104A is in direct physical contact with doped region 92M of source / drain contact 92, and conductive feature 104B is in direct physical contact with doped region 94M of gate contact 94. In some embodiments, conductive feature 104 includes a conductive material different from contacts 92, 94. For example, contacts 92, 94 may be formed of cobalt, and conductive feature 104 may be formed of tungsten. Note that the conductive material (e.g., cobalt) of contacts 92, 94 may have a different (e.g., greater) work function than the conductive material (e.g., tungsten) of conductive feature 104. According to some embodiments, doped region 92M helps reduce the work function difference between source / drain contact 92 and conductive feature 104A. Similarly, doped region 94M helps reduce the work function difference between gate contact 94 and conductive feature 104B. Specifically, the work function of the material of doped regions 92M, 94M is less than the work function of the material of contacts 92, 94, and greater than the work function of the material of conductive feature 104. Reducing the work function difference between the contacts 92 , 94 and the conductive feature 104 may help reduce the resistance of the contacts.

[0068] Fig.11 is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to the embodiment described above except that the source / drain contacts include a lower source / drain contact 92A and an upper source / drain contact 92B. Fig.10 The lower source / drain contact 92A extends through the first ILD layer 74 and the CESL 72, and the upper source / drain contact 92B extends through the second ILD layer 90. The recess 98 (see Fig. 9 ) thus exposes portions of the sidewalls of the contacts 92B, 94. The lower source / drain contact 92A is thus arranged between the upper source / drain contact 92B and the epitaxial source / drain region 70.

[0069] As an example of forming a lower source / drain contact 92A, before forming the second ILD layer 90, an opening for the lower source / drain contact 92A can be formed by the first ILD layer 74 and the CESL 72. The opening can be formed using acceptable photolithography and etching techniques. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the first ILD layer 74. The remaining liner and conductive material form a lower source / drain contact 92A in the opening. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain region 70 and the lower source / drain contact 92A. The lower source / drain contact 92A is connected to the epitaxial source / drain region 70. After formation, the top surfaces of the gate spacers 66 , the first ILD layer 74 , the gate electrode 84 , and the lower source / drain contacts 92A are coplanar.

[0070] As an example of forming an upper source / drain contact 92B, after forming the second ILD layer 90, an opening for an upper source / drain contact 92B is formed by the second ILD layer 110. The opening can be formed using acceptable photolithography and etching techniques. A liner (e.g., a diffusion barrier, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD layer 110. The remaining liner and conductive material form an upper source / drain contact 92B in the opening. The upper source / drain contact 92B is connected to the lower source / drain contact 92A, and the lower source / drain contact 92A is connected to the epitaxial source / drain region 70. The upper source / drain contacts 92B and the gate contact 94 may be formed in different processes, or may be formed in the same process. After formation, the top surfaces of the second ILD layer 90, the upper source / drain contacts 92B, and the gate contact 94 are coplanar.

[0071] It should be understood that some embodiments may combine Fig.10 and Fig.11 For example, the source / drain contacts in the first die region (eg, input / output region) may be continuous conductive features (eg, Fig.10 ), while the source / drain contacts in the second die region (eg, core logic region) may have separate upper and lower conductive features in the corresponding ILD layer (eg, Fig.11 shown).

[0072] Fig.12 is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to that described with respect to FIG. 1 , except that the upper source / drain contact 92B contacts the top surface and sidewalls of the lower source / drain contact 92A. Fig.11 The lower source / drain contact 92A thus partially extends into the upper source / drain contact 92B. The upper source / drain contact 92B may be formed in such a manner by recessing the first ILD layer 74 before forming the second ILD layer 90, thereby exposing the sidewalls of the lower source / drain contact 92A. As an example of exposing the sidewalls of the lower source / drain contact 92A, the same method as in reference 1 may be used. Fig. 9 The first ILD layer 74 may be recessed by a process similar to the process described for recessing the second ILD layer 90 (e.g., by performing an etching process having a high etch selectivity between the dielectric material of the first ILD layer 74 and the conductive material of the lower source / drain contacts 92A), which may recess the first ILD layer 74 to a depth D of at least about 2 nm. 2 , for example, in the range of about 2 nm to about 15 nm. Depth D 2 It may be about 4% to about 25% of the original height of the first ILD layer 74. After the recess, the second ILD layer 90 may be formed to contact the sidewalls of the CESL 72. An upper source / drain contact 92B may then be formed through the second ILD layer 90 to contact the top surface and sidewalls of the lower source / drain contact 92A.

[0073] Fig.13 is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to that described with respect to FIG. 1 , except that the contacts 92 , 94 and their associated doped regions 92M, 94M have convex top surfaces and no well-defined vertical sidewalls. Fig.10 As an example of forming the contact members 92, 94 with convex top surfaces, HF and NH 3 A mixture of NF 3 and NH 3 The second ILD layer 90 is etched by wet or dry etching (without plasma) for a duration ranging from about 7 seconds to about 60 seconds, which can recess the second ILD layer 90 to a depth D of at least about 2 nm. 3 , for example, in the range of about 2 nm to about 15 nm. Depth D 3 The thickness of the second ILD layer 90 may be about 4% to about 25% of the original height of the second ILD layer 90. Fig. 9Compared to the etching process described above, this etching process can produce a lower etching selectivity between the dielectric material of the second ILD layer 90 and the conductive material of the contacts 92, 94. For example, this etching process can selectively etch the dielectric material of the second ILD layer 90 at a rate up to 10 times that of the conductive material of the contacts 92, 94. Recessing the second ILD layer 90 using a lower selectivity etching process can cause the exposed portions of the contacts 92, 94 to have a convex top surface.

[0074] Fig.14 is a cross-sectional view of a FinFET according to some other embodiments. Fig.11 The embodiment described above is similar to the embodiment described above, except that the source / drain contacts include a lower source / drain contact 92A and an upper source / drain contact 92B. Fig.13 Described embodiments.

[0075] Fig.15 is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to the embodiment described above except that the lower source / drain contact 92A has a convex surface in contact with the upper source / drain contact 92B. Fig.14 The upper source / drain contact 92B may be formed in such a manner by recessing the first ILD layer 74 before forming the second ILD layer 90, thereby exposing the convex surface of the lower source / drain contact 92A. As an example of exposing the sidewall of the lower source / drain contact 92A, the same method as that described above may be used. Fig.13 The first ILD layer 74 may be recessed by a process similar to the process described for recessing the second ILD layer 90 (e.g., by performing an etching process having a low etch selectivity between the dielectric material of the first ILD layer 74 and the conductive material of the lower source / drain contacts 92A), which may recess the first ILD layer 74 to a depth D of at least about 2 nm. 4 , for example, in the range of about 2 nm to about 15 nm. Depth D 4 It may be about 4% to about 25% of the original height of the first ILD layer 74 .

[0076] Fig.16 and Fig.17 is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments. Fig.16 and Fig.17 It is along Figure 1 The reference cross section AA shows a cross-sectional view except that four gate structures are shown. Fig.16 and Fig.17 Also shown are a first region 50A (where a gate contact will be formed) and a second region 50B (where source / drain contacts will be formed).

[0077] exist Fig.16 In, get and about Figure 8 1 . The source / drain contacts 92 and the gate contact 94 are then recessed to form a recess 112. The recess 112 exposes a portion of the surface at the interface of the second ILD layer 90 and the contacts 92 , 94 , for example, a portion of the sidewalls of the second ILD layer 90 . The recessing may be performed by an acceptable etching process, for example, an etching process that is selective to the conductive material of the contacts 92 , 94 . In embodiments where the contacts 92 , 94 are formed of cobalt, plasma etching may be performed using a fluorine or chlorine-based etchant. The etching gas may include additional gases such as hydrogen or oxygen to sublimate solid phase etching byproducts. In other embodiments where the contacts 92 , 94 are formed of cobalt, wet chemical etching may be performed using a sulfur peroxide mixture (SPM), a hydrochloric acid-hydrogen peroxide-water mixture (HPM), a piranha solution, or the like. SPM is sulfuric acid (H 2 SO 4 ), hydrogen peroxide (H 2 O 2 ) and deionized water (DIW). HPM is a mixture of hydrochloric acid (HCl), hydrogen peroxide (H 2 O 2 ) and water (H 2 O). Piranha solution is sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 As an example of forming the recess 112, the contacts 92, 94 may be etched by wet etching using SPM for a duration ranging from about 3 seconds to about 10 seconds, which may form the recess 112 to a depth D of at least about 2 nm. 5 , for example, in the range of about 2 nm to about 15 nm. Depth D 5 The gate contact 94 may be about 4% to about 25% of the original height of the gate contact 94. Such an etching process may produce a high etching selectivity between the dielectric material of the second ILD layer 90 and the conductive material of the contacts 92, 94. For example, such an etching process may selectively etch the dielectric material of the second ILD layer 90 at a rate up to 10 times that of the conductive material of the contacts 92, 94. After forming the recess 112, the contacts 92, 94 have a concave top surface. Recessing the contacts 92, 94 to have a concave top surface increases the exposed surface area of ​​the contacts 92, 94 by an amount in the range of about 100% to about 700%.

[0078] Optionally, one or more implants may be performed to modify the upper region 90M of the second ILD layer 90, the exposed region 92M of the source / drain contact 92, and the exposed region 94M of the gate contact 94. Annealing may be performed after the implantation to activate the implanted impurities. The implantation and annealing may be similar to those described with respect to Fig. 9 Implantation and annealing described.

[0079] exist Fig.17 In the embodiment, an IMD layer 102 is formed on the second ILD layer 90. A conductive feature 104 is formed in the IMD layer 102 and the recess 112. Fig.10 The IMD layer 102 and the conductive features 104 are formed in a similar manner as described.

[0080] The conductive feature 104 contacts the recessed top surfaces of the contacts 92, 94. In other words, the conductive feature 104A contacts the recessed top surfaces of the source / drain contact 92, and the conductive feature 104B contacts the recessed top surface of the gate contact 94. Since the contacts 92, 94 are recessed, the contacts 92, 94 partially extend into the second ILD layer 90, the conductive feature 104 extends through the IMD layer 102, and the conductive feature 104 partially extends into the second ILD layer 90 by a distance D 5 . In addition, the conductive features 104 extend into the contacts 92, 94. Therefore, the conductive features 104 are each in physical contact with the sidewalls of the second ILD layer 90 and the concave top surface of one of the contacts 92, 94. The surface area of ​​the interface between the contacts 92, 94 and the conductive features 104 can therefore be increased. For example, the surface area of ​​each interface can be increased by an amount in the range of about 100% to about 700%. Increasing the surface area of ​​the interface between the contacts 92, 94 and the conductive features 104 can help reduce the resistance of the contacts. Since the conductive features 104 extend through the IMD layer 102 and partially extend into the second ILD layer 90, the final height of the contacts 92, 94 is less than the final height of the second ILD layer 90. Specifically, the top surface of the second ILD layer 90 is arranged to be farther away from the substrate 50 than the top surface of the contacts 92, 94. In addition, as described above, forming the doped regions 92M, 94M can help reduce the work function difference between the contacts 92, 94 and the conductive features 104. Specifically, the work function of the material of doped regions 92M, 94M is greater than the work function of the material of contacts 92, 94 and less than the work function of the material of conductive feature 104. Reducing the work function difference between contacts 92, 94 and conductive feature 104 may help reduce the resistance of the contacts.

[0081] Fig.18 is a cross-sectional view of a FinFET according to some other embodiments. Fig.11The embodiment described above is similar to the embodiment described above, except that the source / drain contacts include a lower source / drain contact 92A and an upper source / drain contact 92B. Fig.17 The lower source / drain contact 92A extends through the first ILD layer 74 and the CESL 72, and the upper source / drain contact 92B extends partially through the second ILD layer 90. Thus, a recess 112 is formed by etching the contacts 92B, 94 (see FIG. Fig.17 ).

[0082] It should be understood that some embodiments may be combined with Fig.17 and Fig.18 For example, the source / drain contacts in the first die region (eg, input / output region) may be continuous conductive features (eg, Fig.17 ), while the source / drain contacts in the second die region (eg, core logic region) may have separate upper and lower conductive features in the corresponding ILD layer (eg, Fig.18 shown).

[0083] Fig.19 is a cross-sectional view of a FinFET according to some other embodiments. This embodiment is similar to that described with respect to the embodiment except that the upper source / drain contact 92B partially extends into the first ILD layer 74 and the lower source / drain contact 92A. Fig.18 The upper source / drain contact 92B may be formed in such a manner that a convex top surface of the lower source / drain contact 92A is formed by recessing the lower source / drain contact 92A before forming the second ILD layer 90. As an example of forming the convex top surface of the lower source / drain contact 92A, the same method as described above may be used. Fig.16 The lower source / drain contact 92A may be recessed by a process similar to that described for recessing the upper source / drain contact 92B, which may recess the lower source / drain contact 92A to a depth D of at least about 2 nm. 6 , for example, in the range of about 2 nm to about 15 nm. Depth D 6 It may be about 4% to about 25% of the original height of the lower source / drain contact 92A.

[0084] Some variations of the embodiments are possible. For example, Fig.18 In the described embodiments, the Fig.12 and Fig.15In a manner similar to the embodiment described above, the first ILD layer 74 is recessed before forming the upper source / drain contact 92B so that the lower source / drain contact 92A extends into the upper source / drain contact 92B. Fig.11 and Fig.14 In the described embodiments, the Fig.19 In a manner similar to the described embodiment, the lower source / drain contact 92A is recessed prior to forming the upper source / drain contact 92B so that the upper source / drain contact 92B extends into the lower source / drain contact 92A.

[0085] Embodiments can achieve advantages. Recessing the second ILD layer 90 or the contacts 92, 94 allows the contacts 92, 94 to have exposed sidewalls, convex top surfaces, or concave top surfaces. Forming the contacts 92, 94 with exposed sidewalls, convex top surfaces, or concave top surfaces can help increase the surface area of ​​the interface between the contacts 92, 94 and the conductive features 104. Increasing the surface area of ​​the interface between the contacts 92, 94 and the conductive features 104 can help reduce the resistance of the contacts, thereby improving the performance of the FinFET. In addition, doping the upper regions of the contacts 92, 94 can reduce the work function difference between the contacts 92, 94 and the conductive features 104, particularly when the contacts 92, 94 and the conductive features 104 are formed of different conductive materials. Reducing the work function difference between the contacts 92, 94 and the conductive features 104 can help reduce the resistance of the contacts, thereby improving the performance of the FinFET.

[0086] In an embodiment, a structure includes: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first ILD layer located above the source / drain region and the gate stack; a first IMD layer located above the first ILD layer; a first conductive feature extending through the first IMD layer; a second conductive feature extending through the first IMD layer; a source / drain contact extending through the first ILD layer and partially extending into the first conductive feature, the source / drain contact being in physical contact with the source / drain region and the first conductive feature; and a gate contact extending through the first ILD layer and partially extending into the second conductive feature, the gate contact being in physical contact with the gate stack and the second conductive feature.

[0087] In some embodiments of the structure, the source / drain contact has a first convex top surface in physical contact with the first conductive feature, and the gate contact has a second convex top surface in physical contact with the second conductive feature. In some embodiments of the structure, the source / drain contact has a first sidewall and a first flat top surface each in physical contact with the first conductive feature, and the gate contact has a second sidewall and a second flat top surface each in physical contact with the second conductive feature. In some embodiments, the structure further includes: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact is a continuous conductive feature extending through the first ILD layer, through the second ILD layer, and partially extending into the first conductive feature. In some embodiments, the structure further includes: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact includes: a third conductive feature extending through the first ILD layer and partially extending into the first conductive feature; and a fourth conductive feature located between the third conductive feature and the source / drain region, the fourth conductive feature extending through the second ILD layer. In some embodiments, the structure further comprises: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact comprises: a third conductive feature extending through the first ILD layer and partially extending into the first conductive feature; and a fourth conductive feature located between the third conductive feature and the source / drain region, the fourth conductive feature extending through the second ILD layer and partially extending into the third conductive feature. In some embodiments of the structure, the source / drain contact and the gate contact each comprise a first conductive material, the first conductive feature and the second conductive feature each comprise a second conductive material, and the first conductive material is different from the second conductive material. In some embodiments of the structure, the first conductive material has a greater work function than the second conductive material.

[0088] In an embodiment, a structure includes: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first ILD layer located above the source / drain region and the gate stack; a first IMD layer located above the first ILD layer; a first conductive feature extending through the first IMD layer and partially extending into the first ILD layer; a second conductive feature extending through the first IMD layer and partially extending into the first ILD layer; a source / drain contact extending partially into the first ILD layer, the source / drain contact being in physical contact with the source / drain region and the first conductive feature; and a gate contact extending partially into the first ILD layer, the gate contact being in physical contact with the gate stack and the second conductive feature.

[0089] In some embodiments of the structure, the source / drain contact has a first concave top surface in physical contact with the first conductive feature, and the gate contact has a second concave top surface in physical contact with the second conductive feature. In some embodiments, the structure further comprises: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact is a continuous conductive feature extending partially into the first ILD layer and extending through the second ILD layer. In some embodiments, the structure further comprises: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact comprises: a third conductive feature extending partially into the first ILD layer; and a fourth conductive feature located between the third conductive feature and the source / drain region, the fourth conductive feature extending through the second ILD layer. In some embodiments, the structure further comprises: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact comprises: a third conductive feature extending partially into the first ILD layer and partially into the second ILD layer; and a fourth conductive feature located between the third conductive feature and the source / drain region, the fourth conductive feature extending partially into the second ILD layer. In some embodiments of the structure, the source / drain contact and the gate contact each comprise a first conductive material, the first conductive feature and the second conductive feature each comprise a second conductive material, and the first conductive material is different from the second conductive material. In some embodiments of the structure, the first conductive material has a greater work function than the second conductive material.

[0090] In an embodiment, a method includes: forming a gate stack over a channel region of a substrate; growing a source / drain region adjacent to the channel region; depositing a first interlayer dielectric (ILD) layer over the source / drain region and the gate stack; forming a source / drain contact through the first ILD layer, the source / drain contact being in physical contact with the source / drain region; forming a gate contact through the first ILD layer, the gate contact being in physical contact with the gate stack; recessing the first ILD layer to expose a first sidewall of the source / drain contact and a second sidewall of the gate contact; forming a first conductive feature being in physical contact with a first sidewall and a first top surface of the source / drain contact; and forming a second conductive feature being in physical contact with a second sidewall and a second top surface of the gate contact.

[0091] In some embodiments of the method, recessing the first ILD layer increases the exposed surface area of ​​the source / drain contacts and the exposed surface area of ​​the gate contact by an amount in the range of 100% to 700%. In some embodiments, the method further includes: depositing a second ILD layer over the source / drain region, the first ILD layer being deposited on the second ILD layer, wherein forming the source / drain contacts includes: forming a lower source / drain contact in the second ILD layer; recessing the second ILD layer; and forming an upper source / drain contact in the first ILD layer. In some embodiments, the method further includes: depositing a second ILD layer over the source / drain region, the first ILD layer being deposited on the second ILD layer, wherein forming the source / drain contacts includes: forming a lower source / drain contact in the second ILD layer; recessing the lower source / drain contact; and forming an upper source / drain contact in the first ILD layer. In some embodiments, the method further includes depositing a second ILD layer over the source / drain region, the first ILD layer being deposited on the second ILD layer, wherein forming the source / drain contact includes forming a continuous conductive feature through the first ILD layer and the second ILD layer.

[0092] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0093] Example 1. A structure for manufacturing a semiconductor device, comprising: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first interlayer dielectric (ILD) layer located above the source / drain region and the gate stack; a first intermetallic dielectric (IMD) layer located above the first ILD layer; a first conductive feature extending through the first IMD layer; a second conductive feature extending through the first IMD layer; a source / drain contact extending through the first ILD layer and partially extending into the first conductive feature, the source / drain contact being in physical contact with the source / drain region and the first conductive feature; and a gate contact extending through the first ILD layer and partially extending into the second conductive feature, the gate contact being in physical contact with the gate stack and the second conductive feature.

[0094] Example 2. The structure of Example 1, wherein the source / drain contact has a first convex top surface in physical contact with the first conductive feature, and the gate contact has a second convex top surface in physical contact with the second conductive feature.

[0095] Example 3. A structure according to Example 1, wherein the source / drain contacts have first side walls and a first flat top surface each physically contacting the first conductive feature, and the gate contact has second side walls and a second flat top surface each physically contacting the second conductive feature.

[0096] Example 4. The structure of Example 1 further includes: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact is a continuous conductive feature extending through the first ILD layer, through the second ILD layer, and partially extending into the first conductive feature.

[0097] Example 5. The structure according to Example 1 further includes: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact includes: a third conductive feature extending through the first ILD layer and partially extending into the first conductive feature; and a fourth conductive feature located between the third conductive feature and the source / drain region, the fourth conductive feature extending through the second ILD layer.

[0098] Example 6. The structure according to Example 1 further includes: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact includes: a third conductive feature extending through the first ILD layer and partially extending into the first conductive feature; and a fourth conductive feature located between the third conductive feature and the source / drain region, the fourth conductive feature extending through the second ILD layer and partially extending into the third conductive feature.

[0099] Example 7. The structure of Example 1, wherein the source / drain contacts and the gate contact each include a first conductive material, the first conductive feature and the second conductive feature each include a second conductive material, and the first conductive material is different from the second conductive material.

[0100] Example 8. The structure of Example 7, wherein the first conductive material has a greater work function than the second conductive material.

[0101] Example 9. A structure for manufacturing a semiconductor device, comprising: a gate stack located above a channel region of a substrate; a source / drain region adjacent to the channel region; a first interlayer dielectric (ILD) layer located above the source / drain region and the gate stack; a first intermetallic dielectric (IMD) layer located above the first ILD layer; a first conductive feature extending through the first IMD layer and partially extending into the first ILD layer; a second conductive feature extending through the first IMD layer and partially extending into the first ILD layer; a source / drain contact extending partially into the first ILD layer, the source / drain contact being in physical contact with the source / drain region and the first conductive feature; and a gate contact extending partially into the first ILD layer, the gate contact being in physical contact with the gate stack and the second conductive feature.

[0102] Example 10. The structure of Example 9, wherein the source / drain contact has a first recessed top surface in physical contact with the first conductive feature, and the gate contact has a second recessed top surface in physical contact with the second conductive feature.

[0103] Example 11. The structure of Example 9, further comprising: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact is a continuous conductive feature extending partially into the first ILD layer and extending through the second ILD layer.

[0104] Example 12. The structure according to Example 9 further includes: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact includes: a third conductive feature extending partially into the first ILD layer; and a fourth conductive feature located between the third conductive feature and the source / drain region, the fourth conductive feature extending through the second ILD layer.

[0105] Example 13. The structure of Example 9 further includes: a second ILD layer located between the source / drain region and the first ILD layer, wherein the source / drain contact includes: a third conductive feature extending partially into the first ILD layer and partially into the second ILD layer; and a fourth conductive feature located between the third conductive feature and the source / drain region, the fourth conductive feature extending partially into the second ILD layer.

[0106] Example 14. The structure of Example 9, wherein the source / drain contacts and the gate contact each include a first conductive material, the first conductive feature and the second conductive feature each include a second conductive material, and the first conductive material is different from the second conductive material.

[0107] Example 15. The structure of Example 14, wherein the first conductive material has a greater work function than the second conductive material.

[0108] Example 16. A method for manufacturing a semiconductor device, comprising: forming a gate stack above a channel region of a substrate; growing a source / drain region adjacent to the channel region; depositing a first interlayer dielectric (ILD) layer above the source / drain region and the gate stack; forming a source / drain contact through the first ILD layer, the source / drain contact being in physical contact with the source / drain region; forming a gate contact through the first ILD layer, the gate contact being in physical contact with the gate stack; recessing the first ILD layer to expose a first sidewall of the source / drain contact and a second sidewall of the gate contact; forming a first conductive feature, the first conductive feature being in physical contact with the first sidewall and a first top surface of the source / drain contact; and forming a second conductive feature, the second conductive feature being in physical contact with the second sidewall and a second top surface of the gate contact.

[0109] Example 17. The method of Example 16, wherein recessing the first ILD layer increases an exposed surface area of ​​the source / drain contacts and an exposed surface area of ​​the gate contact by an amount in a range of 100% to 700%.

[0110] Example 18. The method according to Example 16 also includes: depositing a second ILD layer above the source / drain region, the first ILD layer being deposited on the second ILD layer, wherein forming the source / drain contact includes: forming a lower source / drain contact in the second ILD layer; recessing the second ILD layer; and forming an upper source / drain contact in the first ILD layer.

[0111] Example 19. The method according to Example 16 further includes: depositing a second ILD layer above the source / drain region, the first ILD layer being deposited on the second ILD layer, wherein forming the source / drain contact includes: forming a lower source / drain contact in the second ILD layer; recessing the lower source / drain contact; and forming an upper source / drain contact in the first ILD layer.

[0112] Example 20. The method of Example 16 further includes: depositing a second ILD layer over the source / drain region, the first ILD layer being deposited on the second ILD layer, wherein forming the source / drain contact includes: forming a continuous conductive feature through the first ILD layer and the second ILD layer.

Claims

1. A structure for manufacturing a semiconductor device, comprising: a gate stack located above the channel region of the substrate; a source / drain region adjacent to the channel region; A first interlayer dielectric ILD layer, located above the source / drain region and the gate stack; A first intermetal dielectric IMD layer, located on the first ILD layer; a first conductive feature extending through the first IMD layer; a second conductive feature extending through the first IMD layer; a source / drain contact extending through the first ILD layer and partially into the first conductive feature, the source / drain contact being in physical contact with the source / drain region and the first conductive feature; a gate contact extending through the first ILD layer and partially into the second conductive feature, the gate contact being in physical contact with the gate stack and the second conductive feature; as well as a second ILD layer, located between the source / drain region and the first ILD layer, Wherein, the source / drain contact comprises: a third conductive feature extending through the first ILD layer and partially into the first conductive feature; and A fourth conductive feature is located between the third conductive feature and the source / drain region, the fourth conductive feature extends through the second ILD layer and has a non-planar surface in physical contact with the third conductive feature.

2. The structure according to claim 1, wherein: The source / drain contact has a first convex top surface in physical contact with the first conductive feature, and the gate contact has a second convex top surface in physical contact with the second conductive feature.

3. The structure according to claim 1, wherein: The source / drain contacts have first sidewalls and a first planar top surface each physically contacting the first conductive feature, and the gate contacts have second sidewalls and a second planar top surface each physically contacting the second conductive feature.

4. The structure according to claim 1, wherein: The source / drain contact is a continuous conductive feature extending through the first ILD layer, through the second ILD layer, and partially into the first conductive feature.

5. The structure according to claim 1, wherein: The third conductive feature extends partially into the fourth conductive feature.

6. The structure according to claim 1, wherein: The fourth conductive feature extends partially into the third conductive feature.

7. The structure according to claim 1, wherein: The source / drain contacts and the gate contact each include a first conductive material, the first conductive feature and the second conductive feature each include a second conductive material, and the first conductive material is different from the second conductive material.

8. The structure according to claim 7, wherein: The first conductive material has a larger work function than the second conductive material.

9. A structure for manufacturing a semiconductor device, comprising: a gate stack located above the channel region of the substrate; a source / drain region adjacent to the channel region; A first interlayer dielectric ILD layer, located above the source / drain region and the gate stack; A first intermetal dielectric IMD layer, located on the first ILD layer; a first conductive feature extending through the first IMD layer and partially into the first ILD layer; a second conductive feature extending through the first IMD layer and partially into the first ILD layer; a source / drain contact extending partially into the first ILD layer, the source / drain contact being in physical contact with the source / drain region and the first conductive feature; a gate contact extending partially into the first ILD layer, the gate contact being in physical contact with the gate stack and the second conductive feature; as well as a second ILD layer, located between the source / drain region and the first ILD layer, Wherein, the source / drain contact comprises: a third conductive feature extending partially into the first ILD layer; and A fourth conductive feature is located between the third conductive feature and the source / drain region, the fourth conductive feature extends through the second ILD layer and has a non-planar surface in physical contact with the third conductive feature.

10. The structure according to claim 9, wherein: The source / drain contact has a first recessed top surface in physical contact with the first conductive feature, and the gate contact has a second recessed top surface in physical contact with the second conductive feature.

11. The structure according to claim 9, wherein: The source / drain contacts are continuous conductive features extending partially into the first ILD layer and extending through the second ILD layer.

12. The structure according to claim 9, wherein: The third conductive feature extends partially into the fourth conductive feature.

13. The structure according to claim 9, wherein: The fourth conductive feature extends partially into the third conductive feature.

14. The structure according to claim 9, wherein: The source / drain contacts and the gate contact each include a first conductive material, the first conductive feature and the second conductive feature each include a second conductive material, and the first conductive material is different from the second conductive material.

15. The structure according to claim 14, wherein: The first conductive material has a larger work function than the second conductive material.

16. A method for manufacturing a semiconductor device, comprising: forming a gate stack over a channel region of the substrate; growing a source / drain region adjacent to the channel region; Depositing a second interlayer dielectric ILD layer over the source / drain region and the gate stack; depositing a first ILD layer on top of the second ILD layer; forming a source / drain contact through the first ILD layer and the second ILD layer, wherein the source / drain contact is in physical contact with the source / drain region; Wherein, forming the source / drain contact comprises: forming lower source / drain contacts in the second ILD layer; and forming an upper source / drain contact in the first ILD layer, the lower source / drain contact having a non-planar surface in physical contact with the upper source / drain contact; forming a gate contact through the first ILD layer, the gate contact being in physical contact with the gate stack; recessing the first ILD layer to expose a first sidewall of the source / drain contact and a second sidewall of the gate contact; forming a first conductive feature in physical contact with the first sidewall and first top surface of the source / drain contact; and A second conductive feature is formed in physical contact with the second sidewall and the second top surface of the gate contact.

17. The method according to claim 16, wherein: Recessing the first ILD layer increases an exposed surface area of ​​the source / drain contacts and an exposed surface area of ​​the gate contact by an amount in a range of 100% to 700%.

18. The method according to claim 16, wherein: Forming the source / drain contacts includes recessing the second ILD layer.

19. The method according to claim 16, wherein: Forming the source / drain contact includes recessing the lower source / drain contact.

20. The method according to claim 16, wherein: Forming the source / drain contacts includes forming a continuous conductive feature through the first ILD layer and the second ILD layer.

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