Semiconductor structure and method for forming the same

Abstract

Embodiments of the present invention describe a method for forming a conductive structure without a liner or barrier. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening exposing a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a groove in the cobalt contact extending laterally below the etch stop layer. The method also includes depositing ruthenium metal to substantially fill the groove and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric. Embodiments of the present invention also relate to semiconductor structures and methods for forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] In an integrated circuit, conductive structures (e.g., metal contacts, vias, and lines) are electrically coupled to transistor regions, such as gate electrodes and source / drain regions, and are configured to conduct electrical signals to and from the transistors. Depending on the complexity of the integrated circuit, the conductive structures may form one or more layers of metal wiring. Summary of the invention

[0003] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising: depositing an etch stop layer on a cobalt contact disposed on a substrate; depositing a dielectric on the etch stop layer; etching the dielectric and the etch stop layer to form an opening exposing a top surface of the cobalt contact; etching the exposed top surface of the cobalt contact to form a groove in the cobalt contact, the groove extending laterally below the etch stop layer; depositing ruthenium metal to fill the groove and the opening; and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

[0004] Another embodiment of the present invention provides a method for forming a semiconductor structure, comprising: forming a conductive structure on a substrate, the conductive structure comprising a first metal; forming a padless conductive structure on the conductive structure, the padless conductive structure comprising a second metal different from the first metal; wherein forming the padless conductive structure comprises: depositing an etch stop layer on the conductive structure; depositing a dielectric layer on the etch stop layer; performing a first etch to form a through-hole opening in the dielectric layer and the etch stop layer, the through-hole opening exposing the first metal; performing a second etch through the through-hole opening to form a groove in the conductive structure; depositing the second metal to fill the groove and the through-hole opening, wherein the second metal is deposited to be in physical contact with the first metal, the etch stop layer and the dielectric layer; and annealing the second metal to reduce the resistance of the second metal.

[0005] Another embodiment of the present invention provides a semiconductor structure, comprising: a contact member, comprising a first metal disposed on a substrate; a padless via formed in the contact member, wherein the padless via comprises: a second metal, physically contacting the first metal; and a first metal oxide surrounding a portion of the second metal that is not in contact with the first metal; and a second metal oxide disposed on a top surface of the second metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clear illustration and discussion.

[0007] Figure 1A is an isometric view of a barrier-free or liner-free conductive structure formed on a cobalt conductive structure in accordance with some embodiments.

[0008] Figure 1B and Figure 1C is a cross-sectional view of a barrier-free or liner-free conductive structure formed on a cobalt conductive structure in accordance with some embodiments.

[0009] Figure 2A and Figure 2B is a flow chart describing a method of forming a barrier-less or liner-less conductive structure, according to some embodiments.

[0010] Figure 3A / FIG. 3B to FIG. 7A / Figure 7B are cross-sectional views of various fabrication operations during formation of a barrier-less or liner-less conductive structure on a cobalt conductive structure, in accordance with some embodiments.

[0011] Fig. 8A is an enlarged cross-sectional view of a contact opening on a cobalt conductive structure according to some embodiments.

[0012] Figure 8B is an enlarged top view of a contact opening on a cobalt conductive structure according to some embodiments.

[0013] Figures 9 to 11 are enlarged cross-sectional views of various fabrication operations during formation of barrier-less or liner-less conductive structures on cobalt conductive structures, in accordance with some embodiments.

[0014] Fig. 12A and Fig. 12B is a cross-sectional view of an additional layer formed on a barrier-less or liner-less conductive structure formed on a cobalt conductive structure in accordance with some embodiments.

[0015] Fig.13 Shown are trends in ruthenium resistivity and cobalt out-diffusion as a function of annealing temperature and / or annealing time, according to some embodiments.

[0016] Fig.14 is a graphical representation of an annealing process for a linerless conductive structure in accordance with some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process of operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] In some embodiments, the terms "about" and "substantially" may represent a value of a given amount that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art in accordance with the teachings herein.

[0020] Active and passive devices in an integrated circuit (IC) are interconnected at a local level (e.g., within the same region of the IC) and a global level (e.g., between different regions of the IC) through multiple conductive structures such as metal contacts, metal vias, and metal lines. The conductive structures are arranged in vertically stacked metallization layers or interconnect layers. When metallization layers with different conductive materials are stacked on top of each other, design considerations should be taken into account to avoid performance degradation due to undesirable interactions (e.g., diffusion) between the conductive materials. This is particularly important for conductive structures that do not use barrier or liner layers.

[0021] Conductive structures without barrier or liner layers (also referred to herein as "linerless or barrierless conductive structures") are attractive because they exhibit lower resistance than conductive structures with barrier or liner layers. This is because the liner or barrier layer (which has a greater resistivity than the metal fill layer of the conductive structure) takes up space that could otherwise be occupied by the metal fill layer within the conductive structure. Therefore, by eliminating the liner or barrier layer in the conductive structure, the lower resistance metal fill can occupy the entire volume of the conductive structure and further reduce the contact resistance of the conductive structure.

[0022] However, because the liner-less or barrier-less conductive structure does not include a liner or barrier layer that can act as a diffusion barrier, the liner-less or barrier-less conductive structure formed on a conductive structure filled with a different metal may not be able to prevent or inhibit outdiffusion of the underlying metal under certain conditions. For example, a ruthenium-filled liner-less or barrier-less conductive structure located on top of a cobalt conductive structure (e.g., a cobalt contact) may not be able to prevent or inhibit outdiffusion of cobalt through ruthenium metal grain boundaries when both structures are annealed or subjected to thermal cycling. The aforementioned behavior imposes limitations on the implementation of the ruthenium liner-less or barrier-less conductive structure and makes it difficult to integrate the ruthenium liner-less or barrier-less conductive structure with the cobalt conductive structure.

[0023] To address the above shortcomings, the present invention is directed to a method of forming a liner-less or barrier-less ruthenium conductive structure that can mitigate the outward diffusion of cobalt atoms from an underlying cobalt conductive structure (e.g., a cobalt contact). In some embodiments, the liner-less or barrier-less ruthenium conductive structure is subjected to a low temperature annealing process (e.g., below about 360° C.) that allows ruthenium grain growth and minimizes cobalt diffusion through ruthenium metal grain boundaries. In some embodiments, the liner-less or barrier-less ruthenium conductive structure is formed with anchor points located in the cobalt conductive structure to prevent ruthenium metal "pull-out" during a planarization operation.

[0024] According to some embodiments, Figure 1A 1 is a partial isometric view of a liner-free or barrier-free conductive structure 100 (liner-free conductive structure 100) filled with ruthenium metal 110 and formed on a cobalt conductive structure 105. The cobalt conductive structure 105 is formed on a source / drain (S / D) epitaxial structure 115, which in turn is grown on a recessed portion of a fin structure 120 disposed on a substrate 125. The bottom of the fin structure 120 and the S / D epitaxial structure 115 are surrounded by a first dielectric layer 130, which forms an isolation structure (e.g., a shallow trench isolation structure) according to some embodiments.

[0025] also, Figure 1AThe transistor gate structure 140 is disposed between the cobalt conductive structures 105. The gate structure 140 is connected to the cobalt conductive structure 105 by a spacer 145 and Figure 1A The dielectric layer not shown in the figure is electrically isolated from the cobalt conductive structure 105. In some embodiments, the transistor gate structure 140, the fin structure 120 and the S / D epitaxial structure 115 form a corresponding fin-based transistor. In some embodiments, the cobalt conductive structure 105 is formed for Figure 1A S / D contacts of a fin-based transistor are shown. In some embodiments, the cobalt conductive structure 105 has an elongated rectangular shape and may extend to two or more S / D epitaxial structures 115 . As a result, one or more linerless conductive structures 100 may be formed on each cobalt conductive structure 105 .

[0026] like Figure 1A As shown, the bottom of the linerless conductive structure 100 includes an "anchor point" 160, which is formed within the top of the cobalt conductive structure 105. In some embodiments, the anchor point 160 has an arc or hemispherical shape to prevent the ruthenium metal 110 from being "pulled out" during the ruthenium planarization process. The anchor point 160 also increases the surface area between the ruthenium metal 110 and the cobalt conductive structure 105 and reduces the contact resistance between the two structures. In some embodiments, a silicide layer 165 is interposed between the cobalt conductive structure 105 and the S / D epitaxial structure 115 to provide further contact resistance reduction.

[0027] In some embodiments, Figure 1B and Figure 1C Along the cutting lines AB and CD Figure 1A For example, Figure 1B 1 along the zx plane (eg, along the fin structure 120). Figure 1A part, and Figure 1C The graph shows the zy plane (eg, along the cobalt conductive structure 105). Figure 1A part. Figure 1B and Figure 1C Shows Figure 1A For example, these additional layers include an etch stop layer 150 and an interlayer dielectric (ILD) 155 surrounding the top and middle portions of the linerless conductive structure 100 (e.g., located above the cobalt conductive structure 105), and a second dielectric 135 disposed on the first dielectric layer 130, the second dielectric 135 surrounding the upper portion of the S / D epitaxial structure 115 and the cobalt conductive structure 105.

[0028] Figure 1B and Figure 1C Details of the anchor point 160 at the aforementioned cutting position are shown. Figure 1BAs shown, the arc or hemispherical shape of the anchor point 160 is limited by the width of the cobalt conductive structure 105. This is because the width of the cobalt conductive structure 105 along the x-direction is narrower than the width of the anchor point 160. Figure 1B In the embodiment of the present invention, the arc or hemispherical shape of the anchor point 160 is not limited by the length of the cobalt conductive structure 105. Based on the above, and depending on the cutting direction, the anchor point 160 may appear to have different shapes. For a cobalt conductive structure 105 with a width greater than the width of the anchor point 160, for any cutting direction, the shape of the anchor point 160 will appear similar to Figure 1C shown.

[0029] Figure 1A , Figure 1B and Figure 1C The structures shown are exemplary, and variations of these structures are within the spirit and scope of the present invention. For example, the shape of the cobalt conductive structure 105 and the shape of the S / D epitaxial structure 115 can be different from Figure 1A , Figure 1B and Figure 1C In some embodiments, the conductive structure 105 is Figure 1A , Figure 1B and Figure 1C The conductive structures 105 may be shorter, longer, wider, or narrower than those shown. The conductive structures 105 may be circular contacts, oval contacts, rectangular contacts, or a combination thereof. In some embodiments, multiple linerless conductive structures 100 may be formed on the cobalt conductive structure 105. In some embodiments, some or all of the linerless conductive structures 100 lack anchor points 160. In some embodiments, the linerless conductive structures may be Figure 1A , Figure 1B and Figure 1C The S / D epitaxial structure 115 may have additional facets. In some embodiments, the S / D epitaxial structures 115 from adjacent fin structures 120 are merged to form a merged S / D epitaxial structure, on which the cobalt conductive structure 105 and one or more linerless conductive structures 100 may be formed. In addition, for clarity and ease of description, the S / D epitaxial structure 115 may have additional facets. In some embodiments, the S / D epitaxial structures 115 from adjacent fin structures 120 are merged to form a merged S / D epitaxial structure, on which the cobalt conductive structure 105 and one or more linerless conductive structures 100 may be formed. Figure 1A , Figure 1B and Figure 1C Some layers or structures are not shown. For example, the gate dielectric stack, work function layer, barrier layer, and metal fill for the gate structure 140 are not shown. In addition, the barrier layer for the cobalt conductive structure 105 and the spacer on the bottom sidewall surface of the S / D epitaxial structure 115 located above the first dielectric layer 130 are not shown. Figure 1A , Figure 1B and Figure 1C The above-described layers and structures not shown in the drawings are included in the spirit and scope of the present invention.

[0030] In some embodiments, the linerless conductive structure 100 is formed directly on the cobalt conductive structure 105 without an intermediate layer. For example, there is no barrier layer, liner layer, or adhesion layer between the ruthenium metal 110 and the cobalt conductive structure 105 in the linerless conductive structure 100. By way of example and not limitation, the linerless conductive structure 100 is formed by a network of vias that electrically connects the cobalt conductive structure 105 to the cobalt conductive structure 105. Figure 1A , Figure 1B and Figure 1C 105. In some embodiments, the linerless conductive structure 100 is formed by a method that mitigates the out-diffusion of cobalt through the linerless conductive structure 105 to the upper metallization level (e.g., copper metallization level) not shown. According to some embodiments, the linerless conductive structure 100 is formed by a method that mitigates the out-diffusion of cobalt through the linerless conductive structure 105 to the upper metallization level. The out-diffusion of cobalt can form voids in the cobalt conductive structure 105, which is detrimental to the contact resistance. For example, the voids in the conductive structure 105 can increase the contact resistance by about 15%. Excessive out-diffusion of cobalt can result in an electrical open circuit in the cobalt conductive structure 105.

[0031] In some embodiments, Figure 2A and Figure 2B It is used to form Figure 1A , Figure 1B and Figure 1C 1. A flowchart of a method 200 for manufacturing a linerless conductive structure 100 is shown. Other manufacturing operations may be performed between the various operations of method 200 and may be omitted for clarity and ease of description only. These various operations are within the spirit and scope of the present invention. In addition, not all operations may be required to perform the disclosure provided herein. Some operations may be performed simultaneously or in parallel. Figure 2A and Figure 2B In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described. Figure 3A / FIG. 3B to FIG. 12A / Fig. 12B Describe method 200 - whereby Figure 1B to Figure 1C , FIG. 3A to FIG. 12A It is along Figure 1A Cross-sections along cutting lines AB and CD are shown.

[0032] In some embodiments, Figure 3A and Figure 3B is an intermediate structure used in method 200. Figure 3A and Figure 3B In the method 200, the fin structure 120, the source / drain epitaxial structure 115, the first dielectric layer 130, the second dielectric layer 135, the gate structure 140, the spacer 145, the silicide layer 165 and the cobalt conductive structure 105 have been previously formed in operations not shown in the method 200. In some embodiments, Figure 3Aand Figure 3B FIG. 1 shows a structure after forming a cobalt conductive structure 105 on the silicide layer 165 above the source / drain epitaxial structure 115. Figure 1A and Figure 1B The structure of Figure 3A and Figure 3B After the manufacturing stage shown in , the top surface of the cobalt conductive structure 105 is substantially coplanar with the top surface of the second dielectric layer 135. This can be achieved, for example, by a planarization process after depositing the cobalt metal.

[0033] refer to Figure 2A The method 200 begins at operation 210 and deposits an etch stop layer (eg, cobalt conductive structure 105) on an underlying conductive structure (eg, cobalt conductive structure 105). Figure 1B and Figure 1C As an example and not limitation, Figure 4A and Figure 4B As shown, an etch stop layer 150 may be blanket deposited to cover the top surface of the cobalt conductive structure 105 and the second dielectric layer 135. In some embodiments, the etch stop layer 150 facilitates the formation of the linerless conductive structure 100. As an example and not limitation, the etch stop layer 150 may include silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), or any combination thereof. In addition, the etch stop layer 150 may be deposited by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable deposition process, and the thickness of the etch stop layer 150 is between about 1 nm and about 3 nm.

[0034] like Figure 5A and Figure 5B As shown, reference Figure 2A , the method 200 continues with operation 220 and a process of depositing an ILD 155 on the etch stop layer 150. By way of example and not limitation, the ILD 155 may include a low-k dielectric material having a dielectric constant less than about 3.9, such as a carbon-containing silicon oxide layer. In some embodiments, the ILD 155 includes hydrogen and / or nitrogen. By way of example, the ILD 155 may be deposited by a CVD process, a plasma enhanced CVD (PECVD) process, or any other suitable deposition method. By way of example and not limitation, the ILD 155 may be deposited to a thickness between about 50 nm and 70 nm, depending on the desired aspect ratio of the linerless conductive structure 100.

[0035] refer to Figure 2A, the method 200 continues with operation 230 and a process of forming an opening in the ILD 155 and the etch stop layer 150 to expose the cobalt conductive structure 105. In some embodiments, an opening may be formed simultaneously to expose the top of the cobalt conductive structure 105. By way of example and not limitation, Fig. 6A and Figure 6B 2 shows the opening 600 after forming the opening 600 according to operation 230. Figure 5A and Figure 5B In some embodiments, the opening 600 is formed using photolithography and etching operations. For example, a photoresist layer may be deposited on the ILD 155 and then patterned to form an etching mask. The dry etching process etches the ILD 155 and the portions of the etch stop layer 150 that are not covered by the photoresist etching mask to form a Fig. 6A and Figure 6B Opening 600 is shown.

[0036] Since the ILD 155 and the etch stop layer 150 include different materials, dry etching chemicals with different etch selectivities to each etch layer can be used. In some embodiments, the dry etching process may include two or more sub-operations, wherein each sub-operation uses a different etchant based on the etched material (e.g., the ILD 155 or the etch stop layer 150). For example, the first sub-operation etches the ILD 155 and terminates on the etch stop layer 150. The second sub-operation etches the etch stop layer 150 and terminates on the cobalt conductive structure 105. Additional sub-operations may be used to over-etch the cobalt conductive structure 105 and / or remove polymer materials formed during the etching operation.

[0037] refer to Fig. 6A and Figure 6B , the opening 600 has a sidewall angle θ1 along the x-axis and a sidewall angle θ2 along the y-axis. The sidewall angles θ1 and θ2 can be adjusted by etching process conditions. Independently adjustable sidewall angles θ1 and θ2 are formed between the sidewall surface of the opening 600 and the horizontal xy plane. In addition, each of the angles θ1 and θ2 can be in a range between about 85° and about 90°. In some embodiments, the sidewall angles θ1 and θ2 are substantially equal. In some embodiments, the top width 600tw of the opening 600 (e.g., in the x-direction or the y-direction) can be substantially equal to or greater than the bottom width 600bw (e.g., along the x-direction or the y-direction, respectively). In some embodiments, the aspect ratio of the opening 600 (e.g., the ratio of the height 600h to the top width 600tw) can be in a range between about 3 and about 4. However, this is not restrictive, and an aspect ratio less than about 3 or greater than about 4 is within the spirit and scope of the present invention.

[0038] refer to Figure 2A, the method 200 continues with operation 240 and a process of etching the exposed cobalt conductive structure 105 using a wet etching process to form an anchoring recess (eg, in each conductive structure 105). By way of example and not limitation, Fig. 7A and Figure 7B FIG. 2 shows a wet etching process according to operation 240. Fig. 6A and Figure 6B In some embodiments, the etching chemical includes butoxyethanol (C6H 14 O2), hydroxylamine (H3NO) and diethylenetriaminepentaacetic acid (C 14 H 23 N3O 10 ) in an aqueous solution, wherein the main etchant is water, and C6H 14 O2, H3NO and C 14 H 23 N3O 10 Acts as a cobalt surface protector. Wet etch chemistries that are selective for cobalt will etch exposed cobalt metal isotropically in all directions. As a result, Fig. 7A and Figure 7B As shown, an arc-shaped or hemispherical anchoring groove is formed on the top of the cobalt conductive structure 105 .

[0039] As mentioned above about Figure 1A , Figure 1B and Figure 1C As discussed, Fig. 7A As shown in FIG. 1 , the anchoring groove is limited by the width of the cobalt conductive structure 105 in the x direction. If the width of the cobalt conductive structure 105 is equal to or greater than the width of the anchoring groove, the anchoring groove in the cobalt conductive structure 105 is Fig. 7A and Figure 7B will look the same between.

[0040] In some embodiments, the cobalt conductive structure 105 is exposed to the wet etching chemistry at a time to control the size of the hemispherical or arc-shaped anchoring grooves. For example, the exposure time can be in the range of about 50 s to about 100 s or longer, depending on the etching rate of the etching chemistry to consume the cobalt metal. Fig. 8A yes Figure 7BAn enlarged view of a hemispherical or arc-shaped anchoring groove shown. In some embodiments, the hemispherical or arc-shaped anchoring groove has a width A in the range from about 21nm to about 39nm along the y direction. In some embodiments, the hemispherical or arc-shaped anchoring groove has a height H between about 7nm and about 13nm. In some embodiments, the ratio A / H is about 3. The foregoing range is not restrictive, and larger or smaller groove sizes are within the spirit and scope of the present invention. In some embodiments, large anchoring grooves may be more difficult to fill, while smaller anchoring grooves may not prevent metal pullout during the planarization process. According to some embodiments, the width A of the hemispherical or arc-shaped anchoring groove is greater than the bottom width 600bw of the opening 600 (e.g., A>600bw), and the bottom width 600bw is in the range from about 13nm to about 15nm. In some embodiments, the ratio A / 600bw is in the range from about 1.7 to about 2.6, and the ratio 600bw / H is in the range from about 1 to about 2. Thus, an undercut having a width of about (A-600bw) / 2 along the y-direction is formed on each side of the anchoring groove under the etch stop layer 150. In some embodiments, the undercut is in a range from about 4 nm to about 12 nm.

[0041] As discussed above, since the width of the cobalt conductive structure 105 along the x-direction is small, Fig. 7A The width of the hemispherical or arc-shaped anchoring groove shown in the x-direction is different from the width A in the y-direction. Figure 8B It is shown in Figure 8B is a top view of the anchor groove passing through the opening 600. Figure 8B In the embodiment, the width C of the anchor groove along the x direction is limited by the physical width of the cobalt conductive structure 105; therefore, the width C along the x direction is formed to be smaller than the width A of the anchor groove along the y direction. Figure 7B When viewed in the y direction as shown, the anchoring groove appears to have a hemispherical or arc shape, while when viewed along the y direction as shown Fig. 7A When viewed in the x-direction as shown, the anchoring groove appears to have a "trimmed" hemispherical or arcuate shape.

[0042] According to some embodiments, the anchor groove serves two purposes: (1) providing an anchor point for the metal fill 110 to prevent the metal fill in the opening 600 from being pulled out during a subsequent planarization process, and (2) increasing the contact area between the underlying cobalt conductive structure and the metal fill to improve the overall contact resistance.

[0043] refer to Figure 2B, method 200 continues with operation 250 and a process of depositing metal to fill opening 600. In some embodiments, the metal in operation 250 is deposited directly on the cobalt conductive structure 105 without forming a liner or barrier layer. In some embodiments, and before metal deposition, a pre-cleaning is performed to remove a native oxide layer (e.g., cobalt oxide) formed on the exposed surface of the cobalt conductive structure 105, and prepare the surface of the opening 600 for metal deposition. In some embodiments, the pre-cleaning includes an argon (Ar) plasma treatment, a hydrogen (H2) plasma treatment, or a combination thereof. In some embodiments, the hydrogen pre-cleaning treatment is performed at a temperature equal to or higher than the Ar pre-cleaning treatment. In some embodiments, a bias is applied to the substrate during each treatment, wherein the bias during the Ar pre-cleaning treatment is greater than the bias of the H2 plasma pre-cleaning treatment.

[0044] In some embodiments, a ruthenium carbonyl precursor chemical such as triruthenium dodecacarbonyl (Ru3(CO) 12 ), at a temperature below about 200° C. (e.g., about 180° C.), ruthenium metal is deposited in operation 250 by a thermal CVD process. By way of example and not limitation, ruthenium metal is deposited to a thickness of about 20 nm or a thickness sufficient to fill the opening 600 including the anchoring groove. In some embodiments, the growth of ruthenium metal is performed in a bottom-up manner. For example, ruthenium nucleation first occurs on the exposed surface of the cobalt conductive structure 105 and proceeds vertically along the z direction until the opening 600 is substantially filled. In some embodiments, a deposition temperature below 200° C. promotes the bottom-up growth of ruthenium metal.

[0045] According to some embodiments, Fig. 9 is after operation 250 and depositing ruthenium metal 110 in opening 600 Fig. 8A 600 . In some embodiments, the deposited ruthenium metal 110 extends over the ILD 155 outside the opening 600 and forms a "capping layer" that is removed by a planarization process such as a chemical mechanical planarization (CMP) process. In some embodiments, due to the bottom-up growth process and the low deposition rate of the ruthenium metal 110 on the ILD 155, the thickness of the capping layer is less than about 20 nm.

[0046] In some embodiments, the deposited ruthenium metal 110 is polycrystalline with small grains that together form a Fig. 9A large number of grain boundaries are represented by the dotted lines 900 in . In some embodiments, the large number of grain boundaries is attributed to the low deposition temperature of the ruthenium metal 110 (e.g., below about 200°C). A large number of grain boundaries are not desired because they increase the resistivity of the ruthenium metal 110. For example, when current flows through the contact, the grain boundaries serve as scattering centers for electrons. Higher deposition temperatures (e.g., above about 200°C) can result in fewer grain boundaries, but will not promote the bottom-up growth of the ruthenium metal 110 described above. Therefore, higher deposition temperatures (e.g., above about 200°C) can result in incomplete filling of gaps or voids, which can also increase contact resistance and become a source of defects.

[0047] refer to Figure 2B , the method 200 continues with operation 260 and a process of subjecting the ruthenium metal 110 to an annealing process. In some embodiments, the annealing process serves two purposes: (1) to promote the growth of ruthenium grains, and (2) to promote the formation of a ruthenium oxide interface layer between the ruthenium metal 110 and the ILD 155. A side effect of an annealing process with a long annealing time and / or a high thermal budget is the outdiffusion of cobalt from the cobalt conductive structure 105, which is discussed below.

[0048] Grain growth is desirable because ruthenium metal with larger grains has a lower electrical resistance than ruthenium metal with smaller grains. This is because metal with large grains has fewer grain boundaries (e.g., sites for electron scattering) than metal with small grains.

[0049] The growth of ruthenium oxide is desirable because it promotes adhesion between the ruthenium metal 110 and the ILD 155. Therefore, the ruthenium is less likely to be "pulled out" during subsequent planarization operations. For example, the presence of the ruthenium oxide layer can provide additional adhesion without forming anchor points to prevent ruthenium pull-out.

[0050] In some embodiments, the annealing process is performed in a temperature range between about 200°C and about 360°C to mitigate the outdiffusion of cobalt from the underlying cobalt conductive structure 105. In some embodiments, a low annealing temperature (e.g., closer to about 200°C) is combined with a long annealing time between about 5 minutes to about 10 minutes. In contrast, a high annealing temperature (e.g., close to about 360°C) is combined with a short annealing time between about 1 minute to about 5 minutes. In some embodiments, the annealing environment includes nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), a forming gas (e.g., a mixture of hydrogen and nitrogen), or any combination thereof. Oxygen or oxidizing gases are undesirable because ruthenium metal will be converted to ruthenium oxide, which has a higher resistivity than ruthenium metal. In some embodiments, the annealing process is performed at a process pressure between about 2 Torr and about 20 Torr. Higher or lower annealing pressure values ​​are possible and are within the spirit and scope of the present invention. According to some embodiments, as described below, annealing temperature and annealing time are key process parameters for controlling ruthenium grain size and cobalt out-diffusion.

[0051] Cobalt out-diffusion is undesirable because it creates voids in the cobalt conductive structure 105 and increases the resistance of the cobalt conductive structure. In addition, the out-diffusion of cobalt increases the resistivity of the unlined conductive structure because the resistivity of cobalt metal is higher than that of ruthenium metal. The main mechanism of cobalt out-diffusion is thermally driven diffusion described by Fick's law. Therefore, the annealing temperature (e.g., thermal budget) may be the main contributor to the cobalt out-diffusion process. Cobalt diffusion occurs across the grain boundaries of the ruthenium metal 110. Therefore, fewer grain boundaries can lead to fewer diffusion paths for cobalt atoms. A diffused cobalt atom can continue to move toward the top surface of the ruthenium metal 110 and agglomerate to form a cobalt agglomeration. If not suppressed, the cobalt agglomeration can electrically short the adjacent conductive structures. As discussed above, cobalt out-diffusion is also undesirable because it causes voids and reduced contact resistance.

[0052] In some embodiments, an annealing temperature below about 200°C can delay cobalt outdiffusion, but at the expense of the growth of ruthenium grains. This means that there is a temperature threshold above which ruthenium grain growth occurs and a measurable resistance benefit is obtained. In contrast, an annealing temperature above about 360°C is sufficient to promote the growth of ruthenium grains, but can significantly enhance the outdiffusion of cobalt through ruthenium grain boundaries. For example, due to the accelerated cobalt outdiffusion process, an annealing temperature exceeding about 360°C (e.g., 380°C, 400°C, or higher) can cause large voids in the cobalt conductive structure 105. For example, the voids in the cobalt conductive structure 105 caused by cobalt outdiffusion can have a length and width of about 55nm and a height of about 26nm. Therefore, annealing temperatures above about 360°C should be avoided as much as possible.

[0053] In some embodiments, due to the grain growth process, for higher annealing temperatures and / or longer annealing times, the ruthenium resistivity decreases. At the same time, under the same annealing conditions, the outdiffusion of cobalt increases. The behavior of the ruthenium resistivity and the outdiffusion of cobalt is shown in Figure 2. Fig.13 , where the trends of ruthenium resistivity and cobalt outdiffusion are shown as a function of annealing temperature at a fixed annealing time, or as a function of annealing time at a fixed annealing temperature. Therefore, it is critical to control the annealing temperature and annealing time to obtain a balance between the ideal electrical properties of the ruthenium fill and the "undesirable" cobalt outdiffusion. In some embodiments, high annealing temperatures (e.g., above about 360°C) or long annealing times (e.g., greater than 10 minutes) mitigate the resistivity benefits achieved by the grain growth process due to the cobalt outdiffusion process. In some embodiments, even at a low annealing temperature of about 200°C, annealing times longer than about 10 minutes may result in cobalt outdiffusion without providing additional contact resistance benefits. In addition to the above, longer annealing times (e.g., longer than 10 minutes) unnecessarily increase the duration of the annealing process, which in turn leads to higher manufacturing costs. In contrast, annealing times of less than about 1 minute may not allow the ruthenium grains to grow significantly and reduce the resistivity of the ruthenium metal 110. In some embodiments, annealing conditions including an annealing temperature between about 200° C. and about 360° C. in combination with an appropriate annealing time as discussed above result in a cobalt concentration within the ruthenium metal 110 that is less than about 6 atomic percent (atomic %).

[0054] In some embodiments, the selection of the annealing temperature depends on the volume of the ruthenium metal 110 to be annealed. For example, a high aspect ratio contact (e.g., having an aspect ratio of about 5 or 6) containing more ruthenium metal may require a higher annealing temperature (e.g., closer to about 360° C.) and a shorter annealing time (e.g., between about 1 minute and about 5 minutes). Conversely, a low aspect ratio via (e.g., having an aspect ratio of about 3) containing less ruthenium metal may require a lower annealing temperature (e.g., closer to about 200° C.) and a longer annealing time (e.g., between about 5 minutes and about 10 minutes). Since high and low aspect ratio linerless conductive structures can coexist on the same substrate, selecting an appropriate annealing temperature and annealing time combination can provide good contact resistance for linerless conductive structures with higher and lower aspect ratios.

[0055] According to some embodiments, Fig.14is a graphical representation of the above-mentioned annealing process. In some embodiments, after the ruthenium metal 110 is deposited, the wafer (e.g., substrate) is transferred to the annealing reactor. As an example and not limitation, the annealing reactor can be located on the same main frame as the deposition reactor or on a different main frame. In some embodiments, the annealing reactor is a single wafer reactor or an intermittent reactor (e.g., a furnace). The wafer enters the annealing reactor with a temperature of T1, which corresponds to a temperature lower than the ruthenium metal deposition (e.g., less than about 200°C) and higher than room temperature (e.g., higher than about 24°C). Subsequently, the wafer is heated to an annealing temperature T2. Depending on the design and capacity of the annealing reactor, the duration t1 of the heating process is in the range from about 30s to about 60s. The wafer is then annealed at a target annealing temperature T2 (e.g., between about 200°C and about 360°C) and for a continuous annealing time t2, which is in the range from about 1 minute to about 10 minutes, depending on the annealing temperature T2 as described above. When the annealing process is finished, the wafer is cooled to a temperature T3 corresponding to room temperature (e.g., about 24°C). Depending on the design and capacity of the annealing reactor, the duration t3 of the cooling process is in the range of from about 30s to about 60s. At this point, the wafer is removed from the annealing reactor. In some embodiments, the annealing temperature T2 is controlled within 5°C or less to ensure the accuracy and repeatability of the annealing process. As discussed above, the annealing process is performed at a pressure between about 2 Torr and about 20 Torr in a non-oxidizing environment including N2, Ar, He, H2, forming gas, or any combination thereof.

[0056] Fig.14 The annealing process described in the present invention is not intended to be limiting. For example, the heating (heating) and / or cooling (cooling) process may not be linear. Therefore, nonlinear heating and / or cooling processes are within the spirit and scope of the present invention.

[0057] As discussed above, another reason for the annealing process is to grow an interfacial ruthenium oxide layer between the ruthenium metal 110 and the ILD 155. In some embodiments, during the annealing process, oxygen from the ILD 155 combines with ruthenium metal atoms to form an interfacial ruthenium oxide layer. In some embodiments, the thickness of the interfacial ruthenium oxide layer is less than about 1 nm. In some embodiments, due to the poor interfacial separation between the ruthenium metal 110 and the ruthenium oxide layer, it may be challenging to determine the thickness of the ruthenium oxide layer by electron microscopy-based techniques such as scanning electron microscopy (SEM) and transmission electron microscopy (TEM)).

[0058] Fig.10 shows the annealing process described above with respect to operation 260 during Fig. 9 The structure of Fig.10As shown, the grain boundaries represented by the dashed lines 900 agglomerate as the grain size of the ruthenium metal 110 increases. Cobalt atoms diffuse from the cobalt conductive structure 105 into the ruthenium metal 110, as shown by the arrows at the interface between the ruthenium metal 110 and the cobalt conductive structure 105. In addition, a ruthenium oxide layer 1000 is formed at the interface between the ruthenium metal 110 and the ILD 155. In some embodiments, because the etch stop layer 150 does not contain oxygen, ruthenium oxide is not formed at the interface between the ruthenium metal 110 and the etch stop layer 150.

[0059] In contrast to other metals (such as tungsten, aluminum and copper), their oxides are not conductive, while the oxide of ruthenium metal is conductive. For example, even if the resistivity of ruthenium oxide is higher than that of ruthenium, ruthenium oxide is more conductive than a liner or barrier layer (such as titanium nitride or tantalum nitride). In addition, since the ruthenium oxide layer 1000 occupies a small portion of the total volume of the ruthenium metal 110, the effect of the ruthenium oxide layer on the total resistance can be ignored. As discussed above, the benefit of the ruthenium oxide layer 1000 is to improve the adhesion between the ruthenium metal 110 and the ILD 155, which may be beneficial during the ruthenium planarization process. For example, a planarization process (such as a CMP process) for removing the ruthenium metal capping layer on the ILD 155 can generate a mechanical force or capillary force of sufficient size to pull the ruthenium metal 110 out of the contact opening. The hemispherical or arc-shaped anchor points and the ruthenium oxide layer 1000 can prevent the ruthenium metal 110 from being pulled out during the planarization process.

[0060] refer to Figure 2B The method 200 continues with operation 270 and a process of planarizing the ruthenium metal 110 so that the top surface of the ruthenium metal 110 and the top surface of the ILD 155 are substantially coplanar, as shown in FIG. Fig.11 According to some embodiments, Fig.11 The final linerless conductive structure 100 is shown. In some embodiments, the planarization process is a CMP process that removes excess ruthenium metal deposited on the ILD 155 and planarizes the top surface of the resulting structure. In some embodiments, the planarization process of operation 270 reduces the height of the ILD 155 to about half or less than half of its original height. For example, if the original height of the ILD 155 is about 50 nm, then after the planarization process of operation 270, the height of the ILD 155 can be reduced to about 30 nm or less (e.g., to about 20 nm). This height reduction can change the resulting Figure 1A , Figure 1B and Figure 1C The aspect ratio of the linerless conductive structure 100 is shown.

[0061] refer to Fig.11 ,and Fig. 9Compared to the ruthenium metal 110 before annealing shown in FIG. 2 , the grain boundaries represented by dashed lines 900 are reduced. This reduction is a result of the grain growth that occurs during the annealing process described in operation 260. In addition, as discussed above, some diffusion of cobalt occurs under the annealing conditions described in operation 260. As a result, as shown in FIG. Fig.11 As shown, pockets of cobalt atoms 1100 may be formed along the interface between the ruthenium metal 110 and the cobalt conductive structure 105, along the sidewalls and top surface of the linerless conductive structure 100, and along the grain boundaries 900 of the ruthenium metal. In some embodiments, trace amounts of cobalt may be detected in the ruthenium metal 110 at the aforementioned locations by energy dispersive X-ray spectroscopy (EDS, EDX, EDXS, or XEDS). In some embodiments, about 1 to about 3 cobalt monolayers are formed along the ruthenium grain boundaries.

[0062] In some embodiments, operations 260 and 270 may be performed in reverse order. For example, the annealing process of operation 260 may be performed after the planarization process of operation 270. In some embodiments, if the planarization process is performed before the annealing process, the ruthenium metal 110 will lack the ruthenium oxide layer 1000, which serves as an adhesion layer to prevent the ruthenium metal from pulling out.

[0063] In some embodiments, Fig. 12A and Fig. 12B As shown, after the planarization process of operation 270, a metal oxide etch stop layer 1200 is blanket deposited on the ILD 155 to cover the linerless conductive structure 100. As an example and not a limitation, the metal oxide etch stop layer 1200 may include an aluminum oxide (Al2O3) layer having a thickness of about 3 nm. In some embodiments, the metal oxide etch stop layer 1200 serves as a capping layer that inhibits cobalt agglomeration on the top surface of the linerless conductive structure 100 and inhibits the formation of cobalt agglomerates at the free surface of the ruthenium metal 110. This is because the metal oxide etch stop layer 1200 is configured to prevent cobalt atoms from diffusing through the top surface of the linerless conductive structure 100 even when the linerless conductive structure 100 undergoes additional annealing cycles (e.g., during subsequent processing). In some embodiments, even if the subsequent annealing cycle is performed at a temperature exceeding about 400° C., agglomeration of cobalt is prevented. In some embodiments, since the diffused cobalt atoms are trapped within the linerless conductive structure 110, the cobalt diffusion process reaches a saturation point and stops.

[0064] In some embodiments, additional layers may be formed on the metal oxide etch stop layer 1200, such as Fig. 12A and Fig. 12BThe intermetal dielectric (IMD) 1210 is shown. The IMD 1210 may include a low-k dielectric (e.g., a dielectric having a dielectric constant less than about 3.9), such as carbon-containing silicon oxide. Additional conductive structures may be formed within the IMD 1210 to connect the linerless conductive structure 100 to the Fig. 12A and Fig. 12B The upper metallization levels are not shown.

[0065] As mentioned above about Figure 1B and Figure 1C As discussed, Fig. 12A and Fig. 12B Details of the anchor points 160 along different cutting positions are shown. Fig. 12A As shown, the arc or hemispherical shape of the anchor point 160 is limited by the width of the cobalt conductive structure 105 along the x-direction. This is because the width of the cobalt conductive structure 105 along the x-direction can be narrower than the width of the anchor point 160. Fig. 12B In FIG. 1 , the arc or hemispherical shape of the anchor point 160 is not limited by the length of the cobalt conductive structure 105. Based on the above, and depending on the cutting direction, the anchor point 160 may appear to have different shapes. For a cobalt conductive structure 105 having a width greater than the width of the anchor point 160, for any cutting direction (e.g., x or y), the shape of the anchor point 160 will appear similar to Fig. 12B shown.

[0066] According to some embodiments, Fig. 12A and Fig. 12B The dimensions of the anchor point 160 shown in FIG. 1 may be similar to those of FIG. Fig. 8A and Figure 8B For example, the width W along the y direction y Corresponds to Fig. 8A The anchor grooves shown have a width A (eg, between about 21 nm and about 39 nm) and a width W along the x-direction. x Corresponds to Figure 8B The anchor groove width C is shown. In some embodiments, W x and C are basically equal to Fig. 12A The top width of the cobalt conductive structure 105 is shown. In addition, the height H' of the anchor point 160 corresponds to Fig. 8A The anchor groove height H is shown (e.g., between 7 nm and about 13 nm), and Fig. 8AThe anchor groove width 600bw in corresponds to the width L of the anchor point 160 at the same location (e.g., between 13 nm and about 15 nm). In some embodiments, the ratio Wy / H' is about 3. In some embodiments, a ratio Wy / H' greater than about 3 produces a wider and shallower anchor point 160, which may be challenging due to the isotropic nature of the etching process. On the other hand, a ratio Wy / H' less than about 3 produces a narrower and deeper anchor point 160, which can make the padless conductive structure 110 easier to pull out during ruthenium CMP. In some embodiments, the ratio Wy / L is in a range from about 1.7 to about 2.6. In some embodiments, a ratio Wy / L less than about 1.7 produces a narrower anchor point 160, which can make the padless conductive structure 110 easier to pull out during ruthenium CMP. On the other hand, a ratio Wy / L greater than about 2.6 produces an enlarged anchor point, and therefore a greater difficulty in filling. In some embodiments, the ratio L / H' is in a range from about 1 to about 2.

[0067] In some embodiments, a thin film having a thickness of about (W) in the y direction is formed on each side of the anchor point 160 below the etch stop layer 150. y -L) / 2. In some embodiments, the undercuts in the x-direction and the y-direction are in a range from about 4 nm to about 12 nm. In some embodiments, an undercut less than about 4 nm may not prevent the linerless conductive structure 110 from being pulled out during the CMP process, while an undercut greater than about 12 nm may be more difficult to form by isotropic etching and subsequently fill with ruthenium metal.

[0068] In some embodiments, the linerless conductive structures 100 provide lower resistance than conductive structures filled with other metals (e.g., tungsten) that require one or more liners or barrier layers. As an example and not limitation, depending on the aspect ratio of the linerless conductive structures, the resistance of a single linerless conductive structure 100 can be less than about 80Ω (e.g., about 60Ω).

[0069] The linerless conductive structure 100 fabricated using the method 200 is not limited to cobalt source / drain contacts. For example, the method 200 may be used to form the linerless conductive structure 100 on a cobalt gate contact or any other type of cobalt conductive structure used in integrated circuits.

[0070] A method for manufacturing a conductive structure without a liner or barrier is described according to various embodiments of the present invention. In some embodiments, the conductive structure without a liner or barrier is filled with ruthenium metal deposited directly on the cobalt conductive structure without using an intermediate layer, such as an adhesion layer, a liner layer, or a barrier layer. In some embodiments, the ruthenium metal filler is annealed at an annealing temperature between about 200°C and about 360°C for about 5 minutes to reduce the resistivity of the ruthenium metal and form a ruthenium oxide layer between the ruthenium metal and the surrounding ILD. In some embodiments, the ruthenium oxide layer improves the adhesion of the ruthenium metal to the surrounding ILD. According to some embodiments, the annealing temperature between about 200°C and about 360°C can promote grain growth, but at the same time, reduce the outward diffusion of cobalt from the underlying cobalt conductive structure. The conductive structure without a liner or barrier includes anchor points, which helps to reduce the pull-out of the ruthenium metal during the subsequent ruthenium metal planarization process.

[0071] In some embodiments, a method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening exposing a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally below the etch stop layer. The method also includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

[0072] In the above method, it also includes: planarizing the ruthenium metal to co-planarize the surfaces of the ruthenium metal and the dielectric; and depositing a metal oxide on the planarized ruthenium metal.

[0073] In the above method, annealing the ruthenium metal includes annealing the ruthenium metal in a non-oxidizing environment.

[0074] In the above method, annealing the ruthenium metal includes annealing the ruthenium metal in nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), a forming gas or a combination thereof.

[0075] In the above method, wherein annealing the ruthenium metal includes performing an annealing process at an annealing temperature between 200° C. and 360° C. in a non-oxidizing environment.

[0076] In the above method, wherein annealing the ruthenium metal includes performing an annealing process for a duration between 1 minute and 10 minutes.

[0077] In the above method, wherein depositing the ruthenium metal includes depositing the ruthenium metal in physical contact with the cobalt contact.

[0078] In the above method, wherein depositing the ruthenium metal includes depositing the ruthenium metal in physical contact with the etch stop layer and the dielectric.

[0079] In the above method, wherein etching the exposed top surface of the cobalt contact comprises etching the cobalt contact using a wet etching chemistry comprising an aqueous solution.

[0080] In some embodiments, a method includes forming a conductive structure having a first metal on a substrate, and forming a linerless conductive structure on the conductive structure, wherein the linerless conductive structure includes a second metal different from the first metal. In addition, forming the linerless conductive structure includes depositing an etch stop layer on the conductive structure, depositing a dielectric layer on the etch stop layer, performing a first etch to form a via opening in the dielectric layer and the etch stop layer, the via opening exposing the first metal, and performing a second etch through the via opening to form a groove in the conductive structure. The method also includes depositing a second metal to substantially fill the groove and the via opening, wherein the second metal is deposited in physical contact with the first metal, the etch stop layer, and the dielectric layer. The method also includes annealing the second metal to reduce the resistance of the second metal.

[0081] In the above method, forming the conductive structure includes forming the conductive structure using cobalt.

[0082] In the above method, depositing the second metal includes depositing ruthenium metal.

[0083] In the above method, performing the first etching includes etching using a dry etching process, and performing the second etching includes etching using a wet etching process.

[0084] In the above method, wherein annealing the second metal includes annealing the second metal at between 200° C. and 360° C. for a duration of 5 minutes.

[0085] In the above method, wherein annealing the second metal includes growing a metal oxide on a sidewall surface of the linerless conductive structure between the first metal and the dielectric layer.

[0086] In the above method, wherein annealing the second metal includes growing ruthenium oxide on the sidewall surface of the linerless conductive structure between the first metal and the dielectric layer.

[0087] In the above method, wherein annealing the second metal includes reducing the number of grain boundaries in the second metal.

[0088] In some embodiments, a structure includes: a contact having a first metal disposed on a substrate, and an unlined via formed within the contact. In addition, the unlined via includes a second metal in physical contact with the first metal and a first metal oxide surrounding a portion of the second metal that is not in contact with the first metal. The structure also includes a second metal oxide disposed on a top surface of the second metal.

[0089] In the above structure, wherein the first metal includes cobalt, and the second metal includes ruthenium.

[0090] In the above structure, wherein the first metal oxide includes ruthenium oxide, and the second metal oxide includes aluminum oxide.

[0091] It should be understood that the detailed description section, rather than the abstract, is intended to be used to interpret the claims. The abstract of the disclosure section may set forth one or more but not all contemplated exemplary embodiments and, thus, is not intended to be limiting to the appended claims.

[0092] The present invention summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that this equivalent configuration is not directed away from the spirit and scope of the present invention, and in the case of not directed away from the spirit and scope of the present invention, they can make multiple changes, replacements and changes herein.

Claims

1. A method for forming a semiconductor structure, comprising: depositing an etch stop layer on a cobalt contact disposed on a substrate; depositing a dielectric on the etch stop layer; etching the dielectric and the etch stop layer to form an opening exposing a top surface of the cobalt contact; etching an exposed top surface of the cobalt contact to form a recess in the cobalt contact, the recess extending laterally below the etch stop layer; depositing ruthenium metal to fill the groove and the opening; as well as The ruthenium metal is annealed to convert a portion of the ruthenium metal in physical contact with the dielectric along an interface between the ruthenium metal and the dielectric into a conductive ruthenium oxide layer and to limit the cobalt concentration along grain boundaries in the ruthenium metal to less than 6 atomic percent.

2. The method according to claim 1, further comprising: planarizing the ruthenium metal to co-planarize surfaces of the ruthenium metal and the dielectric; as well as A metal oxide is deposited on the planarized ruthenium metal.

3. The method according to claim 1, wherein: Annealing the ruthenium metal includes annealing the ruthenium metal in a non-oxidizing environment.

4. The method according to claim 1, wherein: Annealing the ruthenium metal includes annealing the ruthenium metal in nitrogen (N2), argon (Ar), helium (He), hydrogen (H2), or a combination thereof.

5. The method according to claim 1, wherein: Annealing the ruthenium metal includes performing an annealing process at an annealing temperature between 200° C. and 360° C. in a non-oxidizing ambient.

6. The method according to claim 1, wherein: Annealing the ruthenium metal includes performing an annealing process for a duration between 1 minute and 10 minutes.

7. The method according to claim 1, wherein: Depositing the ruthenium metal includes depositing the ruthenium metal in physical contact with the cobalt contact.

8. The method according to claim 1, wherein: Depositing the ruthenium metal includes depositing the ruthenium metal in physical contact with the etch stop layer and the dielectric.

9. The method according to claim 1, wherein: Etching the exposed top surface of the cobalt contact includes etching the cobalt contact using a wet etch chemistry including an aqueous solution.

10. A method of forming a semiconductor structure, comprising: forming a conductive structure on a substrate, the conductive structure comprising a first metal; forming a linerless conductive structure on the conductive structure, the linerless conductive structure comprising a second metal different from the first metal; Wherein, forming the padless conductive structure comprises: depositing an etch stop layer on the conductive structure; depositing a dielectric layer on the etch stop layer; performing a first etch to form a via opening in the dielectric layer and the etch stop layer, the via opening exposing the first metal; performing a second etch through the via opening to form a recess in the conductive structure; depositing the second metal to fill the recess and the via opening, wherein the second metal is deposited in physical contact with the first metal, the etch stop layer, and the dielectric layer; and The second metal is annealed to convert a portion of the second metal to a conductive metal oxide along an interface between the second metal and the dielectric layer and to limit a concentration of cobalt diffused from the first metal to less than 6 atomic percent along grain boundaries in the second metal, wherein the first metal comprises cobalt and the second metal comprises ruthenium.

11. The method according to claim 10, wherein: Forming the conductive structure includes forming the conductive structure using cobalt.

12. The method according to claim 10, wherein: Depositing the second metal includes depositing ruthenium metal.

13. The method according to claim 10, wherein: Performing the first etching includes etching using a dry etching process, and performing the second etching includes etching using a wet etching process.

14. The method according to claim 10, wherein: Annealing the second metal includes annealing the second metal at between 200° C. and 360° C. for a duration of 5 minutes.

15. The method according to claim 10, wherein: Annealing the second metal includes growing a conductive metal oxide on sidewall surfaces of the linerless conductive structure between the second metal and the dielectric layer.

16. The method according to claim 10, wherein: Annealing the second metal includes growing conductive ruthenium oxide on sidewall surfaces of the linerless conductive structure between the second metal and the dielectric layer.

17. The method according to claim 10, wherein: Annealing the second metal includes reducing the number of grain boundaries in the second metal.

18. A semiconductor structure comprising: A contact including a first metal disposed on a substrate; A linerless through hole is formed in the contact, wherein the linerless through hole comprises: a second metal in physical contact with the first metal; pockets of atoms of the first metal disposed along grain boundaries in the second metal, wherein the pockets of atoms of the first metal comprise a concentration of less than 6 atomic percent; and a first metal oxide surrounding a portion of the second metal that is not in contact with the first metal; and a second metal oxide disposed on a top surface of the second metal, Wherein, the first metal includes cobalt, the second metal includes ruthenium, and the first metal oxide includes ruthenium oxide.

19. The semiconductor structure according to claim 18, wherein: The bottom of the linerless through hole includes an anchor point having an arc or hemispherical shape.

20. The semiconductor structure of claim 18, wherein: The second metal oxide includes aluminum oxide.

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