Data communication in enhanced speed mode

Abstract

An interconnect controller includes: a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from the transaction layer and sends the data packets to the transaction layer; and a physical layer controller coupled to the data link layer controller and a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is allowed, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and then operates the communication link using the enhanced speed.

Description

Background Art

[0001] Data communication systems are conventionally designed to comply with published communication standards so that components from one manufacturer can interoperate with components from different manufacturers. For example, many modern computing devices utilize input / output (I / O) adapters and buses that utilize a version or implementation of the Peripheral Component Interconnect (PCI) or PCI Express (PCIe) interconnect standards. The PCIe standard specifies a computer communication interconnect for attaching peripheral devices to a host computer. PCIe is an extension of the earlier PCI standard that uses existing PCI programming concepts but bases computer interconnects on a faster physical layer communication protocol. The PCIe physical layer consists of a dual unidirectional link between an upstream device and a downstream device.

[0002] The PCIe standard is published by the Peripheral Component Interconnect Special Interest Group (PCI-SIG). PCI-SIG revises the standard from time to time to reflect enhanced speeds and capabilities. For example, PCIe 1.0 was published in 2003 and specified a transfer rate of 2.5 gigatransfers per second (GT / s). PCIe 2.0 was introduced in 2007 and provided a 5.0GT / s transfer rate, followed by PCIe 3.0 with an 8.0GT / s transfer rate in 2010 and PCIe 4.0 with a 16.0GT / s transfer rate in 2017. Thus, the standard is released in a 3 to 7 year cycle with new versions increasing the transfer rate with longer discrete steps.

[0003] At the same time, semiconductor manufacturing technology has advanced rapidly. Technologies such as deep submicron lithography and low-voltage complementary metal oxide semiconductor (CMOS) transistors have increased processing speeds, making it difficult for standard setting bodies such as PCI-SIG to keep up with the pace of development. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 An exemplary data processing platform using a peripheral component interface express (PCIe) link as known in the art is shown in block diagram form;

[0005] Figure 2 A portion of a data processing platform using a PCIe link with an enhanced speed mode (ESM) according to some embodiments is shown in block diagram form;

[0006] Figure 3 A block diagram is shown in accordance with some embodiments of the present invention. Figure 2 An interconnect controller with an enhanced speed mode for a data processing platform;

[0007] Figure 4 According to some embodiments, Figure 3 A flowchart of a link initialization setup performed by an interconnect controller;

[0008] Figure 5 According to an exemplary embodiment, Figure 3 Enhanced capability descriptor for interconnect controllers;

[0009] Figure 6 Shows Figure 5 PCIe extended capability header of the extended capability descriptor;

[0010] Figure 7 shows an address map, the address map shows Figure 2 The PCIe root complex uses the current extended capability descriptor to locate subsequent extended capability descriptors;

[0011] Figure 8 Shows Figure 5 PCIe ESM header 1 of the extended capability descriptor;

[0012] Fig. 9 Shows Figure 5 PCIe ESM header 2 of the extended capability descriptor;

[0013] Fig.10 Shows Figure 5 ESM status register of the extended capability descriptor;

[0014] Fig.11 Shows Figure 5 ESM control register of the extended capability descriptor;

[0015] Fig.12 Shows Figure 5 ESM Capability 1 Register of the Extended Capability Descriptor;

[0016] Fig.13 Shows Figure 5 ESM Capability 7 register of the extended capability descriptor; and

[0017] Fig.14 Shows Shows Figure 3 a timing diagram for initialization of the interconnect controller; and

[0018] Fig.15 A communications controller supporting a PCIe transaction layer or a CCIX transaction layer according to some embodiments is shown in block diagram form.

[0019] In the following description, the same reference numerals used in different figures indicate similar or identical items. Unless otherwise specified, the word "couple" and its related verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also means an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0020] An interconnect controller for a data processing platform includes a data link layer controller and a physical layer controller. The data link layer controller is coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from the transaction layer and sends data packets to the transaction layer. The physical layer controller is coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed specified by a published standard. The physical layer controller has an enhanced speed mode, wherein in response to performing link initialization, the interconnect controller queries the data processing platform to determine whether the enhanced speed mode is allowed, performs at least one setup operation to select the enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed and is not specified by the published standard, and then operates the communication link using the enhanced speed.

[0021] A data processing platform includes a basic input / output system (BIOS) and a data processor. The data processor includes a central processing unit and a peripheral component interconnect express (PCIe) root complex. The central processing unit is coupled to the BIOS and is responsive to the BIOS to execute an initialization program. The PCIe root complex is coupled to the central processing unit and includes a first PCIe port controller coupled to a PCIe network. The first PCIe port controller supports a first predetermined link speed specified by a published standard and an enhanced speed mode. The BIOS includes instructions that, when executed by the central processing unit, cause the PCIe root complex to query the data processing platform to determine whether the enhanced speed mode is allowed, perform at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed and is not specified by a published standard, and then use the enhanced speed to operate a communication link to the PCIe network.

[0022] A method for use in a data processing platform having an interconnect controller that operates a communication link according to a published standard includes querying the data processing platform to determine whether an enhanced speed mode is allowed. Performing at least one setup operation to select an enhanced speed, wherein the enhanced speed is not specified by the published standard and is greater than a first predetermined link speed specified by the published standard. The communication link is then operated using the enhanced speed.

[0023] Figure 1An exemplary data processing platform 100 using a peripheral component interface (PCI) Express (PCIe) link is shown in block diagram form. Data processing platform 100 generally includes a central processing unit (CPU) 110, a memory 120, a PCIe endpoint 130, a PCI / PCIe bridge 140, a switch 150, legacy endpoints 160 and 170, and PCIe endpoints 180 and 190.

[0024] CPU 110 includes several components, including CPU core 112, root complex 114, and CPU core 112. Figure 1 The CPU core 112 is functionally connected to the root complex 114 through, for example, caches and internal data structures. The root complex 114 is bidirectionally connected to several PCIe links, including a PCIe link to a PCIe endpoint 130, a PCIe link to a PCI / PCIe bridge 140, and a PCIe link to a switch 150. Figure 1 As shown, PCI / PCIe bridge 140 is connected in turn to a hierarchy of PCI or PCIe devices 142 , and switch 150 is connected to legacy endpoints 160 and 170 and PCIe endpoints 180 and 190 .

[0025] The CPU 110 is also bidirectionally connected to the memory 120. Figure 1 The memory 120 is depicted as a single memory system, but it typically includes different types of memory connected to different subcomponents of the CPU 110. For example, a first portion of the memory 120 stores the system basic input / output system (BIOS) 122, and is typically implemented as non-volatile memory and connected to the CPU 110 through a system controller or "south bridge." On the other hand, a second portion of the memory 120 stores an operating system 124. The operating system is typically stored on a mass storage medium, such as a hard drive, and then loaded into a faster volatile random access memory (RAM) at startup.

[0026] In operation, system BIOS 122 is used to boot and initialize data processing platform 100. As part of initialization, system BIOS 122 determines the input / output (I / O) devices present in data processing platform 100 and proceeds with the process of configuring the PCIe fabric, which is known as enumeration. System BIOS 122 reads configuration registers associated with each I / O present in the system to determine their respective characteristics and capabilities. Once system BIOS 122 has completed enumerating the system, initializing root complex 114, and performing various other boot tasks, it transfers control to operating system 124, which forms an environment in which applications run.

[0027] Over the years, as the capabilities of integrated circuit technology have evolved, the PCIe standard has changed to allow for faster and higher speeds and enhanced capabilities. However, the standards setting process has been relatively slow, lagging behind the improvements in the capabilities of integrated circuit manufacturing technology. As a result, PCI and PCIe systems have not yet seamlessly adapted to take advantage of the developments in integrated circuit technology.

[0028] Figure 2 A portion of a data processing platform 200 using a PCIe link with an enhanced speed mode (ESM) according to some embodiments is shown in block diagram form. The data processing platform generally includes a CPU 210, a memory 220, and a PCIe network 230. The CPU 210 includes a CPU core 212, a root complex 214, and a CPU core 212 that is not relevant to the present discussion and is removed for ease of discussion. Figure 2 Several other components are omitted. Figure 2 As shown, root complex 214 includes a PCIe port controller 216 , but may include other PCIe port controllers. PCIe port controller 216 is bidirectionally connected to PCIe network 230 . Figure 2 The PCIe network 230 is shown as a cloud to highlight the fact that at boot time, the system configuration is unknown and must be learned through a discovery process and the interconnect components are assigned system addresses through enumeration. Figure 1 As shown, CPU 210 is also bidirectionally connected to memory 220, and memory 220 has a first portion 222 storing a system BIOS and a second portion 224 storing an operating system.

[0029] Data processing platform 200 and Figure 1The data processing platform 100 of the PCIe network 230 is different in that it supports enhanced speed mode (ESM). ESM extends the link speeds specified by the PCIe standard as it is revised from time to time. Specifically, ESM allows higher and / or different speeds relative to the standard speeds specified in various PCIe standard versions. As long as the link partners in the PCIe network 230 also support ESM at the same speed, the link can be operated at these enhanced speeds. The enhanced speed can take either of two forms. First, the enhanced speed can be higher than the highest supported speed published in the standard. Second, the enhanced speed can be between two discrete speeds specified by the standard.

[0030] Table 1 below shows the speeds supported by different generations of published PCIe standards:

[0031] Table I

[0032]

[0033] In one example of an implementation of the ESM, the enhanced speed may be a speed between 8.0 GT / s specified by the published PCIe 2.0 standard and 16.0 GT / s specified by the published PCIe 3.0 standard. In another example, the enhanced speed may be any one of a plurality of discrete speeds between 8.0 GT / s and 16.0 GT / s. In yet another example, the enhanced speed may be a single discrete speed higher than 16.0 GT / s specified by the published PCIe 3.0 standard, such as 25.0 GT / s. In yet another example, the enhanced speed may be any one of a plurality of discrete speeds between 16.0 GT / s and 25.0 GT / s.

[0034] By supporting speeds higher than published PCIe speeds, data processing platform 200 allows for increased performance of the data processing platform on PCIe links where both link partners support the same enhanced speed capabilities. For example, the speed may be set to the highest speed supported by both link partners. Thus, ESM allows for scalable performance increases that are not limited by the discrete speeds specified by the standard, but only by the capabilities of the semiconductor manufacturing processes used by the upstream and downstream ports and their associated controllers.

[0035] Figure 3 A block diagram is shown in accordance with some embodiments of the present invention. Figure 2 The interconnection controller 300 with enhanced speed mode of the data processing platform 200 includes a PCIe transaction layer controller 310, a PCIe data link layer controller 320 and a PCIe physical layer controller 330.

[0036] The PCIe transaction layer controller 310 has an upstream bidirectional connection for receiving data access and providing data response. Figure 3 The PCIe transaction layer controller 310 is a PCIe transaction layer controller that is uniformly labeled as "access" in the data access agent; and a downstream bidirectional connection that is used to provide and receive PCIe data packets. The system BIOS also provides various accesses for querying downstream system components and enumerating the system. Data access includes memory reads, memory writes, and responses including read data responses returned from PCIe endpoints and completions received from the data access agent. The PCIe transaction layer controller 310 translates memory access requests into PCIe packets and vice versa. Therefore, it abstracts the interconnect protocol from the memory access agent, that is, it provides protocol confidentiality for the memory access agent.

[0037] The PCIe data link layer controller 320 has a bidirectional upstream port connected to the downstream port of the PCIe transaction layer controller 310, and a bidirectional downstream port. It performs link setup, packet sequencing, flow control, retries, and other features typically associated with the data link layer according to the Open Systems Interconnection (OSI) model. The PCIe data link layer controller 320 adds headers, control information, frame check sequences, etc. to form data link layer packets for access requests that it provides to the PCIe physical layer controller 330, and processes the headers, control information, and frame check sequences of data link layer packets received from the PCIe physical layer controller 330 to form PCIe packets for access responses.

[0038] The PCIe physical layer controller 330 has an upstream bidirectional port connected to a downstream bidirectional port of the PCIe data link layer controller 320, and a downstream port connected to the medium 340, the downstream port including a unidirectional transmit port labeled "TX" and a unidirectional receive port labeled "RX". The PCIe physical layer controller 330 supports one or more enhanced speeds as will be further described below.

[0039] In an exemplary embodiment, the PCIe transaction layer controller 310, the PCIe data link layer controller 320, and the PCIe physical layer controller 330 are all circuit blocks on a CPU chip. However, the blocks of the interconnect controller 300 may be implemented in various combinations of hardware and software (e.g., operating system drivers). For example, the PCIe physical layer controller 330 may be implemented in hardware, while the PCIe transaction layer controller 310 may be implemented in software, and the PCIe data link layer controller 320 may be implemented partially in hardware and partially in software.

[0040] Figure 4 According to some embodiments, Figure 3FIG. 4 is a flow chart of a link initialization setup performed by the interconnection controller 300. Upon initialization, the interconnection controller 300 initializes the links connected to it using action blocks 410, 420, and 430 in sequence.

[0041] In action block 410, the system BIOS controls the interconnect controller 300 to query the data processing platform 200 to determine whether ESM is allowed. Querying the platform involves enumerating the bus hierarchy to detect that the platform is of a type that allows the use of ESM. Such allowing involves first determining that the platform is enabled for ESM operation, and secondly determining that there is a port capable of ESM operation at the other end of the link connected to the interconnect controller 300.

[0042] In action box 420, the system BIOS controls the interconnect controller 300 to execute a setup procedure to use the ESM. Once it is determined that the ESM is to be run, one component or the other, both components, or no component may need to perform some setup before actually running in the ESM. The interconnect controller 300 begins the setup phase of the process in response to software such as the system BIOS writing to its configuration register to enable ESM in both the upstream port (USP) and the downstream port (DSP). For ports that support ESM, the setup can be performed when the "ESM Enable" bit of the ESM control register is written to "1". For ports that do not support ESM, a vendor-specific boot program register can be used. The boot program register in the DSP must be written before the boot program in the USP because writing the register in the USP also initiates the transition to the link state L1 and the electrical idle (EI) bus state as defined in the PCIe standard.

[0043] Writing to the Startup Register triggers the following sequence. First, the interconnect controller 300 sets variables that cause the interconnect controller to perform the setup required to prepare for entry into ESM only the next time a port's transmitter enters the EI state and its receiver detects EIOS or detects or infers EI while the link is in the LinkUp state. Second, for USPs that support ESM, the link controller is instructed to initiate entry into the L1 state. USPs that do not support ESM will enter D3 热码 Third, the interconnect controller 300 performs the required environmental changes, such as changing voltages, recalibrating the physical layer controller (PHY) and other hardware, and so on.

[0044] Subsequently, each time the enable bit is written to "1", this sequence is triggered and the interconnect controller 300 performs the setup. The setup is performed only on the first transition to the EI state after writing the enable register, and all subsequent EI occurrences behave normally and do not trigger the setup procedure.

[0045] In action block 430, the interconnect controller 300 operates the link at the selected ESM data rate. Thus, the link is capable of achieving performance beyond that specified in the published standards, limited only by the processing technology capabilities used by the circuits at both ends of the link and not by any speed definition necessary to publish technical standards by standards setting organizations such as PCI-SIG.

[0046] Exemplary PCIe Implementation

[0047] The details of the implementation of ESM in PCIe will now be explained with reference to specific examples.

[0048] Figure 5 According to an exemplary embodiment, Figure 3 The extended capabilities descriptor 500 of the interconnect controller of the present invention is referred to as specifying vendor specific extended capabilities and includes a set of 11 32-bit words containing configuration information, including: a 32-bit PCIe extended capabilities header 510; a 32-bit ESM header 1 520; a 32-bit word 530, which includes a 16-bit ESM header 2 and a 16-bit ESM status register 534; a 32-bit word 540, which includes a 16-bit ESM control register 542 and a 16-bit reserved field 544 marked with "RsvdP"; and a set of ESM capability registers 550. The ESM capability registers 550 include an ESM capability 1 register 551, an ESM capability 2 register 552, an ESM capability 3 register 553, an ESM capability 4 register 554, an ESM capability 5 register 555, an ESM capability 6 register 556, and an ESM capability 7 register 557. The extended capability descriptor 500 is stored in the PCIe configuration space and is accessed by the system BIOS during discovery and enumeration and defines the supported capabilities of the interconnect controller 300. The bits used in the various registers will now be described.

[0049] Figure 6 Shows Figure 5The PCIe Extended Capability Header 510 of the Extended Capability Descriptor 500 is shown in FIG. 5. The PCIe Extended Capability Header 510 includes a PCIe Extended Capability ID field 610 in bits 0 to 15, a Capability Version 612 in bits 16 to 19, and a Next Capability Offset field 613 in bits 20 to 31. The PCIe Extended Capability ID field 610 is a read-only (RO) field storing an identification number in bits 0 to 15 that indicates the nature and format of the extended capability and is defined by the PCIe SIG. The Capability Version 612 is an RO field storing a version number defined by the PCI SIG in bits 16 to 19 that indicates the version of the capability structure that is present. The Next Capability Offset field 620 is an RO field in bits 20 to 31 that stores an offset from the next PCI Express capability structure, or stores 000h if no other item exists in the linked list of capabilities. For extended capabilities implemented in PCIe configuration space, this offset will be relative to the start of the PCI compatible configuration space and therefore must always be 000h (for terminating the capability list) or an offset greater than 0FFh. How the BIOS uses the Next Capability Offset 613 will now be described.

[0050] Figure 7 An address map 700 is shown, which shows Figure 2 How the root complex 214 uses the next capability pointer to locate subsequent extended capability descriptors. The address map 700 includes a base address 710, which forms the beginning of the PCI compatible configuration space at an offset of 00h. The location of the extended capability descriptor 500 is stored at an address location 720 between the base address 710 and FFh. The firmware in the BIOS accesses the information in the extended capability descriptor 500. After accessing the relevant information therein, the system BIOS reads the "next capability offset" in bits 20 to 31 of the PCIe extended capability descriptor 500 from the base address of the extended capability descriptor 500 at an offset of 00h. If this value is equal to 000h, the system BIOS knows that this is the last extended capability descriptor in the port configuration space. If the value is not equal to 000h but is greater than FFh, the system BIOS uses it as an offset from the base address 710 to find the next extended capability descriptor 740.

[0051] Figure 8 Shows Figure 5 1 and 2. The PCIe ESM header 1 520 of the extended capability descriptor 500 includes an ESM vendor ID field 810 in bits 0 to 15, an ESM capability revision 820 in bits 16 to 19, and an ESM capability length 830 in bits 20 to 31. The ESM vendor ID field 810 is populated with a unique number corresponding to the vendor, which defines the extended capability structure.

[0052] ESM Capability Revision 820 is a version number indicating the extended capabilities version. The system BIOS verifies the qualifications of both the ESM Vendor ID and the ESM Capability ID (see below) and then interprets this field. ESM Capability Length 830 indicates the number of bytes in the entire extended capabilities data structure, which includes the PCI Express Extended Capabilities Header, ESM Header, and ESM Registers.

[0053] Fig. 9 Shows Figure 5 500 of the PCIe ESM header 2 532 of the extended capability descriptor 500. The ESM header 2 includes a single field for storing the ESM capability ID in bits 0 to 15. This field is a vendor defined ID number that indicates the nature and format of the specified vendor specific extended capability (DVSEC) structure. The system BIOS must verify the eligibility of the ESM vendor ID field 810 before interpreting the field.

[0054] Fig.10 Shows Figure 5 The ESM status register 534 of the extended capability descriptor 500 of the extended capability descriptor 500. The ESM status register 534 occupies the first 16 bits of the word 530 of the extended capability descriptor 500 and includes the minimum time in the EI value 1010 in bits 0 to 8, the minimum time in the EI scale 1020 in bits 9 to 11, and a reserved field in bits 12 to 15. The minimum time in the EI value 1010 and the minimum time in the EI scale 1020 together define the minimum time in the EI state, which is equal to the minimum time in the EI value multiplied by a multiplier corresponding to the bit value in the minimum time in the EI scale. For example, the minimum time in the EI scale may have a value of 0 to indicate a multiplier of 1 nanosecond (ns), a value of 1 to indicate a multiplier of 32 ns, a value of 2 to indicate a multiplier of 1,024 ns, a value of 3 to indicate a multiplier of 32,768 ns, a value of 4 to indicate a multiplier of 1,045,576 ns, and a value of 5 to indicate a multiplier of 33,554432 ns. Values ​​6 and 7 are reserved. However, it should be understood that these are merely examples.

[0055] Fig.11 Shows Figure 5The ESM control register 542 of the extended capability descriptor 500. The ESM control register 542 includes an ESM "Gen 3" data rate field 1110 in bits 0 to 6, a reserved field 1120 in bit 7, an ESM "Gen 4" generation data rate field 1130 in bits 8 to 14, and an ESM enable bit in bit 15. As used herein, Gen 3 corresponds to the PCIe 8.0GT / s data rate, while Gen 4 corresponds to the PCIe 16.0GT / s data rate. The ESM Gen 3 data rate field 1110 is the data rate at which the interface operates when the speed change is negotiated to the Gen 3 data rate and the link is enabled in the ESM, in GT / s. In one example, the speed is equal to (64+the value in this field)*100x10 6 . For example, 12.8GT / s = value 64. When the ESM Enable bit is set, speed changes to Gen 3 are made using ESM at the data rate defined by this field. When the ESM Enable bit is cleared, speed changes to Gen 3 use normal (non-ESM) values ​​and operate at the normal (8.0GT / s) data rate. The ESM Gen 4 Data Rate field 1130 is a read-write field that indicates the data rate in GT / s that the interface operates at when the speed change is negotiated to the Gen 4 data rate and the link is enabled in ESM. Speed ​​equals (128 + the value in this field) * 100x10 6 . For example, 20.8GT / s = value 80. When the ESM Enable bit is set, speed changes to Gen 4 are made using ESM at the data rate defined by this field. When the ESM Enable bit is cleared, speed changes to Gen 4 use normal (non-ESM) values ​​and operate at the normal (16.0GT / s) data rate. If the port does not support Gen 4, this field can be hardwired to 000 0000b. ESM Enable Bit 1140 is a read / write bit that enables ESM. The default value for this bit is '0', and writing a '1' to this bit triggers an ESM enable bit in the Figure 4 The ESM initialization sequence shown in and described above.

[0056] Fig.12 Shows Figure 5The ESM capability 1 register 551 of the extended capability descriptor 500 of the present invention is shown in FIG. 5. The ESM capability 1 register 551 is a 32-bit register having 30 valid bits in the 0 to 29 bit positions and 2 reserved bits in the 30 and 31 bit positions. In this exemplary embodiment, the root complex 214 is capable of generating a PCIe clock signal in increments corresponding to a transfer rate of 100 MT / s. For example, the root complex 214 includes a phase-locked loop (PLL) with a programmable loop divider that is capable of generating an output PCIe clock signal having a frequency starting at a PCIe 3.0 generation rate of 8.0 GHz, and higher frequencies starting at 8.1 GT / s in the 1 bit position, 8.2 GT / s in the 2 bit position, and so on until it reaches 10.9 GT / s in the 29 bit position. ESM Capability 1 Register 551 is a read-only capability register; therefore, a "0" in the corresponding bit position indicates that ESM at that speed is not supported, while a "1" in the corresponding bit position indicates that ESM at that speed is supported. Note that ESM Capability 1 Register 551 is not a one-hot register; all supported speeds are indicated with a "1" in the corresponding bit position. ESM Capability 2 Register 552 through ESM Capability 7 Register 557 contain the corresponding bit maps.

[0057] Fig.13 Shows Figure 5 The ESM capability 7 register 557 of the extended capability descriptor 500 is shown in FIG. 551. The ESM capability 7 register 557 is a 32-bit register having 31 valid bits in the 0 to 30 bit positions and 1 reserved bit in the 31 bit position. The ESM capability 7 register 557 indicates that frequencies between 25.0GT / S and 28.0GT / s are supported starting with 25.0GT / s in the 0 bit position, 25.1GT / s in the 2 bit position, and so on until it reaches 28.0GT / s in the 30 bit position. The ESM capability 7 register 557 is a read-only capability register; therefore, a "0" in the corresponding bit position indicates that ESM at the speed is not supported, while a "1" in the corresponding bit position indicates that ESM at the speed is supported. As in the ESM capability 1 register 551, the ESM capability 7 register 557 shows all supported speeds with a "1" in the corresponding bit position.

[0058] Although not shown, the ESM capability 2 register 552, the ESM capability 3 register 553, the ESM capability 4 register 554, the ESM capability 5 register 555, and the ESM capability 6 register 556 have bit assignments generally corresponding to the ESM capability 1 register 551. The ESM capability 2 register 552 indicates that a transmission rate between 11.0GT / 2 and 13.9GT / s is supported in increments of 100MT / s. The ESM capability 3 register 553 indicates that a transmission rate between 14.0GT / 2 and 15.9GT / s is supported in increments of 100MT / s, and unlike the other registers, has reserved bits in the 20th to 31st bit positions. The ESM capability 4 register 554 indicates that a transmission rate between 16.0GT / 2 and 18.9GT / s is supported in increments of 100MT / s. The ESM capability 5 register 555 indicates that a transmission rate between 19.0GT / 2 and 21.9GT / s is supported in increments of 100MT / s. The ESM Capability 6 register 556 indicates support for transfer rates between 22.0GT / 2 and 24.9GT / s in increments of 100MT / s.

[0059] During discovery and enumeration, root complex 214 discovers the presence and functionality of all PCIe devices in data processing platform 200 by examining registers in the PCIe configuration space and determining the operating speed between each pair of link partners. Root complex 214 first determines whether extended speed mode is supported, and if so, further checks the ESM capability descriptor of each device and port between the root complex and the endpoints. Typically, the speed determined will be the highest supported speed common to all PCI links with the link controllers in root complex 214 and to the endpoints in the tree.

[0060] Fig.14 A timing diagram 1400 is shown, which shows Figure 3 14. Initialization of the interconnection controller 300. In the timing diagram 1400, the horizontal axis represents time in nanoseconds (ns), and the vertical axis represents various parameters related to link operation. Along the horizontal axis, the timing diagram 1400 shows six points of interest, which are labeled as "t0", "t1", "t2", "t3", "t4", and "t5". Along the vertical axis, the timing diagram 1400 shows five parameters of interest, including a first link state 1410 labeled as "Program Phase", a second link state 1420 labeled as "Operation on Link", a third link state 1430 labeled as "Link Speed", a fourth link state 1440 labeled as "Link State", and a fifth link state 1450 labeled as "Link Attributes".

[0061] Between t0 and t1, the program phase is in the query phase. During this time, the link is used to read registers in the PCIe configuration space, including the vendor ID (VID), device ID (DID) and ESM development program specified vendor specific extended capabilities identified in the extended capability descriptor 500. In addition, the speed is set to the initial startup speed of Gen 3, that is, 8.0GT / s. The link state is in the L0 (fully open) state, and the link attribute is data flow.

[0062] Between t1 and t4, the program phase is in the setup phase. Between t1 and t2, there are no data transfer operations on the link. The speed is changed to Gen 1 (2.5GT / s) link speed, and the link state enters the recovery state before transitioning back to L0 at the new link speed. During this time, the link transmission is marked as a training set of "TSx" separated by the EI condition. Between t2 and t3, the root complex 314 writes to a register, such as the ESM control register 542, to enable ESM on all supported links. The link speed remains at Gen 1, while the link state remains at L0. The link attribute is data flow. Between t3 and t4, the link state is changed from L0 to L1, and recovery is performed before reverting to L0. The link attributes are L1 DLLP, then EI, then training set TSx, then data flow.

[0063] Between t4 and t5, the program phase performs a speed change based on the highest speed commonly supported by all DSPs and USPs on the supporting link. The link speed is changed to the selected ESM link speed, which may be different from the Gen 3 link speed. The link enters the recovery link state before resuming to the L0 state. The link transmits the training sets TSx interrupted by the EI state during the speed change before transmitting other training sets TSx at the new ESM link speed.

[0064] After the end of training occurs at t5, the link operates in ESM and performs data access in the L0 link state at the enhanced rate. Once the necessary setup has been completed and the link returns to L0, any subsequent speed changes negotiated to Gen 3 or Gen 4 data rates will operate at the ESM data rate programmed into the ESM control register. Any speed changes negotiated to Gen 1 or Gen 2 data rates will operate at their 'normal' data rates (2.5GT / s for Gen 1 and 5.0GT / s for Gen 2).

[0065] Fig.15A communication controller 1500 supporting a PCIe transaction layer or a Cache Coherent Interconnect for Accelerators (CCIX) transaction layer according to some embodiments is shown in block diagram form. The communication controller 1500 generally includes a CCIX protocol layer block 1502, a CCIX port having a CCIX link layer block 1504, and a PCIe port 1510.

[0066] The CCIX protocol layer block 1502 is responsible for the consistency protocol, including memory read and write flows. The cache states defined in this layer allow the state of the memory to be determined, for example, whether the data is unique and unmodified (clean) or whether it is shared and modified (dirty). The CCIX protocol layer module 1502 is bidirectionally connected to the CCIX port through the CCIX link layer module 1504. The CCIX protocol layer is responsible for formatting CCIX traffic and forming and decoding CCIX.

[0067] The PCIe port 1510 includes a CCIX transaction layer block 1512, a PCIe transaction layer block 1514, and a PCIe data link layer block 1520, as well as a CCIX / PCIe physical layer block 1530. The CCIX transaction layer block 1512 is responsible for processing CCIX packets, while the PCIe transaction layer block 1514 is responsible for processing PCIe packets. The PCIe port 1510 supports virtual channels to allow different data streams to travel on a single PCIe link. By dividing CCIX traffic into one virtual channel and PCIe traffic into a second virtual channel, the PCIe port 1510 allows both CCIX and PCIe traffic to share the same PCIe medium 1540. The PCIe data link layer block 1520 performs all normal functions for the data link layer, including CRC error checking, packet acknowledgement and timeout checking, and credit initialization and exchange. The CCIX / PCIe physical layer block 1530 is built on the standard PCIe physical layer. CCIX extends PCIe to support 25GT / s ESM (Extended Speed ​​Mode), which extends beyond the 16.0GT / s speed first introduced in the PCI Express 4.0 standard. In addition, it supports extended speeds between the PCI Express 4.0 standard speed (16GT / s) to higher speeds, such as 25GT / s. Therefore, it supports greater granularity and a more robust migration path to higher speeds.

[0068] Therefore, the interconnection controller disclosed herein provides a robust controller that provides a seamless upgrade path to achieve higher performance without waiting for periodic revisions to published standards. Higher performance can take one of two forms. First, it can extend beyond the maximum data transfer rate and / or maximum clock speed specified by the standard, thereby avoiding the need to develop corresponding communication components after a new standard revision has been published. Second, it increases the intermediate data transfer rate and / or clock speed that semiconductor manufacturing technology can support without the need to fully upgrade to the next published rate. Interconnection controllers and data processors incorporating such interconnection controllers take advantage of advances in semiconductor manufacturing technology, which can lead the development of published standards and achieve performance enhancements without being constrained by large discrete speed steps. The technology can be used for a variety of data communication protocols, including PCIe and CCIX (operating using PCIe data links and physical layers).

[0069] The PCIe port controller 216 and the CPU 210 or any portion thereof may be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, the data structure may be a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that may synthesize the description to generate a netlist including a series of gates from a synthesis library. The netlist includes a collection of gates that also represent the functionality of the hardware including the integrated circuit. The netlist may then be placed and routed to generate a data set describing the geometry to be applied to the mask. The mask may then be used in various semiconductor manufacturing steps to produce the integrated circuit. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set or a graphic data system (GDS) II data as desired.

[0070] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, various high frequency oscillators can be used as reference oscillators in time-to-digital converters. These include CMOS ring oscillators, series resonant LC oscillators, parallel resonant LC oscillators, and RC oscillators. In addition, various current controlled oscillator circuits can be used. In resistor-based current controlled oscillator circuits, the resistors can take various forms, such as polysilicon resistors, thin film metal alloy resistors, and thin film metal hybrid resistors. In addition, the divider can use a variety of fixed numbers as numerators.

[0071] Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. An interconnect controller for a data processing platform, comprising: a data link layer controller adapted to be coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from the transaction layer and sends data packets to the transaction layer; as well as a physical layer controller coupled to the data link layer controller and adapted to be coupled to the communication link, the physical layer controller selectively operating at a first predetermined link speed, wherein the physical layer controller has an enhanced speed mode, Wherein in response to performing link initialization, the interconnection controller: querying the data processing platform to determine whether the enhanced speed mode is enabled; If the enhanced speed mode is enabled, the interconnect controller: performing at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed; and then operating the communication link using the enhanced speed, The physical layer controller supports multiple link speeds between the first predetermined link speed and the second predetermined link speed specified by the published standard, and the enhanced speed is a selected speed among the multiple link speeds that is not specified by the published standard, wherein consecutive speeds among the multiple link speeds are separated from each other by the same predetermined link speed.

2. The interconnection controller of claim 1, wherein: The second predetermined link speed is specified by the published standard.

3. The interconnection controller of claim 1, wherein: The physical layer controller complies with the Peripheral Component Interconnect Express (PCIe) base specification.

4. The interconnection controller of claim 3, wherein: The interconnect controller is part of a PCIe root complex that determines the enhanced speed of the interconnect controller based on capabilities of an upstream port of an endpoint.

5. The interconnection controller of claim 4, wherein: The PCIe root complex determines the enhanced speed of the interconnect controller as the highest mutually supported speed of the interconnect controller and the upstream port of the endpoint.

6. The interconnect controller of claim 4, wherein: The PCIe root complex determines the enhanced speed of the interconnect controller by accessing a PCIe configuration space.

7. The interconnection controller of claim 6, wherein: The interconnect controller determines the enhanced speed by accessing an extended capability descriptor in the PCIe configuration space.

8. The interconnect controller of claim 1, wherein: The transaction layer includes a PCIe transaction layer.

9. The interconnect controller of claim 1, wherein: The transaction layer includes a Cache Coherent Interconnect for Accelerators (CCIX) transaction layer.

10. A method for use in a data processing platform having an interconnect controller operating a communication link according to a published standard, comprising: querying the data processing platform to determine whether enhanced speed mode is enabled; If the enhanced speed mode is enabled: performing at least one setup operation to select an enhanced speed, wherein the enhanced speed is a selected speed of a plurality of link speeds and is not specified by the published standard and is between a second predetermined link speed and a first predetermined link speed specified by the published standard, wherein consecutive ones of the plurality of link speeds between the first predetermined link speed and the second predetermined link speed are separated from one another by the same predetermined link speed; as well as The communication link is then operated using the enhanced speed.

11. The method of claim 10, wherein: The interconnect controller supports a second predetermined link speed greater than the first predetermined link speed; and The enhanced speed is between the first predetermined link speed and the second predetermined link speed.

12. The method of claim 11, wherein: The published standard is the Peripheral Component Interconnect Express (PCIe) Base Specification.

13. The method of claim 10, further comprising: The enhanced speed of the interconnection controller is determined as the highest mutually supported speed between the interconnection controller and an upstream port.

14. The method of claim 10, wherein performing at least one setup operation to select the enhanced speed comprises: At least one setting operation is performed to select the enhanced speed, wherein the enhanced speed is greater than a maximum speed specified by the published standard.

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