Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor package device and a manufacturing method thereof. The semiconductor package device comprises a substrate, a first surface of the substrate is provided with a first chip and a second chip; the first chip has a first conductive part and a second conductive part, the first conductive part and the second conductive part have different heights, the first conductive part is electrically connected with the substrate at a first horizontal plane, and the second conductive part is electrically connected with the second chip at a second horizontal plane. The semiconductor package device is conducive to reducing the size of the semiconductor package device while ensuring the functionality and reliability of the semiconductor package device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging apparatus technology, and more specifically to semiconductor packaging apparatus and its manufacturing method. Background Technology

[0002] The semiconductor packaging field is showing a trend towards miniaturization of electronic components in order to achieve more functions in a smaller size.

[0003] In a semiconductor packaging device, the application chip, decoupling chip, and substrate need to be packaged into a single unit. Therefore, reducing the size of this or similar semiconductor packaging device becomes a problem that needs to be solved. Summary of the Invention

[0004] This disclosure provides a semiconductor packaging apparatus and a method for manufacturing the same.

[0005] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0006] A substrate, wherein a first chip and a second chip are disposed on a first surface of the substrate;

[0007] The first chip surface has a first conductive element and a second conductive element, the first conductive element and the second conductive element have different heights, the first conductive element is electrically connected to the substrate on a first horizontal plane, and the second conductive element is electrically connected to the second chip on a second horizontal plane.

[0008] In some alternative embodiments, the electrical connection between the first conductive element and the substrate, and the electrical connection between the second conductive element and the second chip, are formed in one step by thermocompression bonding.

[0009] In some alternative embodiments, the first conductive element is a first conductive post, and the second conductive element is a first conductive pad.

[0010] In some alternative embodiments, the first surface of the second chip has a second conductive pad, and the first surface of the substrate has a third conductive pad; and

[0011] The first conductive post is electrically connected to the third conductive pad via solder, and the first conductive pad is electrically connected to the second conductive pad via solder.

[0012] In some alternative embodiments, the second chip includes a first dielectric layer formed on a first surface of the second chip;

[0013] The second conductive pad is located on the first dielectric layer.

[0014] In some alternative embodiments, the second chip includes a first dielectric layer formed on a first surface of the second chip;

[0015] The first dielectric layer has an opening, and the second conductive pad is located inside the opening.

[0016] In some alternative embodiments, the second surface of the second chip has a second conductive post, the first surface of the substrate has a fourth conductive pad, and the second conductive post and the fourth conductive pad are electrically connected by solder.

[0017] In some alternative embodiments, the second surface of the second chip has a fifth conductive pad, the first surface of the substrate has a fourth conductive pad, and the fifth conductive pad and the fourth conductive pad are electrically connected by solder.

[0018] In some alternative embodiments, a sealing material is disposed between the first chip and the substrate, the sealing material covering the second chip.

[0019] In some alternative embodiments, the sealant is an underfill adhesive or a molding compound.

[0020] In some alternative embodiments, the sealing material fills the space between the first chip and the second chip.

[0021] In some alternative embodiments, the semiconductor packaging device further includes a cap located on the substrate, the cap having an inner cavity in which the first chip and the second chip are located.

[0022] In some alternative implementations, the first chip is an application chip, and the second chip is a decoupling chip.

[0023] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, including:

[0024] A single second chip is placed on the substrate;

[0025] A single first chip is placed on a substrate and positioned above a second chip, wherein the surface of the first chip has a first conductive element and a second conductive element, the first conductive element and the second conductive element having different heights;

[0026] The first chip is subjected to a thermo-pressing operation, which electrically connects the first conductive element to the substrate on a first horizontal plane, and electrically connects the second conductive element to the second chip on a second horizontal plane.

[0027] In some alternative implementations, the method further includes, prior to placing the individual second chip onto the substrate:

[0028] The second wafer is diced to obtain the individual second chips; and

[0029] Before placing a single first chip on the substrate and positioning the first chip above the second chip, the method further includes:

[0030] The first wafer is diced to obtain the individual first chip.

[0031] In some optional embodiments, after performing a thermo-pressing operation on the first chip to electrically connect the first conductive element to the substrate on a first horizontal plane, and to electrically connect the second conductive element to the second chip on a second horizontal plane, the method further includes:

[0032] A sealing material is disposed between the first chip and the substrate, wherein the sealing material covers the second chip.

[0033] In some alternative embodiments, after a sealing material is disposed between the first chip and the substrate, the method further includes:

[0034] A cover is disposed on the substrate, wherein the cover has an inner cavity in which the first chip and the second chip are located.

[0035] In the semiconductor packaging device and manufacturing method disclosed herein, by utilizing a first conductive element and a second conductive element with different heights on the surface of the first chip, electrical connections with the second chip and the substrate are achieved on different horizontal planes. This allows the second chip to be located in the space between the first chip and the substrate, which helps to reduce the size of the semiconductor packaging device while ensuring the functionality and reliability of the semiconductor packaging device. Attached Figure Description

[0036] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0037] Figures 1-4 These are first to fourth schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention;

[0038] Figure 5 and Figure 6 This is a schematic diagram illustrating the technical problems existing in current manufacturing methods;

[0039] Figure 7 This is a flowchart of a method for manufacturing a semiconductor packaging apparatus according to an embodiment of the present invention.

[0040] Symbol explanation:

[0041] 100, First chip; 110, First conductive element; 120, Second conductive element; 200, Second chip; 201, Second conductive pad; 202, Second conductive post; 205, Fifth conductive pad; 209, Opening; 210, First dielectric layer; 220, Second dielectric layer; 300, Substrate; 303, Third conductive pad; 304, Fourth conductive pad; 400, Sealing material; 500, Cap; 600, Adhesive material; 700, Thermal conductive material; 900, Solder. Detailed Implementation

[0042] The specific embodiments of the present invention will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present invention and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0043] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the invention. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and objectives of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0044] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0045] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0046] Figures 1-4 These are first to fourth schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention, wherein a longitudinal cross-section of the semiconductor packaging apparatus is shown.

[0047] like Figure 1As shown, the semiconductor packaging device in this embodiment includes a substrate 300, a first chip 100, and a second chip 200. The first chip 100 is, for example, an application chip, and the second chip 200 is, for example, a decoupling chip.

[0048] In this embodiment, a first chip 100 and a second chip 200 are disposed on the first surface of the substrate 300. The surface of the first chip 100 has a first conductive element 110 and a second conductive element 120, and the first conductive element 110 and the second conductive element 120 have different heights. Specifically, the height of the first conductive element 110 is greater than the height of the second conductive element 120.

[0049] In this embodiment, the first conductive element 110 is electrically connected to the substrate 300 on the first horizontal plane, and the second conductive element 120 is electrically connected to the second chip 200 on the second horizontal plane. The first horizontal plane is located below the second horizontal plane.

[0050] In one example, the first conductive element 110 can be a first conductive post, and the second conductive element 120 can be a first conductive pad. The first conductive post and the first conductive pad can be formed by electroplating, and their materials can be copper, gold, silver, etc.

[0051] In this embodiment, as Figure 2 As shown, the first surface of the second chip 200 has a second conductive pad 201, such as Figure 1 As shown, the first surface of the substrate 300 has a third conductive pad 303. The first conductive element 110 and the third conductive pad 303 can be electrically connected by solder 900, and the second conductive element 120 and the second conductive pad 201 can be electrically connected by solder 900.

[0052] In this embodiment, a sealing material 400 is disposed between the first chip 100 and the substrate 300, and the sealing material 400 covers the second chip 200. The sealing material 400 is, for example, an underfill or a molding material. The sealing material 400 can fill the space between the first chip 100 and the second chip 200, thereby increasing the structural strength of the semiconductor packaging device.

[0053] In this embodiment, the semiconductor packaging device further includes a cap 500, which is located on the substrate 300 and connected to it via an adhesive 600. The cap 500 has an inner cavity in which the first chip 100 and the second chip 200 are located. The cap 500 protects the internal first chip 100 and second chip 200. A thermally conductive material 700 may also be disposed between the cap 500 and the first chip 100. This allows heat from the first chip 100 to be conducted to the cap 500 via the thermally conductive material 700 and then dissipated, thereby improving the heat dissipation performance of the semiconductor packaging device.

[0054] In this embodiment, the semiconductor packaging device utilizes a first conductive element 110 and a second conductive element 120 with different surface heights on the first chip 100 to achieve electrical connection with the second chip 200 and the substrate 300 on different horizontal planes. This allows the second chip 200 to be located in the space between the first chip 100 and the substrate 300, which helps to reduce the size of the semiconductor packaging device while ensuring its functionality and reliability.

[0055] In one example, the electrical connection between the first conductive element 110 and the substrate 300, and the electrical connection between the second conductive element 120 and the second chip 200, can be formed in one step by thermal compression bonding (TCB). Here, thermal compression bonding refers to the method of placing the components to be bonded in a hot environment and bonding them together by pressure.

[0056] In one example, such as Figures 2-4 As shown, the second chip 200 may include a first dielectric layer 210, which may be formed on a first surface of the second chip 200. Figure 2 or Figure 3 As shown, the second conductive pad 201 can be located on the first dielectric layer 210. For example... Figure 4 As shown, the first dielectric layer 210 may have an opening 209, and the second conductive pad 201 may be located within the opening 209. Furthermore, the second chip 200 may also include a second dielectric layer 220 formed on a second surface. The first dielectric layer 210 and the second dielectric layer 220 can provide electrical protection for the second chip 200.

[0057] In one example, such as Figure 1 As shown, the second surface of the second chip 200 may have a second conductive post 202, and the first surface of the substrate 300 may have a fourth conductive pad 304. The second conductive post 202 and the fourth conductive pad 304 can be electrically connected by solder 900. In this way, the electrical connection between the second chip 200 and the substrate 300 can be achieved.

[0058] In one example, such as Figure 3 As shown, the second surface of the second chip 200 may have a fifth conductive pad 205, which may be electrically connected to the fourth conductive pad 304 via solder 900, thereby realizing the electrical connection between the second chip 200 and the substrate 300.

[0059] Existing manufacturing processes present some challenges when bonding the second chip 200 to the first chip 100. For example... Figure 5As shown, the distance d (e.g., 75 micrometers) between the first conductive element 110 of the first chip 100 and the second chip 200 is typically less than the minimum distance required by the dispensing process (e.g., 500 micrometers). On the one hand, forced dispensing can cause the underfill to flood the entire second chip 200, contaminating the conductive elements thereon (e.g., the second conductive post 202). On the other hand, increasing the distance between the second chip 200 and the first conductive element 110 of the first chip 100 will reduce the number of pins on the first chip 100 or increase the size of the first chip 100. To avoid these problems, the first chip 100 and the second chip 200 can be diced after bonding before dispensing. However, silicon residue generated during dicing will remain between the first chip 100 and the second chip 200 (e.g., ...). Figure 6 (As shown by the dashed line in the image), these silicon residues can cause delamination of the underfill adhesive, thus reducing the reliability of semiconductor packaging devices.

[0060] To address the aforementioned problems, this disclosure also provides a method for manufacturing a semiconductor packaging device. For example... Figure 7 As shown, the method includes the following steps:

[0061] First, such as Figure 7 As shown in the upper part, a single second chip 200 can be placed on the substrate first, and then a single first chip 100 can be placed on the substrate 300 with the first chip 100 positioned above the second chip 200. The surface of the first chip 100 has a first conductive element 110 and a second conductive element 120, and the first conductive element 110 and the second conductive element 120 have different heights.

[0062] Secondly, such as Figure 7 As shown in the lower part, a thermo-pressing operation can be performed on the first chip 100 to electrically connect the first conductive element 110 to the substrate 300 on the first horizontal plane, and to electrically connect the second conductive element 120 to the second chip 200 on the second horizontal plane. Here, the first chip 100, the second chip 200, and the substrate 300 can be placed in a thermal environment, and the first chip 100 can be pressed down from above, thereby achieving bonding of the first chip 100 to the substrate 300 and the second chip 200 at different heights.

[0063] In addition to achieving the technical effects of the aforementioned semiconductor packaging device, the manufacturing method in this embodiment can also achieve one-time bonding of the first chip 100, the second chip 200 and the substrate 300, avoiding problems such as imperfect dispensing or delamination of the bottom filler, thereby effectively improving the product yield (for example, increasing the yield to over 95%).

[0064] In one example, before placing the individual first chip 100 and the individual second chip 200 on the substrate 300, the method may further include: dicing the first wafer to obtain the individual first chip 100, and dicing the second wafer to obtain the individual second chip 200. Thus, the individual first chip 100 and the individual second chip 200 can be obtained.

[0065] In one example, after performing a thermo-pressing operation on the first chip 100 to electrically connect the first conductive element 110 to the substrate 300 on a first horizontal surface, and to electrically connect the second conductive element 120 to the second chip 200 on a second horizontal surface, the method may further include: disposing a sealing material 400 between the first chip 100 and the substrate 300, wherein the sealing material 400 covers the second chip 200. Thus, the sealing material 400 can be used to protect internal components and improve the lifespan of the semiconductor packaging device.

[0066] In one example, after the sealing material 400 is placed between the first chip 100 and the substrate 300, the method may further include: placing a cap 500 on the substrate 300, wherein the cap 500 has an inner cavity in which the first chip 100 and the second chip 200 are located. Thus, the cap 500 can provide protection and heat dissipation.

[0067] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: A substrate, wherein a first surface of the substrate is provided with a single first chip and a single second chip; The first chip surface has a first conductive element and a second conductive element, the first conductive element and the second conductive element having different heights. The first conductive element is electrically connected to the substrate on a first horizontal plane, and the second conductive element is electrically connected to the second chip on a second horizontal plane. The distance between the first conductive element and the second chip is less than the minimum distance required by the dispensing process. The first conductive element is a first conductive pillar, the second conductive element is a first conductive pad, the first surface of the second chip has a second conductive pad, and the first surface of the substrate has a third conductive pad. The first conductive post is electrically connected to the third conductive pad via solder, and the first conductive pad is electrically connected to the second conductive pad via solder. The second chip includes a first dielectric layer, which is formed on a first surface of the second chip; The second conductive pad is located on the first dielectric layer; The semiconductor packaging apparatus further includes a cap located on the substrate. The cap has an inner cavity in which the first chip and the second chip are located. A gap is provided between the inner surface of the cap and the first chip. A thermally conductive material is provided between the cap and the first chip.

2. The semiconductor packaging apparatus according to claim 1, wherein, The electrical connection between the first conductive element and the substrate, and the electrical connection between the second conductive element and the second chip, are formed in one step by thermo-press bonding.

3. The semiconductor packaging apparatus according to claim 1, The first dielectric layer has an opening, and the second conductive pad is located inside the opening.

4. The semiconductor packaging apparatus according to claim 1, wherein, The second surface of the second chip has a second conductive post, and the first surface of the substrate has a fourth conductive pad. The second conductive post and the fourth conductive pad are electrically connected by solder.

5. The semiconductor packaging apparatus according to claim 1, wherein, The second surface of the second chip has a fifth conductive pad, and the first surface of the substrate has a fourth conductive pad. The fifth conductive pad and the fourth conductive pad are electrically connected by solder.

6. The semiconductor packaging apparatus according to claim 1, wherein, A sealing material is disposed between the first chip and the substrate, and the sealing material covers the second chip.

7. The semiconductor packaging apparatus according to claim 6, wherein, The sealing material is a bottom filler or a molding material.

8. The semiconductor packaging apparatus according to claim 6, wherein, The sealing material fills the space between the first chip and the second chip.

9. The semiconductor packaging apparatus according to claim 1, wherein, The first chip is an application chip, and the second chip is a decoupling chip.

10. A method for manufacturing a semiconductor packaging device, comprising: A single second chip is placed on the substrate; A single first chip is placed on a substrate and positioned above a second chip, wherein the surface of the first chip has a first conductive element and a second conductive element, the first conductive element and the second conductive element having different heights; The first chip is subjected to a thermo-pressing operation to electrically connect the first conductive element to the substrate on a first horizontal plane, and to electrically connect the second conductive element to the second chip on a second horizontal plane, wherein the first conductive element is a first conductive pillar, the second conductive element is a first conductive pad, the first surface of the second chip has a second conductive pad, and the first surface of the substrate has a third conductive pad; and The first conductive post is electrically connected to the third conductive pad via solder, and the first conductive pad is electrically connected to the second conductive pad via solder. The second chip includes a first dielectric layer, which is formed on a first surface of the second chip; The second conductive pad is located on the first dielectric layer; After performing a thermo-pressing operation on the first chip to electrically connect the first conductive element to the substrate on a first horizontal plane, and to electrically connect the second conductive element to the second chip on a second horizontal plane, the method further includes: A sealing material is disposed between the first chip and the substrate, wherein the sealing material covers the second chip; After providing a sealing material between the first chip and the substrate, the method further includes: A cover is disposed on the substrate, wherein the cover has an inner cavity, the first chip and the second chip are located in the inner cavity, a gap is disposed between the inner surface of the cover and the first chip, and a thermally conductive material is disposed between the cover and the first chip; The distance between the first conductive element and the second chip is less than the minimum distance required by the dispensing process. Before placing the individual second chip onto the substrate, the method further includes: The second wafer is diced to obtain the individual second chips; and Before placing a single first chip on the substrate and positioning the first chip above the second chip, the method further includes: The first wafer is diced to obtain the individual first chip.

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