Power components protected against overheating

Abstract

Embodiments of the present disclosure relate to power components protected against overheating. The triac has a vertical structure formed from a silicon substrate having an upper surface. A first portion of the main coated metal on the upper surface is placed on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main coated metal is placed on a portion of the above layer. The gate coated metal on the upper surface is placed on a second region of the first conductivity type formed in the above layer near the first region. The porous silicon rod formed in the above layer on the upper surface has a first end in contact with the gate coated metal and a second end in contact with the main coated metal.

Description

[0001] This application is a divisional application of the invention patent application with the application date of September 28, 2016, application number 201610862478.4, and invention name "Power components protected against overheating". Technical Field

[0002] The present disclosure relates to power components protected against overheating, and more particularly to triacs and thyristors with a vertical structure protected against temperature increase. Background Art

[0003] Triacs and thyristors with a vertical structure are electronic power switches including a stack of at least four layers and / or semiconductor regions of alternating conduction types. In such components, a first metallization layer or main electrode A1 is placed on the main surface of the stack. A second metallization layer or main electrode A2 is placed on the other main surface of the stack. A metallization layer or gate electrode G is placed on the same surface of the stack as the main electrode A1.

[0004] Generally, when there is a potential difference between the main electrodes A1 and A2 of one of these components, the flow of current between the main electrodes A1 and A2 is conditional upon the application of a gate current on the gate electrode. Once the current flow between the main electrodes has been established, these components remain conducting current until it falls below a threshold value called the holding current.

[0005] Figure 1 Corresponding to FIG. 7 of U.S. Patent Application Publication No. 2015 / 0108537 (incorporated by reference). This drawing is a cross-sectional view of an example of a triac 1 with a vertical structure.

[0006] The triac 1 is formed from a lightly doped N-type silicon substrate 3 (N - ). The upper and lower surfaces of the substrate 3 include P-type doped layers 5 and 7. The upper layer 5 contains a heavily doped N-type region 9 (N + ) and a heavily doped N-type region 11 (N + ). The lower layer 7 contains a heavily doped N-type region 13 (N + ) in a region substantially complementary to the region occupied by the region 9 in a top view. The main electrode A1 is arranged on the upper surface of the substrate 3, straddling a portion of the P-type doped layer 5 and the N + region 9. The main electrode A2 is arranged on the lower surface of the substrate 3, straddling a portion of the P-type doped layer 7 and the N + region 13. The gate electrode G is arranged on the upper surface of the substrate 3, straddling a portion of the P-type doped layer 5 and the N + region 11.

[0007] When the triac 1 is in the off state and a gate signal is applied to terminal G, a gate current IGK flows between terminal G and A1 through the P layer 5, and the P layer 5 forms a resistor RGK between the terminals. If the absolute value of the gate current IGK is greater than the turn-on threshold of the triac 1, the voltage drop VGK between terminal G and A1 is sufficient to turn on the triac 1, and the triac 1 switches from the off state to the on state.

[0008] A drawback of the triac 1 is that when its temperature increases, the resistance of the P layer 5 increases, and thus the value of the equivalent resistor RGK increases. Therefore, even if the current IGK between terminal G and A1 is less than the nominal turn-on current, the flow of this current can still cause a high voltage drop in the P layer 5, resulting in parasitic turn-on of the triac 1. This parasitic turn-on contributes to increasing the triac temperature to a very high value that can cause degradation or even destruction of the triac. The same problem exists for thyristors.

[0009] Figure 2 Corresponding to FIG. 3(a) of U.S. Patent Application Publication No. 2012 / 0250200 (incorporated by reference). This drawing is a circuit diagram of an example of the protection of a triac 20 against overheating.

[0010] The triac 20 includes main terminals A1 and A2 and a gate terminal G. A Shockley diode 30 is connected between terminal G and terminal A1 of the triac 20. The Shockley diode 30 is thermally linked to the triac 20.

[0011] In operation, the Shockley diode 30 is initially in the off state and the triac 20 operates normally. When the triac 20 overheats, the temperature of the Shockley diode increases and its turn-on threshold decreases. Therefore, when a gate signal is applied to terminal G, the signal is diverted through the Shockley diode. Therefore, no current flows through the resistor RGK short-circuited by the Shockley diode, and the triac 20 remains in the off state. This makes it possible to avoid the triac temperature from continuing to increase, thereby preventing its degradation or its destruction.

[0012] Regarding Figure 2 The protection described is relatively difficult to implement and adjust, and is also relatively bulky.

[0013] Therefore, it is desirable to have triacs and thyristors that include protection against overheating, thereby overcoming at least some of the drawbacks of existing protection schemes. Summary of the Invention

[0014] An embodiment provides a triac with a vertical structure, which includes, on an upper side surface of a silicon substrate: a main metallization layer having a first part and a second part, the first part being disposed on a first region of a first conductivity type formed in a layer of a second conductivity type, and the second part being disposed on a part of the above layer; a gate metallization layer disposed on a second region of the first conductivity type formed in the above layer near the first region; and at least one porous silicon rod formed in the above layer, a first end of the rod being in contact with the metallization layer and a second end of the rod being in contact with the main metallization layer.

[0015] According to an embodiment, the gate metallization layer is in electrical contact only with the second region and the at least one porous silicon rod.

[0016] According to an embodiment, the triac includes: a first porous silicon rod having a first end in contact with the first part of the main metallization layer; and a second porous silicon rod having a second end in contact with the second part of the main metallization layer.

[0017] According to an embodiment, the triac includes a rod having a first part extending in the first region and a second part extending in the above part of the above layer.

[0018] Another embodiment provides a thyristor with a vertical structure, which includes, on an upper side surface of a silicon substrate: a main metallization layer disposed on a first region of a first conductivity type formed in a layer of a second conductivity type; a gate metallization layer disposed on a second region made of a porous silicon or doped silicon of the first conductivity type formed in the above layer near the first region; and at least one porous silicon rod formed in the above layer, a first end of the rod being in contact with the gate metallization layer and a second end of the rod being in contact with the main metallization layer.

[0019] According to an embodiment, between its first end and second end, the rod includes a part extending in the first region. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 Previously described and corresponding to FIG. 7 of Publication No. 2015 / 0108537;

[0022] Figure 2 Previously described and corresponding to FIG. 3(a) of Publication No. 2012 / 0250200;

[0023] Figures 3A to 3CSchematically shows an embodiment of a triac protected against temperature increase;

[0024] Figure 4 Schematically shows Figures 3A to 3C an alternative embodiment of the triac; and

[0025] Figure 5A and 5B Schematically shows an embodiment of a thyristor protected against temperature increase. DETAILED DESCRIPTION

[0026] In the various figures, the same elements are denoted by the same reference numerals, and furthermore, the various figures are not to scale.

[0027] In the following description, the terms "right hand", "upper", "lower", etc. refer to the orientation of the element concerned in the corresponding figure. Unless otherwise mentioned, the expressions "arranged on" and "placed on" mean arranged on and in contact with, and "placed on and in contact with".

[0028] Figure 3A , 3B and 3C schematically show an embodiment of a triac 40 protected against overheating. Figure 3A is a top view, Figure 3B and 3C are cross-sectional views along the respective planes AA and BB of Figure 3A .

[0029] The triac 40 includes silicon layers 41, 43, and 45 of alternating conduction types (PNP respectively), which correspond to the layers 7, substrate 3, and layer 5 of the triac 1 described with respect to Figure 1 . A heavily doped N-type silicon region 47 (N + ) is formed in the upper P layer 45, and a heavily doped N-type silicon region 49 (N + ) is formed in the lower P layer 41. At the corners of the triac 40, a heavily doped N-type silicon region 51 (N + ) is formed near the N + region 47 in the upper P layer 45. In this embodiment, the N + region 51 has a square shape in the top view. Additionally, the N + region 47 has a triangular shape in the top view that includes a cut-off angle (on the right hand side of Figure 3A ) and is opposite to the N + region 51. Although not shown in Figures 3A to 3C , the N + region 49 occupies substantially the same area in the top view as that occupied by the N +The region complementary to the region occupied by region 47.

[0030] The upper main metallization layer A1 is placed on the upper surface of the stack of layers and / or regions 41, 43, 45, 47, 49 and 51, spanning N + Region 47 and the upper P layer 45. The main metallization layer A2 is placed on the lower surface of the stack, spanning N + Region 49 and the upper P layer 41. The gate metallization layer G is placed on N + Region 51. The insulating layer 53 is arranged on the upper and lower surfaces of the stack and defines the surfaces of the electrical contacts between the metallization layers A1, A2 and G and the semiconductor regions and / or layers of the stack. The electrical contact surfaces are defined by Figure 3A The dashed line 55 in.

[0031] The triac 40 further includes two rods 57 and 59 made of porous silicon formed in the P layer 45. One end 57A of the rod 57 is arranged in N + Region 51 and is in contact with the gate metallization layer G, and the other end 57B of the rod 57 is arranged in N + Region 47 and is in contact with the main metallization layer A1. One end 59A of the rod 59 is arranged in N + Region 51 and is in contact with the gate metallization layer G, and the other end 59B of the rod 59 is arranged in a portion of the P layer 45, on which a portion of the metallization layer A1 resides, and the end 59B is in contact with this portion of the main metallization layer A1. Between their ends, the rods 57 and 59 are coated with the upper insulating layer 53. Thus, although portions of the rod 57 extend in N + Region 51, and portions of the rod 59 extend in a portion of the P layer coated with the metallization layer A1, these portions of the rods 57 and 59 have no electrical contact with the metallization layer A1. Additionally, the gate metallization layer G is only in electrical contact with N + Region 51 and the ends 57A and 59A of the rods 57 and 59.

[0032] Consider the case where a potential difference is applied between the terminals A1 and A2. If the positive or negative gate current IGK (absolute value) is greater than the turn-on current of the triac 40 flowing between the terminals G and A1, the current IGK basically flows through the porous silicon rods 57 and 59, which forms a resistor RGK between the terminals G and A1. For low temperatures, the resistance RGK is high, so that the voltage VKG between the terminals G and A1 is sufficient to turn on the triac 40. However, when the triac 40 overheats, the resistance RGK decreases, so that the voltage VGK between the terminals G and A1 is no longer sufficient to turn on the triac 40, and the triac 40 remains in the off state.

[0033] A porous silicon rod 57 and 59 are provided between the electrode G and A1 so as to avoid the triac 40 becoming conductive once overheated.

[0034] It should be understood that in the same way, when selecting the doping levels and dimensions of the different semiconductor regions of the triac 40 according to the desired turn-on conditions, the porosity and dimensions of the rods 57 and 59 are also selected such that the triac 40 no longer turns on above a given temperature threshold. For a given temperature threshold, the porosity and dimensions of the rods 57 and 59 can be determined with the aid of simulation tools currently used by those skilled in the art. The formation of a porous silicon region, such as a rod, in a doped semiconductor layer is described, for example, in Publication No. 2015 / 0108537.

[0035] Advantageously, the rods 57 and 59 have a small volume and preferably extend closest to the region of the triac 40 that is subject to the strongest temperature increase. Additionally, in contrast to the case where protection against overheating is performed by a Shockley diode as Figure 2 shown, the rods 57 and 59 enable protection of the triac 40 against overheating regardless of its operating quadrant.

[0036] The triac 40 described above can be considered as two thyristors assembled in antiparallel. The first thyristor includes layers 47, 45, 43, and 41, and the second thyristor includes layers 49, 41, 43, and 45. The rod 57 is more sensitive to the overheating of the first thyristor, and the rod 59 is more sensitive to the overheating of the second thyristor. The protection against overheating described above thus advantageously enables taking into account the temperature increase that occurs in one or the other of the thyristors forming the triac 40.

[0037] Figure 4 is Figures 3A to 3C a top view of an alternative embodiment of the triac.

[0038] Figure 4 The triac 60 of Figures 3A to 3C includes the same elements as the triac 40 of + except that the porous silicon rods 57 and 59 are replaced by a single porous silicon rod 61. One end 61A of the rod 61 is arranged in the N + region 51 and is in contact with the gate metallization layer G. The other end 61B of the rod 61 is arranged in the P layer 45 and is in contact with the main metallization layer A1. Between its ends 61A and 61B, the rod includes a portion extending in the P layer 45 and the N +extends in region 47. Between the ends 61A and 61B, the bar is coated with an insulating layer 53. Thus, the bar 61 is in the P layer and N + The portion extending in region 47 has no electrical contact with the metallization layer A1. In Figure 4 In the triac 40, the gate metallization layer G is only in electrical contact with the N + region 51 and the end 61A of the bar 61.

[0039] Advantageously, the end 61B of the bar 61 is arranged in the substantially central region of the triac, that is, in the region that most represents the temperature of the triac.

[0040] Figure 5A and 5B An embodiment of a thyristor 70 protected against temperature increase is schematically shown. Figure 5A is a top view, Figure 5B is a cross-sectional view along the Figure 5A plane AA.

[0041] The thyristor 70 includes silicon layers 41, 43, and 45 having alternating conduction types (PNP, respectively). A heavily doped N-type silicon region 71 (N + ) is formed in the main portion of the upper P layer 45. In the top view, the N + region 71 has, for example, a substantially square shape. The upper main metallization layer A1 is placed on the N + region 71, and the lower main metallization layer A2 is placed on the lower P layer 41. At the corners of the thyristor, the gate metallization layer G is placed on a heavily doped N-type region 72 (N + ) formed in the upper P layer 45. It should be noted that in such a configuration, the thyristor can be turned on by both positive and negative gate currents, which is not the case for conventional thyristors for which only positive turn-on is possible. As a variant, the region 72 can be made of porous silicon instead of heavily doped N-type silicon (N + ). In the present embodiment, the insulating layer 53 is arranged on the upper and lower surfaces of the stack and defines the surfaces of the electrical contacts between the metallization layers A1, A2, and G and the semiconductor regions and / or layers of the stack. The electrical contact surfaces are defined by the Figure 5A dashed line 55 in.

[0042] A porous silicon bar 73 is formed in layer 45. One end 73A of the bar 73 is arranged under the metallization layer G and in contact with the metallization layer G, and the other end 73B of the bar 73 is arranged under the metallization layer A1 and in contact with the metallization layer A1. Between the ends 73A and 73B of the bar 73, the bar 73 is coated with the insulating layer 53. Thus, although between its ends 73A and 73B, the bar 73 includes in the N +The part extending in region 71, however, this part has no electrical contact with the metallization layer A1. Additionally, the gate metallization layer G is only in electrical contact with region 72 and the end 73A of the rod 73.

[0043] In operation, similar to that described for Figures 3A to 4 the triac, when there is a gate current IGK flowing between terminals G and A1, this current basically flows through the rod 73, which forms a resistor RGK between these terminals. For normal operating temperatures, the equivalent resistor RGK has a high value. Thus, when the current IGK is greater than the nominal thyristor turn-on current, the voltage drop VGK between the metallization layer G and A1 is sufficient to turn on the thyristor. However, when the thyristor overheats, the resistance RGK decreases, so that the voltage drop VGK between the metallization layer G and A1 is no longer sufficient to turn on the thyristor, and the thyristor remains off.

[0044] Advantageously, the end 73B of the rod 73 is arranged in the substantially central region of the N + region 71, that is, in the thyristor region that suffers the strongest temperature increase.

[0045] In the same way as the triac 40 described previously, those skilled in the art can modify the way the rod 73 is arranged in the thyristor 70 such that the rod is closest to the thyristor region that suffers the strongest temperature increase. It is also possible to provide more than one porous silicon arranged in the thyristor to be sensitive to the temperature increases occurring in different regions of the thyristor.

[0046] As an example, the resistivity of the porous silicon of the rods 57, 59, 61, and 73 is selected in the range of 10 3 to 10 4 ohm.cm at 25 °C. Additionally, in the technical method of forming integrated power components, such as the components described previously using silicon, the thicknesses of the different layers and / or regions are:

[0047] - For regions 47, 49, 51, and 71, from 5 to 20 μm, for example 10 μm,

[0048] - For layers 41 and 45, from 10 to 50 μm, for example 35 μm,

[0049] - For rods 57, 59, 61, and 73, from 10 to 25 μm, for example 15 μm, and

[0050] - For layer 43, from 50 to 200 μm, for example 100 μm.

[0051] The doping concentrations are for example:

[0052] - For the lightly doped N-type layer 43 (N -), in the range of 1014 to 1015 at. / cm3,

[0053] - For the heavily doped N-type regions 47, 49, 51 and 71 (N + ), on the order of 1020 at. / cm3, and

[0054] - For the P-type layers 41 and 45, in the range of 5.107 to 5.1018 at. / cm3

[0055] More generally, relatively speaking, the thickness of the bars 57, 59, 61 and 73 is, for example, in the range of 0.5 to 1 times the thickness of the layer 45.

[0056] Specific embodiments have been described. Those skilled in the art will think of various alternatives, modifications and improvements. In particular, although the specific shapes of the regions 47, 49, 51, 71 and 73 and the metallization layers G, A1 and A2 have been described, it should be understood that these shapes can be modified. For example, in Figure 5A and 5B of the thyristor 70, the N + region 71 can be interrupted by an emitter short circuit, which is the region where the material of the P-layer 45 becomes in contact with the metallization layer A1. Although the specific arrangement of the gate metallization layer with respect to the main metallization layer A1 has been described, the embodiments described above can be adapted to other arrangements of the metallization layers G and A1, for example, adapted to a structure with a central gate.

[0057] The above description uses straight bars for illustration. However, it should be understood that the bars can be bent or wavy.

[0058] Such alternatives, modifications and improvements are intended to be part of this disclosure and are intended to be within the spirit and scope of the invention. Therefore, the above description is only an example and is not intended to be limiting. The invention is only limited as defined in the following claims and their equivalents.

Claims

1. An integrated circuit, comprising: a silicon substrate having an upper surface side and a lower surface side and including a stack of layers, the stack of layers including: a first layer doped with a first conduction type, a second layer doped with a second conduction type, and a third layer doped with the first conduction type; a first metallization layer on the upper surface side and having a first portion disposed on a first doped region of the second conduction type, the first doped region being formed in the third layer; a gate metallization layer on the upper surface side and disposed on a second doped region of the second conduction type, the second doped region being formed in the third layer; a porous silicon rod formed in the third layer, wherein a first end of the porous silicon rod contacts the first doped region and the first metallization layer, and wherein a second end of the porous silicon rod contacts the second doped region and the gate metallization layer; and a second metallization layer on the lower surface side.

2. The integrated circuit according to claim 1, wherein the gate metallization layer is in electrical contact only with the second doped region and the porous silicon rod.

3. The integrated circuit according to claim 1, wherein the second doped region is also made of a porous silicon material.

4. The integrated circuit according to claim 1, wherein the first metallization layer further includes a second portion disposed on a portion of the third layer.

5. The integrated circuit according to claim 1, further comprising a third doped region of the second conduction type formed in the first layer, and wherein the second metallization layer contacts the third doped region.

6. The integrated circuit according to claim 1, further comprising a fourth doped region of the first conduction type formed in the third layer, and wherein the first metallization layer contacts the fourth doped region.

7. The integrated circuit according to claim 6, wherein the first end of the porous silicon rod contacts the fourth doped region.

8. An integrated circuit, comprising: a silicon substrate having an upper surface side and a plurality of layers of alternating conduction types; a first metallization layer on the upper surface side and disposed on a first region doped with a first conduction type, the first region being formed in a layer doped with a second conduction type in the plurality of layers; a gate metallization layer on the upper surface side and disposed on a porous silicon region formed in the layer doped with the second conduction type, wherein the first region is separated from the porous silicon region by a portion of the layer doped with the second conduction type; and a porous silicon rod formed in the layer doped with the second conduction type and having a first end in contact with the gate metallization layer and a second end in contact with the first metallization layer.

9. The integrated circuit according to claim 8, wherein between the first end and the second end, the porous silicon rod includes a portion extending in the first region.

10. The integrated circuit according to claim 8, wherein the first end of the porous silicon rod contacts the first region, and wherein the second end of the porous silicon rod contacts the porous silicon region.

11. The integrated circuit according to claim 8, wherein the silicon substrate has a lower surface side and further includes a second metallization layer on the lower surface side.

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