Integrated chip and method for manufacturing the same

Abstract

The disclosed embodiments are related to an integrated chip and a method for manufacturing the same. Various embodiments of the present disclosure relate to an integrated chip, the integrated chip comprising: a first undoped layer overlying a substrate. A first barrier layer overlying the first undoped layer and having a first thickness. A first doped layer overlying the first barrier layer and laterally disposed in an n-channel device region of the substrate. A second barrier layer overlying the first barrier layer and disposed in a p-channel device region laterally adjacent to the n-channel device region. The second barrier layer has a second thickness greater than the first thickness. A second undoped layer overlying the second barrier layer. A second doped layer overlying the second undoped layer. The second undoped layer and the second doped layer are disposed in the p-channel device region.

Description

Technical Field

[0001] The disclosed embodiments relate to an integrated chip and a manufacturing method thereof. Background Art

[0002] Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Depending on the application of the integrated chip (IC), the IC may use many different types of transistor devices. In recent years, the growth of the cellular and radio frequency (RF) device markets has led to a significant increase in the use of high voltage transistor devices. Therefore, compared with silicon-based semiconductor devices, high electron mobility transistor (HEMT) devices have received increasing attention due to their high electron mobility and wide band gap. Such high electron mobility and wide band gap enable improved performance (e.g., fast switching speed, low noise) and high temperature applications. Summary of the invention

[0003] The disclosed embodiment provides an integrated chip, which includes: a first undoped layer overlying a substrate; a first barrier layer overlying the first undoped layer, wherein the first barrier layer has a first thickness; a first doped layer overlying the first barrier layer and laterally disposed in an n-channel device region of the substrate; a second barrier layer overlying the first barrier layer and disposed in a p-channel device region laterally adjacent to the n-channel device region, wherein the second barrier layer has a second thickness greater than the first thickness; a second undoped layer overlying the second barrier layer; and a second doped layer overlying the second undoped layer, wherein the second undoped layer and the second doped layer are disposed in the p-channel device region.

[0004] The disclosed embodiment provides an integrated chip, the integrated chip comprising: a substrate having an n-channel device region located laterally next to a p-channel device region; a first undoped layer overlying the substrate; a first n-channel device disposed in the n-channel device region, wherein the first n-channel device comprises a first barrier layer, a first doped layer, and a first gate electrode overlying the first doped layer, wherein the first doped layer contacts the first barrier layer; a first p-channel device disposed in the p-channel device region, wherein the first p-channel device comprises a second barrier layer, a second undoped layer, a second doped layer, and a second gate electrode overlying the second doped layer, wherein the second barrier layer directly contacts the first barrier layer, and wherein the second undoped layer is disposed between the second barrier layer and the second doped layer; and wherein the first barrier layer comprises a III-V semiconductor material having a first concentration of a plurality of elements and the second barrier layer comprises the III-V semiconductor material having a second concentration of a plurality of elements, the second concentration of the plurality of elements being different from the first concentration of the plurality of elements.

[0005] The disclosed embodiment provides a method for forming an integrated chip, the method comprising: depositing a first undoped layer on a substrate, wherein the substrate comprises an n-channel device region adjacent to a p-channel device region in a laterally direction; depositing a first barrier layer on the first undoped layer; depositing a first doped film on the first barrier layer; performing a first patterning process on the first doped film to define a first doped layer in the n-channel device region, wherein the first patterning process removes the first doped film from the p-channel device region; selectively forming a film layer stack on the first barrier layer and in the p-channel device region, wherein the film layer stack comprises a second barrier layer, a second undoped layer and a second doped layer; forming a first gate electrode on the first doped layer; and forming a second gate electrode on the second undoped layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B A cross-sectional view of an integrated high electron mobility transistor (HEMT) device having n-channel devices and p-channel devices on the same substrate of some embodiments is shown.

[0008] Figure 2 A cross-sectional view of an integrated HEMT device having n-channel devices and p-channel devices on the same substrate is shown for some additional embodiments.

[0009] Figure 3 A cross-sectional view of a HEMT device having an n-channel device region with a plurality of n-channel devices each having a different threshold voltage is shown in accordance with some embodiments.

[0010] Figure 4 A cross-sectional view of a HEMT device having a p-channel device region with a plurality of p-channel devices each having a different threshold voltage is shown in accordance with some embodiments.

[0011] Figure 5 Cross-sectional views of some embodiments of integrated HEMT devices having multiple n-channel devices laterally adjacent to multiple p-channel devices on the same substrate are shown.

[0012] Figures 6 to 11 A cross-sectional view illustrating a method of forming an integrated HEMT device having n-channel devices and p-channel devices on the same substrate according to some embodiments.

[0013] Fig.12 Some embodiments are shown Figures 6 to 11 Flowchart corresponding to the method in .

[0014] [Explanation of Symbols]

[0015] 100a, 100b, 200, 500: Integrated HEMT devices

[0016] 102: Substrate

[0017] 102a: n-channel device area

[0018] 102b: p-channel device area

[0019] 104: First undoped layer

[0020] 106: First barrier layer

[0021] 108: n-channel device

[0022] 110: p-channel device

[0023] 111: The first heterojunction

[0024] 112: First contact

[0025] 114: First doping layer

[0026] 116: first gate electrode

[0027] 117: Second heterojunction

[0028] 118: Second barrier layer

[0029] 120: Second undoped layer

[0030] 122: Second doping layer

[0031] 124: Second contact

[0032] 126: Second gate electrode

[0033] 128: Dielectric Structure

[0034] 201: Lower buffer layer

[0035] 202: Via hole

[0036] 204: Isolation Structure

[0037] 300, 400, 600, 700, 800, 900, 1000, 1100: Section view

[0038] 302a: first n-channel device / n-channel device

[0039] 302b: second n-channel device / n-channel device

[0040] 302n: nth n-channel device / n-channel device

[0041] 402a: first p-channel device / p-channel device

[0042] 402b: second p-channel device / p-channel device

[0043] 402m: mth p-channel device / p-channel device

[0044] 602: First doped film

[0045] 802: Shielding layer

[0046] 804: Opening

[0047] 902: Film stacking

[0048] 1002: Dielectric layer

[0049] 1200: Methods

[0050] 1202, 1204, 1206, 1208, 1210, 1212, 1214, 1216, 1218, 1220: Action

[0051] t1, t2, tn1, tn2~tnN, tp1, tp2~tpM: thickness DETAILED DESCRIPTION

[0052] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0053] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0054] A high electron mobility transistor (HEMT) device includes a heterojunction located at the interface between two materials with different band gaps and serving as a channel region of the HEMT device. In an enhancement mode device (e.g., an enhancement-mode field effect transistor (E-FET)), the HEMT device uses a gate to source voltage (i.e., a threshold voltage) to switch the HEMT device "on" (e.g., "conducting" current between the source and the drain). In a depletion mode device (e.g., a depletion-mode field effect transistor (D-FET)), the HEMT device uses a gate to source voltage (i.e., a threshold voltage) to switch the device "off" (e.g., "turning off" current between the source and the drain).

[0055] For example, in an enhancement mode of an n-channel HEMT device, a conduction band at a heterojunction has a sharp valley that drops below and intersects the Fermi level, so that a two-dimensional electron gas (2DEG) is formed at the heterojunction when a gate-to-source voltage is applied. In another example, in an enhancement mode of a p-channel HEMT device, a valence band at the heterojunction exhibits a peak that is higher than and intersects the Fermi level, so that a two-dimensional hole gas (2DHG) is formed at the heterojunction when a gate-to-source voltage is applied. In some applications, a p-channel HEMT device is integrated with an n-channel HEMT device on the same substrate. However, for optimized performance, the p-channel HEMT device and the n-channel HEMT device have conflicting material concentrations and / or thicknesses of III-V family layers.

[0056] In some embodiments of the integrated HEMT device, a first undoped III-V group layer may be disposed on a substrate, and a barrier layer may be disposed on the first undoped III-V group layer. The barrier layer may include a III-V group material, such as, for example, indium aluminum gallium nitride. On an n-channel device region of the substrate, an n-channel device may be disposed, the n-channel device partially including a second undoped III-V group layer located on the barrier layer and a first doped III-V group layer located on the second undoped III-V group layer. In an enhancement mode, a desired 2DEG in the n-channel device may be formed along a first heterojunction at an interface between the barrier layer and the first undoped III-V group layer. On a p-channel device region of the substrate laterally adjacent to the n-channel device region, a p-channel device may be disposed, the p-channel device partially including a third undoped III-V group layer located on the barrier layer and a second doped III-V group layer located on the third undoped III-V group layer. In the enhancement mode, a desired 2DHG in the p-channel device may be formed along the second heterojunction at the interface between the third undoped III-V group layer and the barrier layer.

[0057] However, to optimize the performance of n-channel devices, the concentration of indium and / or aluminum of the barrier layer and the thickness of the barrier layer may be relatively low, thereby increasing the desired depletion of the 2DEG and facilitating good ohmic contact between the barrier layer and an overlying contact. Conversely, to optimize the performance of p-channel devices, the concentration of indium and / or aluminum of the barrier layer and the thickness of the barrier layer may be relatively high, thereby increasing the 2DHG density (i.e., lowering sheet resistivity) and preventing the 2DEG from leaking from the first heterojunction to the second heterojunction of the p-channel device. Thus, since the n-channel device shares the same barrier layer (with a single thickness and a single concentration of indium and / or aluminum) with the p-channel device, the overall performance of the integrated HEMT device is reduced. Additionally, the first doped III-V group layer of the n-channel device may be formed simultaneously with the second doped III-V group layer of the p-channel device, thereby reducing the cost and time associated with forming the integrated HEMT device. However, in order to maintain the enhancement mode of the n-channel device, the thickness of the first doped III-V family layer is relatively high. In addition, the threshold voltage of the n-channel device can be set by adjusting the thickness and / or doping concentration of the first doped III-V family layer. In addition, in order to maintain a good ohmic contact between the second doped III-V family layer and the overlying contact, the thickness of the second doped III-V family layer is relatively low. Therefore, since the first doped III-V family layer is formed simultaneously with the second doped III-V family layer, they may include the same thickness and / or doping concentration, thereby reducing the performance of the p-channel device and / or the n-channel device.

[0058] Various embodiments of the present disclosure provide a method for forming an integrated HEMT device and a corresponding structure, wherein the thickness and / or material concentration of the III-V layer is optimized for the performance of an n-channel device and a p-channel device disposed on the same substrate. In some embodiments, a lower undoped layer is formed on the substrate, a first barrier layer is formed on the lower undoped layer, and a first doped layer is formed on the first barrier layer. The first doped layer is selectively patterned to define the first doped layer of the n-channel device. Subsequently, a second barrier layer is selectively formed on the first barrier layer, an upper undoped layer is selectively formed on the second barrier layer, and a second doped layer is selectively formed on the upper undoped layer to define the film layer stack of the p-channel device. The thickness and / or material concentration of the first barrier layer and the first doped layer are formed for the optimized performance of the n-channel device. In addition, the thickness and / or material concentration of the second barrier layer and the second doped layer are formed for the optimized performance of the p-channel device. For example, the thickness of the first barrier layer is relatively low (e.g., less than the thickness of the second barrier layer), thereby increasing the depletion of the desired 2DEG and facilitating good ohmic contact for n-channel devices. In addition, the thickness of the second barrier layer is relatively high (e.g., greater than the thickness of the first barrier layer), thereby increasing the 2DHG density (i.e., reducing the sheet resistivity) and preventing the 2DEG from leaking to the heterojunction of the p-channel device. This, in turn, improves the performance of both n-channel devices and p-channel devices disposed on the same substrate.

[0059] Figure 1A A cross-sectional view of some embodiments of an integrated HEMT device 100 a having an n-channel device 108 and a p-channel device 110 is shown.

[0060] The integrated HEMT device 100a includes a first undoped layer 104 overlying a substrate 102. In some embodiments, the first undoped layer 104 may be, for example, or include a binary III-V semiconductor material, such as, for example, aluminum nitride, gallium nitride, indium nitride, etc. In other embodiments, the substrate 102 may include, for example, silicon, silicon carbide, sapphire, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or another suitable semiconductor substrate material. A first barrier layer 106 overlies the first undoped layer 104. In still other embodiments, the first barrier layer 106 may include a III-V semiconductor material, such as, for example, aluminum gallium nitride (e.g., InN). x Aly Ga 1-x-y N, wherein x and y are respectively in the range of 0 to 1) and / or has a thickness t1.

[0061] The n-channel device 108 is disposed in the n-channel device region 102a of the substrate 102. The n-channel device 108 may include a first doped layer 114 overlying the first barrier layer 106. A plurality of first contacts 112 are overlying the first barrier layer 106, and the first contacts 112 are spaced apart from each other by the first doped layer 114. In addition, a first gate electrode 116 is overlying the first doped layer 114, and the first gate electrode 116 is disposed in the dielectric structure 128. In some embodiments, the first doped layer 114 may include the same material as the first undoped layer 104. However, the first doped layer 114 includes a first doping type (e.g., p-type). In yet other embodiments, the first doped layer 114 may be, for example, or include a binary III-V semiconductor material, such as, for example, aluminum nitride, gallium nitride, indium nitride, etc., having a first doping type. Furthermore, in some embodiments, the thickness tn1 of the first doping layer 114 is greater than the thickness t1 of the first barrier layer 106 .

[0062] In the enhancement mode, a two-dimensional electron gas (2DEG) may be formed along a first heterojunction 111 at an interface between the first undoped layer 104 and the first barrier layer 106. In some embodiments, the first heterojunction 111 may be formed due to a band gap difference between the first undoped layer 104 and the first barrier layer 106. In some embodiments, the thickness t1 of the first barrier layer 106 is relatively thin and is conducive to the formation of a 2DEG along the first heterojunction 111. In some embodiments, the thickness t1 is, for example, less than about 35 nanometers, or another suitable value. In addition, the formation of a 2DEG along the first heterojunction 111 may depend on the concentration of multiple elements within the first barrier layer 106. For example, the concentration of indium and / or aluminum within the first barrier layer 106 may be relatively low to enhance the formation of a 2DEG along the first heterojunction 111. In addition, since the thickness t1 of the first barrier layer 106 and the concentration of indium and / or aluminum in the first barrier layer 106 are relatively low, a good contact (e.g., an ohmic contact) can be formed between the first contact 112 and the first barrier layer 106. In some embodiments, the thickness tn1 of the first doping layer 114 is relatively large, so that the flow and / or formation of the 2DEG along the first heterojunction 111 is increased. In addition, the thickness tn1 and / or the doping concentration of the first doping layer 114 can be adjusted to set the threshold voltage of the n-channel device 108. Therefore, in some embodiments, the thickness t1 of the first barrier layer 106, the concentration of each element in the first barrier layer 106, the thickness tn1 of the first doping layer 114, and / or the doping concentration of the first doping layer 114 can be designed so that the conduction band is below the Fermi level at the interface between the first barrier layer 106 and the first doping layer 114 to form a 2DEG, while forming a good contact (e.g., an ohmic contact) with the first contact 112. This may partially improve the performance of n-channel device 108 .

[0063] The p-channel device 110 is disposed in a p-channel device region 102b of the substrate 102, wherein the p-channel device region 102b is laterally adjacent to the n-channel device region 102a. The p-channel device 110 may include a second barrier layer 118 overlying the first barrier layer 106, a second undoped layer 120 overlying the second barrier layer 118, and a second doped layer 122 overlying the second undoped layer 120. In some embodiments, the second barrier layer 118 may include a III-V semiconductor material such as, for example, indium aluminum gallium nitride (e.g., InGaN). a Al b Ga 1-a-bN, where a and b are respectively in the range of 0 to 1) and / or has a thickness t2. In some embodiments, a+b=1, and a may be in the range of 0 to 1. In some embodiments, the thickness t1 of the first barrier layer 106 is less than the thickness t2 of the second barrier layer 118. In some further embodiments, the concentration of indium and aluminum in the second barrier layer 118 is greater than the concentration of indium and aluminum in the first barrier layer 106 (e.g., a is greater than x, b is greater than y, and / or a+b is greater than x+y). Therefore, in various embodiments, the concentration of multiple elements in the second barrier layer 118 is different from the concentration of multiple elements in the first barrier layer 106. In some embodiments, the second undoped layer 120 may, for example, be or include a binary III-V semiconductor material such as (for example) aluminum nitride, gallium nitride, indium nitride, etc. In some further embodiments, the second undoped layer 120 may include the same material as the first undoped layer 104 and / or the thickness of the second undoped layer 120 may be less than the thickness of the first undoped layer 104. In some embodiments, the second doped layer 122 may include the same material as the second undoped layer 120. However, the second doped layer 122 may include a second doping type (e.g., p-type). In yet other embodiments, the second doped layer 122 may be, for example, or include a binary III-V semiconductor material such as, for example, aluminum nitride, gallium nitride, indium nitride, etc. having a first doping type. In addition, in some embodiments, the thickness tp1 of the second doped layer 122 is less than the thickness t2 of the second barrier layer 118 and / or less than the thickness tn1 of the first doped layer 114. A plurality of second contacts 124 each overlie a section of the second doped layer 122 disposed on opposite sides of the second gate electrode 126. The second gate electrode 126 overlies the second undoped layer 120 and is disposed within the dielectric structure 128.

[0064] In the enhancement mode, a two-dimensional hole gas (2DHG) may be formed along the second heterojunction 117 at the interface between the second barrier layer 118 and the second undoped layer 120. In some embodiments, since the thickness t2 of the second barrier layer 118 is substantially thick, the valence band at the second heterojunction 117 exhibits a peak that is higher than the Fermi level and intersects the Fermi level, thereby forming the 2DHG. In addition, due to the concentration of multiple elements within the second barrier layer 118, the 2DHG may be formed along the second heterojunction 117. In addition, since the thickness t2 of the second barrier layer 118 and / or the concentration of each element within the second barrier layer 118 is substantially thick, the density of the 2DHG along the second heterojunction 117 increases (thereby reducing the sheet resistance) and the 2DEG from the first heterojunction 111 may be prevented from passing through the substantially thick second barrier layer 118 to reach the second heterojunction 117. In addition, since the thickness tp1 of the second doping layer 122 is substantially thin (e.g., less than the thickness tn1 of the first doping layer 114), a good contact (e.g., an ohmic contact) can be formed between the second contact 124 and the second doping layer 122. Therefore, in some embodiments, the p-channel device 110 can utilize the 2DHG along the second heterojunction 117 without being disturbed by the 2DEG formed along the first heterojunction 111, thereby improving the performance of the p-channel device 110. Therefore, in some embodiments, the n-channel device 108 and the p-channel device 110 can be integrated on the same substrate 102 while optimizing the performance of the two devices.

[0065] Figure 1B Show according to Figure 1A Cross-sectional views of some embodiments of the integrated HEMT device 100b of some alternative embodiments of the integrated HEMT device 100a are shown, wherein the second doped layer 122 extends continuously along the top surface of the second undoped layer 120. In addition, the second gate electrode 126 is disposed above the top surface of the second doped layer 122 and laterally between the second contacts 124. In such embodiments, the p-channel device 110 may be a depletion mode device, wherein a voltage applied between the second gate electrode 126 and the second contact 124 (i.e., a threshold voltage) causes the p-channel device 110 to be “turned off”.

[0066] Figure 2 A cross-sectional view of some embodiments of an integrated HEMT device 200 including an n-channel device 108 and a p-channel device 110 is shown.

[0067] A lower buffer layer 201 is disposed between the substrate 102 and the first undoped layer 104. In some embodiments, the lower buffer layer 201 includes a III-V semiconductor material, such as, for example, aluminum nitride, indium nitride, gallium nitride, aluminum gallium nitride, any combination of the foregoing materials, and the like. In yet other embodiments, the lower buffer layer 201 may include a single layer including a III-V semiconductor material or a multilayer stack each including a III-V semiconductor material (each layer in the multilayer stack may include a different III-V semiconductor material). The lower buffer layer 201 may, for example, be used to compensate for differences in lattice constant, crystal structure, thermal expansion coefficient, or any combination of the foregoing between the substrate 102 and the overlying layers (e.g., the first undoped layer 104, the first barrier layer 106, the second barrier layer 118, etc.).

[0068] The integrated HEMT device 200 includes a plurality of conductive vias 202 embedded in a dielectric structure 128. In some embodiments, the dielectric structure 128 may be, for example, or include silicon dioxide, a low-k dielectric material, an extreme low-k dielectric material, or another suitable dielectric material. In other embodiments, the conductive vias 202 may be, for example, or include titanium nitride, tantalum nitride, copper, tungsten, aluminum, another suitable conductive material, or any combination of the foregoing materials. Each of the first contact 112, the second contact 124, the first gate electrode 116, and the second gate electrode 126 may be electrically coupled to one of the conductive vias 202. In other embodiments, the p-channel device 110 of the integrated HEMT device 200 may be configured as Figure 1AThe p-channel device 110 of the integrated HEMT device 100a of the embodiment of the present invention is connected to the p-channel device 110 of the integrated HEMT device 100a. The via 202 can be coupled to a voltage source to control the operation (e.g., "turning on" and / or "turning off") of the n-channel device 108 and the p-channel device 110. In some embodiments, a voltage of up to 20 volts can be applied across the n-channel device 108 and / or the p-channel device 110 through the via 202. In other embodiments, the voltage bias applied to the n-channel device 108 and the p-channel device 110 can be in the range of about 1 volt to 12 volts. In yet other embodiments, the first gate electrode 116 can be biased away from the first doped layer 114 (not shown) so that the dielectric structure 128 is disposed between the bottom surface of the first gate electrode 116 and the top surface of the first doped layer 114. In some other embodiments, an isolation structure 204 may be disposed in the first barrier layer 106 and the first undoped layer 104 between the n-channel device 108 and the p-channel device 110. The isolation structure 204 is configured to increase the isolation between the device disposed in the n-channel device region 102a and the device disposed in the p-channel device region 102b. The isolation structure 204 may be configured, for example, as a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or another suitable isolation structure. In some other embodiments, the isolation structure 204 may be, for example, or include silicon dioxide, silicon nitride, silicon carbide, another suitable dielectric material, or any combination of the foregoing materials.

[0069] Figure 3 Show Figure 1A , Figure 1B or Figure 2 300 of some embodiments of an n-channel device region 102a of FIG. 1 , wherein a plurality of n-channel devices 302a to 302n are disposed within the n-channel device region 102a. In some embodiments, the n-channel devices 302a to 302n may each be configured as Figure 1A , Figure 1B or Figure 2 An n-channel device 108 is provided.

[0070] In various embodiments, the n-channel device region 102a may include any number of n-channel devices 302a to 302n. In some embodiments, the isolation structure 204 continuously surrounds each n-channel device 302a to 302n in the lateral direction to enhance the isolation between adjacent devices. In addition, the thickness tn1 to the thickness tnN of the first doping layer 114 of each n-channel device 302a to 302n and / or the doping concentration of the first doping layer 114 of each n-channel device 302a to 302n may be different from each other. The threshold voltage of each n-channel device 302a to 302n may be set by setting the thickness and / or doping concentration of the first doping layer 114 of each n-channel device 302a to 302n. In various embodiments, the n-channel devices 302a to 302n may be configured as enhancement mode devices or depletion mode devices. In some embodiments, a threshold voltage may be applied to each n-channel device 302a to 302n to control the operation (e.g., "on" and / or "off") of the n-channel device 302a to 302n. In some embodiments, for example, as the thickness of the first doping layer 114 of the n-channel device increases, the threshold voltage of the n-channel device increases. In yet other embodiments, as the doping concentration of the first doping type (e.g., p-type) in the first doping layer 114 increases, the threshold voltage of the n-channel device increases.

[0071] In various embodiments, the thickness tn1 of the first doped layer 114 of the n-channel device (also referred to as the first n-channel device) 302a is less than the thickness tn2 of the first doped layer 114 of the n-channel device (also referred to as the second n-channel device) 302b, and the thickness tn2 of the first doped layer 114 of the second n-channel device 302b is less than the thickness tnN of the first doped layer 114 of the n-channel device (also referred to as the nth n-channel device) 302n. In some further embodiments, the first doping concentration of the first doped layer 114 of the first n-channel device 302a is less than the second doping concentration of the first doped layer 114 of the second n-channel device 302b, and the second doping concentration of the first doped layer 114 of the second n-channel device 302b is less than the third doping concentration of the first doped layer 114 of the nth n-channel device 302n. Therefore, in some embodiments, the first threshold voltage of the first n-channel device 302a is less than the second threshold voltage of the second n-channel device 302b, and the second threshold voltage of the second n-channel device 302b is less than the third threshold voltage of the n-th n-channel device 302n. Therefore, in some embodiments, the thickness and doping concentration of the first doping layer 114 of each n-channel device 302a to 302n can be designed to set the threshold voltage of each n-channel device 302a to 302n so that the threshold voltages are different from each other.

[0072] Figure 4 Show Figure 1A , Figure 1B or Figure 2 400 of some embodiments of a p-channel device region 102b, wherein a plurality of p-channel devices 402a to 402m are disposed within the p-channel device region 102b. In some embodiments, the p-channel devices 402a to 402m may each be configured as Figure 1A , Figure 1B or Figure 2 A p-channel device 110 is provided.

[0073] In some embodiments, the p-channel device region 102b may include any number of p-channel devices 402a to 402m. In some embodiments, the thickness tp1 to tpM of the second barrier layer 118 of each p-channel device 402a to 402m and / or the concentration of multiple elements in the second barrier layer 118 of each p-channel device 402a to 402m may be different from each other. The threshold voltage of each p-channel device 402a to 402m may be set by adjusting the thickness of the second barrier layer 118 and / or the concentration of the elements of each p-channel device 402a to 402m.

[0074] In some embodiments, the second barrier layer 118 of the p-channel device (also referred to as the first p-channel device) 402a may include a III-V semiconductor material such as, for example, indium aluminum gallium nitride (eg, InGaN). a Al b Ga 1-a-b N, where a and b are in the range of 0 to 1, respectively), which has a first concentration of each element in the above III-V semiconductor material. In some other embodiments, the second barrier layer 118 of the p-channel device (also referred to as the second p-channel device) 402b may include a III-V semiconductor material (e.g., In c Al d Ga 1-c-d N, where c and d are in the range of 0 to 1, respectively), which has a second concentration of each element in the above III-V semiconductor material. In some other embodiments, the second barrier layer 118 of the p-channel device (also referred to as the m-th p-channel device) 402m may include a III-V semiconductor material (e.g., In e Al f Ga 1-e-f N, where e and f are in the range of 0 to 1, respectively), having a third concentration of each element in the above III-V semiconductor material. In various embodiments, the first concentration is different from the second concentration and / or the third concentration, and the second concentration is different from the first concentration and / or the third concentration (for example, a≠c≠e and / or b≠d≠f). In addition, in some embodiments, as the concentration of indium / aluminum in the second barrier layer 118 increases, the threshold voltage of the p-channel device decreases.

[0075] In addition, in various embodiments, as the thickness tp1 to the thickness tpM of the second barrier layer 118 decreases, the 2DHG carrier density along the second heterojunction 117 decreases, thereby increasing the threshold voltage of the p-channel device. In some embodiments, the first threshold voltage of the first p-channel device 402a is greater than the second threshold voltage of the second p-channel device 402b, and the second threshold voltage of the second p-channel device 402b is greater than the third threshold voltage of the m-th p-channel device 402m. Therefore, in some embodiments, the concentration of each element of the second barrier layer 118 of each p-channel device 402a to 402m and the thickness of the second barrier layer 118 can be designed to set the threshold voltage of each p-channel device 402a to 402m so that the threshold voltages are different from each other. In some embodiments, as the thickness tp1-M of the second barrier layer 118 increases, the isolation between the first heterojunction 111 and the second heterojunction 117 is increased.

[0076] Figure 5 A cross-sectional view of some embodiments of an integrated HEMT device 500 is shown having an n-channel device region 102a laterally adjacent to a p-channel device region 102b.

[0077] In some embodiments, the n-channel device region 102a includes a plurality of n-channel devices 302a to 302n. In some embodiments, the plurality of n-channel devices 302a to 302n are as follows: Figure 3 As shown and described in the above, the n-channel devices 302a to 302n can each have a different threshold voltage from each other. In some other embodiments, the p-channel device region 102b includes a plurality of p-channel devices 402a to 402m. In some embodiments, the plurality of p-channel devices 402a to 402m are as follows: Figure 4 As shown and described in FIG. 4 , the p-channel devices 402 a - 402 m may each have a different threshold voltage from one another.

[0078] Figures 6 to 11 Cross-sectional views 600 through 1100 illustrate some embodiments of methods of forming an integrated HEMT device having an n-channel device disposed laterally adjacent to a p-channel device according to the present disclosure. Figures 6 to 11 The cross-sectional views 600 to 1100 shown in FIG. 1 are described with reference to one method, but it should be understood that Figures 6 to 11 The structures shown in are not limited to the described methods, but can be independently separated from the described methods. Figures 6 to 11 It is described as a series of actions, but it should be understood that these actions are not limited to the order of actions that can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0079] like Figure 6 As shown in the cross-sectional view 600 of , a substrate 102 is provided, and a first undoped layer 104 is deposited on the substrate 102. In some embodiments, the substrate 102 includes silicon, sapphire, or silicon carbide. In addition, the substrate 102 may, for example, include a first doping type (e.g., p-type). In some further embodiments, the first undoped layer 104 may, for example, be or include a III-V semiconductor material, or a III-N semiconductor material (e.g., for example, aluminum nitride, indium nitride, gallium nitride, etc.). A first barrier layer 106 with a thickness t1 is deposited on the first undoped layer 104. In some embodiments, the first barrier layer 106 may, for example, be or include a III-V semiconductor material, such as, for example, indium aluminum gallium nitride (e.g., InN). x Al y Ga 1-x-y N, where x and y are respectively in the range of 0 to 1). In some embodiments, a first doped film 602 is formed on the first barrier layer 106. In some other embodiments, the first doped film 602 may include the same material as the first undoped layer 104. However, the first doped film 602 includes a first doping type (e.g., p-type). In some other embodiments, the first doped film 602 may be, for example, or include a III-V semiconductor material, such as (for example) aluminum nitride, gallium nitride, indium nitride, etc. with a first doping type. In addition, in some embodiments, the thickness tn1 of the first doped film 602 is greater than the thickness t1 of the first barrier layer 106.

[0080] In some embodiments, the first undoped layer 104, the first barrier layer 106 and / or the first doped film 602 may be deposited by an epitaxial process and / or another form of deposition process (e.g., chemical vapor deposition (CVD), metal organic chemical vapor deposition (MO-CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, electron beam / thermal evaporation, etc.). In some other embodiments, forming the first doped film 602 may include performing a selective ion implantation process, in which a dopant (e.g., boron) is selectively implanted into the first doped film 602, so that the first doped film 602 includes a first doping type (p-type).

[0081] like Figure 7 As shown in the cross-sectional view 700 of FIG. 7 , the first doping film 602 ( Figure 6 ) to perform an etching process, thereby defining a first doping layer 114 in the n-channel device region 102a of the substrate 102. In some embodiments, a thickness tn1 of the first doping layer 114 is greater than a thickness t1 of the first barrier layer 106. In some other embodiments, the etching process includes: Figure 6 ) to form a masking layer; the first doping film 602 ( Figure 6 ) is exposed to one or more etchants to define the first doped layer 114; and a removal process is performed to remove the shielding layer. In some embodiments, the etching process is performed in the following manner: at least a portion of the first barrier layer 106 is removed in an area laterally offset from the first doped layer 114. In such an embodiment, the thickness t1 of the first barrier layer 106 directly below the first doped layer 114 is greater than the thickness of multiple segments of the first barrier layer 106 laterally offset from the first doped layer 114. In some embodiments, the etching process may include performing wet etching and / or dry etching.

[0082] In some further embodiments, another shielding layer (not shown) may be formed on the first barrier layer 106 and the first doping layer 114. The other shielding layer includes an opening that exposes the upper surface of the first barrier layer 106. The opening is laterally offset from the first doping layer 114 and is laterally disposed in the n-channel device region 102a. Subsequently, a selective epitaxial growth process may be performed to selectively deposit another doping layer (not shown) in the opening of the other shielding layer, so that the other doping layer has a greater thickness and / or a greater doping concentration than the first doping layer 114. In such an embodiment, the first doping layer 114 may be adjacent to the first n-channel device region 102a ( Figure 3 ) corresponds to the first doped layer 114, and the other doped layer may correspond to the second n-channel device 302b ( Figure 3 ) corresponds to the first doped layer 114 of the n-channel device region 102a. In some other embodiments, the aforementioned process may be repeated as many times as needed to form any number of doped layers (i.e., any number of n-channel devices) in the n-channel device region 102a. The selective epitaxial growth process may be an epitaxial process or another form of deposition process (e.g., chemical vapor deposition (CVD), metal organic chemical vapor deposition (MO-CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, electron beam / thermal evaporation, etc.).

[0083] like Figure 8 As shown in the cross-sectional view 800 of FIG. 8 , a shielding layer 802 is formed over the n-channel device region 102a of the substrate 102 and extends over at least a portion of the p-channel device region 102b of the substrate 102. Since the n-channel device region 102a and the p-channel device region 102b are part of the same substrate 102, the n-channel device region 102a of the substrate 102 may be laterally located beside the p-channel device region 102b of the substrate 102 and continuously connected to the p-channel device region 102b of the substrate 102. The shielding layer 802 includes opposing sidewalls within the p-channel device region 102b, the opposing sidewalls defining the opening 804 and exposing the upper surface of the first barrier layer 106. In some embodiments, the shielding layer 802 may be, for example, or include a photosensitive material, a hard mask material, silicon nitride, silicon carbide, another suitable mask material, or any combination of the foregoing materials.

[0084] like Fig. 9 As shown in the cross-sectional view 900 of FIG. 8 , in the opening 804 ( Figure 8) is formed on the first barrier layer 106 in the film layer stack 902. In some embodiments, the film layer stack 902 includes a second barrier layer 118 directly in contact with the first barrier layer 106, a second undoped layer 120 in contact with the second barrier layer 118, and a second doped layer 122 in contact with the second undoped layer 120. In some other embodiments, the second barrier layer 118, the second undoped layer 120, and / or the second doped layer 122 can each be formed by a selective epitaxial growth process. The selective epitaxial growth process can be an epitaxial process or another form of deposition process (e.g., CVD, MO-CVD, PE-CVD, ALD, PVD, sputtering, electron beam / thermal evaporation, etc.). The selective epitaxial growth process can be selective to the first barrier layer 106 and the layers in the film layer stack 902, for example, because the first barrier layer 106 can be a crystalline material, the second barrier layer 118 directly contacts the first barrier layer 106. Since the shielding layer 802 is an amorphous material, the selective epitaxial growth process can prevent the layers within the film layer stack 902 from being formed on the shielding layer 802 .

[0085] In some embodiments, the second barrier layer 118 may include a III-V semiconductor material such as, for example, indium aluminum gallium nitride (eg, InGaN). a Al b Ga 1-a-bN, where a and b are in the range of 0 to 1, respectively) and / or have a thickness t2. In some embodiments, the thickness t1 of the first barrier layer 106 is less than the thickness t2 of the second barrier layer 118. In some further embodiments, the concentration of indium and aluminum in the second barrier layer 118 is greater than the concentration of indium and aluminum in the first barrier layer 106 (e.g., a is greater than x, b is greater than y, and / or a+b is greater than x+y). Therefore, in various embodiments, the concentration of the element in the second barrier layer 118 is different from the concentration of the element in the first barrier layer 106. In some embodiments, the second undoped layer 120 may be, for example, or include a III-V semiconductor material, such as, for example, aluminum nitride, gallium nitride, indium nitride, etc. In some further embodiments, the second undoped layer 120 may include the same material as the first undoped layer 104. In some embodiments, the second doped layer 122 may include the same material as the second undoped layer 120. However, the second doped layer 122 may include a second doping type (e.g., p-type). In some further embodiments, the second doped layer 122 may be, for example, or include a III-V semiconductor material, such as, for example, aluminum nitride, gallium nitride, indium nitride, etc., having a first doping type. In addition, in some embodiments, the thickness tp1 of the second doped layer 122 is less than the thickness t2 of the second barrier layer 118 and / or less than the thickness tn1 of the first doped layer 114. In some further embodiments, a removal process may be performed to remove the shielding layer 802 (not shown). In some further embodiments, forming the second doped layer 122 may include performing a selective ion implantation process, wherein a dopant (e.g., boron) is selectively implanted into the second doped layer 122, so that the second doped layer 122 includes the first doping type (p-type).

[0086] In still other embodiments, after removing the shielding layer 802, a second shielding layer (not shown) may be formed over the n-channel device region 102a and the film layer stack 902. The second shielding layer includes an opening (not shown) that exposes the upper surface of the first barrier layer 106. The opening is laterally offset from the film layer stack 902 and is laterally disposed within the p-channel device region 102b. Subsequently, another film layer stack (not shown) may be formed within the opening of the second shielding layer by one or more selective epitaxial growth processes, such that the second barrier layer (not shown) of the another film layer stack has a greater thickness and / or a different element concentration (e.g., a higher concentration of indium and / or aluminum) than the second barrier layer 118 of the film layer stack 902. In some embodiments, the film layer stack 902 may be Figure 4 The first p-channel device 402a corresponds to the layer of the first p-channel device 402a, and the other film layer stack may correspond to the first p-channel device 402a. Figure 4 In some other embodiments, the above process may be repeated multiple times as needed to form any number of film layer stacks (ie, any number of p-channel devices) in the p-channel device region 102b.

[0087] like Fig.10 As shown in the cross-sectional view 1000 of , a first contact 112 is formed on the first barrier layer 106, and a second contact 124 is formed on the second doped layer 122. In some embodiments, a process for forming the first contact 112 and the second contact 124 may include: depositing (e.g., by CVD, ALD, physical vapor deposition (PVD), sputtering, electroless plating, electroplating, or another suitable deposition or growth process) a conductive layer (e.g., including titanium, aluminum, copper, tungsten, another suitable conductive material, or any combination of the foregoing materials) on the n-channel device region 102a and the p-channel device region 102b; forming a masking layer (not shown) on the conductive layer; patterning the conductive layer according to the masking layer to define the first contact 112 and the second contact 124; and performing a removal process to remove the masking layer.

[0088] In addition, if Fig.10 As shown in the cross-sectional view 1000 of , a first gate electrode 116 is formed on the first doped layer 114 and a second gate electrode 126 is formed on the second doped layer 122, thereby defining the n-channel device 108 and the p-channel device 110, respectively. In some embodiments, a process for forming the first gate electrode 116 and the second gate electrode 126 may include: forming a dielectric layer 1002 on the n-channel device region 102a and the p-channel device region 102b; patterning the dielectric layer 1002 to define a plurality of gate electrode openings on the first doped layer 114 and the second doped layer 122; depositing a gate layer (e.g., including titanium nitride, nickel, tungsten, titanium, platinum, another suitable conductive material, or any combination of the foregoing) on ​​the dielectric layer 1002 so that the gate layer fills the gate electrode openings; and patterning the gate layer to define the first gate electrode 116 and the second gate electrode 126.

[0089] like Fig.11As shown in the cross-sectional view 1100 of , a dielectric structure 128 is formed over the n-channel device 108 and the p-channel device 110. Subsequently, a plurality of vias 202 are formed within the dielectric structure 128 and over the first contact 112, the second contact 124, the first gate electrode 116, and the second gate electrode 126. In some embodiments, the dielectric structure 128 may be deposited, for example, by CVD, PVD, ALD, or another suitable growth or deposition process. In yet other embodiments, the dielectric structure 128 may be, for example, or include silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, or another suitable dielectric material. In yet other embodiments, the vias 202 may be formed by a single damascene process. Additionally, in various embodiments, the vias 202 may be, for example, or include copper, aluminum, tungsten, titanium nitride, tantalum nitride, another suitable conductive material, or any combination of the foregoing materials. In yet other embodiments, the dielectric layer 1002 ( Fig.10 ) may be at least a portion of the dielectric structure 128.

[0090] Fig.12 A flow chart illustrating some embodiments of a method 1200 of forming an integrated HEMT device on the same substrate and including an n-channel device and a p-channel device.

[0091] Although method 1200 is shown and described as a series of actions or events below, it should be understood that the order in which these actions or events are shown should not be interpreted as having a limiting meaning. For example, some actions can occur in different orders, and / or can occur simultaneously with other actions or events other than the actions or events shown and / or described in this article. In addition, all the actions shown may not be needed when implementing one or more aspects or embodiments described herein. In addition, one or more actions in the actions depicted herein can be implemented in one or more separate actions and / or stages.

[0092] At act 1202, a first undoped layer is deposited over a substrate.

[0093] At act 1204 , a first barrier layer is deposited over the first undoped layer.

[0094] At act 1206, a first doped film is deposited over the first barrier layer. Figure 6 Cross-sectional view 600 of some embodiments corresponding to act 1202 , act 1204 , and act 1206 is shown.

[0095] At act 1208, the first doped film is patterned to define a first doped layer over the first barrier layer. The first doped layer is laterally disposed within the n-channel device region of the substrate. Figure 7Cross-sectional view 700 of some embodiments corresponding to act 1208 is shown.

[0096] At act 1210, a shielding layer is formed over an n-channel device region, wherein the shielding layer includes a plurality of sidewalls defining an opening within a p-channel device region of a substrate. The p-channel device region is laterally adjacent to the n-channel device region. Figure 8 Cross-sectional view 800 of some embodiments corresponding to act 1210 is shown.

[0097] At action 1212, a film layer stack is selectively grown in the opening. The film layer stack includes a second barrier layer, a second doped layer, and a second undoped layer between the second barrier layer and the second doped layer. The second barrier layer contacts the first barrier layer. Fig. 9 Cross-sectional view 900 of some embodiments corresponding to act 1212 is shown.

[0098] At act 1214 , a plurality of first contacts are formed on the first barrier layer.

[0099] At act 1216 , a plurality of second contacts are formed on the second doped layer.

[0100] At act 1218 , a first gate electrode is formed on the first doped layer and is laterally spaced apart from the first contact.

[0101] At act 1220 , a second gate electrode is formed over the second doped layer and is laterally spaced apart from the second contact. Fig.10 Cross-sectional view 1000 of some embodiments corresponding to act 1214 , act 1216 , act 1218 , and act 1220 is shown.

[0102] Thus, in some embodiments, the present disclosure is directed to an integrated HEMT device including an n-channel device and a p-channel device on the same substrate, wherein the n-channel device includes a first barrier layer and the p-channel device includes a second barrier layer that is thicker than the first barrier layer.

[0103] In some embodiments, the present disclosure provides an integrated chip, which includes: a first undoped layer overlying a substrate; a first barrier layer overlying the first undoped layer, wherein the first barrier layer has a first thickness; a first doped layer overlying the first barrier layer and laterally disposed in an n-channel device region of the substrate; a second barrier layer overlying the first barrier layer and disposed in a p-channel device region laterally adjacent to the n-channel device region, wherein the second barrier layer has a second thickness greater than the first thickness; a second undoped layer overlying the second barrier layer; and a second doped layer overlying the second undoped layer, wherein the second undoped layer and the second doped layer are disposed in the p-channel device region.

[0104] In some embodiments, in the integrated chip, the second doped layer is thinner than the first doped layer. In some embodiments, in the integrated chip, the first barrier layer and the second barrier layer comprise the same III-V semiconductor material, wherein the first barrier layer comprises a first concentration of multiple elements in the III-V semiconductor material and the second barrier layer comprises a second concentration of multiple elements in the III-V semiconductor material, and the second concentration is different from the first concentration. In some embodiments, in the integrated chip, the III-V semiconductor material is indium aluminum gallium nitride, wherein the concentration of indium and / or aluminum in the first barrier layer is less than the concentration of indium and / or aluminum in the second barrier layer. In some embodiments, in the integrated chip, the second barrier layer directly contacts the first barrier layer. In some embodiments, in the integrated chip, the second undoped layer is thinner than the first undoped layer. In some embodiments, the integrated chip further comprises a first gate electrode overlying the first doped layer; and a second gate electrode overlying the second undoped layer. In some embodiments, in the integrated chip, the second doping layer includes a first segment and a second segment disposed on opposite sides of the second gate electrode, wherein a bottom surface of the second gate electrode is disposed below a top surface of the second doping layer.

[0105] In some embodiments, the present disclosure provides an integrated chip, the integrated chip comprising: a substrate having an n-channel device region located laterally next to a p-channel device region; a first undoped layer overlying the substrate; a first n-channel device disposed in the n-channel device region, wherein the first n-channel device comprises a first barrier layer, a first doped layer, and a first gate electrode overlying the first doped layer, wherein the first doped layer contacts the first barrier layer; a first p-channel device disposed in the p-channel device region, wherein the first p-channel device comprises a second barrier layer, a second undoped layer, a second doped layer, and a second gate electrode overlying the second doped layer, wherein the second barrier layer directly contacts the first barrier layer, and wherein the second undoped layer is disposed between the second barrier layer and the second doped layer; and wherein the first barrier layer comprises a III-V semiconductor material having a first concentration of multiple elements and the second barrier layer comprises the III-V semiconductor material having a second concentration of multiple elements, the second concentration of the multiple elements being different from the first concentration of the multiple elements.

[0106] In some embodiments, in the integrated chip, the first barrier layer is thinner than the second barrier layer. In some embodiments, in the integrated chip, the first undoped layer and the second undoped layer comprise binary III-V semiconductor materials, wherein the first doped layer and the second doped layer respectively comprise the binary III-V semiconductor materials having a first doping type. In some embodiments, in the integrated chip, a second n-channel device is further included, which is disposed in the n-channel device region, wherein the second n-channel device comprises a section of the first barrier layer, a third doped layer, and a third gate electrode overlying the third doped layer, wherein the third doped layer contacts the first barrier layer and is laterally offset from the first doped layer at a non-zero distance. In some embodiments, in the integrated chip, the first doped layer comprises a III-V semiconductor material having a first doping type and a first doping concentration, wherein the third doped layer comprises the III-V semiconductor material having the first doping type and a second doping concentration, wherein the first doping concentration is different from the second doping concentration. In some embodiments, in the integrated chip, the third doped layer is thicker than the first doped layer. In some embodiments, in the integrated chip, a second p-channel device is further included, which is arranged in the p-channel device area, wherein the second p-channel device includes a third barrier layer, a third undoped layer, a fourth doped layer and a fourth gate electrode overlying the fourth doped layer, wherein the third barrier layer directly contacts the first barrier layer, and wherein the third undoped layer is arranged between the third barrier layer and the fourth doped layer. In some embodiments, in the integrated chip, the second barrier layer includes a III-V semiconductor material having a first concentration of multiple elements and the third barrier layer includes the III-V semiconductor material having a second concentration of multiple elements, and the second concentration of the multiple elements is different from the first concentration of the multiple elements. In some embodiments, in the integrated chip, the third barrier layer is thicker than the second barrier layer.

[0107] In some embodiments, the present disclosure provides a method for forming an integrated chip, the method comprising: depositing a first undoped layer on a substrate, wherein the substrate comprises an n-channel device region laterally adjacent to a p-channel device region; depositing a first barrier layer on the first undoped layer; depositing a first doped film on the first barrier layer; performing a first patterning process on the first doped film to define a first doped layer in the n-channel device region, wherein the first patterning process removes the first doped film from the p-channel device region; selectively forming a film layer stack on the first barrier layer and in the p-channel device region, wherein the film layer stack comprises a second barrier layer, a second undoped layer and a second doped layer; forming a first gate electrode on the first doped layer; and forming a second gate electrode on the second undoped layer.

[0108] In some embodiments, in the method for forming an integrated chip, the selectively forming the film layer stack includes forming a shielding layer on the first barrier layer, so that the shielding layer includes opposite sidewalls, and the opposite sidewalls define an opening in the p-channel device region; and performing one or more selective epitaxial growth processes to form the film layer stack in the opening, so that the second barrier layer directly contacts the first barrier layer. In some embodiments, the method for forming an integrated chip also includes forming a first group of multiple contacts on the first barrier layer, and the first group of multiple contacts are spaced apart from the first gate electrode in the lateral direction; and forming a second group of multiple contacts on the second doped layer, and the second group of multiple contacts are spaced apart from the second gate electrode in the lateral direction.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, comprising: a first undoped layer overlying the substrate; A first barrier layer overlying the first undoped layer, wherein the first barrier layer has a first thickness; a first doping layer, overlying the first barrier layer and laterally disposed in an n-channel device region of the substrate; a second barrier layer overlying the first barrier layer and disposed in a p-channel device region laterally adjacent to the n-channel device region, wherein the second barrier layer has a second thickness greater than the first thickness; a second undoped layer, covering the second barrier layer; as well as A second doped layer is overlying the second undoped layer, wherein the second undoped layer and the second doped layer are arranged in the p-channel device region, and wherein an outer sidewall of the second barrier layer is aligned with an outer sidewall of the second undoped layer and an outer sidewall of the second doped layer. 2 . The integrated chip according to claim 1 , wherein the second doped layer is thinner than the first doped layer.

3. An integrated chip according to claim 1, wherein the first barrier layer and the second barrier layer contain the same III-V semiconductor material, wherein the first barrier layer contains a first concentration of multiple elements in the III-V semiconductor material and the second barrier layer contains a second concentration of multiple elements in the III-V semiconductor material, and the second concentration is different from the first concentration. 4 . The integrated chip according to claim 3 , wherein the III-V semiconductor material is indium aluminum gallium nitride, wherein the concentration of indium and / or aluminum in the first barrier layer is less than the concentration of indium and / or aluminum in the second barrier layer. 5 . The integrated chip according to claim 1 , wherein the second barrier layer directly contacts the first barrier layer. The integrated chip according to claim 1 , wherein the second undoped layer is thinner than the first undoped layer.

7. The integrated chip according to claim 1, further comprising: a first gate electrode, overlying the first doped layer; as well as A second gate electrode is overlying the second undoped layer. 8 . The integrated chip according to claim 7 , wherein the second doped layer comprises a first segment and a second segment disposed on opposite sides of the second gate electrode, wherein a bottom surface of the second gate electrode is disposed below a top surface of the second doped layer.

9. An integrated chip comprising: A substrate having an n-channel device region laterally adjacent to the p-channel device region; a first undoped layer overlying the substrate; a first n-channel device disposed in the n-channel device region, wherein the first n-channel device comprises a first barrier layer, a first doping layer, and a first gate electrode overlying the first doping layer, wherein the first doping layer contacts the first barrier layer; a first p-channel device disposed in the p-channel device region, wherein the first p-channel device comprises a second barrier layer, a second undoped layer, a second doped layer, and a second gate electrode overlying the second doped layer, wherein the second barrier layer directly contacts the first barrier layer, wherein the second undoped layer is disposed between the second barrier layer and the second doped layer, and wherein an outer sidewall of the second barrier layer is aligned with an outer sidewall of the second undoped layer and an outer sidewall of the second doped layer; and The first barrier layer includes a III-V semiconductor material having a first concentration of multiple elements and the second barrier layer includes the III-V semiconductor material having a second concentration of multiple elements, and the second concentration of the multiple elements is different from the first concentration of the multiple elements. 10 . The integrated chip according to claim 9 , wherein the first barrier layer is thinner than the second barrier layer.

11. The integrated chip of claim 9, wherein the first undoped layer and the second undoped layer comprise binary III-V semiconductor materials, wherein the first doped layer and the second doped layer respectively comprise the binary III-V semiconductor materials having a first doping type.

12. The integrated chip according to claim 9, further comprising: A second n-channel device is disposed in the n-channel device region, wherein the second n-channel device comprises a segment of the first barrier layer, a third doping layer, and a third gate electrode overlying the third doping layer, wherein the third doping layer contacts the first barrier layer and is laterally offset from the first doping layer by a non-zero distance.

13. An integrated chip according to claim 12, wherein the first doping layer comprises a III-V semiconductor material having a first doping type and a first doping concentration, wherein the third doping layer comprises the III-V semiconductor material having the first doping type and a second doping concentration, wherein the first doping concentration is different from the second doping concentration. The integrated chip according to claim 13 , wherein the third doped layer is thicker than the first doped layer.

15. The integrated chip according to claim 9, further comprising: A second p-channel device is disposed in the p-channel device region, wherein the second p-channel device comprises a third barrier layer, a third undoped layer, a fourth doped layer, and a fourth gate electrode overlying the fourth doped layer, wherein the third barrier layer directly contacts the first barrier layer, and wherein the third undoped layer is disposed between the third barrier layer and the fourth doped layer.

16. An integrated chip according to claim 15, wherein the second barrier layer comprises a III-V semiconductor material having a first concentration of multiple elements and the third barrier layer comprises the III-V semiconductor material having a second concentration of multiple elements, and the second concentration of the multiple elements is different from the first concentration of the multiple elements. 17 . The integrated chip according to claim 16 , wherein the third barrier layer is thicker than the second barrier layer.

18. A method for forming an integrated chip, comprising: depositing a first undoped layer over a substrate, wherein the substrate includes an n-channel device region laterally adjacent to a p-channel device region; depositing a first barrier layer on the first undoped layer; depositing a first doped film on the first barrier layer; performing a first patterning process on the first doped film to define a first doped layer in the n-channel device region, wherein the first patterning process removes the first doped film from the p-channel device region; selectively forming a film layer stack on the first barrier layer and in the p-channel device region, wherein the film layer stack includes a second barrier layer, a second undoped layer, and a second doped layer; forming a first gate electrode on the first doped layer; as well as A second gate electrode is formed on the second undoped layer.

19. The method of claim 18, wherein selectively forming the film layer stack comprises: forming a shielding layer over the first barrier layer such that the shielding layer includes opposing sidewalls defining an opening in the p-channel device region; as well as One or more selective epitaxial growth processes are performed to form the film layer stack in the opening so that the second barrier layer directly contacts the first barrier layer.

20. The method of claim 18, further comprising: forming a first group of multiple contacts on the first barrier layer, wherein the first group of multiple contacts are laterally spaced apart from the first gate electrode; as well as A second set of multiple contacts is formed on the second doped layer, and the second set of multiple contacts is laterally spaced apart from the second gate electrode.

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