Magnetic memory device

Abstract

A magnetic memory device includes a lower contact plug located on a substrate and a data storage structure located on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have first and second thicknesses, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0012067, filed on January 31, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a magnetic memory device including a magnetic tunnel junction and a method for manufacturing the same. Background Technology

[0004] As electronic products trend towards higher speeds and / or lower power consumption, there is an increasing need for higher speeds and lower operating voltages for semiconductor memory devices integrated into these products. To meet these demands, magnetic memory devices have been developed as semiconductor memory devices. Because magnetic memory devices can operate at high speeds and possess non-volatility characteristics, they have attracted considerable attention as a next-generation semiconductor memory device.

[0005] Typically, a magnetic memory device may include a magnetic tunnel junction pattern (MTJ). A MTJ includes two magnetic structures and an insulating layer interposed between them. The resistance of the MTJ varies depending on the magnetization directions of the two magnetic structures. For example, the MTJ may have a high-resistance state when the magnetization directions of the two magnetic structures are antiparallel, and a low-resistance state when the magnetization directions are parallel. The magnetic memory device can use the resistance difference between the high-resistance and low-resistance states of the MTJ to write and read data.

[0006] With the significant advancements in the electronics industry, the demand for higher integration and / or lower power consumption in magnetic memory devices is likely to continue to increase. Summary of the Invention

[0007] Some exemplary embodiments of the present invention provide a magnetic memory device having a structure configured to reduce or minimize process defects and a method for manufacturing the same.

[0008] Some exemplary embodiments of the present invention provide a magnetic memory device with improved characteristics and a method for manufacturing the same.

[0009] According to some exemplary embodiments of the present invention, a magnetic memory device may include: a lower contact plug located on a substrate; and a data storage structure located on the lower contact plug. The data storage structure may include a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure may each have a first thickness and a second thickness, respectively, in a first direction perpendicular to the top surface of the substrate. The first thickness of the lower contact plug may be approximately 2.0 to 3.6 times the second thickness of the data storage structure.

[0010] According to some exemplary embodiments of the present invention, a magnetic memory device may include a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked on a substrate. The magnetic tunnel junction pattern may include: a free layer; a pinned layer located between the bottom electrode and the free layer; and a tunnel barrier layer located between the pinned layer and the free layer. In a direction parallel to the top surface of the substrate, the middle portion of the pinned layer may be wider than the upper portion of the pinned layer and may be wider than the lower portion of the pinned layer. Attached Figure Description

[0011] Figure 1 The diagram shows a circuit diagram of a unit memory cell of a magnetic memory device presenting some example embodiments of the concept according to the present invention.

[0012] Figure 2 A plan view of a magnetic memory device presenting some example embodiments of the concept according to the present invention is shown.

[0013] Figure 3 Show along Figure 2 The cross-sectional views taken from lines I-I' and II-II'.

[0014] Figure 4A and Figure 4B A cross-sectional view is shown illustrating a magnetic tunnel junction pattern of a magnetic memory device, exemplarily representing some exemplary embodiments of the concept according to the present invention.

[0015] Figure 5A and Figure 5B A cross-sectional view is shown illustrating the data storage structure of a magnetic memory device presenting some example embodiments of the concept according to the present invention.

[0016] Figure 6 A cross-sectional view is shown illustrating the data storage structure of a magnetic memory device presenting some example embodiments of the concept according to the present invention.

[0017] Figures 7 to 12 Show along Figure 2 The cross-sectional views taken by lines I-I' and II-II' illustrate methods for manufacturing magnetic memory devices according to some exemplary embodiments of the present invention. Detailed Implementation

[0018] Some exemplary embodiments of the inventive concept will now be described in detail below with reference to the accompanying drawings.

[0019] Figure 1 The diagram shows a circuit diagram of a unit memory cell of a magnetic memory device presenting some example embodiments of the concept according to the present invention.

[0020] Reference Figure 1 A unit memory cell MC may include a memory element ME and a select element SE. The memory element ME may be connected between a bit line BL and the select element SE, and the select element SE may be connected between the memory element ME and a word line WL. As described herein, an element "on" or "connected to" or "in contact with" another element may be directly on or directly connected to the other element, or an intermediate element may be present. When an element is "directly" on or directly connected to or directly in contact with another element, no intermediate element is present. "Connected" elements may be electrically connected and / or physically connected. The memory element ME may be a variable resistor device that switches between two resistance states when an electrical pulse is supplied. The memory element ME may have a resistance that changes due to the spin-transfer phenomenon of the current flowing through the memory element ME. The memory element ME may have a thin-film structure configured to exhibit magnetoresistive properties and may include at least one ferromagnetic material and / or at least one antiferromagnetic material. The select element SE may be configured to selectively control the charge passing through the memory element ME. For example, the select element SE can be one of a diode, a PNP bipolar transistor, an NPN bipolar transistor, an NMOS field-effect transistor, and a PMOS field-effect transistor. When the select element SE is configured as a three-terminal device (such as a bipolar transistor or a MOS field-effect transistor), additional wires can be connected to the select element SE.

[0021] The memory element ME may include a magnetic tunnel junction pattern MTJ. The magnetic tunnel junction pattern MTJ may include a first magnetic structure MS1, a second magnetic structure MS2, and a tunnel barrier pattern TBR between the first magnetic structure MS1 and the second magnetic structure MS2. The terms "first," "second," etc., may be used herein to distinguish one element from another. Each of the first magnetic structure MS1 and the second magnetic structure MS2 may include at least one magnetic layer formed of a magnetic material. The memory element ME may also include a bottom electrode BE between the magnetic tunnel junction pattern MTJ and a select element SE, and a top electrode TE between the magnetic tunnel junction pattern MTJ and a bit line BL.

[0022] Figure 2A plan view of a magnetic memory device presenting some example embodiments of the concept according to the present invention is shown. Figure 3 Show along Figure 2 The cross-sectional views taken from lines I-I' and II-II'. Figure 4A and Figure 4B A cross-sectional view is shown illustrating a magnetic tunnel junction pattern of a magnetic memory device, exemplarily representing some exemplary embodiments of the concept according to the present invention.

[0023] Reference Figure 2 and Figure 3 The lower line 104 and the lower contact 102 can be disposed on the substrate 100. The substrate 100 can be a semiconductor substrate including silicon, silicon-on-insulator (SOI), silicon-germanium (SiGe), germanium (Ge), gallium-arsenide (GaAs), etc. The substrate 100 can include a cell region CR and a peripheral circuit region PR. The cell region CR can be a region of the substrate 100 in which memory cells are disposed. The peripheral circuit region PR can be another region of the substrate in which peripheral circuitry for driving memory cells is disposed. The lower line 104 and the lower contact 102 can be disposed on the cell region CR and the peripheral circuit region PR of the substrate 100.

[0024] The lower line 104 may be spaced apart from the top surface 100U of the substrate 100 in a first direction D1 perpendicular to the top surface 100U of the substrate 100. Lower contacts 102 may be disposed between the substrate 100 and the lower lines 104, and each of the lower lines 104 may be electrically connected to the substrate 100 via a corresponding lower contact 102. The lower lines 104 and the lower contacts 102 may comprise metal (e.g., copper).

[0025] The selection element can be disposed in the substrate 100. The selection element can be, for example, a field-effect transistor. Each of the lower lines 104 can be electrically connected to a terminal of the corresponding one of the selection elements via a corresponding one of the lower contacts 102.

[0026] A first interlayer dielectric layer 108 may be disposed thereon on substrate 100, covering cell region CR and peripheral circuit region PR, and also covering lower line 104 and lower contact 102. As used herein, the element “covering” another element does not need to be completely covered. The top surface of lower line 104 may be substantially coplanar with the top surface of first interlayer dielectric layer 108. For example, the top surface of lower line 104 may be positioned at substantially the same height as the top surface of first interlayer dielectric layer 108. In this specification, the term “height” may indicate the distance measured from the top surface 100U of substrate 100 along a first direction D1. The first interlayer dielectric layer 108 may include one or more of, for example, oxides, nitrides, and oxide oxynitrides.

[0027] A second interlayer dielectric layer 125 may be disposed on the first interlayer dielectric layer 108, and a lower dielectric layer 110 may be interposed between the first interlayer dielectric layer 108 and the second interlayer dielectric layer 125. The lower dielectric layer 110 and the second interlayer dielectric layer 125 may cover the cell region CR and the peripheral circuit region PR. The second interlayer dielectric layer 125 may include one or more of, for example, oxides, nitrides, and oxide oxynitrides. The lower dielectric layer 110 may include a material different from the materials of the first interlayer dielectric layer 108 and the second interlayer dielectric layer 125. The lower dielectric layer 110 may include a material with etch selectivity relative to the first interlayer dielectric layer 108 and the second interlayer dielectric layer 125. The lower dielectric layer 110 may include a nitride (e.g., silicon nitride).

[0028] Lower contact plugs 120 may be disposed on cell regions CR of substrate 100. Multiple lower contact plugs 120 may be provided, spaced apart from each other in a second direction D2 parallel to the top surface 100U of substrate 100. Each of the multiple lower contact plugs 120 may penetrate the second interlayer dielectric layer 125 and the lower dielectric layer 110, and may be connected to a corresponding one of the lower lines 104. Lower contact plugs 120 may include a lower contact pattern 124 and a lower barrier pattern 122. The lower contact pattern 124 may be disposed in the second interlayer dielectric layer 125 and the lower dielectric layer 110. The lower barrier pattern 122 may be interposed between the second interlayer dielectric layer 125 and the side surfaces (e.g., sidewalls or side surfaces) of the lower contact pattern 124, and between the lower dielectric layer 110 and the side surfaces of the lower contact pattern 124, and may extend between the lower lines 104 and the bottom surface of the lower contact pattern 124. The lower contact pattern 124 may include a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium and / or tantalum) and / or a metal semiconductor compound (e.g., a metal silicide), and the lower barrier pattern 122 may include a conductive metal nitride (e.g., titanium nitride, tantalum nitride and / or tungsten nitride).

[0029] Data storage structures DS can be disposed on the cell region CR of the substrate 100. Multiple data storage structures DS can be configured, and these structures can be spaced apart from each other in the second direction D2. The multiple data storage structures DS can be disposed on corresponding lower contact plugs 120 and connected to those lower contact plugs 120.

[0030] The data storage structure DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE, sequentially stacked on the lower contact plug 120. The bottom electrode BE may be disposed between the lower contact plug 120 and the magnetic tunnel junction pattern MTJ, and the magnetic tunnel junction pattern MTJ may be disposed between the bottom electrode BE and the top electrode TE. The magnetic tunnel junction pattern MTJ may include a first magnetic structure MS1, a second magnetic structure MS2, and a tunnel barrier pattern TBR between the first magnetic structure MS1 and the second magnetic structure MS2. The first magnetic structure MS1 may be disposed between the bottom electrode BE and the tunnel barrier pattern TBR, and the second magnetic structure MS2 may be disposed between the top electrode TE and the tunnel barrier pattern TBR. The bottom electrode BE may include, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The top electrode TE may include a metal (e.g., Ta, W, Ru, or Ir) and / or a conductive metal nitride (e.g., TiN).

[0031] Reference Figure 4A and Figure 4B The first magnetic structure MS1 may include a reference layer having a unidirectional fixed magnetization direction MD1, and the second magnetic structure MS2 may include a free layer having a magnetization direction MD2 that can be parallel or antiparallel to the magnetization direction MD1 of the first magnetic structure MS1. Figure 4A and Figure 4B An example is shown in which the second magnetic structure MS2 includes a free layer, but the inventive concept is not necessarily limited thereto. Figure 4A and Figure 4B In alternatives to those shown, the first magnetic structure MS1 may include a free layer, and the second magnetic structure MS2 may include a reference layer. As an example, Figure 4A As shown, the magnetization direction MD1 of the first magnetic structure MS1 and the magnetization direction MD2 of the second magnetic structure MS2 can be parallel to the interface between the tunnel barrier pattern TBR and the second magnetic structure MS2. In this case, each of the first magnetic structure MS1 and the second magnetic structure MS2 can include a ferromagnetic material. The first magnetic structure MS1 can also include an antiferromagnetic material to fix the magnetization direction of the ferromagnetic material in the first magnetic structure MS1. As another example, such as Figure 4B As shown, the magnetization direction MD1 of the first magnetic structure MS1 and the magnetization direction MD2 of the second magnetic structure MS2 can be perpendicular to the interface between the tunnel barrier pattern TBR and the second magnetic structure MS2. In this case, each of the first magnetic structure MS1 and the second magnetic structure MS2 may include a perpendicular magnetic material (e.g., CoFeTb, CoFeGd, or CoFeDy) having L 10 Vertically magnetic materials with hexagonal close-packed (HCP) lattice structures, CoPt, and / or vertically magnetized structures. Having L...10 The vertical magnetic material of the structure can include L 10 FePt, L structure 10 FePd, L structure 10 CoPd and / or L structure 10 The structure is CoPt. The vertical magnetization structure may include alternating and repeatedly stacked magnetic and non-magnetic layers. For example, the vertical magnetization structure may include (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, and / or (CoCr / Pd)n (where n is the number of stacked layers). As yet another example, each of the first magnetic structure MS1 and the second magnetic structure MS2 may include a Heusler alloy or a Co-based Heusler alloy.

[0032] The tunnel barrier pattern (TBR) may include a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium-zinc (Mg-Zn) oxide layer, and / or a magnesium-boron (Mg-B) oxide layer.

[0033] Return to reference Figure 2 and Figure 3 Each of the lower contact plug 120 and the data storage structure DS may have a thickness in a first direction D1. The lower contact plug 120 may have a first thickness 120T, which is the vertical length or distance measured from the bottom surface 120L of the lower contact plug 120 along the first direction D1 to the top surface 120U of the lower contact plug 120. The bottom surface 120L of the lower contact plug 120 may contact a corresponding line in the lower line 104, and the top surface 120U of the lower contact plug 120 may contact the bottom electrode BE of the data storage structure DS. The data storage structure DS may have a second thickness DS_T, which is the vertical length measured from the bottom surface BE_L of the bottom electrode BE along the first direction D1 to the top surface TE_U of the top electrode TE. The bottom surface BE_L of the bottom electrode BE may contact the lower contact plug 120.

[0034] The first thickness 120T of the lower contact plug 120 can be approximately 2.0 to 3.6 times the second thickness DS_T of the data storage structure DS. For example, the ratio of the second thickness DS_T to the first thickness 120T can be approximately 1:2 to approximately 1:3.6 (DS_T:120T = 1:2.0 to approximately 3.6), which can be configured to improve electrical characteristics and / or reduce process defects as described herein. When the first thickness 120T is less than approximately twice the second thickness DS_T, the second thickness DS_T of the data storage structure DS can be relatively increased. In this case, the thickness of the magnetic tunnel junction pattern MTJ in the data storage structure DS can be relatively increased, and therefore the magnetic tunnel junction pattern MTJ can have poor characteristics. When the first thickness 120T is greater than approximately 3.6 times the second thickness DS_T, the aspect ratio of the lower contact plug 120 can be relatively increased. In this case, the incidence of process defects such as voids in the lower contact plug 120 increases.

[0035] On the cell region CR, the second lower interlayer dielectric layer 125 may have a recess 125R extending toward the substrate 100 on the opposite side of the data storage structure DS (e.g., between multiple data storage structures DS). The lowermost surface 125RL of the recess 125R may be positioned at a height lower than the top surface 120U of the lower contact plug 120 or closer to the substrate 100 than the top surface 120U of the lower contact plug 120. The top surface 125U of the second lower interlayer dielectric layer 125 on the peripheral circuit region PR may be positioned at a height lower than the lowermost surface 125RL of the recess 125R on the cell region CR of the second lower interlayer dielectric layer 125 or closer to the substrate 100 than the lowermost surface 125RL of the recess 125R on the cell region CR of the second lower interlayer dielectric layer 125.

[0036] The protective dielectric layer 130 may cover the side surfaces (e.g., sidewalls or side surfaces) of the data storage structure DS. When viewed in a plane, the protective dielectric layer 130 may surround the side surfaces of the data storage structure DS. The protective dielectric layer 130 may cover the side surfaces of each of the bottom electrode BE, the magnetic tunnel junction pattern MTJ, and the top electrode TE, and when viewed in a plane, the protective dielectric layer 130 may surround the side surfaces of each of the bottom electrode BE, the magnetic tunnel junction pattern MTJ, and the top electrode TE. The protective dielectric layer 130 may extend to the inner surface of the recess 125R on the cell region CR of the second lower interlayer dielectric layer 125, and may conformally cover the inner surface of the recess 125R. The protective dielectric layer 130 may extend to the peripheral circuit region PR, and may cover the top surface 125U of the second lower interlayer dielectric layer 125 on the peripheral circuit region PR.

[0037] A first upper interlayer dielectric layer 135 may be disposed on a protective dielectric layer 130 and may cover the cell region CR and the peripheral circuit region PR. The first upper interlayer dielectric layer 135 may cover the data storage structure DS on the cell region CR. The protective dielectric layer 130 may be interposed between the first upper interlayer dielectric layer 135 and the side surface of the data storage structure DS, and may extend between the first upper interlayer dielectric layer 135 and the inner surface of the recess 125 of the second lower interlayer dielectric layer 125 located on the cell region CR. The protective dielectric layer 130 may extend between the first upper interlayer dielectric layer 135 and the top surface 125U of the second lower interlayer dielectric layer 125 located on the peripheral circuit region PR.

[0038] The first upper interlayer dielectric layer 135 may include one or more of oxides, nitrides, and oxide oxynitrides. The protective dielectric layer 130 may include a material different from the material of the first upper interlayer dielectric layer 135 and the material of the second lower interlayer dielectric layer 125. The protective dielectric layer 130 may include a material having etch selectivity relative to the first upper interlayer dielectric layer 135 and the second lower interlayer dielectric layer 125. The protective dielectric layer 130 may include a nitride (e.g., silicon nitride).

[0039] A second upper interlayer dielectric layer 145 may be disposed on the first upper interlayer dielectric layer 135, and an upper dielectric layer 140 may be interposed between the first upper interlayer dielectric layer 135 and the second upper interlayer dielectric layer 145. The upper dielectric layer 140 and the second upper interlayer dielectric layer 145 may cover the cell region CR and the peripheral circuit region PR. The top surface 140U of the upper dielectric layer 140 on the peripheral circuit region PR may be positioned at a lower height than the top surface 140U of the upper dielectric layer 140 on the cell region CR. The second upper interlayer dielectric layer 145 may include one or more of oxides, nitrides, and oxide oxynitrides. The upper dielectric layer 140 may include a material different from the materials of the first and second upper interlayer dielectric layers 135 and 145. The upper dielectric layer 140 may include a material with etch selectivity relative to the first and second upper interlayer dielectric layers 135 and 145. The upper dielectric layer 140 may include a nitride (e.g., silicon nitride).

[0040] The top line 150 can be disposed on the cell region CR of the substrate 100. Multiple top lines 150 can be configured, and these multiple top lines 150 can be spaced apart from each other in the second direction D2. Each of the multiple top lines 150 can be connected to one or more corresponding data storage structures DS.

[0041] The upper line 150 can penetrate the second interlayer dielectric layer 145 and the upper dielectric layer 140, and can be connected to the data storage structure DS. The upper line 150 can contact the top surface TE_U of the top electrode TE included in the data storage structure DS. According to some example embodiments, the upper line 150 can cover the top surface TE_U of the top electrode TE and can extend to the side surface of the top electrode TE to partially cover the side surface of the top electrode TE. The upper line 150 can include an upper line pattern 154 and an upper barrier pattern 152. The upper line pattern 154 can penetrate the second interlayer dielectric layer 145 and the upper dielectric layer 140. The upper barrier pattern 152 can be interposed between the second interlayer dielectric layer 145 and the side surface of the upper line pattern 154 and between the upper dielectric layer 140 and the side surface of the upper line pattern 154, and can extend between the bottom surface of the upper line pattern 154 and the top surface TE_U of the top electrode TE. According to some example embodiments, the upper barrier pattern 152 may extend to and partially cover the side surface of the top electrode TE. The upper line pattern 154 may include metal (e.g., copper), and the upper barrier pattern 152 may include a conductive metal nitride.

[0042] The upper line 150 may have a thickness in the first direction D1. The upper line 150 may have a third thickness 150T, which is the vertical length measured from the bottom surface 150L of the upper line 150 along the first direction D1 to the top surface 150U of the upper line 150. The bottom surface 150L of the upper line 150 may contact the top surface TE_U of the top electrode TE. The third thickness 150T of the upper line 150 may be approximately 1.0 to 2.2 times the second thickness DS_T of the data storage structure DS. For example, the ratio of the second thickness DS_T to the third thickness 150T may be approximately 1:1 to approximately 1:2.2 (DS_T:150T = 1:1 to approximately 2.2), which may be configured to improve electrical characteristics as described herein. When the third thickness 150T is smaller than the second thickness DS_T, the second thickness DS_T of the data storage structure DS may be relatively increased. In this case, the thickness of the magnetic tunnel junction pattern MTJ in the data storage structure DS can be relatively increased, and therefore the magnetic tunnel junction pattern MTJ will have poor characteristics. Furthermore, when the third thickness 150T is approximately 2.2 times larger than the second thickness DS_T, the second thickness DS_T of the data storage structure DS can be relatively decreased. In this case, the thickness of the magnetic tunnel junction pattern MTJ in the data storage structure DS can be relatively decreased, and therefore the magnetic tunnel junction pattern MTJ will have poor characteristics.

[0043] The peripheral line structure 160 can be disposed on the peripheral circuit region PR of the substrate 100. On the peripheral circuit region PR, the peripheral line structure 160 can penetrate the second upper interlayer dielectric layer 145, the upper dielectric layer 140, the first upper interlayer dielectric layer 135, the protective dielectric layer 130, the second lower interlayer dielectric layer 125, and the lower dielectric layer 110, and can be connected to the lower line 104. The peripheral line structure 160 may include a peripheral conductive pattern 164 and a peripheral barrier pattern 162 extending along the side and bottom surfaces of the peripheral conductive pattern 164. On the peripheral circuit region PR, the peripheral conductive pattern 164 can penetrate the second upper interlayer dielectric layer 145, the upper dielectric layer 140, the first upper interlayer dielectric layer 135, the protective dielectric layer 130, and the second lower interlayer dielectric layer 125, and can also penetrate at least a portion of the lower dielectric layer 110.

[0044] The peripheral conductive pattern 164 may include a line pattern LP extending in a direction parallel to the top surface 100U of the substrate 100 (e.g., a second direction D2), and may also include contact patterns CP extending from the line pattern LP toward the substrate 100. The contact patterns CP may be horizontally spaced apart from each other along a direction parallel to the top surface 100U of the substrate 100 (e.g., a second direction D2). The contact patterns CP may be connected to corresponding lower lines 104, and the line patterns LP may be collectively connected to (e.g., multiple) contact patterns CP. In the peripheral circuit region PR, the line pattern LP may penetrate the second interlayer dielectric layer 145 and the upper dielectric layer 140, and may also penetrate the upper portion of the first interlayer dielectric layer 135. In the peripheral circuit region PR, each of the contact patterns CP may penetrate the lower portion of the first interlayer dielectric layer 135, the protective dielectric layer 130, and the second interlayer dielectric layer 125, and may also penetrate at least a portion of the lower dielectric layer 110. A portion of each of the first upper interlayer dielectric layer 135, the protective dielectric layer 130, and the second lower interlayer dielectric layer 125 may be interposed between contact patterns CP. In some example embodiments, the first upper interlayer dielectric layer 135 may have a stepped shape at the side surface of the portion between the contact patterns CP. Each of the contact patterns CP may have a side surface facing the side surface of the portion of the first upper interlayer dielectric layer 135, thus the side surface of each of the contact patterns CP may have a stepped shape.

[0045] The peripheral barrier pattern 162 can be interposed between each of the lower dielectric layer 110 and the contact pattern CP, between each of the second lower interlayer dielectric layer 125 and the contact pattern CP, between the protective dielectric layer 130 and the contact pattern CP, and between the first upper interlayer dielectric layer 135 and the contact pattern CP. The peripheral barrier pattern 162 can extend between each of the contact patterns CP and the corresponding lower line 104. The peripheral barrier pattern 162 can extend between the line pattern LP and the first upper interlayer dielectric layer 135, between the line pattern LP and the upper dielectric layer 140, and between the line pattern LP and the second upper interlayer dielectric layer 145. The line pattern LP and the contact pattern CP can contact each other to form a single unit or a single entity, without a boundary between them.

[0046] The top surface of the peripheral conductive pattern 164 (or the top surface of the line pattern LP) may be substantially coplanar with the top surface of the second upper interlayer dielectric layer 145, and the uppermost surface of the peripheral barrier pattern 162 may be substantially coplanar with the uppermost surface of the second upper interlayer dielectric layer 145. The line pattern LP and the contact pattern CP may comprise the same material as each other. The line pattern LP and the contact pattern CP may comprise the same material as the upper line pattern 154. The line pattern LP and the contact pattern CP may comprise a metal (e.g., copper). The peripheral barrier pattern 162 may comprise the same material as the upper barrier pattern 152. The peripheral barrier pattern 162 may comprise a conductive metal nitride.

[0047] Figure 5A and Figure 5B A cross-sectional view is shown illustrating the data storage structure of a magnetic memory device presenting some example embodiments of the concept according to the present invention.

[0048] Reference Figure 5A and Figure 5B , Figure 3 The data storage structure DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE. The magnetic tunnel junction pattern MTJ may include a first magnetic structure MS1, a second magnetic structure MS2, and a tunnel barrier pattern TBR between the first magnetic structure MS1 and the second magnetic structure MS2.

[0049] According to some example embodiments, the first magnetic structure MS1 may include a seed layer 200 between the bottom electrode BE and the tunnel barrier pattern TBR, a first pinning layer 210 between the seed layer 200 and the tunnel barrier pattern TBR, and a second pinning layer 220 between the first pinning layer 210 and the tunnel barrier pattern TBR. The second magnetic structure MS2 may include a free layer 230 between the tunnel barrier pattern TBR and the top electrode TE, a non-magnetic layer 240 between the free layer 230 and the top electrode TE, and a capping layer 250 between the non-magnetic layer 240 and the top electrode TE.

[0050] Seed layer 200 may include materials that facilitate the crystal growth of the magnetic layer that forms the magnetic tunnel junction pattern MTJ. For example, seed layer 200 may include chromium (Cr), iridium (Ir), and / or ruthenium (Ru).

[0051] According to some example embodiments, the first pinning layer 210 and the second pinning layer 220 may each have a magnetization direction 210MD and a magnetization direction 220MD perpendicular to the interface between the tunnel barrier pattern TBR and the free layer 230, respectively. The first pinning layer 210 may include the above-mentioned references. Figure 4B One or more of the vertically magnetic materials discussed. For example, the first pinning layer 210 may include iron (Fe), cobalt (Co), and / or nickel (Ni). The second pinning layer 220 may include a plurality of magnetic layers and a plurality of non-magnetic layers alternately stacked on the first pinning layer 210. Each of the plurality of magnetic layers may include iron (Fe), cobalt (Co), and / or nickel (Ni), and each of the plurality of non-magnetic layers may include iridium (Ir) and / or ruthenium (Ru). The second pinning layer 220 may be antiferromagnetically coupled to the first pinning layer 210 via at least one of the plurality of non-magnetic layers. Therefore, the magnetization direction 220MD of the second pinning layer 220 may be antiparallel to the magnetization direction 210MD of the first pinning layer 210.

[0052] According to some example embodiments, the free layer 230 may include a magnetic material having perpendicular magnetism due to perpendicular magnetic anisotropy at the interface between the free layer 230 and the tunnel barrier pattern TBR. For example, the free layer 230 may include cobalt iron boron (CoFeB). In another example, the free layer 230 may include the above-mentioned references. Figure 4BOne or more of the vertically magnetic materials discussed. The non-magnetic layer 240 may include a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium-zinc (Mg-Zn) oxide layer, and / or a magnesium-boron (Mg-B) oxide layer. For example, the non-magnetic layer 240 may include the same material as the material of the tunnel barrier pattern TBR. The magnetic anisotropy of the free layer 230 may be increased due to magnetic anisotropy caused at the interface between the non-magnetic layer 240 and the free layer 230. The capping layer 250 may be used to prevent degradation of the free layer 230. The capping layer 250 may include, for example, tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), silver (Ag), titanium (Ti), tantalum nitride (TaN), and / or titanium nitride (TiN).

[0053] The bottom electrode BE, the top electrode TE, and each of the layers 200, 210, 220, TBR, 230, 240, and 250 constituting the magnetic tunnel junction pattern MTJ can have a width in a direction parallel to the interface between the tunnel barrier pattern TBR and the free layer 230 (e.g., a second direction D2). For example, the second direction D2 can be... Figure 3 The top surface 100U of the substrate 100 shown is parallel.

[0054] The width 230UW of the free layer 230 at its upper portion can be greater than the width 230LW of the free layer 230 at its lower portion. The free layer 230 can have a width that gradually increases from its lower portion to its upper portion. Therefore, the free layer 230 can have a negative profile at its side surface, which is inclined at an obtuse angle relative to the bottom surface of the free layer 230. The width 230UW of the free layer 230 at its upper portion can be greater than the width TBR_W of the tunnel barrier pattern TBR. The width TBR_W of the tunnel barrier pattern TBR can be substantially the same as the width 230LW of the free layer 230 at its lower portion.

[0055] The width 240W of the non-magnetic layer 240 can be greater than the width TBR_W of the tunnel barrier pattern TBR. The width 240W of the non-magnetic layer 240 can be greater than the width 230LW at the lower part of the free layer 230, and is substantially the same as the width 230UW at the upper part of the free layer 230.

[0056] The width 250UW at the upper portion of the cover layer 250 can be smaller than the width 250LW at the lower portion of the cover layer 250. The cover layer 250 can have a width that gradually decreases from its lower portion to its upper portion. Therefore, the cover layer 250 can have a positive profile at its side surface, which is inclined at an acute angle relative to the bottom surface of the cover layer 250. The width 250UW at the upper portion of the cover layer 250 can be smaller than the width 240W of the non-magnetic layer 240. The width 240W of the non-magnetic layer 240 can be substantially the same as the width 250LW at the lower portion of the cover layer 250.

[0057] According to some example embodiments, the width TE_UW of the top electrode TE at its upper portion can be substantially the same as the width TE_LW of the top electrode TE at its lower portion. The top electrode TE can have a substantially constant width from its upper portion to its lower portion. Therefore, the side surface or sidewall of the top electrode TE can be substantially perpendicular to the bottom surface of the top electrode TE. The width TE_LW of the top electrode TE at its lower portion can be substantially the same as the width 250UW of the cover layer 250 at its upper portion.

[0058] The width 220MW at the middle portion of the second pinning layer 220 can be greater than the width 220UW at the upper portion of the second pinning layer 220 and the width 220LW at the lower portion of the second pinning layer 220. Therefore, the side surface of the second pinning layer at the middle portion of 220 can protrude more laterally (e.g., in the second direction D2) than the side surfaces at the upper and lower portions of the second pinning layer 220. That is, the side surface at the middle portion of the second pinning layer 220 can protrude beyond the upper and lower portions of the second pinning layer 220 in direction D2. The width 220MW at the middle portion of the second pinning layer 220 can be greater than the width TBR_W of the tunnel barrier pattern TBR. The width 220UW at the upper portion of the second pinning layer 220 and the width 220LW at the lower portion of the second pinning layer 220 can be substantially the same as the width TBR_W of the tunnel barrier pattern TBR. The width 230UW at the upper part of the free layer 230 can be greater than the width 220UW at the upper part of the second pinning layer 220, the width 220LW at the lower part of the second pinning layer 220, and the width 220MW at the middle part of the second pinning layer 220.

[0059] The width 210UW at the upper portion of the first pinning layer 210 can be smaller than the width 210LW at the lower portion of the first pinning layer 210. The first pinning layer 210 can have a width that gradually decreases from its lower portion to its upper portion. Therefore, the first pinning layer 210 can have a positive profile at its side surface that is inclined at an acute angle relative to the bottom surface of the first pinning layer 210. The width 210UW at the upper portion of the first pinning layer 210 can be smaller than the width 220MW at the middle portion of the second pinning layer 220, and substantially the same as the width 220LW at the lower portion of the second pinning layer 220. The width 210LW at the lower portion of the first pinning layer 210 can be larger than the width 220LW at the lower portion of the second pinning layer 220 and the width 220MW at the middle portion of the second pinning layer 220.

[0060] The width 200UW at the upper portion of the seed layer 200 can be smaller than the width 200LW at the lower portion of the seed layer 200. The seed layer 200 can have a width that gradually decreases as it approaches its upper portion from its lower portion. Therefore, the seed layer 200 can have a positive profile at its side surface, which is inclined at an acute angle relative to the bottom surface of the seed layer 200. The width 200UW at the upper portion of the seed layer 200 can be larger than the width 210UW at the upper portion of the first pinning layer 210, and is substantially the same as the width 210LW at the lower portion of the first pinning layer 210. The width 200LW at the lower portion of the seed layer 200 can be larger than the width 210LW at the lower portion of the first pinning layer 210.

[0061] The width BE_UW at the upper portion of the bottom electrode BE can be smaller than the width BE_LW at the lower portion of the bottom electrode BE. The bottom electrode BE can have a width that gradually decreases as it approaches the upper portion from its lower portion. Therefore, the bottom electrode BE can have a positive profile at its side surface, which is inclined at an acute angle relative to the bottom surface of the bottom electrode BE. According to some example embodiments, the angle between the side surface of the bottom electrode BE and the bottom surface can be larger (e.g., more perpendicular) than the angle between the side surface of the seed layer 200 and the bottom surface. The width BE_UW at the upper portion of the bottom electrode BE can be greater than the width 200UW at the upper portion of the seed layer 200, and substantially the same as the width 200LW at the lower portion of the seed layer 200. The width BE_LW at the lower portion of the bottom electrode BE can be greater than the width 200LW at the lower portion of the seed layer 200.

[0062] The bottom electrode BE, the top electrode TE, and each of the layers 200, 210, 220, TBR, 230, 240, and 250 constituting the magnetic tunnel junction pattern MTJ may have a thickness in a direction perpendicular to the interface between the tunnel barrier pattern TBR and the free layer 230 (e.g., a first direction D1). For example, the first direction D1 may be perpendicular to the top surface 100U of the substrate 100.

[0063] The thickness 230T of the free layer 230 can be greater than the thickness TBR_T of the tunnel barrier pattern TBR and the thickness 240T of the nonmagnetic layer 240. The thickness TBR_T of the tunnel barrier pattern TBR can be substantially the same as the thickness 240T of the nonmagnetic layer 240. The thickness 250T of the capping layer 250 can be greater than the thickness 230T of the free layer 230, and the thickness TE_T of the top electrode TE can be greater than the thickness 250T of the capping layer 250.

[0064] The thickness 220T of the second pinning layer 220 can be greater than the thickness 230T of the free layer 230 and the thickness 250T of the capping layer 250. The thickness 220T of the second pinning layer 220 can be less than the thickness TE_T of the top electrode TE. The thickness 210T of the first pinning layer 210 can be less than the thickness 220T of the second pinning layer 220 and greater than the thickness 230T of the free layer 230. The thickness 210T of the first pinning layer 210 can be less than the thickness 250T of the capping layer 250.

[0065] The thickness 200T of the seed layer 200 can be greater than the thickness 210T of the first pinning layer 210 and less than the thickness 220T of the second pinning layer 220. The thickness 200T of the seed layer 200 can be less than the thickness 250T of the cover layer 250.

[0066] The thickness BE_T of the bottom electrode BE can be greater than the thickness of each of the seed layer 200, the first pinning layer 210, the second pinning layer 220, the tunnel barrier pattern TBR, the free layer 230, the nonmagnetic layer 240, and the capping layer 250. The thickness BE_T of the bottom electrode BE can be less than the thickness TE_T of the top electrode TE.

[0067] According to some example embodiments, Figure 3 The data storage structure DS can have a profile defined by the width and thickness of each of the layers 200, 210, 220, TBR, 230, 240 and 250 that constitute the magnetic tunnel junction pattern MTJ, thereby preventing the magnetic tunnel junction pattern MTJ in the data storage structure DS from degrading its characteristics.

[0068] Figure 6A cross-sectional view is shown illustrating the data storage structure of a magnetic memory device presenting some example embodiments of the concept according to the present invention.

[0069] Reference Figure 6 According to some example embodiments, the width TE_UW at the upper portion of the top electrode TE can be smaller than the width TE_LW at the lower portion of the top electrode TE. The top electrode TE can have a width that gradually decreases as it approaches its upper portion from its lower portion. Therefore, the top electrode TE can have a positive profile at a side surface that is inclined at an acute angle relative to the bottom surface of the top electrode TE. The width TE_UW at the upper portion of the top electrode TE can be smaller than the width 250UW at the upper portion of the cover layer 250, and the width TE_LW at the lower portion of the top electrode TE can be substantially the same as the width 250UW at the upper portion of the cover layer 250. Apart from the differences described above, the data storage structure DS according to this embodiment can be compared with the reference Figure 5A and Figure 5B The data storage structure DS discussed is basically the same.

[0070] Figures 7 to 12 Show along Figure 2 The cross-sectional views taken along lines I-I' and II-II' illustrate methods for manufacturing magnetic memory devices according to some exemplary embodiments of the present invention. For brevity, references will be omitted. Figures 1 to 6 The technical features of the magnetic memory devices discussed are the same or similar.

[0071] Reference Figure 7 The substrate 100 can be configured to include a cell region CR and a peripheral circuit region PR. Select elements can be formed in the substrate 100, and lower lines 104 and lower contacts 102 can be formed on the substrate 100. Each of the lower lines 104 can be electrically connected to a terminal of a corresponding select element via a corresponding lower contact 102. A first interlayer dielectric layer 108 can be formed on the substrate 100 to cover the cell region CR and the peripheral circuit region PR, and also to cover the lower lines 104 and lower contacts 102. The top surface of the lower lines 104 can be substantially coplanar with the top surface of the first interlayer dielectric layer 108.

[0072] A lower dielectric layer 110 and a second lower dielectric layer 125 may be sequentially formed on a first lower interlayer dielectric layer 108. The lower dielectric layer 110 and the second lower interlayer dielectric layer 125 may cover the cell region CR and the peripheral circuit region PR. A lower contact plug 120 may be formed on the cell region CR of the substrate 100. The lower contact plug 120 may penetrate the second lower interlayer dielectric layer 125 and the lower dielectric layer 110, and may be connected to a corresponding line in the lower line 104. For example, the formation of the lower contact plug 120 may include: forming a lower contact hole penetrating the lower dielectric layer 110 and the second lower interlayer dielectric layer 125; sequentially forming a lower barrier layer and a lower contact layer on the second lower interlayer dielectric layer 125 to fill the lower contact hole; and performing a planarization process to planarize the lower barrier layer and the lower contact layer until the top surface of the second lower interlayer dielectric layer 125 is exposed. The planarization process allows the lower contact plug 120 to include a lower contact pattern 124 and a lower barrier pattern 122 locally formed in the lower contact hole. The second lower interlayer dielectric layer 125 may not cover but rather expose the top surface 120U of the lower contact plug 120. The lower contact plug 120 may be formed with a first thickness 120T, which may be a vertical length measured along a first direction D1 from the bottom surface 120L of the lower contact plug 120 to the top surface 120U of the lower contact plug 120.

[0073] A bottom electrode layer (BEL) and a magnetic tunnel junction layer (MTJL) can be sequentially formed on the second lower interlayer dielectric layer 125. The bottom electrode layer (BEL) can be formed to cover the exposed top surface 120U of the lower contact plug 120 and the exposed top surface of the second lower interlayer dielectric layer 125. Each of the bottom electrode layer (BEL) and the magnetic tunnel junction layer (MTJL) can cover the cell region CR and the peripheral circuit region PR of the substrate 100. The magnetic tunnel junction layer (MTJL) can include a first magnetic layer ML1, a tunnel barrier layer (TBL), and a second magnetic layer ML2 sequentially stacked on the bottom electrode layer (BEL). Each of the first magnetic layer ML1 and the second magnetic layer ML2 can include at least one magnetic layer. For example, the first magnetic layer ML1 can include the above-mentioned references. Figure 5A and Figure 5B The seed layer 200, the first pinning layer 210, and the second pinning layer 220 discussed above, and the second magnetic layer ML2 may include the above-mentioned references. Figure 5A and Figure 5B The discussion focuses on the free layer 230, the non-magnetic layer 240, and the capping layer 250. The first magnetic layer ML1, the tunnel barrier layer TBL, and the second magnetic layer ML2 can be formed by sputtering, chemical vapor deposition, or atomic layer deposition.

[0074] A conductive mask pattern 300 can be formed on a magnetic tunnel junction layer (MTJL) on the cell region CR. As discussed below, the conductive mask pattern 300 can define the region on which the magnetic tunnel junction pattern is formed. The conductive mask pattern 300 can include a metal (e.g., Ta, W, Ru, or Ir) and / or a conductive metal nitride (e.g., TiN).

[0075] Reference Figure 8 An etching process can be performed, wherein the conductive mask pattern 300 can be used as an etching mask to sequentially etch the magnetic tunnel junction layer MTJL and the bottom electrode layer BE. Therefore, the magnetic tunnel junction pattern MTJ and the bottom electrode BE can be formed on the second lower interlayer dielectric layer 125 on the cell region CR. The bottom electrode BE can be connected to the lower contact plug 120, and the magnetic tunnel junction pattern MTJ can be formed on the bottom electrode BE. The magnetic tunnel junction pattern MTJ may include a first magnetic structure MS1, a tunnel barrier pattern TBR, and a second magnetic structure MS2 sequentially stacked on the bottom electrode BE. The first magnetic structure MS1 and the second magnetic structure MS2 may be spaced apart from each other across the tunnel barrier pattern TBR. Etching of the magnetic tunnel junction layer MTJL may include using the conductive mask pattern 300 as an etching mask to sequentially etch the second magnetic layer ML2, the tunnel barrier layer TBL, and the first magnetic layer ML1. The second magnetic layer ML2, the tunnel barrier layer TBL, and the first magnetic layer ML1 can be etched to form the second magnetic structure MS2, the tunnel barrier pattern TBR, and the first magnetic structure MS1, respectively. For example, the first magnetic structure MS1 may include the above reference. Figure 5A and Figure 5B The seed layer 200, the first pinning layer 210, and the second pinning layer 220 discussed above, and the second magnetic structure MS2 may include the above-mentioned references. Figure 5A and Figure 5B The free layer 230, the non-magnetic layer 240, and the capping layer 250 are discussed.

[0076] For example, an ion beam etching process using an ion beam can be used as the etching process for etching the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL. The ion beam may include inert ions. The etching process can recess the upper portion of the second interlayer dielectric layer 125 on the opposite side of the magnetic tunnel junction pattern MTJ. Therefore, the second interlayer dielectric layer 125 on the cell region CR can have a recess 125R extending toward the substrate 100 on the opposite side of the magnetic tunnel junction pattern MTJ. The lowermost surface 125RL of the recess 125R can be positioned at a height lower than the top surface 120U of the lower contact plug 120. In addition, the etching process can etch the upper portion of the second interlayer dielectric layer 125 on the peripheral circuit region PR. The top surface 125U of the second interlayer dielectric layer 125 on the peripheral circuit region PR can be positioned at a height lower than the lowermost surface 125RL of the recess 125R on the cell region CR of the second interlayer dielectric layer 125.

[0077] After the etching process, the residue of the conductive mask pattern 300 can be retained on the magnetic tunnel junction pattern MTJ. The residue of the conductive mask pattern 300 can be used as the top electrode TE. Hereinafter, the residue of the conductive mask pattern 300 may be referred to as the top electrode TE. The top electrode TE, the magnetic tunnel junction pattern MTJ, and the bottom electrode BE can constitute the data storage structure DS.

[0078] An etching process can be performed to form the data storage structure DS with a second thickness DS_T. The second thickness DS_T can be a vertical length measured along a first direction D1 from the bottom surface BE_L of the bottom electrode BE to the top surface TE_U of the top surface TE. The first thickness 120T of the lower contact plug 120 can be approximately 2.0 to 3.6 times the second thickness DS_T of the data storage structure DS. Furthermore, a deposition process for depositing layers constituting the data storage structure DS and an etching process for etching the deposited layers can be performed to form the data storage structure DS with the above-mentioned thickness DS_T. Figure 5A , Figure 5B or Figure 6 Outline of the discussion.

[0079] Reference Figure 9 A protective dielectric layer 130 can be formed on the second interlayer dielectric layer 125 to cover the data storage structure DS. The protective dielectric layer 130 can be formed to conformally cover the top and side surfaces of the data storage structure DS and extend along the inner surface of the recess 125R of the second interlayer dielectric layer 125. The protective dielectric layer 130 can extend along the top surface 125U of the second interlayer dielectric layer 125 located on the peripheral circuit region PR.

[0080] A first interlayer dielectric layer 135 can be formed on the protective dielectric layer 130 to cover the data storage structure DS. The first interlayer dielectric layer 135 can cover the protective dielectric layer 130 on the peripheral circuit region PR. An upper dielectric layer 140 and a second interlayer dielectric layer 145 can be sequentially formed on the first interlayer dielectric layer 135. An upper dielectric layer 140 can be interposed between the first interlayer dielectric layer 135 and the second interlayer dielectric layer 145. Each of the upper dielectric layer 140 and the second interlayer dielectric layer 145 can cover the cell region CR and the peripheral circuit region PR of the substrate 100. The first lower interlayer dielectric layer 108 and the second lower interlayer dielectric layer 125, the first upper interlayer dielectric layer 135 and the second upper interlayer dielectric layer 145, the lower dielectric layer 110, the protective dielectric layer 130, and the upper dielectric layer 140 can each be formed by performing a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0081] Initial vias PH can be formed on the peripheral circuit region PR of substrate 100. Each of the initial vias PH can penetrate the second upper interlayer dielectric layer 145, the upper dielectric layer 140, the first upper interlayer dielectric layer 135, the guard dielectric layer 130, and the second lower interlayer dielectric layer 125, and can expose the top surface of the lower dielectric layer 110. The formation of the initial vias PH may include: forming a first mask pattern on the second upper interlayer dielectric layer 145 having openings defining the region where the initial vias PH will be formed, and then using the first mask pattern as an etching mask to sequentially etch the second upper interlayer dielectric layer 145, the upper dielectric layer 140, the first upper interlayer dielectric layer 135, the guard dielectric layer 130, and the second lower interlayer dielectric layer 125. Afterwards, the first mask pattern can be removed.

[0082] Reference Figure 10 A sacrificial layer 170 can be formed on the second upper interlayer dielectric layer 145 to fill the initial via PH. The sacrificial layer 170 can cover the second upper interlayer dielectric layer 145 on the cell region CR and the peripheral circuit region PR. The sacrificial layer 170 can include, for example, a carbon-containing material.

[0083] Reference Figure 11 On the cell region CR, a first etching process can be performed, wherein the sacrificial layer 170, the second upper interlayer dielectric layer 145, and the upper dielectric layer 140 can be patterned to form a cell trench 180 in the second upper interlayer dielectric layer 145. The first etching process can continue until the protective dielectric layer 130 on the cell region CR is exposed. The cell trench 180 can expose the top surface of the protective dielectric layer 130 located on the cell region CR.

[0084] On the peripheral circuit region PR, a first etching process can pattern the sacrificial layer 170, the second upper interlayer dielectric layer 145, the upper dielectric layer 140, the first upper interlayer dielectric layer 135, the protective dielectric layer 130, and the second lower interlayer dielectric layer 125. Therefore, on the peripheral circuit region PR, a via 190 can be formed to penetrate the second upper interlayer dielectric layer 145, the upper dielectric layer 140, the first upper interlayer dielectric layer 135, the protective dielectric layer 130, and the second lower interlayer dielectric layer 125. The via 190 may include a peripheral trench 192 extending in a direction parallel to the top surface 100U of the substrate 100 (e.g., second direction D2), and may also include contact holes 194 extending from the peripheral trench 192 toward the substrate 100. The contact holes 194 may be spaced apart from each other in a horizontal direction (e.g., second direction D2), and the peripheral trench 192 may be spatially connected to (e.g., multiple) the contact holes 194. The peripheral trench 192 can penetrate the second upper interlayer dielectric layer 145 and the upper dielectric layer 140, and can also penetrate the upper portion of the first upper interlayer dielectric layer 135. Each of the contact holes 194 can penetrate the first upper interlayer dielectric layer 135, the protective dielectric layer 130, and the second lower interlayer dielectric layer 125. The first etching process can continue until the lower dielectric layer 110 on the peripheral circuit region PR is exposed. Each of the contact holes 194 can expose the top surface of the lower dielectric layer 110.

[0085] Reference Figure 10 and Figure 11 During the first etching process, the sacrificial layer 170 can be etched at an etch rate greater than that of each of the second upper interlayer dielectric layer 145, the upper dielectric layer 140, the first upper interlayer dielectric layer 135, the protective dielectric layer 130, and the second lower interlayer dielectric layer 125. When the first etching process etches the sacrificial layer 170, the top surface of the second upper interlayer dielectric layer 145 located on the cell region CR and the peripheral circuit region PR can be exposed during the first etching process. In addition, on the peripheral circuit region PR, when the first etching process etches the sacrificial layer 170 filling the initial via PH, the side surfaces of each of the second upper interlayer dielectric layer 145, the upper dielectric layer 140, the first upper interlayer dielectric layer 135, the protective dielectric layer 130, and the second lower interlayer dielectric layer 125 can be exposed during the first etching process. In this case, while etching the second upper interlayer dielectric layer 145 and the upper dielectric layer 140 on the cell region CR during the first etching process, the first etching process can also etch the second upper interlayer dielectric layer 145, the upper dielectric layer 140, the first upper interlayer dielectric layer 135, the protective dielectric layer 130, and the second lower interlayer dielectric layer 125 on the peripheral circuit region PR. Therefore, the first etching process can simultaneously form the cell trench 180 on the cell region CR with the via 190 on the peripheral circuit region PR.

[0086] During the first etching process, the upper dielectric layer 140 can be etched at an etch rate lower than that of the first interlayer dielectric layer 135. In this case, during the first etching process, at least a portion of the first interlayer dielectric layer 135 located on the peripheral circuit region PR can be etched faster at its upper portion than at its side surface. For this purpose, the first interlayer dielectric layer 135 can have a stepped profile at a portion of its side surface.

[0087] Reference Figure 12 A second etching process can be performed to partially etch the protective dielectric layer 130 exposed in the cell trench 180 and the lower dielectric layer 110 exposed in the contact hole 194. Thus, the cell trench 180 can expose the top surface of the top electrode TE, and the contact hole 194 can expose the corresponding lower line 104 on the peripheral circuit region PR. According to some example embodiments, the second etching process can extend the cell trench 180 to the side surface of the top electrode TE and expose a portion of the side surface of the top electrode TE.

[0088] Return to reference Figure 2 and Figure 3 An upper line 150 and a peripheral line structure 160 can be formed in the unit slot 180 and the through hole 190, respectively. The upper line 150 may include an upper line pattern 154 and an upper barrier pattern 152 extending along the side and bottom surfaces of the upper line pattern 154. The peripheral line structure 160 may include a peripheral conductive pattern 164 and a peripheral barrier pattern 162 extending along the side and bottom surfaces of the peripheral conductive pattern 164. The peripheral conductive pattern 164 may include a line pattern LP in the peripheral slot 192 and a contact pattern CP in the contact hole 194.

[0089] The upper line 150 can be formed to have a third thickness 150T, which can be the vertical length measured along the first direction D1 from the bottom surface 150L of the upper line 150 to the top surface 150U of the upper line 150. The third thickness 150T of the upper line 150 can be approximately 1.0 to 2.2 times the second thickness DS_T of the data storage structure DS.

[0090] The formation of the upper line 150 and the peripheral line structure 160 may include: forming a barrier layer on the second interlayer dielectric layer 145 that partially fills the cell slots 180 and vias 190; forming a conductive layer on the barrier layer that fills the remaining portion of each of the cell slots 180 and vias 190; and performing a planarization process to planarize the conductive layer and the barrier layer until the top surface of the second interlayer dielectric layer 145 is exposed. The barrier layer may be formed to conformally cover the inner surface of each of the cell slots 180 and vias 190. The barrier layer may include a conductive metal nitride, and the conductive layer may include a metal (e.g., copper). The planarization process may be performed such that the top surface of the upper line pattern 154 and the uppermost surface of the upper barrier pattern 152 are substantially coplanar with the top surface of the second interlayer dielectric layer 145 located on the cell region CR. In addition, a planarization process can be performed so that the top surface of the peripheral conductive pattern 164 and the uppermost surface of the peripheral barrier pattern 162 can be substantially coplanar with the top surface of the second upper interlayer dielectric layer 145 located on the peripheral circuit region PR.

[0091] According to the present invention, the first thickness 120T of the lower contact plug 120 can be approximately 2.0 to 3.6 times the second thickness DS_T of the data storage structure DS, and the third thickness 150T of the upper line 150 can be approximately 1.0 to 2.2 times the second thickness DS_T of the data storage structure DS. In this case, it may be possible to reduce or minimize process defects caused by the increased aspect ratio of the lower contact plug 120, and also reduce or prevent the degradation of the characteristics of the magnetic tunnel junction pattern MTJ in the data storage structure DS. In addition, the data storage structure DS can be formed having the above-mentioned references. Figure 5A , Figure 5B or Figure 6 The outline of the discussion thus allows for the reduction or prevention of degradation of the characteristics of the magnetic tunnel junction pattern (MTJ) in the data storage structure (DS). As a result, a magnetic memory device and its manufacturing method with a structure capable of reducing or minimizing process defects and possessing excellent characteristics can be provided.

[0092] According to the present invention, it is possible to reduce or minimize process defects caused by the increased aspect ratio of the lower contact plug, and also to reduce or prevent the degradation of the characteristics of the magnetic tunnel junction pattern in the data storage structure. In summary, the present invention can provide a magnetic memory device and a method for manufacturing the same, having a structure that reduces or minimizes process defects and possesses excellent characteristics.

[0093] The foregoing description provides some exemplary embodiments to illustrate the inventive concept. Therefore, the inventive concept is not limited to the above embodiments, and those skilled in the art will understand that changes in form and detail may be made herein without departing from the spirit and essential characteristics of the inventive concept.

Claims

1. A magnetic memory device, comprising: The lower contact plug is located on the substrate; as well as The data storage structure is located on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure each have a first thickness and a second thickness in a first direction perpendicular to the top surface of the substrate. The first thickness is a vertical length measured from the bottom surface of the lower contact plug along the first direction to the top surface of the lower contact plug, and the second thickness is a vertical length measured from the bottom surface of the bottom electrode along the first direction to the top surface of the top electrode. Wherein, the first thickness of the lower contact plug is 2.0 to 3.6 times the second thickness of the data storage structure, and The magnetic tunnel junction pattern includes: Free layer; A pinning layer, located between the bottom electrode and the free layer; and A tunnel barrier layer, located between the pinned layer and the free layer. In a direction parallel to the top surface of the substrate, the middle portion of the pinning layer is wider than the upper portion and wider than the lower portion of the pinning layer. In a direction parallel to the top surface of the substrate, the upper portion of the free layer is wider than the lower portion of the free layer, and also wider than the tunnel barrier layer.

2. The magnetic memory device according to claim 1, further comprising: A lower line, located between the substrate and the lower contact plug, wherein the lower line connects the lower contact plug to the selection element; and An upline is located on the data storage structure, wherein the upline connects the data storage structure to a bit line.

3. The magnetic memory device according to claim 2, wherein: The bottom surface of the lower contact plug is in contact with the lower wire; The top surface of the lower contact plug contacts the bottom electrode of the data storage structure.

4. The magnetic memory device according to claim 2, wherein: The bottom surface of the bottom electrode contacts the lower contact plug; The top surface of the top electrode is in contact with the upper wire; The magnetic tunnel junction pattern is located between the bottom electrode and the top electrode.

5. The magnetic memory device according to claim 2, wherein, The upper line extends to the top surface of the top electrode and to a portion of the side surface of the top electrode.

6. The magnetic memory device according to claim 2, wherein, The upper line has a third thickness in the first direction, and wherein the third thickness of the upper line is 1.0 to 2.2 times the second thickness of the data storage structure.

7. The magnetic memory device according to claim 6, wherein: The bottom surface of the upper line contacts the top electrode of the data storage structure; and The third thickness is defined between the bottom surface of the upper line and the top surface of the upper line.

8. The magnetic memory device according to claim 2, further comprising: A first lower interlayer dielectric layer is located on the substrate and covers the lower line; The second lower interlayer dielectric layer is located on the first lower interlayer dielectric layer and covers the lower contact plug; as well as The lower dielectric layer is located between the first lower interlayer dielectric layer and the second lower interlayer dielectric layer. The data storage structure is located on the second lower interlayer dielectric layer. The lower contact plug penetrates the second lower interlayer dielectric layer and the lower dielectric layer, and contacts the lower wire. The second lower interlayer dielectric layer includes a recess located on one side of the data storage structure. In this embodiment, the lowest surface of the recess in the second lower interlayer dielectric layer is closer to the substrate than the top surface of the lower contact plug.

9. The magnetic memory device according to claim 8, wherein: The substrate includes a cell region and a peripheral circuit region; The lower line, the lower contact plug, the data storage structure, and the upper line are located on the cell area; The first lower interlayer dielectric layer, the second lower interlayer dielectric layer, and the lower dielectric layer cover the cell region and the peripheral circuit region; and The top surface of the second lower interlayer dielectric layer located on the peripheral circuit region is closer to the substrate than the bottom surface of the recess of the second lower interlayer dielectric layer located on the cell region.

10. The magnetic memory device according to claim 9, further comprising: A first upper interlayer dielectric layer is located on the second lower interlayer dielectric layer and covers the data storage structure; The second upper interlayer dielectric layer is located on the first upper interlayer dielectric layer and covers the upper line; as well as The upper dielectric layer is located between the first upper interlayer dielectric layer and the second upper interlayer dielectric layer. The upper line penetrates the second upper interlayer dielectric layer and the upper dielectric layer, and contacts the data storage structure. Wherein, the first upper interlayer dielectric layer, the second upper interlayer dielectric layer, and the upper dielectric layer cover the cell region and the peripheral circuit region, and Wherein, the first top surface of the upper dielectric layer located on the peripheral circuit region is closer to the substrate than the second top surface of the upper dielectric layer located on the cell region.

11. The magnetic memory device of claim 10, further comprising: A protective dielectric layer is located between the first upper interlayer dielectric layer and the side surface of the data storage structure, and between the first upper interlayer dielectric layer and the recess of the second lower interlayer dielectric layer on the cell region. The protective dielectric layer extends between the second lower interlayer dielectric layer and the first upper interlayer dielectric layer on the peripheral circuit region.

12. A magnetic memory device, comprising: A bottom electrode, a magnetic tunnel junction pattern, and a top electrode are sequentially stacked on a substrate. The magnetic tunnel junction pattern includes: Free layer; A pinning layer, located between the bottom electrode and the free layer; and A tunnel barrier layer, located between the pinned layer and the free layer. In a direction parallel to the top surface of the substrate, the middle portion of the pinning layer is wider than the upper portion and wider than the lower portion of the pinning layer. In a direction parallel to the top surface of the substrate, the upper portion of the free layer is wider than the lower portion of the free layer, and also wider than the tunnel barrier layer.

13. The magnetic memory device according to claim 12, wherein, In the direction parallel to the top surface of the substrate, the upper portion of the free layer is wider than the upper portion of the pinned layer, wider than the lower portion of the pinned layer, and wider than the middle portion of the pinned layer.

14. The magnetic memory device according to claim 12, wherein, The magnetic tunnel junction pattern also includes: A non-magnetic layer is located between the top electrode and the free layer; and A capping layer is located between the top electrode and the non-magnetic layer. The non-magnetic layer is wider than the lower portion of the free layer and wider than the tunnel barrier layer.

15. The magnetic memory device according to claim 14, wherein, In the direction parallel to the top surface of the substrate, the upper portion of the cover layer is narrower than the lower portion of the cover layer, and narrower than the non-magnetic layer.

16. The magnetic memory device according to claim 15, wherein, In the direction parallel to the top surface of the substrate, the upper portion of the top electrode is wider than the lower portion of the top electrode, but not wider than the upper portion of the cover layer.

17. The magnetic memory device according to claim 12, wherein: The pinning layer is a second pinning layer; and The magnetic tunnel junction pattern also includes: A first pinning layer, located between the bottom electrode and the second pinning layer; and A seed layer, located between the bottom electrode and the first pinning layer, The lower portion of the first pinning layer is wider than the upper portion of the first pinning layer.

18. The magnetic memory device according to claim 17, wherein, In the direction parallel to the top surface of the substrate, the lower portion of the first pinning layer is wider than the lower portion of the second pinning layer.

19. A magnetic memory device, comprising: The lower contact plug connects to the selection element on the substrate; as well as The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode sequentially stacked on the lower contact plug. The magnetic tunnel junction pattern includes: Free layer; A pinning layer, located between the bottom electrode and the free layer; and A tunnel barrier layer, located between the pinned layer and the free layer. In a direction parallel to the top surface of the substrate, the middle portion of the pinning layer is wider than the upper portion and wider than the lower portion of the pinning layer. In a direction parallel to the top surface of the substrate, the upper portion of the free layer is wider than the lower portion of the free layer, and also wider than the tunnel barrier layer.

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