Configurable control of integrated circuits

Abstract

According to one embodiment of the present disclosure, an integrated circuit includes a first word line decoder circuit and a second word line decoder circuit, one or more core arrays, a respective input / output (I / O) circuit for each of the one or more core arrays, and a control circuit coupled to the first word line decoder circuit and the second word line decoder circuit, the one or more core arrays, and the respective I / O circuits. Additionally, one or more control signals activated according to one or more control signals generated in the control circuit can be configured to select a corresponding one or more core arrays of the one or more core arrays.

Description

Technical Field

[0001] This disclosure generally relates to configurable control over integrated circuit devices. Background Technology

[0002] Technological advancements have led to smaller and more powerful computing devices. For example, a variety of personal computing devices, including cordless phones such as mobile phones and smartphones, game consoles, tablets, and laptops, are small, lightweight, and easily portable. These devices can transmit voice and data packets over wireless networks. Furthermore, many such devices incorporate additional features such as digital still cameras, digital video cameras, digital recorders, and audio file players. Additionally, such devices can process executable instructions, including software applications (such as web browser applications) that can be used to access the Internet. Therefore, these devices can include significant computing and networking capabilities. For such devices, there is a growing demand for greater efficiency in terms of memory storage capacity and power, performance, and area (PPA) of read / write operations. In one instance, for graphics processing units (GPUs), there is a persistent need in the art to reduce power supply voltage during various computational operations. Attached Figure Description

[0003] The present technology will be further described by way of example with reference to embodiments illustrated in the accompanying drawings. However, it should be understood that the drawings are merely illustrative of the various embodiments described herein and are not intended to limit the scope of the various technologies, methods, systems, circuits, or apparatuses described herein.

[0004] Figure 1 This is a schematic diagram of a portion of an example integrated circuit according to the various embodiments described herein.

[0005] Figure 2A It is based on the various embodiments described herein. Figure 1 A block diagram of a specific layer of an example integrated circuit.

[0006] Figure 2B It is based on the various embodiments described herein. Figure 2A Detailed block diagram of the layers.

[0007] Figure 2C These are schematic diagrams of circuits according to the various embodiments described herein.

[0008] Figure 3 This is a schematic diagram of a portion of an example integrated circuit according to the various embodiments described herein.

[0009] Figure 4A It is based on the various embodiments described herein. Figure 3 A block diagram of a specific layer of an example integrated circuit.

[0010] Figure 4B It is based on the various embodiments described herein. Figure 3 Detailed block diagram of the layers.

[0011] Figure 4C These are schematic diagrams of circuits according to the various embodiments described herein.

[0012] Figure 5 This is a schematic diagram of a portion of an example integrated circuit according to the various embodiments described herein.

[0013] Figure 6A It is based on the various embodiments described herein. Figure 5 A block diagram of a specific layer of an example integrated circuit.

[0014] Figure 6B It is based on the various embodiments described herein. Figure 6A Detailed block diagram of the layers.

[0015] Figure 6C These are schematic diagrams of circuits according to the various embodiments described herein.

[0016] Figure 7 These are schematic diagrams of circuits according to the various embodiments described herein.

[0017] Figure 8 These are schematic diagrams of circuits according to the various embodiments described herein.

[0018] Figures 9A-9B These are schematic diagrams of circuits according to the various embodiments described herein.

[0019] The following detailed description refers to the accompanying drawings, which form a part thereof, wherein similar reference numerals may indicate corresponding and / or similar parts throughout the drawings. It will be understood that the drawings are not necessarily drawn to scale, for example, to simplify and / or clarify the description. For example, the dimensions of some aspects may be enlarged relative to others. Furthermore, it is to be understood that other embodiments may be utilized. Additionally, structural changes and / or other modifications may be made without departing from the claimed subject matter. Throughout the specification, references to “claimed subject matter” refer to the subject matter intended to be covered by one or more claims or any part thereof, and are not necessarily intended to refer to the complete set of claims, a particular combination of claims (e.g., method claims, apparatus claims, etc.), or a particular claim. It should also be noted that directions and / or references, such as above, below, top, bottom, etc., may be used to facilitate the discussion of the drawings and are not intended to limit the application of the claimed subject matter. Therefore, the following detailed description is not considered to limit the claimed subject matter and / or its equivalents. Specific Implementation

[0020] Specific embodiments of the present disclosure are described below with reference to the accompanying drawings. Throughout the description, common features are indicated by common reference numerals.

[0021] Advantageously, certain aspects of the invention allow for power, performance, and area (PPA) optimized memory configurations for integrated circuits (e.g., graphics processing units (GPUs)). More specifically, in some cases, the integrated circuit may be a 272-word × 256-bit Turse execution engine general-purpose register file RAM (EE-GPRF-RAM). In other cases, the integrated circuit may be other memory types and / or have any size, including larger sizes (e.g., 512, 1024, 2048 bit units per row, or more than 272 rows) or smaller sizes (e.g., 128, 64, 32, 16, 8 bit units per row, or less than 272 rows).

[0022] Therefore, in certain schemes and techniques, as described herein, aspects of the invention allow for customization of the functionality of the “butterfly” EE-GPRF-RAM core array structure (via the circuit schematics in the control block circuitry and / or input / output circuitry) to control (e.g., activate for read operations) any sub-section of the memory core array (i.e., column groups, segments) in each execution cycle. In some embodiments, the sub-sections can have any granularity, including: 128, 64 (as referenced). Figure 5 and 6A - Figure 6C (as discussed), 32 (as referenced) Figure 3 and 4A - Figure 4C (as discussed), 16 (as referenced) Figure 1 and 2A - Figure 2C The discussed portion comprises 8, 4, or 2 bit unit sub-parts. In other schemes and techniques, aspects of the invention can also be implemented in any other core array structure. Therefore, such schemes and techniques are not limited to "butterfly" core arrays or RAM core arrays.

[0023] Furthermore, aspects of the invention allow for further customization (e.g., read functionality) by selecting the function of specific bit cell sub-sections or any number of consecutive or non-consecutive individual bit cells. In various instances, this can be achieved by including additional circuitry implemented in each input / output circuit of the example integrated circuit to read the mask schema (e.g., such as reference . Figure 7 , Figure 8 and Figures 9A-9B Each of the descriptions in the document is used to achieve this. Furthermore, further reference is made to... Figure 7 , Figure 8 and Figures 9A-9B This invention allows for the control and selection of specific bit units through each individual I / O circuit of an integrated circuit.

[0024] Reference Figure 1 and Figures 2A-2B This illustrates an example portion of integrated circuit 100 (e.g., the Turse Execution Engine (EE) General Purpose Register File Random Access Memory (EE-GPRF-RAM), a “butterfly architecture” that can be implemented on a system-on-a-chip (SoC). As... Figure 1 As shown, an example portion (e.g., a core array structure, "planar view") may include: control circuitry (i.e., the central block) ("CK") 110, a first word line decoder circuitry 112 and a second word line decoder circuitry 114, one or more core arrays 120 (e.g., 120a, 120b, etc.), and corresponding input / output circuitry (I / O circuitry) 130. In some embodiments, the control circuitry 110 may be coupled to the first word line decoder circuitry 112 and the second word line decoder circuitry 114, one or more core arrays 120, and the corresponding input / output circuitry 130. Additionally, one or more control signals 105 (e.g., 105a-105p) (i.e., sense amplifier driver signals, read mask signals) activated by one or more control signals (e.g., sense amplifier enable signals (NSAE)) generated in control circuit 110 can be configured to select one or more corresponding core arrays (e.g., 120a corresponding to the first core array (e.g., for both the upper 136 rows and the lower 136 rows), 120b corresponding to the second core array (e.g., for both the upper 136 rows and the lower 136 rows) etc.) (i.e., to provide independent control over each individual core array (e.g., 120a-120p) (e.g., core groupings).

[0025] like Figure 1 As shown, the example EE-GPRF-RAM memory can have 272 memory words × 256 bits (bit cells) per row. For example, as illustrated, the example 256 bits per row can be organized into 16 columns, with 8 columns on a first side (e.g., the "left" side of control circuitry 110) and 8 columns on a second side (e.g., the "right" side of control circuitry 110). Correspondingly, refer to Figure 1One or more core arrays 120 (e.g., 120a (e.g., for both the upper and lower 136 rows), 120b (e.g., for both the upper and lower 136 rows) etc.) can be organized into a first group (i.e., memory “blocks,” modules, segments, multiple core arrays) of eight memory columns 120a, 120b, 120c, 120d, 120e, 120f, 120g, 120h) on a first side, and a second group of eight memory columns 120i, 120j, 120k, 120l, 120m, 120n, 120o, 120p) on a second side. Therefore, in this example, each of the 16 columns can include a 16-bit group (i.e., 16-bit units per group) to obtain a total of 256 bits. However, in other examples where the total number of bit units per row is different (more or less bit units per row), the number of bit units per group will be different so that they can be evenly organized into 16 columns.

[0026] Advantageously, in Figure 1 In this invention, one or more control signals 105 (e.g., 105a-105p) can allow the functionality of "opening" (i.e., activating) 16-bit blocks at once (i.e., in one read cycle) (e.g., enabling 16-bit block read operations (i.e., read mask feature)). In contrast, in a memory without such a read mask feature, during a read operation, for example, all 256 bits (of a row) of integrated circuit 100 would be read for the same cycle. Therefore, power would be "wasted" (ineffectively used) for 240 bits (of a row). Thus, this aspect of the invention allows the functionality of reading 16 bits (bit cells) in a signal operation cycle (or multiples of 16 bits by activating multiple control signals). By doing so, such as through memory dynamic power breakdown comparison, this read mask feature can save up to 65% of clock power utilization. Additionally, further power savings can be achieved in terms of memory output pin power and system-on-chip (SoC) cache and line power.

[0027] In some implementations, refer to Figure 1 Each of the 16 core array groups (120a-120p) can be coupled to a corresponding input / output circuit (I / O circuit) 130 (130a-130p). Each of the I / O circuits 130 may include a sense amplifier driver circuit, a precharge circuit, a column multiplexer, and input and output latches. Additionally, each of the sense amplifier driver circuits may include a sense amplifier circuit and a write driver circuit.

[0028] In some respects, each of the first word line decoder block (circuit) 112 and the second word line decoder block (circuit) 114 may include post-word line decoder and driver circuitry. In certain cases, word line decoder blocks (circuits) 112, 114 may be configured to select word lines coupled to one or more core arrays 120 (120a, 120b, etc.) based on one or more control signals 105 (e.g., 105a to 105h) generated by control block 110.

[0029] Reference Figure 2A The figure illustrates an example "layer" of integrated circuit 100. As shown, example layers are provided to depict the overall positioning of the layers relative to each other, and are not drawn to scale or provided as an accurate graphical representation of any particular layer. Correspondingly, in Figure 2A In the example layer, the layer includes a layout configuration layer 210 (i.e., a column multiplexer layer), a first metal layer 220 (e.g., an M2 metal layer), and a second metal layer 230 (e.g., an M3 metal layer). In some embodiments, the first metal layer 220 may be coupled and positioned above the layout configuration layer 210, and the second metal layer 230 may be coupled and positioned above the first metal layer 220.

[0030] refer to Figure 2B It shows more details Figure 2A Each of the three layers 210, 220, and 230 of the integrated circuit 100. See the figure, refer to... Figure 1 An example layer may be provided to generally depict one or more specific control signals 105 (e.g., 105a-105h) that can be activated for one or more control signals (e.g., sense amplifier enable signals (NSAE)). In this example, up to 16 control signals (i.e., 16 NSAE signals (nsae-top[7:0] and nsae-bot[7:0]) 105 (105a-105p)) can be activated at a given time (within one cycle) to control the corresponding core array 120 (120a-120p) (i.e., 16-bit modules (groups, segments)) (wherein, for example, each 16-bit module comprises 16 bit units).

[0031] In operation, as referred to Figure 2BAs shown, initially, the control circuit (CK) 110 may send one or more control signals 105 (105a to 105p). One or more control signals 105 (105a-105p) are sent from the control block 110 on the layout configuration layer 210, "up" through the first metal layer 220, and further "up" to the second metal layer 230. Subsequently, the control signals 105 (105a-105p) are sent "down" from the second metal layer 230, through the first metal layer 220, and are received by a specific designated I / O circuit 130 (e.g., 130a-130p) corresponding to a specific bit cell group to be activated (e.g., 120a-120p).

[0032] like Figure 2B As shown, the first metal layer 220 (e.g., the M2 layer) and the second metal layer 230 can each receive eight control signals 105 (i.e., 105a-105h) (e.g., NSAETOP[0] to NSAETOP[7]) and eight control signals 105 (i.e., 105i-105p) (e.g., NSAEBOT[0] to NSAEBOT[7]) from the control circuit 110, which are to be sent to the corresponding I / O circuit 130 (130a). The corresponding column multiplexers ([0:15], [16:31], [32:47], [16:31], [48:63], [64:79], [80:95], [96:111], [112:127], [128:143], [144:159], [160:175], [176:191], [192:207], [208:223], [224:239], and [240:255]) of the -130p array are then used. Next, one or more activation control signals 105 will access one or more core arrays 120 (120a-120p) (i.e., the corresponding 16-bit modules) from the corresponding I / O circuits 130 for read operations.

[0033] Reference Figure 2C This illustrates the control signal 105 (Sense amplifier enable signal (NSAE)) for one or more control signals 105 (e.g., for the "top" signal (e.g., for the control amplifier enable signal (NSAE)). Figure 1The circuit implementation (circuit 290) of the core array 120a-h on the "left" side. In some instances, circuit 290 (i.e., the first read mask circuit schematic) may be provided in control block 110. As shown, circuit 290 may include NAND gate 292 that receives an initialization input signal (netsa) and a bit read enable mask (e.g., REN[7:0]) for specifying a particular column group to be activated. The output of NAND gate 292 will provide a sense amplifier signal (e.g., sae[7:0]), which can be inverted by inverter 294 to provide one or more control signals 105 (e.g., nsae-top[7:0]). Similarly, for one or more control signals 105 (sense amplifier enable signal (NSAE) (e.g., for the "bottom" signal ... Figure 1 The core array 120i-120p on the "right" side (105(ip)) will have another circuit implementation (not shown) in the control block 110.

[0034] refer to Figure 3 and Figures 4A-4B This illustrates an example portion of integrated circuit 300 (e.g., the Turse Execution Engine (EE) General Purpose Register File Random Access Memory (EE-GPRF-RAM), a “butterfly architecture” that can be implemented on a system-on-chip (SoC). As... Figure 3 As shown, an example portion (e.g., a core array structure, "planar view") may include: control circuitry (i.e., the central block) ("CK") 310, a first word line decoder circuitry 312 and a second word line decoder circuitry 314, one or more core arrays 320 (e.g., 320a to 320h) and corresponding input / output circuitry (I / O circuitry) 330 (e.g., 330a to 330h). In some embodiments, the control circuitry 310 may be coupled to the first word line decoder circuitry 312 and the second word line decoder circuitry 314, one or more core arrays 320, and the corresponding input / output circuitry 330. Additionally, one or more control signals 305 (e.g., 305a-305h) activated by one or more control signals (e.g., sense amplifier enable signal (NSAE)) generated in control circuit 310 (i.e., sense amplifier driver signal, read mask signal) can be configured to select one or more corresponding core arrays from one or more core arrays 320 (e.g., 320a corresponding to the first core array (e.g., for both the upper 136 rows and the lower 136 rows), 320b corresponding to the second core array (e.g., for both the upper 136 rows and the lower 136 rows) etc.) (i.e., to provide independent control over each individual core array (e.g., 320a-320h) (e.g., core grouping).

[0035] like Figure 3 As shown, the example EE-GPRF-RAM memory can have 272 memory words × 256 bits (bit cells) per row. For example, as shown, the example 256 bits per row can be organized into 8 columns, with 4 columns on the first side (e.g., the "left" side of control circuitry 310) and 4 columns on the second side (e.g., the "right" side of control circuitry 310). Correspondingly, refer to Figure 3 One or more core arrays 320 (e.g., 320a (e.g., for both the top 136 rows and the bottom 136 rows), 320b (e.g., for both the top 136 rows and the bottom 136 rows), etc.) can be organized into a first group (i.e., memory “blocks,” modules, segments, multiple core arrays) of four memory columns 320a, 320b, 320c, and 320d on a first side) and a second group of four memory columns 320e, 320f, 320g, and 320h on a second side. Thus, in this example, each of the eight columns can include a 32-bit group (i.e., a 32-bit cell group) to obtain a total of 256 bits. However, in other examples where the total number of bit cells per row differs (more or less bit cells per row), the number of bit cells in each group will differ so that they are evenly organized into eight columns.

[0036] Advantageously, in Figure 3 In this invention, one or more control signals 305 (305a-305h) can enable the function of "opening" (i.e., activating) a 32-bit block at once (i.e., in one read cycle) (e.g., enabling a read operation of a 32-bit block (i.e., a read mask feature)). In contrast, in a memory device without such a read mask feature, for example, all 256 bits (of a row) of integrated circuit 300 would be read for the same cycle, and therefore, power would be "wasted" (ineffectively used) for 232 bits (of a row). Therefore, this aspect of the invention allows the function of reading 32 bits (or multiples of 32 bits by activating multiple control signals) in a signal operation cycle. By doing so, such as through memory dynamic power cancellation (breakdown) comparison, this read mask feature can save up to 65% of clock power utilization. Additionally, further power savings can be achieved in terms of memory output pin power and system-on-chip (SoC) cache and line power.

[0037] In some implementations, refer to Figure 3Each of the eight core array groups (320a-320h) can be coupled to a corresponding input / output circuit (I / O circuit) 330 (330a-330h). Each of the I / O circuits 330 may include a sense amplifier driver circuit, a precharge circuit, a column multiplexer, and input and output latches. Additionally, each of the sense amplifier driver circuits may include a sense amplifier circuit and a write driver circuit.

[0038] In some respects, each of the first word line decoder block (circuit) 312 and the second word line decoder block (circuit) 314 may include post-word line decoder and driver circuitry. In certain cases, word line decoder blocks (circuits) 312, 314 may be configured to select word lines coupled to one or more core arrays 320 (320a, 320b, etc.) based on one or more control signals 305 (e.g., 305a to 305h) generated by control block 310.

[0039] Reference Figure 4A The figure illustrates an example "layer" of integrated circuit 300. As shown, example layers are provided to depict the overall positioning of the layers relative to each other, and are not drawn to scale or provided as an accurate graphical representation of any particular layer. Correspondingly, in Figure 4A In the example layer, the layer includes a layout configuration layer 410 (i.e., a column multiplexer layer), a first metal layer 420 (e.g., an M2 metal layer), and a second metal layer 430 (e.g., an M3 metal layer). In some embodiments, the first metal layer 420 may be coupled and positioned above the layout configuration layer 410, and the second metal layer 430 may be coupled and positioned above the first metal layer 420.

[0040] Reference Figure 4B It shows more details Figure 4A Each of the three layers 410, 420, and 430 of the integrated circuit 300. See the figure, refer to... Figure 3 An example layer can be provided to generally depict one or more specific control signals 305 (e.g., 305a-305h) that can be activated for one or more control signals (i.e., sense amplifier enable signals (NSAE)). In this example, up to eight control signals (i.e., eight NSAE signals) 305 (305a-305h) can be activated at a given time (within one cycle) to control the corresponding core array 320 (320a-320h) (i.e., 32-bit modules (groups, segments)) (wherein, for example, each 32-bit module comprises 32 bit units).

[0041] In operation, as referred to Figure 4BAs shown, initially, the control circuit (CK) 310 can send control signals 105 (105a to 105h). Control signals 105 (105a-105h) are sent from the control block 110 on the layout configuration layer 410, "up" through the first metal layer 420, and further "up": to the second metal layer 430. Subsequently, control signals 105 (105a-105h) are sent "down" from the second metal layer 430, through the first metal layer 420, and are received by specific I / O circuits 330 (e.g., 330a-330h) corresponding to specific bit cell groups to be activated (e.g., 320a-320h).

[0042] like Figure 4B As shown, the first metal layer 420 (e.g., the M2 layer) and the second metal layer 430 can each receive four control signals 305 (i.e., 305a-305d) (e.g., two instances of each of NSAETOP[0] to NSAETOP[3]) and four control signals 305 (i.e., 305e-305h) (e.g., two instances of each of NSAEBOT[0] to NSAEBOT[3]) from the control circuit 310, which are to be sent to the corresponding I / O circuit 33. The corresponding column multiplexers for 0 (330a-330h) ([0:15], [16:31], [32:47], [16:31], [48:63], [64:79], [80:95], [96:111], [112:127], [128:143], [144:159], [160:175], [176:191], [192:207], [208:223], [224:239], and [240:255]). Next, one or more activated control signals 305 will access one or more corresponding core arrays 320 (320a-320h) (i.e., the corresponding 32-bit modules) from the corresponding I / O circuits 330 for read operations.

[0043] Reference Figure 4C The diagram illustrates one or more control signals 305 (i.e., the sense amplifier enable signal (NSAE)) (e.g., for the "top" signal (e.g., for the...). Figure 3The circuit implementation (circuit 490) of the core array 320a-320d on the "left" side of the core array 305(ah) is described. In some cases, circuit 490 (i.e., the schematic of the first read mask circuit) may be provided in control block 310. As shown, circuit 490 may include NAND gate 492, which receives an initialization input signal (netsa) and a bit read enable mask (e.g., REN[3:0]) for specifying a particular column group to be activated. The output of NAND gate 492 will provide a sense amplifier signal (e.g., sae[3:0]), which can be inverted by inverter 494 to provide one or more control signals 305 (i.e., 305a-305d) (e.g., nsae-top[3:0]). Similarly, for one or more control signals 305 (sense amplifier enable signal (NSAE)) (e.g., for the "bottom" signal (e.g., for the "bottom" signal (e.g., for the "top" signal)). Figure 3 The core array 320e-320h on the "right" side (305(eh)) will have another circuit implementation (not shown) in the control block 310.

[0044] Reference Figure 5 and Figures 6A-6B This illustrates an example portion of the integrated circuit 500 (e.g., the Turse Execution Engine (EE) General Purpose Register File Random Access Memory (EE-GPRF-RAM), a “butterfly architecture” that can be implemented on a System-on-Chip (SoC). As... Figure 5As shown, integrated circuit 500 may include a core array structure comprising: a control circuit (i.e., a central block) (“CK”) 510, a first word line decoder circuit 512 and a second word line decoder circuit 514, one or more core arrays 520 (e.g., 520a to 520d) and corresponding input / output circuits (I / O circuits) 530 (e.g., 530a to 530d). In some embodiments, the control circuit 510 may be coupled to the first word line decoder circuit 512 and the second word line decoder circuit 514, one or more core arrays 520 and corresponding input / output circuits 530. Additionally, one or more control signals 505 (e.g., 505a-505d) (i.e., sense amplifier driver signals, read mask signals) activated by one or more control signals (e.g., sense amplifier enable signals (NSAE)) generated in control circuit 510 can be configured to select one or more corresponding core arrays of one or more core arrays 520 (e.g., 520a corresponding to the first core array (e.g., for both the upper 136 rows and the lower 136 rows), 520b corresponding to the second core array (e.g., for both the upper 136 rows and the lower 136 rows) etc.) (i.e., to provide independent control over each individual core array (e.g., 520a to 520d) (e.g., core groupings).

[0045] like Figure 5 As shown, the example EE-GPRF-RAM memory can have 272 memory words × 256 bits (bit cells) per row. For example, as illustrated, the example 256 bits per row can be organized into 4 columns, with 2 columns on the first side (e.g., as shown on the "left" side of control circuitry 510) and 2 columns on the second side (e.g., as shown on the "right" side of control circuitry 510). Correspondingly, refer to Figure 5 One or more core arrays 520 (e.g., 520a (e.g., for both the top 136 rows and the bottom 136 rows), 520b (e.g., for both the top 136 rows and the bottom 136 rows) etc.) can be organized into a first group (i.e., memory “blocks,” modules, segments, multiple core arrays) of two memory columns 520a and 520b on a first side and a second group of two memory columns 520c and 520d on a second side. Thus, in this example, each of the four columns can include a 64-bit group (i.e., a 64-bit cell group) to obtain a total of 256 bits. However, in other examples where the total number of bit cells per row is different (more or less bit cells per row), the number of bit cells in each group will be different so that they are evenly organized into four columns.

[0046] Advantageously, in Figure 5In this invention, one or more control signals 505 (505a-505d) can enable the functionality of "opening" (i.e., activating) a 64-bit block at once (i.e., in one read cycle) (e.g., enabling a 64-bit block read operation (i.e., a read mask feature)). In contrast, in a memory device without such a read mask feature, for example, all 256 bits (of a row) of integrated circuit 500 would be read for the same cycle, and therefore, power would be "wasted" (ineffectively used) for 192 bits of a row. Therefore, this aspect of the invention allows the functionality of reading 64 bits (or multiples of 64 bits by activating multiple control signals) in a signal operation cycle. By doing so, such a read mask feature can save up to 65% of clock power utilization, as achieved through memory dynamic power decomposition comparison. Additionally, further power savings can be achieved in terms of memory output pin power and system-on-chip (SoC) cache and line power.

[0047] In some implementations, refer to Figure 5 Each of the four core array groups (520a-520d) can be coupled to a corresponding input / output circuit (I / O circuit) 530 (530a-530d). Each of the I / O circuits 530 may include a sense amplifier driver circuit, a precharge circuit, a column multiplexer, and input and output latches. Additionally, each of the sense amplifier driver circuits may include a sense amplifier circuit and a write driver circuit.

[0048] In some respects, each of the first word line decoder block (circuit) 512 and the second word line decoder block (circuit) 514 may include post-word line decoder and driver circuitry. In certain cases, word line decoder blocks (circuits) 512, 514 may be configured to select word lines coupled to one or more core arrays 520 (520a to 520d) based on one or more control signals 505 (e.g., 505a-505d) generated by control block 510.

[0049] Reference Figure 6A The figure illustrates an example "layer" of integrated circuit 500. As shown, example layers are provided to depict the overall positioning of the layers relative to each other, and are not drawn to scale or provided as an accurate graphical representation of any particular layer. Correspondingly, in Figure 6A In the example layer, the layer includes a layout configuration layer 610 (i.e., a column multiplexer layer), a first metal layer 620 (e.g., an M2 metal layer), and a second metal layer 630 (e.g., an M3 metal layer). In some embodiments, the first metal layer 620 may be coupled and positioned above the layout configuration layer 610, and the second metal layer 630 may be coupled and positioned above the first metal layer 620.

[0050] Reference Figure 6B It shows more details Figure 6A Each of the three layers 610, 620, and 630 of the integrated circuit 300. See the figure, refer to... Figure 6B An example layer can be provided to generally depict one or more specific control signals 505 (e.g., 505a-505d) that can be activated from one or more control signals (i.e., sense amplifier enable signals (NSAE)). In this example, up to four control signals (i.e., four NSAE signals) 505 (505a-505d) can be activated at a given time (within one cycle) to control the corresponding core array 520 (520a-520d) (i.e., 64-bit modules (groups, segments)) (wherein, for example, each 64-bit module comprises 64 bit units).

[0051] In operation, as referred to Figure 6B As shown, initially, the control circuit (CK) 610 can send control signals 605 (605a to 605d). Control signals 605 (605a to 605d) are sent from the control block 510 on the layout configuration layer 610, upwards through the first metal layer 620, and further upwards to the second metal layer 630. Subsequently, control signals 605 (605a to 605d) are sent downwards from the second metal layer 630, through the first metal layer 620, and are received by specific I / O circuits 530 (e.g., 530a to 530d) corresponding to specific bit cell groups to be activated (e.g., 520a to 520d).

[0052] like Figure 6BAs shown, the first metal layer 620 (e.g., layer M2) and the second metal layer 630 (e.g., layer M3) can each receive two control signals 505 (i.e., 505a-505d) from the control circuit 510 (e.g., two instances of each of NSAETOP[0] to NSAETOP[1] and two instances of each of NSAEBOT[0] to NSAEBOT[1]), which are to be sent to the corresponding I / O circuits 530 (530a-505d). The corresponding column multiplexers of 530d ([0:15], [16:31], [32:47], [16:31], [48:63], [64:79], [80:95], [96:111], [112:127], [128:143], [144:159], [160:175], [176:191], [192:207], [208:223], [224:239], and [240:255]). Next, one or more activated control signals 505 will access one or more corresponding core arrays 520 (520a-520d) (i.e., the corresponding 64-bit modules) from the corresponding I / O circuits 530 for read operations.

[0053] Reference Figure 6C The diagram illustrates one or more control signals 505 (i.e., the sense amplifier enable signal (NSAE)) (e.g., for the "top" signal (e.g., for the...). Figure 5 The circuit implementation (circuit 690) of the core arrays 520a-520b on the "left" side of the core arrays 505a-505b. In some cases, circuit 690 (i.e., the first read mask circuit schematic) may be provided in control block 510. As shown, circuit 690 may include NAND gate 692, which receives an initialization input signal (netsa) and a bit read enable mask (e.g., REN[1:0]) for specifying a particular column group to be activated; the output of NAND gate 692 will provide a sense amplifier signal (e.g., sae[1:0]), which may be inverted by inverter 694 to provide one or more control signals 505 (e.g., nsae-top[1:0]). Similarly, for one or more control signals 505 (sense amplifier enable signal (NSAE)) (e.g., for the "bottom" signal (e.g., for the... Figure 5 The core array 320c-320d on the "right side" of the core array 505(cd) will have another circuit implementation (not shown) in the control block 510.

[0054] Reference Figure 7The diagram illustrates circuit 700 (i.e., the schematic of the first alternative second readmask circuit). Circuit 700 can be implemented simultaneously with or independently of circuits 290, 490, 690 (such as those implemented within example control blocks 110, 310, and 510 to generate and activate control signals 105, 305, and 505). In some embodiments, reference is made to... Figure 1 , Figure 3 and Figure 5 Circuit 700 can be coupled within each column multiplexer of the I / O circuits (130, 330, 530). Advantageously, circuit 700 allows for more flexible usage in dividing bits into a variable number of segments. For example, circuit 700 allows for specific selection of one or more bit cells within a corresponding active core array. Thus, independent control of each specific bit cell in a particular core array group can be achieved. Furthermore, the implementation of circuit 700 can be carried out by the circuit designer without requiring additional changes to the corresponding sense amplifier driver circuitry.

[0055] As shown in the figure, circuit 700 may include a read / write enable latch 710, a first inverter 712 and a second inverter 714, a NOR gate 720, and a NAND gate 730. In one operation, a read / write enable bit (signal) can be input to latch 710, and the output of latch 710 can be inverted and input to NOR gate 720 along with one or more control signals (nsae) to generate a sense amplifier enable signal (sae). Additionally, the output of latch 710 will also be inverted and input to NAND gate 730 along with a write enable clock (wclk) to generate a write driver signal (we_nwclkc). Correspondingly, the read / write enable bit (e.g., read[n-1:0]) can be used to control both the sense amplifier enable (SAE) signal and the write driver signal. For example, when the write enable is "active low," the digital "1" will be on the input, the read latch 710 will be "1," and therefore, the sense amplifier will be "clamped" low, and the write clock will be clamped to "1." Thus, both read and write operations can be disabled. In a specific aspect, circuit 700 can perform a bit write mask during the write cycle and a bit read mask during the read cycle. Furthermore, the bit write mask input and latch can be reused.

[0056] In one instance, when circuit 700 (or circuit 800, and combinations of circuits 900, 950 as discussed in the following paragraphs) can be implemented simultaneously with circuit 290 (or circuits 490, 690) in example integrated circuits (e.g., integrated circuits 100, 300, 500), one or more control signals will be activated according to the control block circuits (e.g., control block circuits 110, 310, 510). In this instance, the control logic for the integrated circuit will be the same as the control logic without circuit 700; however, the number of activated control signals (i.e., NSAE control signals) is different.

[0057] In another example, when circuit 700 (or circuit 800, and combinations of circuits 900, 950 as discussed in the following paragraphs) can be implemented with example integrated circuits (e.g., integrated circuits 100, 300, and 500) and without circuit 290 (or circuits 490, 690) in control block circuits (e.g., corresponding control block circuits 110, 310, and 510), there will be a single activation signal (i.e., a single NSAE control signal) that will be controlled by the RWEN input in each I / O circuit (e.g., I / O circuits 130, 330, 530). Therefore, in this example, each of the I / O circuits will individually control the selection and read operations for the integrated circuit.

[0058] Reference Figure 8 The circuit 800 is shown as ( Figure 7 A second alternative to the second read mask circuit schematic is shown. As illustrated, circuit 800 includes a variant of circuit 700, which can alternatively be implemented simultaneously with or independently of circuits 290, 490, and 690 (as implemented within example control blocks (e.g., control blocks 110, 310, and 510)) to generate and activate one or more control signals (e.g., control signals 105, 305, and 505). In a particular embodiment, reference is made to... Figure 1 , Figure 3 and Figure 5 Circuit 800 can be coupled within each column multiplexer of the I / O circuits (130, 330, 530). Advantageously, circuit 800 allows for more flexible usage in dividing bits into a variable number of segments. For example, circuit 800 can allow for specific selection of one or more bit cells within a corresponding active core array (120, 320, 520). Thus, independent control of each specific bit cell in a particular core array group can be achieved. Furthermore, the implementation of circuit 800 can be carried out by the circuit designer without requiring additional changes to the corresponding sense amplifier driver circuitry.

[0059] As shown in the figure, similar to circuit 700, circuit 800 may include a read / write enable (rwen) latch 810, a first inverter 812 and a second inverter 814, a NOR gate 820, and a NAND gate 830. Correspondingly, circuit 800 may additionally include a write clock (wclk) and a read enable clock (ren_clk) input to a third inverter 842 and a fourth inverter 844, the outputs of which are input to a second NAND gate 850. The output of NAND gate 850 is input to the rwen latch 810. Advantageously, circuit 800 provides a locally generated clock (rwen_clk) for the rwen latch 810, which improves internal contention tolerance.

[0060] Reference Figures 9A-9B Two circuit implementations, 900 and 950, are shown as ( Figure 7 The third alternative to the second read mask circuit schematic is shown. Advantageously, circuits 900 and 950 illustrate separate read bit enable latches (900) and separate write enable latches (950). Similar to... Figure 7 and Figure 8 Two circuit implementation methods 900 (in Figure 9A in) and 950 (in Figure 9B Together with circuit 700, it can be a variant of circuit 700, which can be alternatively implemented simultaneously or independently with circuits 290, 490, 690 (as implemented within example control blocks (e.g., control blocks 110, 310, and 510)) to generate and activate one or more control signals (e.g., control signals 105, 305, and 505). In some embodiments, refer to Figure 1 , Figure 3 and Figure 5 Circuits 900 and 950 can be coupled in combination within each column multiplexer of the I / O circuits (130, 330, 530). Advantageously, the combination of circuits 900 and 950 allows for more flexible use in dividing bits into a variable number of segments. For example, circuits 900 and 950 allow for specific selection of one or more bit cells within the corresponding active core array. Thus, independent control of each specific bit cell in a specific core array group can be achieved. Furthermore, the implementation of circuits 900 and 950 can be carried out by the circuit designer without additional changes to the corresponding sense amplifier driver circuitry.

[0061] Circuit 900 may include a read enable latch 910, an inverter 912, and a NAND gate 920. In operation, a sense enable signal (SAE) can be generated in circuit 900 based on a read enable bit, a read enable clock, and one or more control signals (NSAE). Circuit 950 may include a write enable latch 960, an inverter 912, and a NAND gate 970. In operation, a write driver signal (we_nwclkc) can be generated in circuit 950 based on a write enable bit (wen) and a write enable clock (wclk).

[0062] In such Figures 1-9B Other circuit implementations are also envisioned in other solutions and techniques of the present invention described herein. Furthermore, the present invention can utilize this integrated circuit in combination with various standard macros to reduce power, performance, and area (PPA) constraints.

[0063] According to one embodiment of this disclosure, an integrated circuit includes a first word line decoder circuit and a second word line decoder circuit; one or more core arrays; corresponding input / output (I / O) circuitry for each of the one or more core arrays; and control circuitry coupled to the first word line decoder circuit, the second word line decoder circuit, the one or more core arrays, and the corresponding I / O circuitry. Furthermore, one or more control signals activated by one or more control signals generated in the control circuitry can be configured to select a corresponding one or more core arrays.

[0064] According to one embodiment of the present invention, an integrated circuit includes: a first word line decoder circuit and a second word line decoder circuit; one or more core arrays coupled to each of the first word line decoder circuit and the second word line decoder circuit; and corresponding input / output (I / O) circuitry for each of the one or more core arrays. Furthermore, one or more control signals generated according to an activation signal sent from a control block circuit can be configured in one or more of the corresponding I / O circuits to select one or more bit cells of the one or more core arrays.

[0065] In the example implementation, it has already been... Figures 1-9B Certain circuit elements are provided herein, and their redundant descriptions are not repeated in the related descriptions of similar circuit elements herein. It is explicitly included that the same circuit elements having the same symbols and / or reference numerals are included in the corresponding drawings for each embodiment.

[0066] although Figures 1-9B One or more of these may illustrate a system or apparatus according to the teachings of this disclosure, but this disclosure is not limited to these illustrated systems or apparatuses. As shown or described herein Figures 1 to 9B One or more functions or components of any image in the diagram can be related to Figures 1 to 9B The embodiments described herein are combinations of one or more other portions of another figure. Therefore, the individual embodiments described herein should not be construed as limiting, and embodiments of this disclosure can be appropriately combined without departing from the teachings of this disclosure.

[0067] The block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present disclosure. In this regard, each block in the block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions marked in the blocks in the figures may not occur in the order indicated in the figures. For example, depending on the function involved, two blocks shown consecutively may be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagram, and combinations of blocks in the block diagram, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0068] In the following description, numerous specific details are set forth to provide a thorough understanding of the disclosed concepts, which can be practiced without some or all of these details. In other instances, details of known devices and / or processes have been omitted to avoid unnecessarily obscuring this disclosure. While some concepts will be described in conjunction with specific examples, it will be understood that these examples are not intended to be limiting.

[0069] Unless otherwise stated, the terms “first,” “second,” etc., are used herein as illustrative purposes only and are not intended to impose any order, position, or hierarchy requirements on the items referred to by these terms. Furthermore, a reference to an item such as “second” does not require or exclude the existence of an item such as “first” or a lower-numbered item and / or an item such as “third” or a higher-numbered item.

[0070] The reference to "an example" herein means that one or more features, structures, or characteristics described in connection with that example are included in at least one implementation. The phrase "an example" throughout the specification may or may not refer to the same example.

[0071] Those skilled in the art will further understand that the various illustrative logic blocks, configurations, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software executed by a processor, or a combination of both. The various illustrative components, blocks, configurations, modules, circuits, and steps have been generally described above in terms of their functionality. Whether this functionality is implemented as hardware or processor-executable instructions depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0072] The steps of the methods or algorithms used in conjunction with the disclosure herein can be implemented directly in hardware, in a software module executed by a processor, or in a combination of both. The software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, optical disc read-only memory (CD-ROM), or any other form of non-transitory storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an application-specific integrated circuit (ASIC). The ASIC can reside in a computing device or user terminal. Alternatively, the processor and storage medium can reside as discrete components in a computing device or user terminal.

[0073] The foregoing description is provided to enable those skilled in the art to form or use the disclosed embodiments. Various modifications to these embodiments will be apparent to those skilled in the art, and the principles defined herein can be applied to other embodiments without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments shown herein, but should be given the widest possible scope consistent with the principles and novel features as defined by the appended claims.

Claims

1. An integrated circuit, comprising: First word line decoder circuit and second word line decoder circuit; One or more core arrays; Corresponding input / output I / O circuits, each I / O circuit being used for each of the one or more core arrays; as well as A control circuit coupled to the first word line decoder circuit and the second word line decoder circuit, the one or more core arrays and the corresponding I / O circuits, wherein one or more control signals activated according to one or more control signals generated in the control circuit are configured to select a corresponding one or more sub-sections in the one or more core arrays, each sub-section comprising one or more bit units.

2. The integrated circuit of claim 1, wherein each of the input / output circuits comprises: The circuitry includes a readout amplifier, a precharge circuit, a column multiplexer, and input and output latches.

3. The integrated circuit according to claim 2, further comprising: Column multiplexer layer; First metal layer; as well as A second metal layer, wherein the first metal layer is coupled and positioned above the column multiplexer layer, and wherein the second metal layer is coupled and positioned above the first metal layer.

4. The integrated circuit of claim 3, wherein the first metal layer and the second metal layer are configured to send the one or more control signals from the control block circuit to the input / output circuit.

5. The integrated circuit of claim 1, wherein the one or more core arrays comprise sixteen core arrays, wherein the one or more control signals comprise sixteen corresponding control signals, and wherein each of the one or more core arrays comprises sixteen bit units in each row.

6. The integrated circuit of claim 5, wherein the one or more control signals are configured to read up to sixteen bit units per line per execution cycle.

7. The integrated circuit of claim 5, wherein the one or more control signals are configured to control a corresponding one or more core arrays among the sixteen core arrays.

8. The integrated circuit of claim 1, wherein the one or more core arrays comprise eight core arrays, wherein the one or more control signals comprise eight corresponding control signals, and wherein each of the one or more core arrays comprises thirty-two bit units per row.

9. The integrated circuit of claim 8, wherein the one or more control signals are configured to control a corresponding one or more core arrays among the eight core arrays.

10. The integrated circuit of claim 8, wherein the one or more control signals are configured to read up to thirty-two bit units per line in each execution cycle.

11. The integrated circuit of claim 1, wherein the one or more core arrays comprise four core arrays, wherein the one or more control signals comprise four corresponding control signals, and wherein each of the one or more core arrays comprises sixty-four bit units in each row.

12. The integrated circuit of claim 11, wherein the one or more control signals are configured to control one or more of the four core arrays.

13. The integrated circuit of claim 11, wherein the one or more control signals are configured to read up to sixty-four bit units per line per execution cycle.

14. The integrated circuit of claim 1, wherein each of the respective I / O circuits includes a second control circuit, wherein the second control circuit is configured to generate one or more second control signals for controlling the selection of one or more bit cells of a selected one or more core arrays.

15. The integrated circuit of claim 14, wherein the one or more bit units are non-contiguous bit units.

16. The integrated circuit of claim 15, wherein the second control circuit includes a read / write bit enable latch, wherein the output signal of the read / write bit enable latch is configured to control the corresponding I / O circuit for selecting the one or more bit cells.

17. The integrated circuit of claim 15, wherein the second control circuit includes a first clock signal and a second clock signal input to a read / write bit enable latch, wherein the output signal of the read / write bit enable latch is configured to control the corresponding I / O circuit for selecting the one or more bit cells.

18. The integrated circuit of claim 15, wherein the second control circuit includes a first latch and a second latch, wherein the first latch is a read enable latch and the second latch is a write enable latch, wherein the output signal of the read enable latch is configured to control the corresponding I / O circuit to perform a read operation of the one or more bit units, and wherein the output signal of the write enable latch is configured to control the corresponding I / O circuit to perform a write operation of the one or more bit units.

19. An integrated circuit, comprising: First word line decoder circuit and second word line decoder circuit; One or more core arrays, said one or more core arrays being coupled to each of the first word line decoder circuit and the second word line decoder circuit; as well as Corresponding input / output I / O circuits, wherein one or more control signals generated according to an activation signal sent from a control block circuit are configured to select one or more bit cells of the one or more core arrays in one or more of the corresponding I / O circuits.

20. The integrated circuit of claim 19, wherein the respective I / O circuit is configured to individually control the selection of the one or more bit units, and wherein the control block circuit is disposed separately from each of the respective I / O circuits.

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