Impedance calibration circuit and storage device including impedance calibration circuit

Abstract

An impedance calibration circuit includes: a first code generation circuit connected to a first reference resistor and configured to: generate a first code for forming a resistance based on the first reference resistor using the first reference resistor; a second code generation circuit configured to: form a resistance of a second reference resistor smaller than the resistance of the first reference resistor based on the first code, and generate a second code using the second reference resistor; and a target impedance code generation circuit configured to: generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit based on the target impedance code.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0013730, filed on February 5, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to an impedance calibration circuit, an impedance calibration method performed by the impedance calibration circuit, and a storage device, and more specifically, to an impedance calibration circuit that forms a target impedance by using a reference resistor, an impedance calibration method performed by the impedance calibration circuit, and a storage device including the impedance calibration circuit. Background Technology

[0004] As the operating speed of semiconductor memory devices increases, the swing of signals transmitted and received between the semiconductor memory device and the controller decreases, and signal distortion due to impedance mismatch can become severe. To address this signal distortion, impedance calibration is being investigated, in which the output and / or termination impedance of the semiconductor memory device is continuously adjusted using an external resistor, making the output and / or termination impedance independent of variations in process, voltage, and temperature (PVT). This impedance calibration operation can be referred to as input / output mismatch elimination or ZQ calibration.

[0005] As the operating speed of semiconductor memory devices gradually increases, it is necessary to accurately provide the impedance calibration circuits that perform impedance calibration operations with the required target impedance value. Summary of the Invention

[0006] The present invention provides an impedance calibration circuit, an impedance calibration method performed by the impedance calibration circuit, and a storage device including the impedance calibration circuit for providing reliable termination impedance for a wide range of target impedance values, and reducing the driver area and capacitance of the output terminal with termination impedance.

[0007] According to one aspect of the present invention, an impedance calibration circuit is provided, comprising: a first code generation circuit connected to a first reference resistor, and the first code generation circuit being configured to: generate a first code for forming a resistance based on the first reference resistor using the first reference resistor; a second code generation circuit being configured to: form a resistance of a second reference resistor less than the resistance of the first reference resistor based on the first code, and generate a second code using the second reference resistor; and a target impedance code generation circuit being configured to: generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit based on the target impedance code.

[0008] According to another aspect of the present invention, an impedance calibration circuit is provided, comprising: a first code generation circuit configured to generate a first code using a first reference resistor and to form a resistance based on the first reference resistor and the first code; a second code generation circuit including a plurality of ZQ pull-up drivers configured to form a resistance of a second reference resistor based on the first code, the second code generation circuit being configured to generate a second code using the second reference resistor; and a target impedance code generation circuit configured to select a code from the first code and the second code based on a comparison of a target impedance value with a threshold impedance value, and to generate a target impedance code based on the selected code, and to form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit. Each ZQ pull-up driver includes one or more PMOS transistors or one or more NMOS transistors.

[0009] According to another aspect of the present invention, a storage device is provided, comprising: a storage cell region including a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the storage cell region via the first metal pad and the second metal pad; a first code generation circuit in the peripheral circuit region connected to a first reference resistor and configured to: generate a first pull-up code for forming a resistance based on the first reference resistor in at least one ZQ pull-up driver, and generate a first pull-down code for forming the resistance based on the first reference resistor in at least one ZQ pull-down driver, using the first reference resistor; a second code generation circuit in the peripheral circuit region configured to: generate a second pull-up code and a second pull-down code for forming a resistance of a second reference resistor based on the first pull-up code or the first pull-down code, using the second reference resistor; and a target impedance code in the peripheral circuit region. The generation circuit is configured to: generate a target impedance pull-up code based on the first pull-up code, the second pull-up code, and the target impedance value; and generate a target impedance pull-down code based on the first pull-down code, the second pull-down code, and the target impedance value; a plurality of DQ pins in the peripheral circuit region are used to send or receive data from or located in the storage device; a plurality of target pull-up drivers in the peripheral circuit region, each target pull-up driver being connected to a corresponding DQ pin among the plurality of DQ pins, and each target pull-up driver being configured to: form a target pull-up impedance corresponding to the target impedance value based on the target impedance pull-up code; and a plurality of target pull-down drivers in the peripheral circuit region, each target pull-down driver being connected to a corresponding DQ pin among the plurality of DQ pins, and each target pull-down driver being configured to: form a target pull-down impedance corresponding to the target impedance value based on the target impedance pull-down code.

[0010] According to another aspect of the present invention, an impedance calibration method is provided, performed by an impedance calibration circuit in a storage device, the storage device comprising: a storage cell region including a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the storage cell region via the first metal pad and the second metal pad; the impedance calibration circuit being connected to a first reference resistor, the impedance calibration method comprising: generating a first code for forming a resistance based on the first reference resistor using the first reference resistor; forming a resistance of a second reference resistor based on the first code, and generating a second code using the second reference resistor; and generating a target impedance code corresponding to the target impedance value based on the first code, the second code, and a target impedance value.

[0011] According to another aspect of the present invention, a circuit is provided in a storage device, the storage device comprising: a storage cell region including a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the storage cell region via the first metal pad and the second metal pad; the circuit including a pull-down driver in the peripheral circuit region, the pull-down driver forming a pull-down impedance between a ground node and a first node based on a pull-down code; multiple pull-up drivers in the peripheral circuit region including a plurality of pull-up drivers connected in parallel between a drive voltage node and the first node, wherein the plurality of pull-up drivers have the same configuration; a comparator in the peripheral circuit region configured to: compare the voltage of the first node with a reference voltage and output the comparison result; and a code generation circuit in the peripheral circuit region connected to the comparator and configured to: generate the pull-down code and provide the pull-down code to the pull-down driver.

[0012] According to another aspect of the present invention, a circuit is provided, comprising: a pull-up driver that forms a pull-up impedance between a drive voltage node and a first node based on a pull-up code; multiple pull-down drivers including a plurality of pull-down drivers connected in parallel between a ground node and the first node, wherein the plurality of pull-down drivers have the same configuration; a comparator configured to compare the voltage of the first node with a reference voltage and output the comparison result; and a code generation circuit connected to the comparator and configured to generate the pull-up code and provide the pull-up code to the pull-up driver. Attached Figure Description

[0013] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a block diagram of an impedance calibration circuit according to an embodiment of the present invention.

[0015] Figure 2A and Figure 2B This is a block diagram of a first code generation circuit according to an embodiment of the present invention.

[0016] Figure 3 This is a circuit diagram of a pull-up driver according to an embodiment of the present invention.

[0017] Figure 4 This is a circuit diagram of a pull-down driver according to an embodiment of the present invention.

[0018] Figure 5This is a block diagram of a second code generation circuit according to an embodiment of the present invention.

[0019] Figure 6 This is a circuit diagram of a termination driver according to an embodiment of the present invention.

[0020] Figure 7 This is a block diagram of a second reference resistor forming circuit according to an embodiment of the present invention.

[0021] Figure 8 This is a block diagram of a second code generation circuit according to an embodiment of the present invention.

[0022] Figure 9 This is a block diagram of a second reference resistor forming circuit according to an embodiment of the present invention.

[0023] Figure 10 This is a block diagram of a target impedance code generation circuit according to an embodiment of the present invention.

[0024] Figure 11 This is a circuit diagram of a pull-up decoder according to an embodiment of the present invention.

[0025] Figure 12 This is a circuit diagram of a pull-down decoder according to an embodiment of the present invention.

[0026] Figure 13 This is a flowchart of an impedance calibration method performed by an impedance calibration circuit according to an embodiment of the present invention;

[0027] Figure 14 This is a flowchart of an impedance calibration method performed by an impedance calibration circuit according to an embodiment of the present invention.

[0028] Figure 15 This is a block diagram of a storage device according to an embodiment of the concept of the present invention;

[0029] Figure 16 This is a block diagram of a storage system according to an exemplary embodiment of the present invention; and

[0030] Figure 17 This is a cross-sectional view showing an exemplary embodiment of a storage device according to a concept conceived in the present invention. Detailed Implementation

[0031] In the following description, the inventive concept will be more fully described with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are illustrated.

[0032] Figure 1This is a block diagram of an impedance calibration circuit 20 according to an embodiment of the present invention. The impedance calibration circuit 10 may include a first code generation circuit 100, a second code generation circuit 200, a target impedance code generation circuit 300, and a termination driver 400. The impedance calibration circuit 10 can provide a termination impedance with a target impedance value R_tar to the output terminal OUT using an external resistor R_ZQ. The impedance calibration circuit 10 can be implemented in a device at the output terminal OUT that requires a termination impedance with a specific impedance value. For example, the impedance calibration circuit 10 can be implemented in… Figure 15 The memory devices shown are implemented in the memory devices, etc. As used herein, a memory device (and other devices described herein) may refer to a device such as a semiconductor chip forming an integrated circuit (e.g., a memory chip and / or logic chip formed from a wafer), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips stacked on a package substrate, or a multilayer package device including multiple packages.

[0033] The first code generation circuit 100 can generate a first code Code_1 using a first reference resistor. As used herein, the term "reference resistor" can refer to a resistive circuit that may include a single resistor or may include multiple resistors connected together (e.g., as part of a circuit providing variable resistance). The first reference resistor can be an external resistor, such as an external resistor R_ZQ connected via the ZQ pin ZQ. The first code Code_1 can indicate a code used to form the same resistance as the external resistor R_ZQ. For reference, in this specification, resistance can have substantially the same meaning as impedance. For example, resistance is substantially the same as impedance when a specific circuit element with a reactance component of "0" or greater is ideal. The impedance calibration circuit 100 can provide the first code Code_1 to the second code generation circuit 200 and the target impedance code generation circuit 300. According to an embodiment, the first code generation circuit 100 may include at least one ZQ pull-up driver and at least one ZQ pull-down driver, and the first code Code_1 may include a first pull-up code and a first pull-down code. The first pull-up code can indicate the code used to form an external resistor R_ZQ in the at least one ZQ pull-up driver, and the first pull-down code can indicate the code used to form an external resistor R_ZQ in the at least one ZQ pull-down driver. According to an embodiment, the first code generation circuit 100 can be implemented using two ZQ pull-up drivers and one ZQ pull-down driver. However, embodiments of the inventive concept are not limited thereto. For example, the first code generation circuit 100 can be implemented using one ZQ pull-up driver and two ZQ pull-down drivers. Reference will be made later. Figure 2A and Figure 2B The impedance calibration circuit 100 is described in more detail.

[0034] The second code generation circuit 200 can generate a second code Code_2 using a second reference resistor. The resistance of the second reference resistor can be less than the resistance of the first reference resistor (or external resistor R_ZQ). According to an embodiment, the second reference resistor can be formed based on the first code Code_1 provided by the first code generation circuit 100. The second code generation circuit 200 can provide the second code Code_2 to the target impedance code generation circuit 300. According to an embodiment, the second code generation circuit 200 may include a second reference resistor forming circuit configured to form the resistance of the second reference resistor based on the first code Code_1. For example, the second reference resistor forming circuit may include a plurality of ZQ pull-up drivers, each ZQ pull-up driver forming the resistance of the first reference resistor based on the first pull-up code included in the first code Code_1, the plurality of ZQ pull-up drivers being connected in parallel with each other. However, embodiments of the inventive concept are not limited thereto. For example, the second reference resistor forming circuit may include: a plurality of ZQ pull-down drivers, each ZQ pull-down driver forming the resistance of a first reference resistor based on a first pull-down code included in a first code Code_1, the plurality of ZQ pull-down drivers being connected in parallel with each other. According to an embodiment, the second code generation circuit 200 may form a second reference resistor using a plurality of ZQ drivers (e.g., m ZQ drivers; m is a natural number greater than or equal to 2) that form the first reference resistor based on the first code Code_1 and are connected in parallel with each other. According to an embodiment, the resistance of the second reference resistor may correspond to a value obtained by dividing the resistance of the first reference resistor by the number of ZQ drivers (m). According to an embodiment, the number of bits in the second code Code_2 may be greater than the number of bits in the first code Code_1. (See below for further details.) Figure 5 ,as well as Figures 7 to 9 The second code generation circuit 200 is described in more detail.

[0035] The target impedance code generation circuit 300 can generate and output the target impedance code Code_tar based on the first code Code_1, the second code Code_2, and the target impedance value R_tar. The target impedance code Code_tar can indicate the code used to form a termination impedance with the target impedance value R_tar in the termination driver 400. For example, the target impedance code Code_tar can be a code corresponding to the target impedance value R_tar. The target impedance value R_tar is a value required by the impedance calibration circuit 10, and therefore can be input from outside the impedance calibration circuit 10. According to an embodiment, the target impedance value R_tar can be a value set by a setting feature command.

[0036] According to an embodiment, the target impedance code generation circuit 300 can obtain multiple impedance value sections and can perform operations based on the impedance value section to which the target impedance value R_tar belongs by using a first code Code_1 and a second code Code_2 to generate a target impedance code Code_tar. As a non-limiting example, the multiple impedance value sections can be sections obtained based on a threshold impedance value. For example, the target impedance code generation circuit 300 can compare the target impedance value R_tar with a threshold impedance value, select a code from the first code Code_1 and the second code Code_2 based on the comparison result, and generate the target impedance code Code_tar by performing operations on the selected code. The operations may include shift operations. For example, when the target impedance value R_tar is greater than the threshold impedance value, the target impedance code generation circuit 300 can select the first code Code_1 and generate the target impedance code Code_tar using the first code Code_1. For example, when the target impedance value R_tar is less than the threshold impedance value, the target impedance code generation circuit 300 can select the second code Code_2 and generate the target impedance code Code_tar using the second code Code_2. The target impedance code generation circuit 300 can provide the target impedance code Code_tar to the termination driver 400. According to an embodiment, the target impedance code Code_tar may include target impedance pull-up codes and target impedance pull-down codes. (See later...) Figures 10 to 12 The target impedance code generation circuit 300 is described in more detail.

[0037] Termination driver 400 can provide a termination impedance with a target impedance value R_tar to output terminal OUT based on a target impedance code Code_tar. For example, termination driver 400 may include a termination pull-up driver and a termination pull-down driver. Because the termination pull-up driver forms a termination pull-up impedance based on a target impedance pull-up code, and the termination pull-down driver forms a termination pull-down impedance based on a target impedance pull-down code, termination driver 400 can provide a termination impedance with a target impedance value R_tar to output terminal OUT.

[0038] An impedance calibration circuit 10 according to an embodiment of the present invention can generate a target impedance code Code_tar for forming a target impedance value R_tar based on a first code Code_1 formed using a first reference resistor and a second code Code_2 formed using a second reference resistor. An impedance calibration circuit that generates a target impedance code based on a code formed using a single reference resistor, as described in a first comparison example, requires shifting the code by a large number of bits to cover a wide range of target impedance values. This results in non-linearity between the code and the impedance value of the termination impedance. Compared to the impedance calibration circuit according to the first comparison example, the impedance calibration circuit 10 according to an embodiment of the present invention can maintain linearity between the code and the impedance value for a wide range of target impedance values ​​R_tar by generating the target impedance code Code_tar based on a first code Code_1 formed using a first reference resistor and a second code Code_2 formed using a second reference resistor (where the second reference resistor is smaller than the first reference resistor). For example, the impedance calibration circuit 10 according to an embodiment of the present invention can provide reliable termination impedances for a wide range of target impedance values ​​R_tar.

[0039] Furthermore, in the impedance calibration circuit 10 according to the embodiment of the inventive concept, instead of connecting multiple ZQ drivers that occupy a relatively large area and have a large capacitance to the output terminal OUT, the multiple ZQ drivers are included in the second code generation circuit 200, thereby reducing the driver area and capacitance of the drivers connected to the output terminal OUT compared to the comparative example where multiple drivers are connected to the output terminal.

[0040] Figure 2A and Figure 2B This is a block diagram of first code generation circuits 100a and 100b according to embodiments of the inventive concept. The first code generation circuits 100a and 100b can be used with... Figure 1 The first code generation circuit 100 corresponds to this. Now refer to... Figure 1 To describe Figure 2A and Figure 2B .

[0041] refer to Figure 2A The first code generation circuit 100a may include a first pull-up code generation circuit 110a, a first ZQ pull-up driver 120a, a second ZQ pull-up driver 130a, a first pull-down code generation circuit 150a, a ZQ pull-down driver 160a, a first comparator 170a, and a second comparator 180a. Although Figure 2A The illustration shows two comparators, but embodiments of the present invention are not limited thereto. For example, the first code generation circuit 100a may include only one comparator. For example, a comparator may be shared within the first code generation circuit 100a. Figure 2A The first comparator 170a and the second comparator 180a.

[0042] An external resistor R_ZQ can be connected between the ZQ pin (or ZQ pad) and the ground node.

[0043] The first comparator 170a provides a first comparison result Comp_1 to the first pull-up code generation circuit 110a by comparing the voltage of the first node Node_1, which indicates the electrical node between the external resistor R_ZQ and the first ZQ pull-up driver 120a, with a reference voltage V_ref. The reference voltage V_ref can be provided by a reference voltage generation circuit in the impedance calibration circuit 10. According to an embodiment, the reference voltage V_ref can be half of the drive voltage. The drive voltage can be applied to the various pull-up drivers disclosed herein.

[0044] The first pull-up code generation circuit 110a can generate a first pull-up code Code_PU_1 based on the first comparison result Comp_1. The first pull-up code generation circuit 110a can provide the first pull-up code Code_PU_1 to the first ZQ pull-up driver 120a and the second ZQ pull-up driver 130a, and can also output the first pull-up code Code_PU_1 to the outside of the first code generation circuit 100a.

[0045] The first ZQ pull-up driver 120a can form an impedance based on the first pull-up code Code_PU_1, and the second ZQ pull-up driver 130a can also form an impedance based on the first pull-up code Code_PU_1. Each of the first ZQ pull-up driver 120a and the second ZQ pull-up driver 130a can be implemented as follows: Figure 3 The pull-up driver. Through closed-loop operation including the first pull-up code generation circuit 110a, the first ZQ pull-up driver 120a, and the first comparator 170a, the first ZQ pull-up driver 120a can thus form the same impedance as the external resistor R_ZQ, and the second ZQ pull-up driver 130a can thus form the same impedance as the external resistor R_ZQ.

[0046] The second comparator 180a can provide a second comparison result Comp_2 to the first pull-down code generation circuit 150a by comparing the voltage of the second node Node_2, which indicates the electrical node between the ZQ pull-down driver 160a and the first ZQ pull-up driver 130a, with a reference voltage V_ref. The reference voltage V_ref can be provided by a reference voltage generation circuit in the impedance calibration circuit 10. According to an embodiment, the reference voltage V_ref can be half of the drive voltage. In an embodiment, the reference voltage V_ref applied to the second comparator 180a can be the same as the reference voltage V_ref applied to the first comparator 170a.

[0047] The first pull-down code generation circuit 150a can generate a first pull-down code Code_PD_1 based on the second comparison result Comp_2. The first pull-down code generation circuit 150a can provide the first pull-down code Code_PD_1 to the ZQ pull-down driver 160a, and can also output the first pull-down code Code_PD_1 to the outside of the first code generation circuit 100a.

[0048] The ZQ pull-down driver 160a can form an impedance based on the first pull-down code Code_PD_1. The ZQ pull-down driver 160a can be implemented as... Figure 4 The pull-down driver. Through the operation of a loop including a first pull-down code generation circuit 150a, a first ZQ pull-down driver 160a, and a second comparator 180a, the ZQ pull-down driver 160a can thus form an impedance with the same impedance value as the second ZQ pull-up driver 130a. For example, the ZQ pull-down driver 160a can form an impedance with the same impedance value as the external resistor R_ZQ.

[0049] The first code generation circuit 100a can output the first pull-up code Code_PU_1 and the first pull-down code Code_PD_1 as the first code Code_1.

[0050] refer to Figure 2B The first code generation circuit 100b may include a first pull-up code generation circuit 110b, a ZQ pull-up driver 130b, a first pull-down code generation circuit 150b, a first ZQ pull-down driver 140b, a second ZQ pull-down driver 160b, a first comparator 170b, and a second comparator 180b. Although Figure 2B The illustration shows two comparators, but embodiments of the present invention are not limited thereto. For example, the first code generation circuit 100b may include only one comparator. For example, a comparator may be shared within the first code generation circuit 100b. Figure 2B The first comparator 170b and the second comparator 180b.

[0051] An external resistor R_ZQ can be connected between the ZQ pin and the drive voltage node VDD. In some examples, various supply voltages, such as the external supply voltage, the output driver voltage, and the supply voltage, can be applied to the drive voltage node VDD.

[0052] The second comparator 180b provides a second comparison result, Comp_2, to the first pull-down code generation circuit 150b by comparing the voltage of the third node Node_3, which indicates the electrical node between the external resistor R_ZQ and the first ZQ pull-down driver 140b, with a reference voltage V_ref. The reference voltage V_ref can be provided by a reference voltage generation circuit in the impedance calibration circuit 10. According to an embodiment, the reference voltage V_ref can be half of the drive voltage.

[0053] The first pull-down code generation circuit 150b can generate a first pull-down code Code_PD_1 based on the second comparison result Comp_2. The first pull-down code generation circuit 150b can provide the first pull-down code Code_PD_1 to the first ZQ pull-down driver 140b and the second ZQ pull-down driver 160b, and can also output the first pull-down code Code_PD_1 to the outside of the first code generation circuit 100b.

[0054] The first ZQ pull-down driver 140b can form an impedance based on the first pull-down code Code_PD_1, and the second ZQ pull-down driver 160b can also form an impedance based on the first pull-down code Code_PD_1. Each of the first ZQ pull-down driver 140b and the second ZQ pull-down driver 160b can be implemented as follows: Figure 4 The pull-down driver. Through closed-loop operation including a first pull-down code generation circuit 150b, a first ZQ pull-down driver 140b, and a second comparator 180b, the first ZQ pull-down driver 140b can thus form an impedance with the same resistance as the external resistor R_ZQ, and the second ZQ pull-down driver 160b can also thus form an impedance with the same resistance as the external resistor R_ZQ.

[0055] The first comparator 170b can provide a first comparison result Comp_1 to the first pull-up code generation circuit 110b by comparing the voltage of the fourth node Node_4, which indicates the electrical node between the ZQ pull-up driver 130b and the second ZQ pull-down driver 160b, with a reference voltage V_ref. The reference voltage V_ref can be provided by a reference voltage generation circuit in the impedance calibration circuit 10. According to an embodiment, the reference voltage V_ref can be half of the drive voltage. In an embodiment, the reference voltage V_ref applied to the first comparator 170b can be the same as the reference voltage V_ref applied to the second comparator 180b.

[0056] The first pull-up code generation circuit 110b can generate a first pull-up code Code_PU_1 based on the first comparison result Comp_1. The first pull-up code generation circuit 110b can provide the first pull-up code Code_PU_1 to the ZQ pull-up driver 130b, and can also output the first pull-up code Code_PU_1 to the outside of the first code generation circuit 100b.

[0057] The ZQ pull-up driver 130b can form an impedance based on the first pull-up code Code_PU_1. The ZQ pull-up driver 130b can be implemented as follows: Figure 3 The pull-up driver. Through the operation of a loop including a first pull-up code generation circuit 110b, a first ZQ pull-up driver 130b, and a first comparator 170b, the ZQ pull-up driver 130b can thus form an impedance with the same impedance value as the second ZQ pull-down driver 160b. For example, the ZQ pull-up driver 130b can form an impedance with the same impedance value as the external resistor R_ZQ.

[0058] The first code generation circuit 100b can output the first pull-up code Code_PU_1 and the first pull-down code Code_PD_1 as the first code Code_1.

[0059] Figure 3 This is a circuit diagram of a pull-up driver according to an embodiment of the present invention. Figure 2A The first ZQ pull-up driver 120a and the second ZQ pull-up driver 130a and Figure 2B Each of the ZQ pull-up drivers 130b can be implemented as Figure 3 The pull-up driver.

[0060] A pull-up driver may include a plurality of P-type metal-oxide-semiconductor (PMOS) transistor-resistor sets connected between a drive voltage node VDD and a connection node Node_con. For example, a first PMOS transistor P1 and a first resistor R1 may be connected in series between the drive voltage node VDD and the connection node Node_con; a second PMOS transistor P_2 and a second resistor R_2 may be connected in series between the drive voltage node VDD and the connection node Node_con; and an Mth PMOS transistor P_M and an Mth resistor R_M may be connected in series between the drive voltage node VDD and the connection node Node_con (where M is a natural number greater than or equal to 2). According to an embodiment, the first resistors R_1 to the Mth resistors R_M may have the same resistance. The first PMOS transistors P_1 to the Mth PMOS transistors P_M may be driven by an M-bit pull-up code Code_PU[M-1∶0]. In an example embodiment, the first resistors R_1 to the Mth resistors R_M may be omitted. In this case, each of the first PMOS transistor P_1 to the Mth PMOS transistor P_M can have a resistance value corresponding to the on-resistance of each of the first PMOS transistor P_1 to the Mth PMOS transistor P_M.

[0061] According to an embodiment, the pull-up driver may include a plurality of N-type metal-oxide-semiconductor (NMOS) transistor-resistor sets connected between the drive voltage node VDD and the connection node Node_con.

[0062] According to an embodiment, the pull-up driver can be implemented as a binary driver. A binary driver can indicate a driver configured such that the widths of multiple PMOS transistors are successively doubled. For example, the width of the first PMOS transistor P1 can be twice the width of the second PMOS transistor P2, and the width of the second PMOS transistor P2 can be twice the width of the third PMOS transistor P3. Because the pull-up driver is implemented as a binary driver, it can provide various impedance values.

[0063] According to an embodiment, the gate of the first PMOS transistor P_1 can be driven by the value of the most significant bit of the M-bit pull-up code Code_PU[M-1:0], the gate of the second PMOS transistor P_2 can be driven by the value of the second most significant bit of the M-bit pull-up code Code_PU[M-1:0], and the gate of the M-th PMOS transistor P_M can be driven by the value of the least significant bit of the M-bit pull-up code Code_PU[M-1:0]. However, the embodiments of the present invention are not limited thereto. For example, the gate of the first PMOS transistor P_1 can be driven by the value of the least significant bit of the M-bit pull-up code Code_PU[M-1:0], and the gate of the M-th PMOS transistor P_M can be driven by the value of the most significant bit of the M-bit pull-up code Code_PU[M-1:0].

[0064] The connection node Node_con can indicate the electrical node to which external circuitry elements of the pull-up driver are connected. For example, when... Figure 2A The first ZQ pull-up driver 120a, such as Figure 3 In the implementation shown, the connecting node Node_con can be connected to the first node Node_1. For example, when Figure 2A The second ZQ pull-up driver 130a, such as Figure 3 In the implementation shown, the connecting node Node_con can be connected to the second node Node_2. For example, when Figure 2B ZQ pull-up driver 130b, such as Figure 3 In the implementation shown, the connecting node Node_con can be connected to the fourth node Node_4.

[0065] Figure 4 This is a circuit diagram of a pull-down driver according to an embodiment of the present invention. Figure 2A ZQ pull-down driver 160a and Figure 2B Each of the first ZQ pull-down driver 140b and the second ZQ pull-down driver 160b can be implemented as Figure 4 The drop-down driver.

[0066] A pull-down driver may include a set of NMOS transistor-resistors connected between a ground node and a connection node Node_con. For example, a first NMOS transistor N_1 and a first resistor R_1 may be connected in series between the ground node and the connection node Node_con, a second NMOS transistor N_2 and a second resistor R_2 may be connected in series between the ground node and the connection node Node_con, and an Mth NMOS transistor N_M and an Mth resistor R_M may be connected in series between the ground node and the connection node Node_con (where M is a natural number greater than or equal to 2). According to an embodiment, the first resistors R_1 through the Mth resistors R_M may have the same resistance. The first NMOS transistors N_1 through the Mth NMOS transistors N_M may be driven by an M-bit pull-down code Code_PD[M-1∶0]. In an example embodiment, the first resistors R_1 through the Mth resistors R_M may be omitted. In this case, each of the first NMOS transistor N_1 to the Mth NMOS transistor N_M can have a resistance value corresponding to the on-resistance of each of the first NMOS transistor N_1 to the Mth NMOS transistor N_M.

[0067] According to an embodiment, the pull-down driver can be implemented as a binary driver. A binary driver can indicate a driver configured such that the widths of multiple NMOS transistors are successively doubled. For example, the width of the first NMOS transistor N_1 can be twice the width of the second NMOS transistor N_2, and the width of the second NMOS transistor N_2 can be twice the width of the third NMOS transistor. Because the pull-down driver is implemented as a binary driver, it can provide various impedance values.

[0068] According to an embodiment, the gate of the first NMOS transistor N_1 can be driven by the value of the most significant bit of the M-bit pull-down code Code_PD[M-1:0], the gate of the second NMOS transistor N_2 can be driven by the value of the second most significant bit of the M-bit pull-down code Code_PD[M-1:0], and the gate of the M-th NMOS transistor N_M can be driven by the value of the least significant bit of the M-bit pull-down code Code_PD[M-1:0]. However, the embodiments of the present invention are not limited thereto. For example, the gate of the first NMOS transistor N_1 can be driven by the value of the least significant bit of the M-bit pull-down code Code_PD[M-1:0], while the gate of the M-th NMOS transistor N_M can be driven by the value of the most significant bit of the M-bit pull-down code Code_PD[M-1:0].

[0069] The connection node Node_con can indicate the electrical node to which external circuitry elements of the pull-down driver are connected. For example, when... Figure 2AZQ pull-down driver 160a, such as Figure 4 In the implementation shown, the connecting node Node_con can be connected to the second node Node_2. For example, when Figure 2B The first ZQ pull-down driver 140b, such as Figure 4 In the implementation shown, the connecting node Node_con can be connected to the third node Node_3. For example, when Figure 2B The second ZQ pull-down driver 160b, such as Figure 4 In the implementation shown, the connecting node Node_con can be connected to the fourth node Node_4.

[0070] Figure 5 This is a block diagram of a second code generation circuit 200a according to an embodiment of the present invention. Reference will now be made to... Figure 1 To describe Figure 5 The second code generation circuit 200a can be used with... Figure 1 The second code generation circuit 200 corresponds to this.

[0071] The second code generation circuit 200a may include a second pull-up code generation circuit 210, a second reference resistor forming circuit 220, a pull-up driver 230, a second pull-down code generation circuit 240, a first pull-down driver 250, a second pull-down driver 260, a first comparator 270, and a second comparator 280.

[0072] The second reference resistor forming circuit 220 can form the resistance of the second reference resistor based on the first pull-up code Code_PU_1 included in the first code Code_1 provided by the first code generation circuit 100. To this end, according to an embodiment, the second reference resistor forming circuit 220 may include multiple drivers (e.g., multiple pull-up drivers), the multiple drivers including multiple ZQ drivers (e.g., multiple ZQ pull-up drivers) connected in parallel with each other, each of the multiple ZQ drivers can form the resistance of the first reference resistor based on the first pull-up code Code_PU_1, so the second reference resistor forming circuit 220 can form a second reference resistor with a resistance smaller than that of the first reference resistor. According to an embodiment, the resistance of the second reference resistor may correspond to a value obtained by dividing the resistance of the first reference resistor by the number of ZQ drivers. (See below for further details.) Figure 7 The second reference resistor forming circuit 220 is described in more detail.

[0073] According to an embodiment, when the second reference resistor forming circuit 220 includes a plurality of ZQ drivers, each of the plurality of ZQ drivers, the first pull-down driver 250, and the second pull-down driver 260 may include at least one NMOS transistor. However, embodiments of the present invention are not limited thereto. According to an embodiment, each of the plurality of ZQ drivers may include at least one PMOS transistor, and each of the first pull-down driver 250 and the second pull-down driver 260 may include at least one NMOS transistor. However, embodiments of the present invention are not limited thereto. According to an embodiment, each of the plurality of ZQ drivers may include at least one PMOS transistor, and each of the first pull-down driver 250 and the second pull-down driver 260 may include at least one NMOS transistor.

[0074] According to an embodiment, each of the plurality of ZQ drivers can form an impedance based on an n-bit code, and the first pull-down driver 250, the second pull-down driver 260, and the pull-up driver 230 can form an impedance based on an (n+k)-bit code.

[0075] The second comparator 280 provides a fourth comparison result, Comp_4, to the second pull-down code generation circuit 240 by comparing the voltage at node_a between the second reference resistor forming circuit 220 and the first pull-down driver 250 with a reference voltage V_ref. The reference voltage V_ref can be provided by a reference voltage generation circuit in the impedance calibration circuit 10. According to an embodiment, the reference voltage V_ref can be half of the drive voltage.

[0076] The second pull-down code generation circuit 240 can generate a second pull-down code Code_PD_2 based on the fourth comparison result Comp_4. The second pull-down code generation circuit 240 can provide the second pull-down code Code_PD_2 to the first pull-down driver 250 and the second pull-down driver 260, and can also output the second pull-down code Code_PD_2 to the outside of the second code generation circuit 200a.

[0077] The first pull-down driver 250 can form an impedance based on the second pull-down code Code_PD_2, and the second pull-down driver 260 can also form an impedance based on the second pull-down code Code_PD_2. Each of the first pull-down driver 250 and the second pull-down driver 260 can be implemented as follows: Figure 4 The pull-down driver. Through closed-loop operation including the second pull-down code generation circuit 240, the first pull-down driver 250 and the second comparator 280, the first pull-down driver 250 can thus form the same impedance as the resistance of the second reference resistor, and the second pull-down driver 260 can thus form the same impedance as the resistance of the second reference resistor.

[0078] The first comparator 270 can provide a third comparison result, Comp_3, to the second pull-up code generation circuit 210 by comparing the voltage of node_b between pull-up driver 230 and the second pull-down driver 260 with a reference voltage V_ref. The reference voltage V_ref can be provided by a reference voltage generation circuit in the impedance calibration circuit 10. According to an embodiment, the reference voltage V_ref can be half of the drive voltage.

[0079] The second pull-up code generation circuit 210 can generate a second pull-up code Code_PU_2 based on the third comparison result Comp_3. The second pull-up code generation circuit 210 can provide the second pull-up code Code_PU_2 to the pull-up driver 230, and can also output the second pull-up code Code_PU_2 to the outside of the second code generation circuit 200a.

[0080] The pull-up driver 230 can form an impedance based on the second pull-up code Code_PU_2. The pull-up driver 230 can be implemented as follows: Figure 3 The pull-up driver 230, through closed-loop operation including the second pull-up code generation circuit 210, the pull-up driver 230, and the first comparator 270, can thus form an impedance with the same impedance value as the second pull-down driver 260. For example, the pull-up driver 230 can form an impedance with the same impedance value as the second reference resistor.

[0081] The second code generation circuit 200a can output the second pull-up code Code_PU_2 and the first pull-down code Code_PD_2 as the second code Code_2.

[0082] Figure 6 This is a block diagram of a termination driver 400 according to an embodiment of the present invention. The termination driver 400 can be used with... Figure 1 The termination driver 400 corresponds to this. Now refer to... Figure 1 To describe Figure 6 .

[0083] Termination driver 400 may include termination pull-up driver 420 and termination pull-down driver 440.

[0084] The termination pull-up driver 420 can form a termination pull-up impedance based on the target impedance pull-up code Code_PU_tar included in the target impedance code Code_tar. According to an embodiment, the termination pull-up driver 420 can be implemented as follows: Figure 3 The pull-up driver, more specifically, the termination pull-up driver 420 can be used as... Figure 3 The connection node Node_con is connected to the output terminal OUT of type implementation.

[0085] The termination pull-down driver 440 can form a termination pull-down impedance based on the target impedance pull-down code Code_PD_tar included in the target impedance code Code_tar. According to an embodiment, the termination pull-down driver 440 can be implemented as follows: Figure 4 The pull-down driver, more specifically, the termination pull-down driver 440 can be used as... Figure 4 The connection node Node_con is connected to the output terminal OUT.

[0086] Because the termination pull-up driver 420 forms the pull-up impedance in the output terminal OUT based on the target impedance pull-up code Code_PU_tar, and the termination pull-down driver 440 forms the pull-down impedance in the output terminal OUT based on the target impedance pull-down code Code_PD_tar, an impedance with the target impedance value R_tar can be formed in the output terminal OUT.

[0087] Figure 7 This is a block diagram of a second reference resistor forming circuit 220 according to an embodiment of the present invention. Figure 7 The second reference resistor forming circuit 220 can be connected with Figure 5 The second reference resistor forms the circuit 220. Now the reference... Figure 1 To describe Figure 7 .

[0088] The second reference resistor forming circuit 220 may include a plurality of ZQ pull-up drivers, for example, a first ZQ pull-up driver 222_1 to an m-th ZQ pull-up driver 222_m (where M is a natural number greater than or equal to 2).

[0089] The first ZQ pull-up drivers 222_1 to the m-th ZQ pull-up drivers 222_m can be connected in parallel with each other. Each of the first ZQ pull-up drivers 222_1 to the m-th ZQ pull-up drivers 222_m can form an impedance based on a first pull-up code Code_PU_1 provided by the first code generation circuit 100. Therefore, each of the first ZQ pull-up drivers 222_1 to the m-th ZQ pull-up drivers 222_m can form an impedance value that is the same as the resistance of the first reference resistor. Therefore, the second reference resistor forming circuit 220 can form a second reference resistor in node Node_a, and the resistance of the second reference resistor can correspond to the value obtained by dividing the resistance of the first reference resistor by m. According to an embodiment, each of the first ZQ pull-up drivers 222_1 to the m-th ZQ pull-up drivers 222_m can be implemented with the same circuit structure as at least one ZQ pull-up driver included in the first code generation circuit 100. For example, the circuit structure of each of the first ZQ pull-up drivers 222_1 to the m-th ZQ pull-up drivers 222_m can correspond to the circuit structure of at least one ZQ pull-up driver included in the first code generation circuit 100.

[0090] In some examples, the resistance of the first reference resistor is 300 ohms. In this case, when m is 4, the resistance of the second reference resistor can be 75 ohms, while when m is 8, the resistance of the second reference resistor can be 37.5 ohms. Therefore, the resistance value of the second reference resistor can have a wide range depending on various values ​​of m.

[0091] According to an embodiment, at least some of the ZQ pull-up drivers may each include NMOS transistors with different on-resistances. According to an embodiment, the plurality of ZQ pull-up drivers may share a gate node.

[0092] According to an embodiment, the first ZQ pull-up driver 222_1 may include a first number of NMOS transistors connected in parallel or series with each other, and the second ZQ pull-up driver 222_2 may include a second number of NMOS transistors connected in parallel or series with each other, wherein the second number is different from the first number. According to an embodiment, the first number of NMOS transistors and the second number of NMOS transistors may have the same width. According to an embodiment, the first number of NMOS transistors may be connected in parallel with each other and may share contacts.

[0093] According to an embodiment, the NMOS transistors included in the plurality of ZQ pull-up drivers may have different widths or lengths from each other.

[0094] Figure 8This is a block diagram of a second code generation circuit 200b according to an embodiment of the present invention. Reference will now be made to... Figure 1 To describe Figure 8 The second code generation circuit 200b can be used with... Figure 1 The second code generation circuit 200 corresponds to this.

[0095] The second code generation circuit 200b may include a second pull-up code generation circuit 210, a second reference resistor forming circuit 225, a first pull-up driver 215, a second pull-up driver 235, a second pull-down code generation circuit 240, a pull-down driver 265, a first comparator 270, and a second comparator 280.

[0096] The second reference resistor forming circuit 225 can form the resistance of the second reference resistor based on the first pull-down code Code_PD_1 included in the first code Code_1 provided by the first code generation circuit 100. To this end, according to an embodiment, the second reference resistor forming circuit 225 may include multiple drivers (e.g., multiple pull-down drivers), the multiple drivers including multiple ZQ drivers (e.g., multiple ZQ pull-down drivers) connected in parallel with each other, each of the multiple ZQ drivers can form the resistance of the first reference resistor based on the first pull-down code Code_PD_1, so the second reference resistor forming circuit 225 can form a second reference resistor with a resistance smaller than that of the first reference resistor. According to an embodiment, the resistance of the second reference resistor may correspond to a value obtained by dividing the resistance of the first reference resistor by the number of ZQ drivers. (See below for further details.) Figure 9 The second reference resistor forming circuit 225 is described in more detail.

[0097] The first comparator 270 can provide a third comparison result, Comp_3, to the second pull-up code generation circuit 210 by comparing the voltage at node_c between the second reference resistor forming circuit 225 and the first pull-up driver 215 with a reference voltage V_ref. The reference voltage V_ref can be provided by a reference voltage generation circuit in the impedance calibration circuit 10. According to an embodiment, the reference voltage V_ref can be half of the drive voltage.

[0098] The second pull-up code generation circuit 210 can generate a second pull-up code Code_PU_2 based on the third comparison result Comp_3. The second pull-up code generation circuit 210 can provide the second pull-up code Code_PU_2 to the first pull-up driver 215 and the second pull-up driver 235, and can also output the second pull-up code Code_PU_2 to the outside of the second code generation circuit 200b.

[0099] The first pull-up driver 215 can form an impedance based on the second pull-up code Code_PU_2, and the second pull-up driver 235 can also form an impedance based on the second pull-up code Code_PU_2. Each of the first pull-up driver 215 and the second pull-up driver 235 can be implemented as follows: Figure 3 The pull-up driver. Through the closed-loop operation including the second pull-up code generation circuit 210, the first pull-up driver 215, and the first comparator 270, the first pull-up driver 215 can thus form the same impedance as the resistance of the second reference resistor, and the second pull-up driver 235 can thus form the same impedance as the resistance of the second reference resistor.

[0100] According to an embodiment, the first pull-up driver 215, the second pull-up driver 235, and the pull-down driver 265 can form impedances based on (n+k) bit codes.

[0101] The second comparator 280 provides a fourth comparison result, Comp_4, to the second pull-down code generation circuit 240 by comparing the voltage of node_D between the pull-down driver 265 and the second pull-up driver 235 with a reference voltage V_ref. The reference voltage V_ref can be provided by a reference voltage generation circuit in the impedance calibration circuit 10. According to an embodiment, the reference voltage V_ref can be half of the drive voltage.

[0102] The second pull-down code generation circuit 240 can generate a second pull-down code Code_PD_2 based on the fourth comparison result Comp_4. The second pull-down code generation circuit 240 can provide the second pull-down code Code_PD_2 to the pull-down driver 265, and can also output the second pull-down code Code_PD_2 to the outside of the second code generation circuit 200b.

[0103] The pull-down driver 265 can form an impedance based on the second pull-down code Code_PD_2. The pull-down driver 265 can be implemented as follows: Figure 4 The pull-down driver 265, through closed-loop operation including the second pull-down code generation circuit 240, the pull-down driver 265, and the second comparator 280, can thus form an impedance with the same impedance value as the second pull-up driver 235. For example, the pull-down driver 265 can form an impedance with the same impedance value as the second reference resistor.

[0104] The second code generation circuit 200b can output the second pull-up code Code_PU_2 and the second pull-down code Code_PD_2 as the second code Code_2.

[0105] Figure 9This is a block diagram of a second reference resistor forming circuit 225 according to an embodiment of the present invention. Figure 9 The second reference resistor forming circuit 225 can be connected with Figure 8 The second reference resistor corresponds to circuit 225. Now the reference... Figure 1 To describe Figure 9 .

[0106] The second reference resistor forming circuit 225 may include a plurality of ZQ pull-down drivers, for example, a first ZQ pull-down driver 227_1 to an m-th ZQ pull-down driver 227_m (where m is a natural number greater than or equal to 2).

[0107] The first ZQ pull-down drivers 227_1 to the m-th ZQ pull-down drivers 227_m can be connected in parallel with each other. Each of the first ZQ pull-down drivers 227_1 to the m-th ZQ pull-down drivers 227_m can form an impedance based on the first pull-down code Code_PD_1 provided by the first code generation circuit 100. Therefore, each of the first ZQ pull-down drivers 227_1 to the m-th ZQ pull-down drivers 227_m can form an impedance value that is the same as the resistance of the first reference resistor. Therefore, the second reference resistor forming circuit 225 can form a second reference resistor in node Node_a, and the resistance of the second reference resistor can correspond to the value obtained by dividing the resistance of the first reference resistor by m. According to an embodiment, each of the first ZQ pull-down drivers 227_1 to the m-th ZQ pull-down drivers 227_m can be implemented with the same circuit structure as at least one ZQ pull-down driver included in the first code generation circuit 100. For example, according to an embodiment, the circuit structure of each of the first ZQ pull-down drivers 227_1 to the m-th ZQ pull-down drivers 227_m can correspond to the circuit structure of at least one ZQ pull-down driver included in the first code generation circuit 100.

[0108] Figure 10 This is a block diagram of a target impedance code generation circuit 300 according to an embodiment of the present invention. Figure 10 The target impedance code generation circuit 300 can be used with Figure 1 The target impedance code generation circuit 300 corresponds to this. Now refer to... Figure 1 To describe Figure 10 .

[0109] The target impedance code generation circuit 300 may include a pull-up decoder 320 and a pull-down decoder 340.

[0110] The first code Code_1 provided by the first code generation circuit 100 may include a first pull-up code Code_PU_1 and a first pull-down code Code_PD_1, and the second code Code_2 provided by the second code generation circuit 200 may include a second pull-up code Code_PU_2 and a second pull-down code Code_PD_2.

[0111] The pull-up decoder 320 can output a target impedance pull-up code Code_PU_tar based on a first pull-up code Code_PU_1, a second pull-up code Code_PU_2, and a target impedance value R_tar. The pull-up decoder 320 can compare the target impedance value R_tar with a threshold impedance value, and can perform operations based on the comparison result using the first pull-up code Code_PU_1 and the second pull-up code Code_PU_2 to generate the target impedance pull-up code Code_PU_tar. For example, the pull-up decoder 320 can select one of the first pull-up code Code_PU_1 and the second pull-up code Code_PU_2 based on the comparison result, and can generate the target impedance pull-up code Code_PU_tar based on the selected code. See later. Figure 11 A more detailed description of the pull-up decoder 320.

[0112] The pull-down decoder 340 can output a target impedance pull-down code Code_PD_tar based on a first pull-down code Code_PD_1, a second pull-down code Code_PD_2, and a target impedance value R_tar. The pull-down decoder 340 can compare the target impedance value R_tar with a threshold impedance value, and can perform operations based on the comparison result using the first pull-down code Code_PD_1 and the second pull-down code Code_PD_2 to generate the target impedance pull-down code Code_PD_tar. For example, the pull-down decoder 340 can select one of the first pull-down code Code_PD_1 and the second pull-down code Code_PD_2 based on the comparison result, and can generate the target impedance pull-down code Code_PD_tar based on the selected code. See later. Figure 12 A more detailed description of the pull-down decoder 340.

[0113] The target impedance code generation circuit 300 can output the target impedance pull-up code Code_PU_tar and the target impedance pull-down code Code_PD_tar as the target impedance code Code_tar.

[0114] The target impedance code generation circuit 300 can be implemented in various ways. According to embodiments, the target impedance code generation circuit 300 can be implemented as hardware or software. When the target impedance code generation circuit 300 is implemented as hardware, it may include circuitry for generating a target impedance code Code_tar based on a first code Code_1 and a second code Code_2. For example, when the target impedance code generation circuit 300 is implemented as software, a program and / or instructions loaded on any memory in the device implementing the impedance calibration circuit 10 can be executed by any processor in that device to generate the target impedance code Code_tar. However, embodiments of the inventive concept are not limited thereto. For example, the target impedance code generation circuit 300 can be implemented as a combination of software and firmware, such as firmware.

[0115] Figure 11 This is a block diagram of a pull-up decoder 320 according to an embodiment of the present invention. Figure 11 The pull-up decoder 320 can be used with Figure 10 The pull-up decoder 320 corresponds to this. Now, refer to... Figure 1 and Figure 10 To describe Figure 11 .

[0116] The pull-up decoder 320 may include an impedance comparator 322 and an operator 324 (as used herein, the "operator" may be referred to as the "operation circuit").

[0117] Impedance comparator 322 can output a first impedance comparison result Res_Comp_1 by comparing a target impedance value R_tar with a threshold impedance value. As a non-limiting example, when the target impedance value R_tar is greater than the threshold impedance value, impedance comparator 322 can output a first impedance comparison result Res_Comp_1 with a first logic level (e.g., "1"), and when the target impedance value R_tar is less than the threshold impedance value, impedance comparator 322 can output a first impedance comparison result Res_Comp_1 with a second logic level (e.g., "0"). According to an embodiment, the threshold impedance value can be less than the resistance of the first reference resistor and can be greater than the resistance of the second reference resistor.

[0118] In the example embodiment, impedance comparator 322 may be omitted.

[0119] Operator 324 can select a code from the first pull-up code Code_PU_1 and the second pull-up code Code_PU_2 based on the logic level of the first impedance comparison result Res_Comp_1, and can generate the target impedance pull-up code Code_PU_tar by performing an operation using the selected code. The operation may include a shift operation.

[0120] In the example embodiment, when the target impedance value R_tar is greater than the threshold impedance value, the operator 324 can select the first pull-up code Code_PU_1, and can generate the target impedance pull-up code Code_PU_tar by using the first pull-up code Code_PU_1.

[0121] In the example embodiment, when the impedance comparator 322 is omitted and the target impedance value R_tar is closer to the resistance of the first reference resistor relative to the resistance of the second reference resistor, the operator 324 can select the first pull-up code Code_PU_1 and can generate the target impedance pull-up code Code_PU_tar by using the first pull-up code Code_PU_1.

[0122] According to an embodiment, when the target impedance value R_tar is the same as the resistance of the first reference resistor, the operator 324 can output a first pull-up code Code_PU_1 as the target impedance pull-up code Code_PU_tar. According to an embodiment, when the target impedance value R_tar is different from the resistance of the first reference resistor, the operator 324 can generate the target impedance pull-up code Code_PU_tar by performing an operation that shifts the first pull-up code Code_PU_1 by at least one bit. As a non-limiting example for ease of illustration, when the resistance of the first reference resistor is 300 ohms and the target impedance value R_tar is 150 ohms, the operator 324 can generate the target impedance pull-up code Code_PU_tar by shifting the first pull-up code Code_PU_1 by one bit.

[0123] In the embodiment, when the first pull-up code Code_PU_1 is shifted to the left once, the impedance can be half of the impedance corresponding to the previous first pull-up code Code_PU_1, and when the first pull-up code Code_PU_1 is shifted to the left twice, the impedance can be 1 / 4 of the impedance corresponding to the previous first pull-up code Code_PU_1.

[0124] In the embodiment, when the first pull-up code Code_PU_1 is shifted to the right once, the impedance can be twice the impedance corresponding to the previous first pull-up code Code_PU_1, and when the first pull-up code Code_PU_1 is shifted to the right twice, the impedance can be four times the impedance corresponding to the previous first pull-up code Code_PU_1.

[0125] Similarly, in the example embodiment, when the target impedance value R_tar is less than the threshold impedance value, the operator 324 can select the second pull-up code Code_PU_2, and the target impedance pull-up code Code_PU_tar can be generated by using the second pull-up code Code_PU_2.

[0126] In the example embodiment, when the impedance comparator 322 is omitted and the target impedance value R_tar is closer to the resistance of the second reference resistor relative to the resistance of the first reference resistor, the operator 324 can select the second pull-up code Code_PU_2 and can generate the target impedance pull-up code Code_PU_tar by using the second pull-up code Code_PU_2.

[0127] According to an embodiment, when the target impedance value R_tar is the same as the resistance of the second reference resistor, the operator 324 can output the second pull-up code Code_PU_2 as the target impedance pull-up code Code_PU_tar. According to an embodiment, when the target impedance value R_tar is different from the resistance of the second reference resistor, the operator 324 can generate the target impedance pull-up code Code_PU_tar by performing an operation that shifts the second pull-up code Code_PU_2 by at least one bit. As a non-limiting example for ease of illustration, when the resistance of the second reference resistor is 75 ohms and the target impedance value R_tar is 37.5 ohms, the operator 324 can generate the target impedance pull-up code Code_PU_tar by shifting the second pull-up code Code_PU_2 by one bit. As a non-limiting example for ease of illustration, when the resistance of the second reference resistor is 75 ohms and the target impedance value R_tar is 25 ohms, the operator 324 can generate the target impedance pull-up code Code_PU_tar by performing an operation of adding the second pull-up code Code_PU_2 to the code obtained by shifting the second pull-up code Code_PU_2 by one bit.

[0128] In some examples, when the second pull-up code Code_PU_2 is shifted to the left once, the impedance can be half the impedance corresponding to the previous second pull-up code Code_PU_2, and when the second pull-up code Code_PU_2 is shifted to the left twice, the impedance can be 1 / 4 of the impedance corresponding to the previous second pull-up code Code_PU_2.

[0129] In some examples, when the second pull-up code Code_PU_2 is shifted to the right once, the impedance can be twice the impedance corresponding to the previous second pull-up code Code_PU_2, and when the second pull-up code Code_PU_2 is shifted to the right twice, the impedance can be four times the impedance corresponding to the previous second pull-up code Code_PU_2.

[0130] Figure 12 This is a block diagram of a pull-down decoder 340 according to an embodiment of the present invention. Figure 12 The pull-down decoder 340 can be used with Figure 10 The corresponding pull-down decoder 340. Now refer to Figure 1 and Figure 10 To describe Figure 12 .

[0131] The pull-down decoder 340 may include an impedance comparator 342 and an operator 344 (as used herein, the "operator" may be referred to as the "operation circuit").

[0132] Impedance comparator 342 can output a second impedance comparison result Res_Comp_2 by comparing a target impedance value R_tar with a threshold impedance value. As a non-limiting example, when the target impedance value R_tar is greater than the threshold impedance value, impedance comparator 342 can output a second impedance comparison result Res_Comp_2 with a first logic level (e.g., "1"), and when the target impedance value R_tar is less than the threshold impedance value, impedance comparator 342 can output a second impedance comparison result Res_Comp_2 with a second logic level (e.g., "0"). According to an embodiment, the threshold impedance value can be less than the resistance of the first reference resistor and greater than the resistance of the second reference resistor.

[0133] In the example embodiment, impedance comparator 342 may be omitted.

[0134] Operator 344 can select a code from the first pull-down code Code_PD_1 and the second pull-down code Code_PD_2 based on the logic level of the second impedance comparison result Res_Comp_2, and can generate the target impedance pull-down code Code_PD_tar by performing an operation using the selected code. The operation may include a shift operation.

[0135] For example, when the target impedance value R_tar is greater than the threshold impedance value, the operator 344 can select the first pull-down code Code_PD_1, and can generate the target impedance pull-down code Code_PD_tar by using the first pull-down code Code_PD_1. According to an embodiment, when the target impedance value R_tar is the same as the resistance of the first reference resistor, the operator 344 can output the first pull-down code Code_PD_1 as the target impedance pull-down code Code_PD_tar. According to an embodiment, when the target impedance value R_tar is different from the resistance of the first reference resistor, the operator 344 can generate the target impedance pull-up code Code_PD_tar by performing an operation that shifts the first pull-down code Code_PD_1 by at least one bit. As a non-limiting example for ease of illustration, when the resistance of the first reference resistor is 300 ohms and the target impedance value R_tar is 150 ohms, the operator 344 can generate the target impedance pull-down code Code_PD_tar by shifting the first pull-down code Code_PD_1 by one bit.

[0136] In some examples, when the first pull-down code Code_PD_1 is shifted to the left once, the impedance can be half the impedance corresponding to the previous first pull-down code Code_PD_1, and when the first pull-down code Code_PD_1 is shifted to the left twice, the impedance can be 1 / 4 of the impedance corresponding to the previous first pull-down code Code_PD_1.

[0137] In some examples, when the first pull-down code Code_PD_1 is shifted to the right once, the impedance can be twice the impedance corresponding to the previous first pull-down code Code_PD_1, and when the first pull-down code Code_PD_1 is shifted to the right twice, the impedance can be four times the impedance corresponding to the previous first pull-down code Code_PD_1.

[0138] Similarly, for example, when the target impedance value R_tar is less than the threshold impedance value, the operator 344 can select the second pull-down code Code_PD_2, and can generate the target impedance pull-down code Code_PD_tar by using the second pull-down code Code_PD_2. According to an embodiment, when the target impedance value R_tar is the same as the resistance of the second reference resistor, the operator 344 can output the second pull-down code Code_PD_2 as the target impedance pull-down code Code_PD_tar. According to an embodiment, when the target impedance value R_tar is different from the resistance of the second reference resistor, the operator 344 can generate the target impedance pull-down code Code_PD_tar by performing an operation that shifts the second pull-down code Code_PD_2 by at least one bit. As a non-limiting example for ease of illustration, when the resistance of the second reference resistor is 75 ohms and the target impedance value R_tar is 37.5 ohms, the operator 344 can generate the target impedance pull-down code Code_PD_tar by shifting the second pull-down code Code_PD_2 by one bit. As a non-limiting example for ease of illustration, when the resistance of the second reference resistor is 75 ohms and the target impedance value R_tar is 25 ohms, the operator 344 can generate the target impedance pull-down code Code_PD_tar by performing an operation of adding the second pull-down code Code_PD_2 to the code obtained by shifting the second pull-down code Code_PD_2 by one bit.

[0139] In some examples, when the second pull-down code Code_PD_2 is shifted to the left once, the impedance can be half the impedance corresponding to the previous second pull-down code Code_PD_2, and when the second pull-down code Code_PD_2 is shifted to the left twice, the impedance can be 1 / 4 of the impedance corresponding to the previous second pull-down code Code_PD_2.

[0140] In some examples, when the second pull-down code Code_PD_2 is shifted to the right once, the impedance can be twice the impedance corresponding to the previous second pull-down code Code_PD_2, and when the second pull-down code Code_PD_2 is shifted to the right twice, the impedance can be four times the impedance corresponding to the previous second pull-down code Code_PD_2.

[0141] Figure 13 This is a flowchart of an impedance calibration method performed by an impedance calibration circuit according to an embodiment of the present invention. Reference will now be made to... Figure 1 To describe Figure 13 .

[0142] In operation S120, the impedance calibration circuit 10 can generate a first code Code_1 using a first reference resistor. For example, the first code generation circuit 100 can generate the first code Code_1 using an external resistor R_ZQ connected to the ZQ pin ZQ. The first code Code_1 can indicate the code used to form the resistance of the first reference resistor. The first code Code_1 may include a first pull-up code and a first pull-down code.

[0143] In operation S140, the impedance calibration circuit 10 can generate a second code Code_2 using a second reference resistor. For example, the second code generation circuit 200 can form a second reference resistor with a smaller resistance than the first reference resistor based on the first code Code_1, and can generate the second code Code_2 using the second reference resistor. The second code Code_2 can indicate the code used to form the resistance of the second reference resistor. The second code Code_2 may include a second pull-up code and a second pull-down code.

[0144] In operation S160, the impedance calibration circuit 10 can generate a target impedance code Code_tar corresponding to the target impedance value R_tar based on the first code Code_1, the second code Code_2, and the target impedance value R_tar. For example, the target impedance code generation circuit 300 can compare the target impedance value R_tar with a threshold impedance value, and select a code from the first code Code_1 and the second code Code_2 according to the comparison result. The target impedance code generation circuit 300 can generate the target impedance code Code_tar by performing an operation using the selected code.

[0145] Figure 14 This is a flowchart of an impedance calibration method performed by an impedance calibration circuit according to an embodiment of the present invention. Figure 14 It can be Figure 13 The flowchart for operation S160. Now refer to... Figure 1 To describe Figure 14 .

[0146] In operation S162, the impedance calibration circuit 10 can compare the target impedance value R_tar with the threshold impedance value. For example, the target impedance code generation circuit 300 can generate an impedance comparison result by comparing the target impedance value R_tar with the threshold impedance value.

[0147] In operation S164, when the target impedance value R_tar is greater than the threshold impedance value, the impedance calibration circuit 10 can select the first code Code_1 and can generate the target impedance code Code_tar based on the first code Code_1.

[0148] In operation S166, when the target impedance value R_tar is less than the threshold impedance value, the impedance calibration circuit 10 can select the second code Code_2 and can generate the target impedance code Code_tar based on the second code Code_2.

[0149] Figure 15 This is a block diagram of a storage device 1000 according to an embodiment of the present invention. Specifically, Figure 15 A storage device 1000 is shown, in which a reference is implemented. Figure 1 , Figure 2A , Figure 2B ,as well as Figures 3 to 14 The impedance calibration circuit 10 described above.

[0150] The memory device 1000 can be implemented using volatile or non-volatile memory devices. Volatile memory devices may include, for example, dynamic random access memory (DRAM) and static random access memory (SRAM). Non-volatile memory devices may include, for example, NAND flash memory, vertical NAND (VNAND) flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-transfer torque random access memory (STT-RAM), and combinations thereof. According to embodiments, the non-volatile memory device may have a stacked structure of 100 or more layers. According to embodiments, the non-volatile memory device may have a cell-on-periphery (COP) or cell-over-periphery (COP) structure.

[0151] According to an embodiment, the operating frequency of the storage device 1000 may be, but is not limited to, 1.2 GHz or higher.

[0152] The storage device 1000 may include a first code generation circuit 1100, a second code generation circuit 1200, a target impedance code generation circuit 1300, and a termination driver 1400.

[0153] The first code generation circuit 1100 can be compared with the reference. Figure 1 , Figure 2A , Figure 2B ,as well as Figures 3 to 14This corresponds to the first code generation circuits 100, 100a, and 100b described above. For example, the first code generation circuit 1100 can generate the first pull-up code Code_PU_1 and the first pull-down code Code_PD_1 by using an external resistor R_ZQ connected to the ZQ pin ZQ.

[0154] The second code generation circuit 1200 can be compared with the reference. Figure 1 , Figure 2A , Figure 2B ,as well as Figures 3 to 14 This corresponds to the second code generation circuits 200, 200a, and 200b described above. For example, the second code generation circuit 1200 can generate a second pull-up code Code_PU_2 and a second pull-down code Code_PD_2 by using a second reference resistor formed based on the first pull-up code Code_PU_1 and / or the first pull-down code Code_PD_1.

[0155] The target impedance code generation circuit 1300 can be used with a reference. Figure 1 , Figure 2A , Figure 2B ,as well as Figures 3 to 14 This corresponds to the target impedance code generation circuit 300 described above. For example, the target impedance code generation circuit 1300 can generate the target impedance pull-up code Code_PU_tar and the target impedance pull-down code Code_PD_tar based on the first pull-up code Code_PU_1, the first pull-down code Code_PD_1, the second pull-up code Code_PU_2, the second pull-down code Code_PD_2, and the target impedance value R_tar.

[0156] Termination driver 1400 can be used with reference Figure 1 , Figure 2A , Figure 2B ,as well as Figures 3 to 14 Corresponding to the termination driver 400 described above, each of the first DQ pin DQ_1 to the Nth DQ pin DQ_N can be associated with a reference. Figure 1 , Figure 2A , Figure 2B ,as well as Figures 3 to 14 Corresponding to the output terminal OUT described above, each of the first terminal connected to pull-up driver 1420_1 to the Nth terminal connected to pull-up driver 1420_N can be connected to... Figure 6 The termination corresponds to the pull-up driver 420, and each of the first to Nth pull-down drivers 1440_1 can be connected to the pull-down driver 1440_N. Figure 6 The termination pull-down driver 440 corresponds to this. Although Figure 15An embodiment of the termination driver 1400 being connected to the DQ pin is shown, but embodiments of the present invention are not limited thereto, and the termination driver 1400 may be connected to the DQS pin.

[0157] In the example embodiment, the circuit structure of each of the first-terminal pull-up driver 1420_1 to the Nth-terminal pull-up driver 1420_N can be the same as... Figure 5 Pull-up driver 230 and Figure 8 The circuit structure of each of the first pull-up driver 215 and the second pull-up driver 235 is the same. The circuit structure of each of the first terminal pull-down drivers 1440_1 to the Nth terminal pull-down drivers 1440_N can be the same as... Figure 5 The first pull-down driver 250 and the second pull-down driver 260 and Figure 8 Each of the pull-down drivers 265 has the same circuit structure.

[0158] The storage device 1000 can send or receive data via the first DQ pin DQ_1 to the Nth DQ pin DQ_N.

[0159] The storage device 1000 according to an embodiment of the present invention can generate target impedance pull-up code Code_PU_tar and target impedance pull-down code Code_PD_tar for forming a target impedance value R_tar based on a first pull-up code Code_PU_1 and a first pull-down code Code_PD_1 formed using a first reference resistor, and a second pull-up code Code_PU_2 and a second pull-down code Code_PD_2 formed using a second reference resistor. The storage device generating the target impedance code based on a first comparison example using a code formed with a reference resistor requires shifting the code by a large number of bits to cover a wide range of target impedance values. This results in non-linearity between the code and the impedance value of the termination impedance. Compared to the impedance calibration circuit according to the first comparison example, the storage device 1000 according to an embodiment of the present invention can maintain linearity between the code and the impedance value for a target impedance value R_tar over a wide range by generating the target impedance code based on a first code formed using a first reference resistor and a second code formed using a second reference resistor smaller than the first reference resistor. For example, the storage device 1000 according to an embodiment of the present invention can provide reliable termination impedance for a wide range of target impedance values ​​R_tar.

[0160] Furthermore, in the memory device 1000 according to the embodiment of the inventive concept, instead of connecting multiple ZQ drivers, which occupy a relatively large area and have a large capacitance, to multiple DQ pins DQ_1 to DQ_N respectively, the multiple ZQ drivers are included in the second code generation circuit 1200. As a result, compared with the comparative example where multiple drivers are connected to the output terminal, the driver area and capacitance of the drivers that are connected to multiple DQ pins DQ_1 to DQ_N respectively can be reduced.

[0161] Figure 16 This is a block diagram of a storage system according to an exemplary embodiment of the present invention.

[0162] refer to Figure 16 The storage system 1500 may include a storage controller 500 and a storage device 600. The storage controller 500 provides various types of signals to the storage device 600 to control storage operations such as write and read operations. For example, the storage controller 500 includes a storage interface 510 and provides the storage device 600 with commands CMD and addresses ADD to access data DATA in the storage cell array 610 of the storage device 600.

[0163] Command CMDs can include commands for normal storage operations such as write and read operations. Additionally, the storage controller 500 can provide command CMDs for various types of control operations within the storage device 600, such as providing the calibration command CMD_ZQ to the storage device 600.

[0164] The storage controller 500 can access the storage device 600 in response to a request from the host. The storage controller 500 can communicate with the host using various protocols.

[0165] The storage device 600 may include a storage cell array 610 and an impedance calibration circuit 10. For storage operations, the storage device 600 may also include various other components.

[0166] In example embodiments, for instance Figure 16 The storage device 600 described herein can operate and may include device components according to one or more example embodiments of the previously described example embodiments.

[0167] Figure 17 This is a cross-sectional view showing an exemplary embodiment of a storage device according to a concept conceived in the present invention.

[0168] Reference Figure 17The storage device 2000 may have a chip-to-chip (C2C) structure. A C2C structure can refer to a structure formed by fabricating an upper chip including cell regions (CELL) on a first wafer, fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer different from the first wafer, and then connecting the upper and lower chips by bonding. For example, the bonding method may include a method of electrically connecting bonding metals formed on the topmost metal layer of the upper chip and bonding metals formed on the topmost metal layer of the lower chip. For example, when the bonding metals can be formed of copper (Cu), the bonding method can be Cu-Cu bonding, and the bonding metals can also be formed of aluminum or tungsten.

[0169] Each of the peripheral circuit region (PERI) and cell region (CELL) of the storage device 2000 may include an external pad bonding area (PA), a word line bonding area (WLBA), and a bit line bonding area (BLBA). In an example embodiment, Figure 16 The storage cell array 610 can be located in Figure 17 In the cell area CELL, and Figure 16 The impedance calibration circuit 10 can be located in Figure 17 In the peripheral circuit region PERI.

[0170] The Peripheral Circuit Region (PERI) may include: a first substrate 2210; an interlayer insulating layer 2215; a plurality of circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210; first metal layers 2230a, 2230b, and 2230c respectively connected to the plurality of circuit elements 2220a, 2220b, and 2220c; and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c. Each of the circuit elements 2220a, 2220b, and 2220c may include one or more transistors. In an example embodiment, the first metal layers 2230a, 2230b, and 2230c may be formed of tungsten, which has relatively high resistance, and the second metal layers 2240a, 2240b, and 2240c may be formed of copper, which has relatively low resistance.

[0171] exist Figure 17In the example embodiments shown, although first metal layers 2230a, 2230b, and 2230c and second metal layers 2240a, 2240b, and 2240c are shown and described, they are not limited thereto, and one or more metal layers may be formed on the second metal layers 2240a, 2240b, and 2240c. At least a portion of the one or more metal layers formed on the second metal layers 2240a, 2240b, and 2240c may be formed of aluminum or the like, which has a lower resistance than the copper used to form the second metal layers 2240a, 2240b, and 2240c.

[0172] An interlayer insulating layer 2215 may be disposed on a first substrate 2210 and cover a plurality of circuit elements 2220a, 2220b and 2220c, first metal layers 2230a, 2230b and 2230c, and second metal layers 2240a, 2240b and 2240c. The interlayer insulating layer 2215 may include an insulating material such as silicon oxide or silicon nitride.

[0173] The lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b in the word line bonding region (WLBA). In the WLBA, the lower bonding metals 2271b and 2272b in the peripheral circuit region (PERI) can be electrically connected to the upper bonding metals 2371b and 2372b in the cell region (CELL) by bonding. The lower bonding metals 2271b and 2272b, as well as the upper bonding metals 2371b and 2372b, can be formed of aluminum, copper, tungsten, or the like. Furthermore, the upper bonding metals 2371b and 2372b in the cell region (CELL) can be referred to as first metal pads, and the lower bonding metals 2271b and 2272b in the peripheral circuit region (PERI) can be referred to as second metal pads.

[0174] A cell region (CELL) may include at least one memory block. The cell region (CELL) may include a second substrate 2310 and a common source line 2320. Multiple word lines 2331 to 2338 (i.e., 2330) may be stacked on the second substrate 2310 in a direction perpendicular to the upper surface of the second substrate 2310 (Z-axis direction). At least one string select line and at least one ground select line may be arranged above and below the multiple word lines 2330, respectively, and the multiple word lines 2330 may be disposed between the at least one string select line and the at least one ground select line.

[0175] In the bit line bonding area (BLBA), the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 2310 and pass through multiple word lines 2330, the at least one string select line, and the at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the third metal layer 2350c and the fourth metal layer 2360c. For example, the third metal layer 2350c may be a bit line contact, and the fourth metal layer 2360c may be a bit line. In an example embodiment, the bit line 2360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 2310.

[0176] exist Figure 17 In the example embodiment shown, the region in which the channel structure CH, bit line 2360c, etc., are provided can be defined as the bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 2360c can be electrically connected to the circuit element 2220c providing the page buffer 2393 in the peripheral circuit region PERI. For example, the bit line 2360c can be connected to the upper bonding metals 2371c and 2372c in the cell region CELL, and the upper bonding metals 2371c and 2372c can be connected to the lower bonding metals 2271c and 2272c, which are connected to the circuit element 2220c of the page buffer 2393.

[0177] In the word line bonding area (WLBA), multiple word lines 2330 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 2310 and can be connected to multiple cell contact plugs 2341 to 2347 (i.e., 2340). The multiple word lines 2330 and the multiple cell contact plugs 2340 can be connected to each other in pads provided by at least a portion of the multiple word lines 2330 extending at different lengths in the second direction. A third metal layer 2350b and a fourth metal layer 2360b can be sequentially connected to the upper portion of the multiple cell contact plugs 2340 connected to the multiple word lines 2330. The multiple cell contact plugs 2340 can be connected to the circuit region PERI via upper bonding metals 2371b and 2372b of the cell region CELL in the word line bonding area (WLBA) and lower bonding metals 2271b and 2272b of the peripheral circuit region PERI.

[0178] Multiple cell contact plugs 2340 can be electrically connected to circuit element 2220b, which provides the line decoder 2394 in the peripheral circuitry region PERI. In an example embodiment, the operating voltage of circuit element 2220b providing the line decoder 2394 may differ from the operating voltage of circuit element 2220c providing the page buffer 2393. For example, the operating voltage of circuit element 2220c providing the page buffer 2393 may be greater than the operating voltage of circuit element 2220b providing the line decoder 2394.

[0179] A common source line contact plug 2380 can be disposed in the external pad bonding region PA. The common source line contact plug 2380 can be formed of a conductive material such as metal, metal compound, or polysilicon, and can be electrically connected to the common source line 2320. A third metal layer 2350a and a fourth metal layer 2360a can be sequentially stacked on top of the common source line contact plug 2380. For example, the area where the common source line contact plug 2380, the third metal layer 2350a, and the fourth metal layer 2360a are disposed can be defined as the external pad bonding region PA.

[0180] Input / output pads 2205 and 2305 can be set in the external pad bonding area PA. (See reference...) Figure 17 A lower insulating film 2201 covering the lower surface of the first substrate 2210 can be formed below the first substrate 2210, and a first input / output pad 2205 can be formed on the lower insulating film 2201. The first input / output pad 2205 can be connected to at least one of a plurality of circuit elements 2220a, 2220b, and 2220c disposed in the peripheral circuit region PERI via a first input / output contact plug 2203, and the first input / output pad 2205 can be separated from the first substrate 2210 via the lower insulating film 2201. In addition, a side insulating film can be provided between the first input / output contact plug 2203 and the first substrate 2210 to electrically separate the first input / output contact plug 2203 from the first substrate 2210.

[0181] Reference Figure 17 An upper insulating film 2301 covering the upper surface of the second substrate 2310 can be formed on the second substrate 2310, and second input / output pads 2305 can be disposed on the upper insulating film 2301. The second input / output pads 2305 can be connected to at least one of a plurality of circuit elements 2220a, 2220b and 2220c disposed in the peripheral circuit region PERI via second input / output contact plugs 2303.

[0182] According to an embodiment, the second substrate 2310 and the common source line 2320 may not be located in the area where the second input / output contact plug 2303 is provided. Additionally, the second input / output pad 2305 may not overlap with the word line 2330 in the third direction (Z-axis direction). (See also...) Figure 17 The second input / output contact plug 2303 can be separated from the second substrate 2310 in a direction parallel to the upper surface of the second substrate 2310, and can pass through the interlayer insulating layer 2315 of the cell region CELL to connect to the second input / output pad 2305 and the upper metal pattern 2372a of the cell region CELL.

[0183] According to embodiments, the first input / output pad 2205 and the second input / output pad 2305 can be selectively formed. For example, the storage device 2000 may include only the first input / output pad 2205 disposed on the lower insulating film 2201 in contact with the first substrate 2210 or the second input / output pad 2305 disposed on the upper insulating film 2301 in contact with the second substrate 2310. Alternatively, the storage device 2000 may include both the first input / output pad 2205 and the second input / output pad 2305.

[0184] In each of the external pad bonding area PA and bit line bonding area BLBA included in the cell region CELL and the peripheral circuit region PERI respectively, the metal pattern in the uppermost metal layer can be set as a dummy pattern or the uppermost metal layer can be absent.

[0185] In the external pad bonding area PA, the memory device 2000 may include a lower metal pattern 2273a corresponding to an upper metal pattern 2372a formed in the uppermost metal layer of the cell region CELL, and having the same shape as the upper metal pattern 2372a in the uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern 2273a formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern may be formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same shape as the lower metal pattern in the peripheral circuit region PERI.

[0186] Lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 2371b and 2372b of the cell region CELL via Cu-Cu bonding.

[0187] Furthermore, in the bit line bonding region (BLBA), an upper metal pattern 2392 can be formed in the uppermost metal layer of the cell region (CELL). This upper metal pattern 2392 corresponds to the lower metal pattern 2252 formed in the uppermost metal layer of the peripheral circuit region (PERI), and has the same shape as the lower metal pattern 2252 of the PERI. No contact portion may be formed on the upper metal pattern 2392 formed in the uppermost metal layer of the cell region (CELL).

[0188] In an example embodiment, a reinforcing metal pattern having the same shape as the metal pattern can be formed in the uppermost metal layer of the other of the cell region CELL and peripheral circuit region PERI, corresponding to the metal pattern formed in the uppermost metal layer of the cell region CELL and peripheral circuit region PERI, and no contact portion may be formed on the reinforcing metal pattern.

[0189] In example embodiments, for instance Figure 17 The storage device 2000 described herein can operate and may include device components according to one or more example embodiments of the previously described example embodiments. In the example embodiments, Figure 16 The storage cell array 610 can be located in Figure 17 In the cell area CELL, and Figure 16 The impedance calibration circuit 10 can be located in Figure 17 In the peripheral circuit region PERI. For example, Figure 1 , Figure 2A , Figure 2B , Figures 3 to 12 ,as well as Figure 15 The impedance calibration circuit described in [the document] can be located in [the location]. Figure 17 In the peripheral circuit region PERI.

[0190] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An impedance calibration circuit, comprising: A first code generation circuit is connected to a first reference resistor and is configured to generate a first code for forming a resistance based on the first reference resistor by using the first reference resistor. The second code generation circuit is configured as follows: Based on the first code, a second reference resistor with a resistance smaller than that of the first reference resistor is formed, and The second code is generated by using the second reference resistor; as well as The target impedance code generation circuit is configured as follows: Generate a target impedance code based on the first code, the second code, and the target impedance value, and Based on the target impedance code, an impedance with the target impedance value is formed in the termination driver connected to the impedance calibration circuit. The first code generation circuit includes: At least one ZQ pull-up driver is configured to form a first pull-up impedance based on the first pull-up code included in the first code; as well as At least one ZQ pull-down driver is configured to form a first pull-down impedance based on a first pull-down code included in the first code.

2. The impedance calibration circuit according to claim 1, wherein the target impedance code generation circuit is configured as follows: Compare the target impedance value with the threshold impedance value; and The target impedance code is generated based on the code selected from the first code and the second code according to the result of the comparison.

3. The impedance calibration circuit according to claim 2, wherein the target impedance code generation circuit is configured as follows: When the target impedance value is greater than the threshold impedance value, the first code is generated as the target impedance code, or the target impedance code is generated by shifting the first code. When the target impedance value is less than the threshold impedance value, the second code is generated as the target impedance code, or the target impedance code is generated by shifting the second code.

4. The impedance calibration circuit according to claim 1, wherein the target impedance code generation circuit comprises: An impedance comparator is configured to output a comparison result by comparing the target impedance value with a threshold impedance value; as well as The operating circuit is configured to generate the target impedance code based on a code selected from the first code and the second code according to the result of the comparison.

5. The impedance calibration circuit according to claim 1, wherein the second code generation circuit comprises: The second reference resistor forming circuit is configured to form the resistance of the second reference resistor based on the first pull-up code or the first pull-down code; At least one pull-up driver is configured to form a second pull-up impedance based on the second pull-up code included in the second code; as well as At least one pull-down driver is configured to form a second pull-down impedance based on the second pull-down code included in the second code.

6. The impedance calibration circuit of claim 5, wherein the second reference resistor forming circuit comprises a plurality of ZQ pull-up drivers connected in parallel with each other, and Each of the plurality of ZQ pull-up drivers is configured to form an impedance value that is the same as the first pull-up impedance, based on the first pull-up code.

7. The impedance calibration circuit of claim 5, wherein the second reference resistor forming circuit comprises a plurality of ZQ pull-down drivers connected in parallel with each other, and Each of the plurality of ZQ pull-down drivers is configured to: form an impedance value that is the same as the first pull-down impedance based on the first pull-down code.

8. The impedance calibration circuit according to claim 5, wherein the target impedance code generation circuit comprises: The pull-up decoder is configured to generate target impedance pull-up codes included in the target impedance codes based on the first pull-up code, the second pull-up code, and the target impedance value. as well as The pull-down decoder is configured to generate target impedance pull-down codes included in the target impedance codes based on the first pull-down code, the second pull-down code, and the target impedance value.

9. The impedance calibration circuit of claim 8, wherein the termination driver is configured to form a termination impedance and includes: The pull-up termination driver is configured to: form a pull-up termination impedance value based on the target impedance pull-up code; as well as The termination pull-down driver is configured to generate a pull-down termination impedance value based on the target impedance pull-down code.

10. The impedance calibration circuit of claim 9, wherein the termination pull-up driver comprises a plurality of PMOS transistors having successively doubled widths, each of the plurality of PMOS transistors being driven by a bit value included in the target impedance pull-up code, and The termination pull-down driver includes a plurality of NMOS transistors having progressively doubled widths, each of which is driven by a bit value included in the target impedance pull-down code.

11. An impedance calibration circuit, comprising: The first code generation circuit is configured as follows: The first code is generated by using the first reference resistor, and A resistor is formed based on the first reference resistor and the first code; The second code generation circuit includes a plurality of ZQ pull-up drivers, the plurality of ZQ pull-up drivers being configured to form a second reference resistor based on the first code, and the second code generation circuit being configured to generate a second code by using the second reference resistor; as well as The target impedance code generation circuit is configured as follows: Based on the comparison between the target impedance value and the threshold impedance value, one code is selected from the first code and the second code. Based on the selected code, generate the target impedance code, and An impedance with the target impedance value is formed in the termination driver connected to the impedance calibration circuit. Each ZQ pull-up driver includes one or more PMOS transistors or one or more NMOS transistors.

12. The impedance calibration circuit of claim 11, wherein the target impedance code generation circuit is configured to: When the target impedance value is greater than the threshold impedance value, the first code is selected, and When the target impedance value is less than the threshold impedance value, the second code is selected.

13. The impedance calibration circuit of claim 11, wherein the resistance of the second reference resistor corresponds to a value obtained by dividing the resistance of the first reference resistor by the number of ZQ pull-up drivers.

14. The impedance calibration circuit of claim 11, wherein the threshold impedance value is less than the resistance of the first reference resistor and greater than the resistance of the second reference resistor.

15. The impedance calibration circuit of claim 11, wherein the target impedance code generation circuit is configured to: When the target impedance value is greater than the threshold impedance value, in response to the target impedance value being the same as the resistance of the first reference resistor, the first code is output as the target impedance code; and in response to the target impedance value being different from the resistance of the first reference resistor, the target impedance code is generated by shifting the first code by one bit. When the target impedance value is less than the threshold impedance value, in response to the target impedance value being the same as the resistance of the second reference resistor, the second code is output as the target impedance code, and in response to the target impedance value being different from the resistance of the second reference resistor, the target impedance code is generated by shifting the second code by one bit.

16. The impedance calibration circuit of claim 11, wherein the first code generation circuit comprises: At least one ZQ pull-up driver is configured to form a first pull-up impedance based on the first pull-up code included in the first code; as well as At least one ZQ pull-down driver is configured to: form a first pull-down impedance based on the first pull-down code included in the first code, and Each of the plurality of ZQ pull-up drivers corresponds to the at least one ZQ pull-up driver.

17. An impedance calibration method performed by an impedance calibration circuit in a storage device, the storage device comprising: The storage cell area includes a first metal pad; the peripheral circuit area includes a second metal pad and is vertically connected to the storage cell area via the first metal pad and the second metal pad. The impedance calibration circuit is connected to the first reference resistor, and the impedance calibration method includes: By using the first reference resistor, a first code for forming a resistor based on the first reference resistor is generated; The resistance of the second reference resistor is formed based on the first code, and the second code is generated by using the second reference resistor; and Based on the first code, the second code, and the target impedance value, a target impedance code corresponding to the target impedance value is generated. The generation of the target impedance code includes: Compare the target impedance value with the threshold impedance value; and The target impedance code is generated by using a code selected from the first code and the second code based on the result of the comparison.

18. The impedance calibration method of claim 17, wherein generating the target impedance code by using the selected code comprises: When the target impedance value is greater than the threshold impedance value, the target impedance code is generated based on using the first code as the target impedance code or using a code obtained by shifting the first code by at least one bit; as well as When the target impedance value is less than the threshold impedance value, the target impedance code is generated based on using the second code as the target impedance code or using a code obtained by shifting the second code by at least one bit.

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