Metal to source / drain plug gap patterning in semiconductor devices

Abstract

The present disclosure relates to gap patterning of metal to source / drain plugs in semiconductor devices. A method may include providing a mask layer on top of a first dielectric layer provided on a first source / drain and a second source / drain, and creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain. The method may include filling the opening with a metal layer covering the exposed portions of the first source / drain and the second source / drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may be electrically coupled to the first source / drain, and the second metal contact may be electrically coupled to the second source / drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Description

Technical Field

[0001] The present disclosure relates generally to the field of manufacturing semiconductor devices, and more particularly to gap patterning of metal to source / drain plugs in semiconductor devices. Background Art

[0002] A fin field effect transistor (finFET) is a multi-gate device that includes a metal oxide semiconductor field effect transistor (MOSFET) built on a substrate. The gates are placed on two, three or four sides of the channel, or around the channel, forming a dual gate structure. Summary of the invention

[0003] According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: forming a mask layer on top of a first dielectric layer, the first dielectric layer being formed on a first source / drain and a second source / drain; creating openings in the mask layer and the first dielectric layer, the openings exposing portions of the first source / drain and the second source / drain; filling the openings with a metal layer, the metal layer covering the exposed portions of the first source / drain and the second source / drain; forming a gap in the metal layer to create a first metal contact and a second metal contact; wherein the first metal contact is electrically coupled to the first source / drain and the second metal contact is electrically coupled to the second source / drain, and wherein the gap separates the first metal contact from the second metal contact by less than nineteen nanometers; and filling the gap with material for the first dielectric layer.

[0004] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: providing a mask layer on top of a first dielectric layer formed on a first source / drain and a second source / drain; creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain; filling the openings with a sacrificial layer covering the exposed portions of the first source / drain and the second source / drain; forming a gap in the sacrificial layer; filling the gap with a material for the first dielectric layer to form a spacer; removing the sacrificial layer to create a first opening that exposes a portion of the first source / drain and a second opening that exposes a portion of the second source / drain; filling the first opening with a metal to form a first metal contact; and filling the second opening with a metal to form a second metal contact, wherein the first metal contact is electrically coupled to the first source / drain and the second metal contact is electrically coupled to the second source / drain, and wherein the spacer separates the first metal contact from the second metal contact by less than nineteen nanometers.

[0005] According to a third aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate layer comprising a plurality of fins; a first source / drain electrically coupled to one or more first fins among the plurality of fins; a second source / drain spaced apart from the first source / drain and electrically coupled to one or more second fins among the plurality of fins; a first metal contact electrically coupled to the first source / drain; a second metal contact electrically coupled to the second source / drain; and a dielectric layer separating the first metal contact from the second metal contact by less than nineteen nanometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a diagram of an example implementation of a semiconductor processing tool as described herein.

[0008] Figure 2A-2N is a diagram of one or more example operations involved in fabricating the example semiconductor devices described herein.

[0009] Figure 3A-3P is a diagram of another one or more example operations involved in fabricating the example semiconductor devices described herein.

[0010] Figure 4 is a diagram of an example semiconductor device described herein.

[0011] Figure 5 yes Figure 1 A diagram of example components of one or more devices.

[0012] Figure 6 and Figure 7 is a flow chart of an example process for fabricating an example semiconductor device based on gap patterning of metal to source / drain plugs in the example semiconductor device. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] In some cases, a semiconductor device such as a finFET includes metal-to-source / drain plugs (e.g., source / drain epitaxial layers) that are electrically coupled to other components of the semiconductor device using an island patterning technique. The island patterning technique includes patterning a photoresist layer between the metal-to-source / drain plugs to create openings that expose the metal-to-source / drain plugs. The openings are filled with metal contacts that are electrically coupled to the corresponding metal-to-source / drain plugs. In the island patterning technique, the metal contacts are separated by at least a minimum distance (e.g., at least nineteen (19) nanometers (nm)). However, some semiconductor designs may dictate that the metal contacts be separated by less than the minimum distance provided by the island patterning technique. In addition, the island patterning technique may result in less interface between the source / drain and the corresponding metal-to-source / drain plug, which may result in an undesirable increase in the resistance of the corresponding metal-to-source / drain plug.

[0016] According to some embodiments described herein, a first method for manufacturing a semiconductor device (e.g., a finFET) is based on gap patterning of a metal to source / drain plug in a semiconductor device. For example, the first method may include forming a mask layer on top of a first dielectric layer formed on a first source / drain plug and a second source / drain plug, and creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain plug and the second source / drain plug. The first method may include filling the opening with a metal layer covering the exposed portions of the first source / drain plug and the second source / drain plug, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may be electrically coupled to the first source / drain plug, and the second metal contact may be electrically coupled to the second source / drain plug. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers. The first method may include filling the gap with a material for the first dielectric layer.

[0017] According to some embodiments described herein, a second method for manufacturing a semiconductor device (e.g., a finFET) is based on gap patterning of a metal to source / drain plug in a semiconductor device. For example, the second method may include forming a mask layer on top of a first dielectric layer formed on a first source / drain plug and a second source / drain plug, and creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain plug and the second source / drain plug. The second method may include filling the opening with a sacrificial layer covering the exposed portions of the first source / drain plug and the second source / drain plug, and forming a gap in the sacrificial layer. The second method may include filling the gap with a material for the first dielectric layer to form a spacer, and removing the sacrificial layer to create a first opening that exposes a portion of the first source / drain plug and a second opening that exposes a portion of the second source / drain plug. The second method may include filling the first opening with a metal to form a first metal contact, and filling the second opening with a metal to form a second metal contact. The first metal contact may be electrically coupled to the first source / drain plug, and the second metal contact may be electrically coupled to the second source / drain plug.The spacer may separate the first metal contact from the second metal contact by less than nineteen nanometers.

[0018] In this way, the first method and the second method for manufacturing a semiconductor device can be based on the gap patterning of the metal to source / drain plug in the semiconductor device. The first method and the second method enable the metal contacts electrically coupled to the corresponding metal to source / drain plug of the semiconductor device to be separated by less than the minimum distance provided by the island patterning technology (e.g., less than nineteen nanometers). Therefore, the first method and the second method can be used for semiconductor designs that indicate that the metal contacts are separated by less than a specific distance (e.g., nineteen nanometers). In addition, the first method and the second method provide more interfaces between the source / drain and the corresponding metal to source / drain plug (e.g., relative to the island patterning technology), which reduces the resistance of the corresponding metal to source / drain plug (e.g., relative to the island patterning technology).

[0019] Figure 1 1 is a diagram of an example implementation 100 of a semiconductor processing tool as described herein. As shown, the tool configuration may include one or more deposition (depo) tools, one or more photoresist (photo) tools, one or more etching tools, one or more metal tools, one or more chemical mechanical polishing (CMP) tools, etc. A semiconductor device may be provided to one or more of the aforementioned tools via a manipulator device (e.g., a robotic arm, multiple robotic arms, etc.). Although Figure 1 Different modules (e.g., deposition, lithography, etching, etc.) in the same tool configuration are shown, but different modules may be provided in different tool configurations. Figure 1 To explain the process sequence. In some embodiments, the tool configuration is used to produce the following combination Figure 2A-4 A semiconductor device is described.

[0020] Deposition tools may include tools for depositing materials such as insulating layers, dielectric layers, mask layers, metal layers, etc. on semiconductor devices. Deposition is any process for growing, coating, or otherwise transferring a material onto a semiconductor device. Deposition tools may include tools for forming a thin film of material on a semiconductor device by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), etc. In some embodiments, deposition includes a chamber capable of depositing a layer on a semiconductor device. The chamber may be filled with a gas (e.g., argon) maintained at a specific temperature, provided at a specific flow rate, maintained at a specific pressure, etc., depending on the material deposited on the semiconductor device.

[0021] A photoresist tool may include a tool for removing material from or providing material to a semiconductor device based on a photoresist layer (e.g., a photoresist mask) applied to the semiconductor device. A photoresist is a photosensitive material used to form a patterned coating on the surface of a semiconductor device in several processes (e.g., photolithography, photoengraving, etc.). A photoresist tool may coat a semiconductor device with a photosensitive organic material, and a patterned mask may be applied to the semiconductor device to block light so that only unmasked areas of the photosensitive organic material will be exposed to light. A photoresist tool or another tool (e.g., an etching tool) may apply a solvent called a developer to the semiconductor device. In the case of a positive photoresist, the photosensitive organic material is photodegraded, and the developer dissolves away the areas exposed to light, leaving a coating where the mask is placed. In the case of a negative photoresist, the photosensitive organic material is photoenhanced (e.g., polymerized or cross-linked), and the developer dissolves away only the areas not exposed to light, leaving a coating where the mask is not placed.

[0022] The etching tool may include a tool for removing material from the surface of the semiconductor device. In some embodiments, a portion of the semiconductor device is protected from the etchant by a masking material that resists etching. For example, the masking material may include a photoresist patterned using photolithography. The etching tool may perform a wet etching process or a dry (e.g., plasma) etching process on the semiconductor device. In a wet etching process, the semiconductor device may be immersed in a series of liquid (e.g., wet) etchants, which may be stirred to achieve process control. For example, buffered hydrofluoric acid (BHF) may be used to etch silicon dioxide on a silicon substrate. The plasma etching process may be operated in several modes based on adjusting the parameters of the plasma. For example, the plasma etching process may be operated at a pressure in the range of about 0.01 torr to about 5 torr. The plasma generates high-energy free radicals that are neutrally charged and react at the surface of the semiconductor device. Plasma etching may be isotropic (e.g., exhibiting a lateral undercut rate that is approximately the same as the downward etching rate on the patterned surface) or anisotropic (e.g., exhibiting a lateral undercut rate that is smaller than the downward etching rate). The gas source of the plasma may include small molecules rich in chlorine or fluorine. For example, carbon tetrafluoride can be used to etch silicon and chlorine can be used to etch aluminum, trifluoromethane can be used to etch silicon dioxide and silicon nitride, etc. The plasma may also include oxygen for oxidizing the photoresist and facilitating its removal.

[0023] The metal tool may include a tool for forming a metal layer on a semiconductor device. In some embodiments, the metal tool includes a chamber capable of depositing a metal layer on a semiconductor device. The chamber may be filled with a gas (e.g., argon), which is maintained at a specific temperature (e.g., 510°C, 530°C, etc.) and provided at a specific flow rate (e.g., 20, 25, 30, etc. standard cubic centimeters per minute (sccm)). In some embodiments, the metal tool may include a heater assembly, a target assembly, and a magnetron disposed in the chamber of the metal tool. The heater assembly may include a support pad that is sized and shaped to support the semiconductor device. The support pad may include one or more heating elements that generate heat, and the heat generated is transferred to the semiconductor device based on the semiconductor device contacting the support pad. The target assembly may include a material for creating a metal layer on a semiconductor device via a technique called thin film deposition. For example, the target assembly may include an aluminum material, a copper material, an aluminum-copper material, etc. The magnetron may include a plurality of magnetic columns that generate a magnetic field when the magnetron rotates.

[0024] In operation, since the magnetron is located behind the target component, the plasma generated from the target component can be confined to the target surface of the semiconductor device. The rotation of the magnetron can generate a magnetic field that forms a closed loop annular path that acts as an electron trap, which shapes the trajectory of the secondary electrons ejected from the target component to a cycloidal path, which increases the possibility of ionization of the sputtering gas in the chamber. An inert gas (e.g., argon) can be used as a sputtering gas because the inert gas tends not to react with the target component or combine with any process gas, and because the inert gas produces a higher sputtering and deposition rate due to the high molecular weight. The positively charged argon ions from the plasma can be accelerated toward the negatively biased target component, causing material to be expelled from the surface of the target component and reach the semiconductor device.

[0025] CMP tools can include tools that use a combination of chemical and mechanical forces (e.g., chemical etching and free-abrasive polishing) to smooth the surface of a semiconductor device. CMP tools can use abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and semiconductor device are squeezed together by a dynamic polishing head and fixed in place by a retaining ring. The dynamic polishing head rotates with different rotation axes to remove material and even out any irregular topography of the semiconductor device, thereby flattening or planarizing the semiconductor device.

[0026] As mentioned above, providing Figure 1 Just one or more examples. Other examples can be related to Figure 1 Different than described.

[0027] Figure 2A-2N2 is a diagram of one or more example operations 200 involved in fabricating an example semiconductor device (eg, a logic device, a memory device, a finFET, a MOSFET, etc.). Figure 2A As shown, the semiconductor device may include a substrate layer having a plurality of fins, an insulating layer, a source / drain epitaxial layer, and a first dielectric layer. The substrate layer and the plurality of fins may include a conductive material or a semiconductive material, such as silicon, aluminum, copper, and the like. The insulating layer may include a material that insulates the substrate layer and the plurality of fins, such as tantalum nitride, silicon oxide, silicate glass, silicon oxycarbide, and the like. In some embodiments, the insulating layer is formed by shallow trench isolation to prevent current leakage between adjacent fins of the substrate layer. The source / drain epitaxial layer may include silicon germanium formed via epitaxial growth. In some embodiments, the source / drain epitaxial layer may form a first source / drain plug electrically coupled to a first pair of fins of the substrate layer, and a second source / drain plug electrically coupled to a second pair of fins of the substrate layer. The first dielectric layer may include a material that electrically insulates the first source / drain plug and the second source / drain plug from each other and from other components of the semiconductor device. For example, the first dielectric layer may include silicon nitride, silicon oxide, a low-k material, and the like.

[0028] like Figure 2A As further shown, and by reference numeral 205, a mask layer may be formed on the semiconductor device. For example, the mask layer may be formed on top of the first dielectric layer of the semiconductor device. The mask layer may include metal oxide, titanium nitride (TiN), tungsten carbide (WC), etc. In some embodiments, the above is combined with Figure 1 The deposition tool and / or the metal tool of the described tool configuration may be used to form a mask layer on top of the first dielectric layer.

[0029] like Figure 2B As shown, and by reference numeral 210, a first bottom layer may be formed on top of the mask layer, a first intermediate layer may be formed on top of the first bottom layer, and a first photoresist layer may be formed on a portion of the first intermediate layer. The first bottom layer may include an organic material, such as carbon, oxygen, hydrogen, thermosetting polyarylether, and the like. The first intermediate layer may include an anti-reflective coating (ARC) material, such as silicon, oxygen, nitrogen, silicon oxide, silicon-containing ARC material, and the like. The first photoresist layer may include a photoresist material, such as a photopolymerizable photoresist (e.g., methyl methacrylate), a photodegradable photoresist (e.g., diazonaphthaquinone), a photocross-linked photoresist, and the like. In some embodiments, the photoresist layer is patterned on a portion of the first intermediate layer so that an opening may be formed to expose the first source / drain plug and the second source / drain plug, as described below. In some embodiments, the above is combined with Figure 1 The photoresist tool of the described tool configuration may be used to form a first bottom layer on top of a mask layer, to form a first intermediate layer on top of the first bottom layer, and to form a first photoresist layer on a portion of the first intermediate layer.

[0030] like Figure 2C As shown and by reference numeral 215, the first bottom layer, the first intermediate layer, the first photoresist layer, and a portion of the mask layer may be removed based on forming a first photoresist layer on a portion of the first intermediate layer. Figure 2C As shown, such removal transfers the pattern to the mask layer and portions of the mask layer to remain on top of the first dielectric layer. In some embodiments, one or more photolithography and / or etching operations can be performed to remove the first bottom layer, the first intermediate layer, the first photoresist layer, and a portion of the mask layer. For example, one or more photolithography operations can be performed to remove the first bottom layer, the first intermediate layer, and portions of the mask layer that are not formed below the first photoresist layer. One or more etching operations can be performed to remove the remaining portions of the first bottom layer, the first intermediate layer, and the first photoresist layer from the semiconductor device. For example, after the first photoresist pattern is transferred to the first mask layer, a dry etching operation using carbon tetrafluoride gas, CF3H gas, etc. is used to etch the first intermediate layer; a dry etching operation using SO2, O2 gas, etc. is used to etch the first bottom layer; and a dry etching operation using carbon tetrafluoride gas, C4F6 gas, etc. is used to etch the first mask layer. In some embodiments, the above is combined with Figure 1 The photoresist tool and / or etching tool of the described tool configuration may be used to etch portions of the first bottom layer, the first intermediate layer, the first photoresist layer, and the mask layer based on forming the first photoresist layer on portions of the first intermediate layer.

[0031] like Figure 2D As shown, and by reference numeral 220, the first dielectric layer that is not formed under the portion of the mask layer can be removed to form an opening that exposes the source / drain epitaxial layer (e.g., the first source / drain plug and the second source / drain plug). In some embodiments, one or more etching operations can be performed to remove the first dielectric layer that is not formed under the portion of the mask layer and form an opening that exposes the source / drain epitaxial layer. For example, a dry etching operation using carbon tetrafluoride gas, hexafluorocyclobutane gas, octafluorocyclobutane gas, oxygen, etc. can be performed to remove the first dielectric layer that is not formed under the portion of the mask layer and form an opening that exposes the source / drain epitaxial layer (e.g., the first source / drain plug and the second source / drain plug). In some embodiments, a CESL (e.g., SiN, etch stop layer) layer can be deposited before depositing the first dielectric layer. In some embodiments, the above is combined with Figure 1The etching tool of the described tool configuration may be used to remove the first dielectric layer not formed under the portion of the mask layer and form openings exposing the source / drain epitaxial layer.

[0032] like Figure 2E As shown, and by reference numeral 225, the openings in the first dielectric layer and the mask layer can be filled with a first metal layer covering the source / drain epitaxial layer (e.g., a first source / drain plug and a second source / drain plug). The first metal layer may include a metal, such as cobalt, tungsten, aluminum, copper, etc. In some embodiments, a metal deposition operation can be performed to fill the openings in the first dielectric layer and the mask layer with the first metal layer covering the source / drain epitaxial layer. For example, PVD, CVD, ALD, MBE, ECD, etc. can be performed to fill the openings in the first dielectric layer and the mask layer with the first metal layer covering the source / drain epitaxial layer. In some embodiments, the above is combined with Figure 1 The deposition tool and / or metal tool of the described tool configuration can be used to fill the openings in the first dielectric layer and the mask layer with a first metal layer covering the source / drain epitaxial layer. In some embodiments, a barrier layer (e.g., TaN, TiN, etc.) can be deposited before the metal fill. In some embodiments, the first metal layer provides a better interface with the source / drain epitaxial layer (e.g., the first source / drain plug and the second source / drain plug) (relative to the island patterning technique), which reduces the resistance between the first metal layer and the source / drain epitaxial layer (relative to the island patterning technique).

[0033] like Figure 2F As shown, and by reference numeral 230, the first metal layer can be polished to be substantially flush with and / or below the first dielectric layer, and the mask layer can be removed. In some embodiments, a CMP operation can be performed to polish the first metal layer to be substantially flush with the first dielectric layer and remove the mask layer. In some embodiments, the above combined Figure 1 The CMP tool of the described tool configuration may be used to polish the first metal layer to be substantially flush with and / or below the first dielectric layer and to remove the mask layer.

[0034] like Figure 2GAs shown, and by reference numeral 235, a second bottom layer can be formed on top of the first metal layer and the first dielectric layer, a second intermediate layer can be formed on top of the second bottom layer, and a second photoresist layer can be formed on a portion of the second intermediate layer. The second bottom layer can include an organic material, such as carbon, oxygen, hydrogen, thermosetting polyarylether, and the like. The second intermediate layer can include an ARC material, such as silicon, oxygen, nitrogen, silicon oxide, silicon-containing ARC material, and the like. The second photoresist layer can include a photoresist material, such as a photopolymerizable photoresist, a photodecomposed photoresist, a photocrosslinked photoresist, and the like. In some embodiments, the second photoresist layer is patterned on a portion of the second intermediate layer so that a gap can be formed in the first metal layer, as described below. In some embodiments, the above is combined with Figure 1 The photoresist tool of the described tool configuration may be used to form a second bottom layer on top of the first metal layer and the first dielectric layer, a second intermediate layer on top of the second bottom layer, and a second photoresist layer on a portion of the second intermediate layer.

[0035] like Figure 2H As shown, and by reference numeral 240, the second bottom layer, the second intermediate layer, the second photoresist layer can be removed, and a portion of the first metal layer can be removed, and the pattern can be transferred to form a gap in the first metal layer. For example, the first metal layer that is not formed below the second photoresist layer can be removed to form a gap in the first metal layer. In some embodiments, one or more photolithography and / or etching operations can be performed to perform etching on the second bottom layer, the second intermediate layer, and the second photoresist layer and form a gap in the first metal layer. For example, one or more photolithography operations can be performed to remove the portion of the second bottom layer and the second intermediate layer that is not formed below the second photoresist layer. One or more etching operations can be performed to remove the remaining portion of the second bottom layer, the second intermediate layer, and the second photoresist layer from the semiconductor device.

[0036] In some embodiments, one or more etching operations may be performed to remove the first metal layer that is not formed under the second photoresist layer and to form a gap in the first metal layer. For example, when the first metal layer is made of cobalt, a dry etching operation using chlorine and hydrogen, chlorine and oxygen, etc. may be performed to remove the first metal layer that is not formed under the second photoresist and to form a gap in the first metal layer. In another example, when the first metal layer is made of tungsten, a dry etching operation using carbon tetrafluoride gas, nitrogen trifluoride gas, sulfur hexafluoride gas, etc. may be performed to remove the first metal layer that is not formed under the second photoresist and to form a gap in the first metal layer. In some embodiments, the above is combined with Figure 1The photoresist tool and / or etching tool of the described tool configuration can be used to etch the second bottom layer, the second intermediate layer, the second photoresist layer, and / or the first metal layer to form a gap in the first metal layer. In some embodiments, the gap creates a first metal contact and a second metal contact, such as Figure 2H As shown. The first metal contact can be electrically coupled to the first source / drain plug, and the second metal contact can be electrically coupled to the second source / drain plug. In some embodiments, the gap separates the first metal contact from the second metal contact by less than nineteen nanometers, for example, a gap of about eight nanometers, a gap in a range of about eight nanometers to less than nineteen nanometers, etc.

[0037] like Fig.2I As shown, and by reference numeral 245, the gap in the first metal layer can be filled with the material used for the first dielectric layer. For example, the gap can be filled with silicon nitride, silicon oxide, low-k material, etc., and then the surface can be planarized using CMP. The dielectric material filled in the gap can electrically isolate the first metal contact from the second metal contact. In some embodiments, the above combination Figure 1 The deposition tool of the described tool configuration may be used to fill gaps in the first metal layer with material for the first dielectric layer.

[0038] like Figure 2J As shown, and by reference numeral 250, a second dielectric layer can be formed on the first metal layer (e.g., the first metal contact and the second metal contact) and the first dielectric layer. The second dielectric layer can include a material that electrically insulates the first metal layer and the first dielectric layer from other components of the semiconductor device. For example, the second dielectric layer can include silicon nitride, silicon oxide, low-k material, etc. In some embodiments, the above combination Figure 1 The deposition tool of the described tool configuration may be used to form a second dielectric layer on the first metal layer and the first dielectric layer.

[0039] like Figure 2K As shown, and by reference numeral 255, a third bottom layer can be formed on top of the second dielectric layer, a third intermediate layer can be formed on top of the third bottom layer, and a third photoresist layer can be formed on a portion of the third intermediate layer. The third bottom layer can include an organic material, such as carbon, oxygen, hydrogen, thermosetting polyarylether, and the like. The third intermediate layer can include an ARC material, such as silicon, oxygen, nitrogen, silicon oxide, silicon-containing ARC material, and the like. The third photoresist layer can include a photoresist material, such as a photopolymerized photoresist, a photodecomposed photoresist, a photocross-linked photoresist, and the like. In some embodiments, the third photoresist layer is patterned on a portion of the third intermediate layer so that a through hole can be formed in the second dielectric layer, as described below. In some embodiments, the above is combined with Figure 1 The photoresist tool of the described tool configuration may be used to form a third bottom layer on top of the second dielectric layer, a third intermediate layer on top of the third bottom layer, and a third photoresist layer on a portion of the third intermediate layer.

[0040] like Figure 2L As shown, and by reference numeral 260, the third bottom layer, the third intermediate layer, and the third photoresist layer can be etched and the pattern can be transferred to the second dielectric layer, and a portion of the second dielectric layer can be removed based on forming the third photoresist layer on a portion of the third intermediate layer to form a through hole in the second dielectric layer. In some embodiments, one or more photolithography and / or etching operations can be performed to remove the third bottom layer, the third intermediate layer, and the third photoresist layer, and form a through hole in the second dielectric layer. For example, one or more photolithography operations can be performed to remove portions of the third bottom layer and the third intermediate layer that are not formed under the third photoresist layer. One or more etching operations can be performed to remove the remaining portions of the third bottom layer, the third intermediate layer, and the third photoresist layer from the semiconductor device.

[0041] In some embodiments, one or more etching operations may be performed to remove the second dielectric layer that is not formed under the third photoresist layer and form a through hole in the second dielectric layer. For example, a dry etching operation using chlorine and hydrogen gas, chlorine and oxygen gas, carbon tetrafluoride gas, nitrogen trifluoride gas, sulfur hexafluoride gas, etc. may be performed to remove the second dielectric layer that is not formed under the third photoresist layer and form a through hole in the second dielectric layer. In some embodiments, the above is combined with Figure 1 The photoresist tool and / or the etching tool of the described tool configuration may be used to remove the third bottom layer, the third intermediate layer and the third photoresist layer and form a via in the second dielectric layer.

[0042] like Figure 2M As shown, and by reference numeral 265, a second metal layer can be formed on the second dielectric layer to fill the through-holes in the second dielectric layer with the second metal layer and make the second metal layer contact with portions of the first metal layer (e.g., the first metal contact and the second metal contact). The second metal layer may include a metal, such as cobalt, tungsten, aluminum, copper, etc. In some embodiments, a metal deposition operation can be performed to form a second metal layer on the second dielectric layer and fill the through-holes in the second dielectric layer with the second metal layer. For example, PVD, CVD, ALD, MBE, ECD, etc. can be performed to form a second metal layer on the second dielectric layer and fill the through-holes in the second dielectric layer with the second metal layer. In some embodiments, the above is combined with Figure 1The deposition tool and / or the metal tool of the described tool configuration may be used to form a second metal layer on the second dielectric layer and to fill vias in the second dielectric with the second metal layer.

[0043] like Figure 2N As shown, and by reference numeral 270, the second metal layer can be polished to be substantially flush with the second dielectric layer. In some embodiments, a CMP operation can be performed to polish the second metal layer to be substantially flush with the second dielectric layer. In some embodiments, the above combination Figure 1 A CMP tool with the tool configuration described can be used to polish the second metal layer to be substantially flush with the second dielectric layer. Figure 2N As further shown, the second metal layer formed in the through hole of the second dielectric layer can form a third metal contact and a fourth metal contact. In some embodiments, the third metal contact is electrically coupled to the first metal contact, and the fourth metal contact is electrically coupled to the second metal contact.

[0044] In this way, combined Figure 2A-2N A method for manufacturing a semiconductor device is described such that metal contacts electrically coupled to respective metal-to-source / drain plugs of the semiconductor device are separated by less than nineteen nanometers, within a range from about eight nanometers to less than nineteen nanometers, etc. Thus, the method can be used to indicate a semiconductor design in which the metal contacts are to be separated by less than nineteen nanometers. In addition, the method provides more interfaces between the source / drain and the respective metal-to-source / drain plugs (e.g., relative to island patterning techniques), which reduces the resistance of the respective metal-to-source / drain plugs (e.g., relative to island patterning techniques).

[0045] As shown above, provide Figure 2A-2N Just one or more examples. Other examples can be related to Figure 2A-2N The examples described are different.

[0046] Figure 3A-3P is a diagram of one or more example operations 300 involved in fabricating an example semiconductor device (eg, a logic device, a memory device, a finFET, a MOSFET, etc.). Figure 3A As shown, the semiconductor device may include a substrate layer having a plurality of fins, an insulating layer, a source / drain epitaxial layer, and a first dielectric layer. Figure 3A The substrate layer, the plurality of fins, the insulating layer, the source / drain epitaxial layer (eg, the first source / drain plug and the second source / drain plug), and the first dielectric layer may include the above combination Figure 2A Features described.

[0047] like Figure 3AAs further shown, and by reference numeral 305, a mask layer may be formed on the semiconductor device. For example, the mask layer may be formed on top of the first dielectric layer of the semiconductor device. The mask layer may include metal oxide, titanium nitride, tungsten carbide, etc. In some embodiments, the above combined Figure 1 The deposition tool and / or the metal tool of the described tool configuration may be used to form a mask layer on top of the first dielectric layer.

[0048] like Figure 3B As shown, and by reference numeral 310, a first bottom layer may be formed on top of the mask layer, a first intermediate layer may be formed on top of the first bottom layer, and a first photoresist layer may be formed on a portion of the first intermediate layer. The first bottom layer may include an organic material, such as carbon, oxygen, hydrogen, thermosetting polyarylether, and the like. The first intermediate layer may include an ARC material, such as silicon, oxygen, nitrogen, silicon oxide, silicon-containing ARC material, and the like. The first photoresist layer may include a photoresist material, such as a photopolymerizable photoresist, a photodecomposed photoresist, a photocross-linked photoresist, and the like. In some embodiments, the photoresist layer is patterned on a portion of the first intermediate layer so that an opening may be formed to expose the first source / drain plug and the second source / drain plug, as described below. In some embodiments, the above is combined with Figure 1 The photoresist tool of the described tool configuration may be used to form a first bottom layer on top of a mask layer, a first intermediate layer on top of the first bottom layer, and a first photoresist layer on a portion of the first intermediate layer.

[0049] like Figure 3C As shown and by reference numeral 315, the first bottom layer, the first intermediate layer, the first photoresist layer, and a portion of the mask layer may be removed based on forming a first photoresist layer on a portion of the first intermediate layer. Figure 3C As shown, such removal may leave portions of the mask layer on top of the first dielectric layer. In some embodiments, one or more photolithography and / or etching operations may be performed to remove the first bottom layer, the first intermediate layer, the first photoresist layer, and a portion of the mask layer. For example, one or more photolithography operations may be performed to remove the first bottom layer, the first intermediate layer, and the portions of the mask layer that are not formed below the first photoresist layer. One or more etching operations may be performed to remove the remaining portions of the first bottom layer, the first intermediate layer, and the first photoresist layer from the semiconductor device. For example, after the first photoresist pattern is transferred to the first mask layer, a dry etching operation using carbon tetrafluoride gas, CF3H gas, etc. is used to etch the first intermediate layer; a dry etching operation using SO2, O2 gas, etc. is used to etch the first bottom layer; and a dry etching operation using carbon tetrafluoride gas, C4F6 gas, etc. is used to etch the first mask layer. In some embodiments, the above is combined with Figure 1The photoresist tool and / or etching tool of the described tool configuration may be used to remove portions of the first bottom layer, the first intermediate layer, the first photoresist layer, and the mask layer based on forming the first photoresist layer on portions of the first intermediate layer.

[0050] like Figure 3D As shown, and by reference numeral 320, the first dielectric layer not formed under the portion of the mask layer can be removed to form an opening exposing the source / drain epitaxial layer (e.g., a first source / drain plug and a second source / drain plug). In some embodiments, one or more etching operations can be performed to remove the first dielectric layer not formed under the portion of the mask layer and form an opening exposing the source / drain epitaxial layer. For example, a dry etching operation using carbon tetrafluoride gas, hexafluorocyclobutane gas, octafluorocyclobutane gas, oxygen, etc. can be performed to remove the first dielectric layer not formed under the portion of the mask layer and form an opening exposing the source / drain epitaxial layer. In some embodiments, the above is combined with Figure 1 The etching tool of the described tool configuration may be used to remove the first dielectric layer not formed under the portion of the mask layer and form openings exposing the source / drain epitaxial layer.

[0051] like Figure 3E As shown, and by reference numeral 325, the openings in the first dielectric layer and the mask layer can be filled with a sacrificial layer covering the source / drain epitaxial layer (e.g., a first source / drain plug and a second source / drain plug). The sacrificial layer may include a material that is subsequently removed from the semiconductor device, such as silicon, silicon nitride, hafnium oxide, etc. In some embodiments, a deposition operation can be performed to fill the openings in the first dielectric layer and the mask layer with the sacrificial layer covering the source / drain epitaxial layer. For example, PVD, CVD, ALD, MBE, ECD, etc. can be performed to fill the openings in the first dielectric layer and the mask layer with the sacrificial layer covering the source / drain epitaxial layer. In some embodiments, the above is combined with Figure 1 The deposition tool of the described tool configuration can be used to fill the openings in the first dielectric layer and the mask layer with a sacrificial layer covering the source / drain epitaxial layer. If silicon is used for the sacrificial layer and the first dielectric layer, a liner layer (e.g., other than silicon) can be formed on the walls and bottom of the opening before the sacrificial layer is deposited in the opening.

[0052] like Figure 3F As shown, and by reference numeral 330, the sacrificial layer may be polished to be substantially flush with the first dielectric layer, and the mask layer may be removed. In some embodiments, a CMP operation may be performed to polish the sacrificial layer to be substantially flush with the first dielectric layer and remove the mask layer. In some embodiments, the above combined Figure 1A CMP tool of the described tool configuration may be used to polish the sacrificial layer to be substantially flush with the first dielectric layer and remove the masking layer.

[0053] like Figure 3G As shown, and by reference numeral 335, a second bottom layer can be formed on top of the sacrificial layer and the first dielectric layer, a second intermediate layer can be formed on top of the second bottom layer, and then, a second photoresist layer can be formed on a portion of the second intermediate layer. The second bottom layer can include an organic material, such as carbon, oxygen, hydrogen, thermosetting polyarylether, and the like. The second intermediate layer can include an ARC material, such as silicon, oxygen, nitrogen, silicon oxide, silicon-containing ARC material, and the like. The second photoresist layer can include a photoresist material, such as a photopolymerizable photoresist, a photodecomposed photoresist, a photocross-linked photoresist, and the like. In some embodiments, the second photoresist layer is patterned on a portion of the second intermediate layer so that a gap can be formed in the sacrificial layer, as described below. In some embodiments, the above is combined with Figure 1 The photoresist tool of the described tool configuration may be used to form a second bottom layer on top of the sacrificial layer and the first dielectric layer, a second intermediate layer on top of the second bottom layer, and a second photoresist layer on a portion of the second intermediate layer.

[0054] like Figure 3H As shown, and by reference numeral 340, the second bottom layer, the second intermediate layer, and the second photoresist layer can be removed, and a portion of the sacrificial layer can be removed to form a gap in the sacrificial layer. For example, the sacrificial layer that is not formed below the second photoresist layer can be removed to form a gap in the sacrificial layer. In some embodiments, one or more photolithography and / or etching operations can be performed to remove the second bottom layer, the second intermediate layer, and the second photoresist layer, and form a gap in the sacrificial layer. For example, one or more photolithography operations can be performed to remove the second bottom layer and the second intermediate layer that are not formed below the second photoresist layer. One or more etching operations can be performed to remove the remaining portions of the second bottom layer, the second intermediate layer, and the second photoresist layer from the semiconductor device.

[0055] In some embodiments, one or more etching operations may be performed to remove the sacrificial layer that is not formed below the second photoresist layer and to form a gap in the sacrificial layer. For example, a dry etching operation may be performed to remove the sacrificial layer that is not formed below the second photoresist and to form a gap in the sacrificial layer. Figure 1 The photoresist tool and / or etching tool of the described tool configuration can be used to remove the second bottom layer, the second intermediate layer, and the second photoresist layer and form a gap in the sacrificial layer. In some embodiments, the gap creates a spacer for the first metal contact and the second metal contact, as described below.

[0056] like Fig. 3I As shown, and by reference numeral 345, the gap in the sacrificial layer can be filled with the material used for the first dielectric layer. For example, the gap can be filled with silicon nitride, silicon oxide, etc. The dielectric material filled in the gap can create a spacer that electrically isolates the first metal contact from the second metal contact, as described below. In some embodiments, the above combined Figure 1 The deposition tool of the described tool configuration may be used to fill the gaps in the sacrificial layer with material for the first dielectric layer.

[0057] like Figure 3J As shown, and by reference numeral 350, the sacrificial layer can be removed to form an opening in the first dielectric layer exposing the source / drain epitaxial layer. In some embodiments, one or more etching operations can be performed to remove the sacrificial layer and form the opening in the first dielectric layer. For example, when the sacrificial layer is formed of silicon, a wet etching operation using ammonium hydroxide can be performed to remove the sacrificial layer and form the opening in the first dielectric layer. In another example, when the sacrificial layer is formed of silicon nitride, a wet etching operation using phosphoric acid can be performed to remove the sacrificial layer and form the opening in the first dielectric layer. In some embodiments, the above is combined with Figure 1 An etching tool of the described tool configuration may be used to remove the sacrificial layer and form an opening in the first dielectric layer.

[0058] like Figure 3K As shown, and by reference numeral 355, the opening in the first dielectric layer can be filled with a first metal layer. The first metal layer can include a metal, such as cobalt, tungsten, aluminum, copper, etc. In some embodiments, a metal deposition operation can be performed to fill the opening in the first dielectric layer with the first metal layer covering the source / drain epitaxial layer. For example, PVD, CVD, ALD, MBE, ECD, etc. can be performed to fill the opening in the first dielectric layer with the first metal layer covering the source / drain epitaxial layer. In some embodiments, the above combined Figure 1 The deposition tool and / or metal tool of the described tool configuration may be used to fill the opening in the first dielectric layer with a first metal layer covering the source / drain epitaxial layer. Figure 3KAs further shown, a spacer having a first dielectric material layer can divide the first metal layer into a first metal contact and a second metal contact. The first metal contact can be electrically coupled to the first source / drain plug, and the second metal contact can be electrically coupled to the second source / drain plug. In some embodiments, the spacer separates the first metal contact from the second metal contact by less than nineteen nanometers. In some embodiments, the first metal layer provides more interfaces with the source / drain epitaxial layer (e.g., the first source / drain plug and the second source / drain plug) (relative to the island patterning technique), which reduces the resistance between the first metal layer and the source / drain epitaxial layer (relative to the island patterning technique).

[0059] The first metal layer can be polished to be substantially flush with the first dielectric layer. In some embodiments, a CMP operation can be performed to polish the first metal layer to be substantially flush with the first dielectric layer. In some embodiments, the above combination Figure 1 The CMP tool of the described tool configuration may be used to polish the first metal layer to be substantially flush with the first dielectric layer and to form a first metal contact and a second metal contact.

[0060] like Figure 3L As shown, and by reference numeral 360, a second dielectric layer can be formed on the first metal layer (e.g., the first metal contact and the second metal contact) and the first dielectric layer. The second dielectric layer can include a material that electrically insulates the first metal layer and the first dielectric layer from other components of the semiconductor device. For example, the second dielectric layer can include silicon nitride, silicon oxide, etc. In some embodiments, the above combination Figure 1 The deposition tool of the described tool configuration may be used to form a second dielectric layer on the first metal layer and the first dielectric layer.

[0061] like Figure 3M As shown, and by reference numeral 365, a third bottom layer can be formed on top of the second dielectric layer, a third intermediate layer can be formed on top of the third bottom layer, and a third photoresist layer can be formed on a portion of the third intermediate layer. The third bottom layer can include an organic material, such as carbon, oxygen, hydrogen, thermosetting polyarylether, and the like. The third intermediate layer can include an ARC material, such as silicon, oxygen, nitrogen, silicon oxide, silicon-containing ARC material, and the like. The third photoresist layer can include a photoresist material, such as a photopolymerized photoresist, a photodecomposed photoresist, a photocross-linked photoresist, and the like. In some embodiments, the third photoresist layer is patterned on a portion of the third intermediate layer so that a through hole can be formed in the second dielectric layer, as described below. In some embodiments, the above is combined with Figure 1The photoresist tool of the described tool configuration may be used to form a third bottom layer on top of the second dielectric layer, a third intermediate layer on top of the third bottom layer, and a third photoresist layer on a portion of the third intermediate layer.

[0062] like Figure 3N As shown, and by reference numeral 370, the third bottom layer, the third intermediate layer, and the third photoresist layer can be removed, and a portion of the second dielectric layer can be removed based on forming the third photoresist layer on a portion of the third intermediate layer to form a through hole in the second dielectric layer. In some embodiments, one or more photolithography and / or etching operations can be performed to remove the third bottom layer, the third intermediate layer, and the third photoresist layer, and form a through hole in the second dielectric layer. For example, one or more photolithography operations can be performed to remove portions of the third bottom layer and the third intermediate layer that are not formed below the third photoresist layer. One or more etching operations can be performed to remove the remaining portions of the third bottom layer, the third intermediate layer, and the third photoresist layer from the semiconductor device.

[0063] In some embodiments, one or more etching operations may be performed to remove the second dielectric layer that is not formed under the third photoresist layer and form a through hole in the second dielectric layer. For example, a dry etching operation using chlorine and hydrogen gas, chlorine and oxygen gas, carbon tetrafluoride gas, nitrogen trifluoride gas, sulfur hexafluoride gas, etc. may be performed to remove the second dielectric layer that is not formed under the third photoresist layer and form a through hole in the second dielectric layer. In some embodiments, the above is combined with Figure 1 The photoresist tool and / or the etching tool of the described tool configuration may be used to remove the third bottom layer, the third intermediate layer and the third photoresist layer and form a via in the second dielectric layer.

[0064] like Fig.3O As shown, and by reference numeral 375, a second metal layer can be formed on the second dielectric layer to fill the through-holes in the second dielectric layer with the second metal layer and make the second metal layer contact with portions of the first metal layer (e.g., the first metal contact and the second metal contact). The second metal layer may include a metal, such as cobalt, tungsten, aluminum, copper, etc. In some embodiments, a metal deposition operation can be performed to form a second metal layer on the second dielectric layer and fill the through-holes in the second dielectric layer with the second metal layer. For example, PVD, CVD, ALD, MBE, ECD, etc. can be performed to form a second metal layer on the second dielectric layer and fill the through-holes in the second dielectric layer with the second metal layer. In some embodiments, the above is combined with Figure 1 The deposition tool and / or the metal tool of the described tool configuration may be used to form a second metal layer on the second dielectric layer and to fill vias in the second dielectric with the second metal layer.

[0065] like Figure 3P As shown, and by reference numeral 380, the second metal layer can be polished to be substantially flush with the second dielectric layer. In some embodiments, a CMP operation can be performed to polish the second metal layer to be substantially flush with the second dielectric layer. In some embodiments, the above combination Figure 1 A CMP tool with the tool configuration described can be used to polish the second metal layer to be substantially flush with the second dielectric layer. Figure 3P As further shown, the second metal layer formed in the through hole of the second dielectric layer can form a third metal contact and a fourth metal contact. In some embodiments, the third metal contact is electrically coupled to the first metal contact, and the fourth metal contact is electrically coupled to the second metal contact.

[0066] In this way, combined Figure 3A-3P A method for manufacturing a semiconductor device is described such that metal contacts electrically coupled to respective metal-to-source / drain plugs of the semiconductor device are separated by less than nineteen nanometers, within a range from about eight nanometers to less than nineteen nanometers, etc. Thus, the method can be used to indicate a semiconductor design in which the metal contacts are to be separated by less than nineteen nanometers. In addition, the method provides a better interface between the metal gate and the respective metal-to-source / drain plug (e.g., relative to island patterning techniques), which reduces the resistance of the metal gate and the respective metal-to-source / drain plug (e.g., relative to island patterning techniques).

[0067] As shown above, provide Figure 3A-3P Just one or more examples. Other examples can be related to Figure 3A-3P The examples described are different.

[0068] Figure 4 4 is a diagram of an example semiconductor device 400 described herein. As shown, the semiconductor device 400 may include a substrate layer 405 having a plurality of fins, an insulating layer 410, a source / drain plug 415, a first dielectric layer 420, and a metal contact 425. The substrate layer 405, the plurality of fins, the insulating layer 410, and the first dielectric layer 420 may correspond to the above combination. Figure 2A-3P The source / drain plugs 415 may correspond to the above combination. Figure 2A-3P The metal contact 425 may correspond to the first source / drain plug and the second source / drain plug described above. Figure 2A-3P The first metal contact and the second metal contact described herein can be used Figure 2A-2N or Figure 3A-3P The semiconductor device 400 is formed by a method.

[0069] like Figure 4As further shown, the metal contacts 425 can be spaced apart by a distance (a) in a range of about eight (8) nanometers to less than nineteen (19) nanometers. In some embodiments, the distance (a) can be about eight (8) nanometers. In some embodiments, patterning using this type of process can provide a distance (a) greater than nineteen (19) nanometers. The sidewall of one of the metal contacts 425 can be spaced apart by a distance (b) in a range of about ten (10) nanometers to about sixty-six (66) nanometers from a corresponding one of the source / drain plugs 415. In some embodiments, as Figure 4 As shown, even with isolation material on the edge of the source / drain epitaxial layer, the distance (b) can be less than ten (10) nanometers. The angle (θ) formed based on the sidewall of one of the metal contacts 425 and based on the top surface of the insulating layer 410 can be in the range of from about eighty-eight (88) degrees to about ninety-two (92) degrees. In contrast, using island patterning technology, the distance (a) can be greater than nineteen (19) nanometers, the distance (b) can be in the range of about ten (10) nanometers to about fifty (50) nanometers, and the angle (θ) can be in the range of about eighty-five (85) degrees to about eighty-eight (88) degrees. In this way, the size of the semiconductor device 400 enables the metal contacts 425 electrically coupled to the corresponding source / drain 415 of the semiconductor device 400 to be separated by less than nineteen nanometers. Therefore, the semiconductor device 400 can be used to indicate a semiconductor design in which the metal contacts are separated by less than nineteen nanometers. In addition, the semiconductor device 400 provides more interfaces between the metal contacts 425 and the corresponding source / drain 415 (eg, relative to island patterning techniques), which reduces the resistance between the metal contacts 425 and the corresponding source / drain 415 (eg, relative to island patterning techniques).

[0070] In this way, combined Figure 4 The described semiconductor device 400 enables the metal contacts 425 electrically coupled to the corresponding metal-to-source / drain plugs 415 of the semiconductor device 400 to be separated by less than 19 nanometers, in a range of about eight nanometers to less than nineteen nanometers, etc. Therefore, the semiconductor device 400 can be used to indicate a semiconductor design in which the metal contacts 425 are separated by less than nineteen nanometers. In addition, the semiconductor device 400 provides a better interface between the metal contacts 425 and the corresponding metal-to-source / drain plugs 415 (e.g., relative to island patterning techniques), which reduces the resistance between the metal contacts 425 and the source / drain 415 (e.g., relative to island patterning techniques).

[0071] Figure 55 is a diagram of example components of apparatus 500. Apparatus 500 may correspond to a deposition tool, a photoresist tool, an etch tool, a metal tool, and / or a CMP tool. In some embodiments, a deposition tool, a photoresist tool, an etch tool, a metal tool, and / or a CMP tool may include one or more apparatus 500 and / or one or more components of apparatus 500. Figure 5 The device 500 may include a bus 510 , a processor 520 , a memory 530 , a storage component 540 , an input component 550 , an output component 560 , and a communication interface 570 .

[0072] Bus 510 includes components that allow communication between components of device 500. Processor 520 is implemented in hardware, firmware, or a combination of hardware and software. Processor 520 is a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or another type of processing component. In some embodiments, processor 520 includes one or more processors that can be programmed to perform functions. Memory 530 includes random access memory (RAM), read-only memory (ROM), and / or other types of dynamic or static storage devices (e.g., flash memory, magnetic memory, and / or optical memory) that store information and / or instructions for use by processor 520.

[0073] Storage component 540 stores information and / or software related to the operation and use of device 500. For example, storage component 540 may include a hard disk (e.g., a magnetic disk, an optical disk, a magneto-optical disk, and / or a solid-state disk), a compact disk (CD), a digital versatile disk (DVD), a floppy disk, a cassette, a tape, and / or other types of non-transitory computer-readable media, and corresponding drives.

[0074] Input components 550 include components that allow device 500 to receive information, for example, via user input (e.g., a touch screen display, a keyboard, a keypad, a mouse, buttons, switches, and / or a microphone). Additionally or alternatively, input components 550 may include sensors for sensing information (e.g., a global positioning system (GPS) component, an accelerometer, a gyroscope, and / or an actuator). Output components 560 include components that provide output information from device 500 (e.g., a display, a speaker, and / or one or more LEDs).

[0075] The communication interface 570 includes a transceiver-like component (e.g., a transceiver and / or a separate receiver and transmitter) that enables the device 500 to communicate with other devices, for example, via a wired connection, a wireless connection, or a combination of a wired connection and a wireless connection. The communication interface 570 can allow the device 500 to receive information from another device and / or provide information to another device. For example, the communication interface 570 can include an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, an RF interface, a universal serial bus (USB) interface, a wireless local area network interface, a cellular network interface, etc.

[0076] Device 500 can perform one or more processes described herein. Device 500 can perform these processes based on processor 520 executing software instructions stored by non-transitory computer readable media (e.g., memory 530 and / or storage component 540). Computer readable media is defined herein as non-transitory storage devices. Storage devices include storage space within a single physical storage device or storage space distributed across multiple physical storage devices.

[0077] The software instructions may be read into the memory 530 and / or storage component 540 from another computer-readable medium or another device via the communication interface 570. When executed, the software instructions stored in the memory 530 and / or storage component 540 may cause the processor 520 to perform one or more processes described herein. Additionally or alternatively, hard-wired circuitry may be used in place of or in combination with software instructions to perform one or more processes described herein. Thus, the embodiments described herein are not limited to any specific combination of hardware circuitry and software.

[0078] Provided Figure 5 The number and arrangement of components shown are provided as examples. In practice, the device 500 may include more than Figure 5 More components, fewer components, different components, or differently arranged components are shown. Additionally or alternatively, one set of components (e.g., one or more components) of device 500 may perform one or more functions described as being performed by another set of components of device 500.

[0079] Figure 6 is a flow chart of an example process 600 for fabricating an example semiconductor device based on gap patterning of metal to source / drain plugs in the example semiconductor device. In some embodiments, Figure 6 One or more process boxes of may be configured by a tool (e.g., Figure 1 In some embodiments, Figure 6 One or more process blocks of the tool configuration may be performed by another device or group of devices separate from or including the tool configuration.

[0080] like Figure 6 As shown, process 600 may include forming a mask layer on top of a first dielectric layer formed on the first source / drain and the second source / drain (block 610). For example, as described above, the tool configuration may form a mask layer on top of the first dielectric layer formed on the first source / drain and the second source / drain.

[0081] like Figure 6 As further shown, the process 600 may include creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain (block 620). For example, as described above, the tool configuration may create openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain.

[0082] like Figure 6 As further shown, process 600 may include filling the opening with a metal layer covering the exposed portions of the first source / drain and the second source / drain (block 630). For example, as described above, the tool configuration may fill the opening with a metal layer covering the exposed portions of the first source / drain and the second source / drain.

[0083] like Figure 6 As further shown, process 600 may include forming a gap in the metal layer to create a first metal contact and a second metal contact, wherein the first metal contact is electrically coupled to the first source / drain and the second metal contact is electrically coupled to the second source / drain, and wherein the gap separates the first metal contact from the second metal contact by less than nineteen nanometers (block 640). For example, as described above, the tool configuration may form a gap in the metal layer to create the first metal contact and the second metal contact. In some embodiments, the first metal contact is electrically coupled to the first source / drain, and the second metal contact is electrically coupled to the second source / drain. In some embodiments, the gap separates the first metal contact from the second metal contact by less than nineteen nanometers.

[0084] like Figure 6 As further shown, process 600 may include filling the gap with material for the first dielectric layer (block 650). For example, as described above, the tool configuration may fill the gap with material for the first dielectric layer (or with material for other types of dielectric layers).

[0085] Process 600 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and / or in conjunction with one or more other processes described elsewhere herein.

[0086] In a first embodiment, process 600 includes: forming a second dielectric layer on top of the first dielectric layer, the first metal contact, and the second metal contact; creating a first through hole in the second dielectric layer to expose a portion of the first metal contact; creating a second through hole in the second dielectric layer to expose a portion of the second metal contact; filling the first through hole to create a third metal contact electrically coupled to the first metal contact; and filling the second through hole to create a fourth metal contact electrically coupled to the second metal contact.

[0087] In a second embodiment, alone or in combination with the first embodiment, creating openings in the mask layer and the first dielectric layer includes: forming a photoresist layer over portions of the mask layer and the first dielectric layer, and performing one or more etching operations to remove portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, wherein the removed portions of the mask layer and the first dielectric layer correspond to openings exposing portions of the first source / drain and the second source / drain.

[0088] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 600 includes polishing the metal layer to be substantially flush with the first dielectric layer and removing the mask layer before forming the gap in the metal layer.

[0089] In a fourth embodiment, either alone or in combination with one or more of the first to third embodiments, forming a gap in the metal layer includes forming a photoresist layer over portions of the metal layer and the first dielectric layer other than a portion of the metal layer associated with the gap, and performing one or more etching operations to remove the portion of the metal layer, wherein the removed portion of the metal layer corresponds to the gap in the metal layer.

[0090] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, forming a gap in the metal layer includes: forming a bottom layer on top of the metal layer and the first dielectric layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the metal layer, the first dielectric layer, the bottom layer, and the intermediate layer except for a portion of the metal layer associated with the gap; and performing one or more etching operations to remove the portion of the metal layer, the entire photoresist layer, the entire bottom layer, and the entire intermediate layer, wherein the removed portion of the metal layer corresponds to the gap in the metal layer.

[0091] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, creating openings in the mask layer and the first dielectric layer includes: forming a bottom layer on top of the mask layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the first dielectric layer, the mask layer, the bottom layer, and the intermediate layer; and performing one or more etching operations to remove the entire photoresist layer, the entire bottom layer, the entire intermediate layer, and portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, wherein the removed portions of the mask layer and the first dielectric layer correspond to openings that expose portions of the first source / drain and the second source / drain.

[0092] In a seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, a semiconductor device includes a substrate having fins and an insulating layer formed on top of the substrate, wherein one or more first fins are electrically coupled to a first source / drain and one or more second fins are electrically coupled to a second source / drain.

[0093] although Figure 6 An example block diagram of process 600 is shown, but in some embodiments, process 600 may include more Figure 6 More blocks, fewer blocks, different blocks, or differently arranged blocks are shown. Additionally or alternatively, two or more blocks of process 600 may be performed in parallel.

[0094] Figure 7 is a flow chart of an example process 700 for fabricating an example semiconductor device based on gap patterning of metal to source / drain plugs in the example semiconductor device. In some embodiments, Figure 7 One or more process boxes of may be configured by a tool (e.g., Figure 1 In some embodiments, Figure 7 One or more processing blocks of may be performed by another device or group of devices separate from or including the tool configuration.

[0095] like Figure 7 As shown, process 700 may include forming a mask layer on top of a first dielectric layer formed on the first source / drain and the second source / drain (block 710). For example, as described above, the tool configuration may form a mask layer on top of the first dielectric layer formed on the first source / drain and the second source / drain.

[0096] like Figure 7As further shown, process 700 may include creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain (block 720). For example, as described above, the tool configuration may create openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain.

[0097] like Figure 7 As further shown, process 700 may include filling the opening with a sacrificial layer covering the exposed portions of the first source / drain and the second source / drain (block 730). For example, as described above, the tool configuration may fill the opening with a sacrificial layer covering the exposed portions of the first source / drain and the second source / drain.

[0098] like Figure 7 As further shown, process 700 may include forming a gap in the sacrificial layer (block 740). For example, as described above, the tool configuration may form the gap in the sacrificial layer.

[0099] like Figure 7 As further shown, process 700 may include filling the gap with the material for the first dielectric layer to form a spacer (block 750). For example, as described above, the tool configuration may fill the gap with the material for the first dielectric layer to form a spacer (or with material for other types of dielectric layers).

[0100] like Figure 7 As further shown, the process 700 may include removing the sacrificial layer to create a first opening exposing a portion of the first source / drain and a second opening exposing a portion of the second source / drain (block 760). For example, as described above, the tool configuration may remove the sacrificial layer to create a first opening exposing a portion of the first source / drain and a second opening exposing a portion of the second source / drain.

[0101] like Figure 7 As further shown, process 700 may include filling the first opening with metal to form a first metal contact (block 770). For example, as described above, the tool configuration may fill the first opening with metal to form a first metal contact.

[0102] like Figure 7As further shown, process 700 may include filling the second opening with metal to form a second metal contact, wherein the first metal contact is electrically coupled to the first source / drain and the second metal contact is electrically coupled to the second source / drain, and wherein a spacer separates the first metal contact from the second metal contact by less than nineteen nanometers (block 780). For example, as described above, the tool configuration may fill the second opening with metal to form the second metal contact. In some embodiments, the first metal contact is electrically coupled to the first source / drain and the second metal contact is electrically coupled to the second source / drain. In some embodiments, the spacer separates the first metal contact from the second metal contact by less than nineteen nanometers.

[0103] Process 700 may include additional embodiments, such as any single embodiment or any combination of embodiments described below, and / or in conjunction with one or more other processes described elsewhere herein.

[0104] In a first embodiment, process 700 includes: forming a second dielectric layer on top of the first dielectric layer, the first metal contact, and the second metal contact; creating a first through hole in the second dielectric layer to expose a portion of the first metal contact; creating a second through hole in the second dielectric layer to expose a portion of the second metal contact; filling the first through hole to form a third metal contact electrically coupled to the first metal contact; and filling the second through hole to form a fourth metal contact electrically coupled to the second metal contact.

[0105] In a second embodiment, alone or in combination with the first embodiment, creating openings in the mask layer and the first dielectric layer includes: forming a photoresist layer over portions of the mask layer and the first dielectric layer, and performing one or more etching operations to remove portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, wherein the removed portions of the mask layer and the first dielectric layer correspond to openings exposing portions of the first source / drain and the second source / drain.

[0106] In a third embodiment, alone or in combination with one or more of the first and second embodiments, process 700 includes polishing the sacrificial layer to be substantially flush with the first dielectric layer and removing the mask layer before forming the gap in the sacrificial layer.

[0107] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming a gap in the sacrificial layer includes: forming a photoresist layer over the sacrificial layer and a portion of the first dielectric layer other than a portion of the sacrificial layer associated with the gap, and performing one or more etching operations to remove the portion of the sacrificial layer, wherein the removed portion of the sacrificial layer corresponds to the gap in the sacrificial layer.

[0108] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, forming a gap in the sacrificial layer includes: forming a bottom layer on top of the sacrificial layer and the first dielectric layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the sacrificial layer, the first dielectric layer, the bottom layer, and the intermediate layer except for a portion of the sacrificial layer associated with the gap; and performing one or more etching operations to remove the portion of the sacrificial layer, the entire photoresist layer, the entire bottom layer, and the entire intermediate layer, wherein the removed portion of the sacrificial layer corresponds to the gap in the sacrificial layer.

[0109] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, creating openings in the mask layer and the first dielectric layer includes: forming a bottom layer on top of the mask layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the first dielectric layer, the mask layer, the bottom layer, and the intermediate layer; and performing one or more etching operations to remove the entire photoresist layer, the entire bottom layer, the entire intermediate layer, and portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, wherein the removed portions of the mask layer and the first dielectric layer correspond to openings that expose portions of the first source / drain and the second source / drain.

[0110] In a seventh embodiment, alone or in combination with one or more of the first to sixth embodiments, an angle formed based on the sidewall of the first metal contact or the second metal contact and based on the top surface of the insulating layer is in a range of approximately eighty-eight degrees to approximately ninety-two degrees.

[0111] In an eighth embodiment, alone or in combination with one or more of the first to seventh embodiments, a distance from a sidewall of the first metal contact to the first source / drain is in a range from about ten nanometers to about sixty-six nanometers.

[0112] In a ninth embodiment, alone or in combination with one or more of the first to eighth embodiments, a distance from a sidewall of the first metal contact to a sidewall of the second metal contact is in a range from about eight nanometers to nineteen nanometers.

[0113] although Figure 7An example block diagram of process 700 is shown, but in some embodiments, process 700 may include more Figure 7 More blocks, fewer blocks, different blocks, or differently arranged blocks are shown. Additionally or alternatively, two or more blocks of process 700 can be performed in parallel.

[0114] In this manner, a method for manufacturing a semiconductor device 400 can be based on gap patterning of metal to source / drain plugs 415 in a semiconductor device 400. The method separates metal contacts 425 electrically coupled to respective source / drain 415 of the semiconductor device 400 by less than the minimum distance provided by island patterning techniques (e.g., less than nineteen nanometers). Thus, the method can be used for semiconductor design. In addition, the method provides more interfaces between metal contacts 425 and respective source / drain 415 (e.g., relative to island patterning techniques), which reduces the resistance between metal contacts 425 and respective source / drain 415 (e.g., relative to island patterning techniques).

[0115] As described in more detail above, some embodiments described herein provide a method for manufacturing a semiconductor device. The method may include providing a mask layer on top of a first dielectric layer provided on a first source / drain and a second source / drain, and creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain. The method may include filling the opening with a metal layer covering the exposed portions of the first source / drain and the second source / drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may be electrically coupled to the first source / drain, and the second metal contact may be electrically coupled to the second source / drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers. The method may include filling the gap with a material for the first dielectric layer.

[0116] As described in more detail above, some embodiments described herein provide a method for manufacturing a semiconductor device. The method may include providing a mask layer on top of a first dielectric layer provided on a first source / drain and a second source / drain, and creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain. The method may include filling the opening with a sacrificial layer covering the exposed portions of the first source / drain and the second source / drain, and forming a gap in the sacrificial layer. The method may include filling the gap with a material for the first dielectric layer to form a spacer, and removing the sacrificial layer to create a first opening that exposes a portion of the first source / drain and a second opening that exposes a portion of the second source / drain. The method may include filling the first opening with a metal to form a first metal contact, and filling the second opening with a metal to form a second metal contact. The first metal contact may be electrically coupled to the first source / drain, and the second metal contact may be electrically coupled to the second source / drain. The spacer may separate the first metal contact from the second metal contact by less than nineteen nanometers.

[0117] As described in more detail above, some embodiments described herein provide a semiconductor device having a substrate layer including a plurality of fins, and an insulating layer formed on top of the substrate layer. The semiconductor device may include: a first source / drain electrically coupled to one or more first fins of the plurality of fins; and a second source / drain spaced apart from the first source / drain and electrically coupled to one or more second fins of the plurality of fins. The semiconductor device may include: a first metal contact electrically coupled to the first source / drain; a second metal contact electrically coupled to the second source / drain; and a dielectric layer separating the first metal contact from the second metal contact by less than nineteen nanometers.

[0118] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0119] Example 1. A method for manufacturing a semiconductor device, the method comprising: forming a mask layer on top of a first dielectric layer, the first dielectric layer being formed on a first source / drain and a second source / drain; creating openings in the mask layer and the first dielectric layer, the openings exposing portions of the first source / drain and the second source / drain; filling the openings with a metal layer, the metal layer covering the exposed portions of the first source / drain and the second source / drain; forming a gap in the metal layer to create a first metal contact and a second metal contact; wherein the first metal contact is electrically coupled to the first source / drain and the second metal contact is electrically coupled to the second source / drain, and wherein the gap separates the first metal contact from the second metal contact by less than nineteen nanometers; and filling the gap with material for the first dielectric layer.

[0120] Example 2. The method according to Example 1 also includes: forming a second dielectric layer on top of the first dielectric layer, the first metal contact and the second metal contact; creating a first through hole in the second dielectric layer to expose a portion of the first metal contact; creating a second through hole in the second dielectric layer to expose a portion of the second metal contact; filling the first through hole to create a third metal contact electrically coupled to the first metal contact; and filling the second through hole to create a fourth metal contact electrically coupled to the second metal contact.

[0121] Example 3. A method according to Example 1, wherein creating the opening in the mask layer and the first dielectric layer includes: forming a photoresist layer above portions of the mask layer and the first dielectric layer; and performing one or more etching operations to remove portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, wherein the removed portions of the mask layer and the first dielectric layer correspond to the opening exposing portions of the first source / drain and the second source / drain.

[0122] Example 4. The method of Example 1 further comprises: before forming the gap in the metal layer, polishing the metal layer to be substantially flush with the first dielectric layer and removing the mask layer.

[0123] Example 5. A method according to Example 1, wherein forming the gap in the metal layer includes: forming a photoresist layer over the metal layer and a portion of the first dielectric layer other than a portion of the metal layer associated with the gap; and performing one or more etching operations to remove the portion of the metal layer, wherein the removed portion of the metal layer corresponds to the gap in the metal layer.

[0124] Example 6. A method according to Example 1, wherein forming the gap in the metal layer includes: forming a bottom layer on top of the metal layer and the first dielectric layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the metal layer, the first dielectric layer, the bottom layer, and the intermediate layer except for a portion of the metal layer associated with the gap; and performing one or more etching operations to remove the portion of the metal layer, the entire photoresist layer, the entire bottom layer, and the entire intermediate layer, wherein the portion of the metal layer that is removed corresponds to the gap in the metal layer.

[0125] Example 7. A method according to Example 1, wherein creating the opening in the mask layer and the first dielectric layer includes: forming a bottom layer on top of the mask layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the first dielectric layer, the mask layer, the bottom layer, and the intermediate layer; and performing one or more etching operations to remove the entire photoresist layer, the entire bottom layer, the entire intermediate layer, and portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, wherein the removed portions of the mask layer and the first dielectric layer correspond to the openings that expose portions of the first source / drain and the second source / drain.

[0126] Example 8. A method according to Example 1, wherein the semiconductor device includes a substrate having fins and an insulating layer formed on top of the substrate, wherein one or more first fins are electrically coupled to the first source / drain, and one or more second fins are electrically coupled to the second source / drain.

[0127] Example 9. A method for manufacturing a semiconductor device, the method comprising: providing a mask layer on top of a first dielectric layer formed on a first source / drain and a second source / drain; creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain; filling the openings with a sacrificial layer covering the exposed portions of the first source / drain and the second source / drain; forming a gap in the sacrificial layer; filling the gap with a material for the first dielectric layer to form a spacer; removing the sacrificial layer to create a first opening that exposes a portion of the first source / drain and a second opening that exposes a portion of the second source / drain; filling the first opening with a metal to form a first metal contact; and filling the second opening with a metal to form a second metal contact, wherein the first metal contact is electrically coupled to the first source / drain and the second metal contact is electrically coupled to the second source / drain, and wherein the spacer separates the first metal contact from the second metal contact by less than nineteen nanometers.

[0128] Example 10. The method according to Example 9 also includes: forming a second dielectric layer on top of the first dielectric layer, the first metal contact and the second metal contact; creating a first through hole in the second dielectric layer to expose a portion of the first metal contact; creating a second through hole in the second dielectric layer to expose a portion of the second metal contact; filling the first through hole to form a third metal contact electrically coupled to the first metal contact; and filling the second through hole to form a fourth metal contact electrically coupled to the second metal contact.

[0129] Example 11. A method according to Example 9, wherein creating the opening in the mask layer and the first dielectric layer includes: forming a photoresist layer above portions of the mask layer and the first dielectric layer; and performing one or more etching operations to remove portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, wherein the removed portions of the mask layer and the first dielectric layer correspond to openings that expose portions of the first source / drain and the second source / drain.

[0130] Example 12. The method of Example 9 further includes: before forming the gap in the sacrificial layer, polishing the sacrificial layer to be substantially flush with the first dielectric layer and removing the mask layer.

[0131] Example 13. A method according to Example 9, wherein forming the gap in the sacrificial layer includes: forming a photoresist layer over portions of the sacrificial layer and the first dielectric layer other than a portion of the sacrificial layer associated with the gap; and performing one or more etching operations to remove the portion of the sacrificial layer, wherein the removed portion of the sacrificial layer corresponds to the gap in the sacrificial layer.

[0132] Example 14. A method according to Example 9, wherein forming the gap in the sacrificial layer includes: forming a bottom layer on top of the sacrificial layer and the first dielectric layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the sacrificial layer, the first dielectric layer, the bottom layer, and the intermediate layer except for a portion of the sacrificial layer associated with the gap; and performing one or more etching operations to remove the portion of the sacrificial layer, the entire photoresist layer, the entire bottom layer, and the entire intermediate layer, wherein the portion of the sacrificial layer that is removed corresponds to the gap in the sacrificial layer.

[0133] Example 15. A method according to Example 9, wherein creating the opening in the mask layer and the first dielectric layer includes: forming a bottom layer on top of the mask layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the first dielectric layer, the mask layer, the bottom layer, and the intermediate layer; and performing one or more etching operations to remove the entire photoresist layer, the entire bottom layer, the entire intermediate layer, and portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, wherein the removed portions of the mask layer and the first dielectric layer correspond to the openings that expose portions of the first source / drain and the second source / drain.

[0134] Example 16. A semiconductor device comprising: a substrate layer comprising a plurality of fins; a first source / drain electrically coupled to one or more first fins of the plurality of fins; a second source / drain spaced apart from the first source / drain and electrically coupled to one or more second fins of the plurality of fins; a first metal contact electrically coupled to the first source / drain; a second metal contact electrically coupled to the second source / drain; and a dielectric layer separating the first metal contact from the second metal contact by less than nineteen nanometers.

[0135] Example 17. The semiconductor device of Example 16, wherein an angle formed based on a sidewall of the first metal contact or the second metal contact and based on a top surface of the insulating layer is in a range of approximately eighty-eight degrees to approximately ninety-two degrees.

[0136] Example 18. The semiconductor device of Example 16, wherein a distance from a sidewall of the first metal contact to the first source / drain is in a range from about ten nanometers to about sixty-six nanometers.

[0137] Example 19. The semiconductor device of Example 16 further includes: a third metal contact formed on top of the first metal contact and electrically coupled to the first metal contact; and a fourth metal contact formed on top of the second metal contact and electrically coupled to the second metal contact.

[0138] Example 20. The semiconductor device of Example 16, wherein a distance from a sidewall of the first metal contact to a sidewall of the second metal contact is in a range from approximately eight nanometers to nineteen nanometers.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a mask layer on top of a first dielectric layer formed on the first source / drain and the second source / drain; creating openings in the mask layer and the first dielectric layer, the openings exposing portions of the first source / drain and the second source / drain; filling the opening with a metal layer, the metal layer covering the exposed portions of the first source / drain and the second source / drain; forming a gap in the metal layer to create a first metal contact and a second metal contact; wherein the first metal contact is electrically coupled to the first source / drain, and the second metal contact is electrically coupled to the second source / drain, and wherein the gap separates the first metal contact from the second metal contact by less than nineteen nanometers; and The gap is filled with material for the first dielectric layer.

2. The method according to claim 1, further comprising: forming a second dielectric layer on top of the first dielectric layer, the first metal contact, and the second metal contact; creating a first via in the second dielectric layer to expose a portion of the first metal contact; creating a second via in the second dielectric layer to expose a portion of the second metal contact; filling the first via to create a third metal contact electrically coupled to the first metal contact; and The second via is filled to create a fourth metal contact electrically coupled to the second metal contact.

3. The method according to claim 1, wherein: Creating the opening in the mask layer and the first dielectric layer comprises: forming a photoresist layer over the mask layer and portions of the first dielectric layer; and performing one or more etching operations to remove portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, The removed portions of the mask layer and the first dielectric layer correspond to the openings that expose portions of the first source / drain and the second source / drain.

4. The method according to claim 1, further comprising: Prior to forming the gap in the metal layer, the metal layer is polished to be substantially flush with the first dielectric layer, and the mask layer is removed.

5. The method according to claim 1, wherein: Forming the gap in the metal layer includes: forming a photoresist layer over the metal layer and a portion of the first dielectric layer except for a portion of the metal layer associated with the gap; and performing one or more etching operations to remove the portion of the metal layer, The removed portion of the metal layer corresponds to the gap in the metal layer.

6. The method according to claim 1, wherein: Forming the gap in the metal layer includes: forming a bottom layer on top of the metal layer and the first dielectric layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the metal layer, the first dielectric layer, the bottom layer, and the intermediate layer except for a portion of the metal layer associated with the gap; and performing one or more etching operations to remove the portion of the metal layer, the entire photoresist layer, the entire bottom layer, and the entire intermediate layer, The removed portion of the metal layer corresponds to the gap in the metal layer.

7. The method according to claim 1, wherein: Creating the opening in the mask layer and the first dielectric layer comprises: forming a bottom layer on top of the mask layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the first dielectric layer, the mask layer, the bottom layer, and the intermediate layer; and performing one or more etching operations to remove the entire photoresist layer, the entire bottom layer, the entire middle layer, and portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, The removed portions of the mask layer and the first dielectric layer correspond to the openings that expose portions of the first source / drain and the second source / drain.

8. The method according to claim 1, wherein: The semiconductor device includes a substrate having a fin and an insulating layer formed on top of the substrate, One or more first fins are electrically coupled to the first source / drain, and one or more second fins are electrically coupled to the second source / drain.

9. A method for manufacturing a semiconductor device, the method comprising: providing a mask layer on top of a first dielectric layer formed on the first source / drain and the second source / drain; creating openings in the mask layer and the first dielectric layer that expose portions of the first source / drain and the second source / drain; filling the opening with a sacrificial layer covering exposed portions of the first source / drain and the second source / drain; forming a gap in the sacrificial layer; filling the gap with a material for the first dielectric layer to form a spacer; removing the sacrificial layer to create a first opening exposing a portion of the first source / drain and a second opening exposing a portion of the second source / drain; filling the first opening with metal to form a first metal contact; as well as filling the second opening with metal to form a second metal contact, wherein the first metal contact is electrically coupled to the first source / drain, and the second metal contact is electrically coupled to the second source / drain, and The spacer separates the first metal contact from the second metal contact by less than nineteen nanometers.

10. The method according to claim 9, further comprising: forming a second dielectric layer on top of the first dielectric layer, the first metal contact, and the second metal contact; creating a first via in the second dielectric layer to expose a portion of the first metal contact; creating a second via in the second dielectric layer to expose a portion of the second metal contact; filling the first via to form a third metal contact electrically coupled to the first metal contact; and The second via is filled to form a fourth metal contact electrically coupled to the second metal contact.

11. The method according to claim 9, wherein: Creating the opening in the mask layer and the first dielectric layer comprises: forming a photoresist layer over the mask layer and portions of the first dielectric layer; and performing one or more etching operations to remove portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, The removed portions of the mask layer and the first dielectric layer correspond to the openings that expose portions of the first source / drain and the second source / drain.

12. The method according to claim 9, further comprising: Before forming the gap in the sacrificial layer, the sacrificial layer is polished to be substantially flush with the first dielectric layer, and the mask layer is removed.

13. The method according to claim 9, wherein: Forming the gap in the sacrificial layer includes: forming a photoresist layer over the sacrificial layer and a portion of the first dielectric layer except for a portion of the sacrificial layer associated with the gap; and performing one or more etching operations to remove the portion of the sacrificial layer, The removed portion of the sacrificial layer corresponds to the gap in the sacrificial layer.

14. The method according to claim 9, wherein: Forming the gap in the sacrificial layer includes: forming a bottom layer on top of the sacrificial layer and the first dielectric layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the sacrificial layer, the first dielectric layer, the bottom layer, and the intermediate layer except for a portion of the sacrificial layer associated with the gap; and performing one or more etching operations to remove the portion of the sacrificial layer, the entire photoresist layer, the entire bottom layer, and the entire intermediate layer, The removed portion of the sacrificial layer corresponds to the gap in the sacrificial layer.

15. The method according to claim 9, wherein: Creating the opening in the mask layer and the first dielectric layer comprises: forming a bottom layer on top of the mask layer; forming an intermediate layer on top of the bottom layer; forming a photoresist layer over portions of the first dielectric layer, the mask layer, the bottom layer, and the intermediate layer; and performing one or more etching operations to remove the entire photoresist layer, the entire bottom layer, the entire middle layer, and portions of the mask layer and the first dielectric layer except for portions of the mask layer and the first dielectric layer formed below the photoresist layer, The removed portions of the mask layer and the first dielectric layer correspond to the openings that expose portions of the first source / drain and the second source / drain.

16. A semiconductor device comprising: a substrate layer including a plurality of fins; a first source / drain electrically coupled to one or more first fins of the plurality of fins; a second source / drain spaced apart from the first source / drain and electrically coupled to one or more second fins of the plurality of fins; a first metal contact electrically coupled to the first source / drain; a second metal contact electrically coupled to the second source / drain; as well as A dielectric layer separates the first metal contact from the second metal contact by less than nineteen nanometers.

17. The semiconductor device according to claim 16, wherein: An angle formed based on a sidewall of the first metal contact or the second metal contact and based on a top surface of the insulating layer is in a range of eighty-eight degrees to ninety-two degrees.

18. The semiconductor device according to claim 16, wherein: A distance from a sidewall of the first metal contact to the first source / drain is in a range of ten nanometers to sixty-six nanometers.

19. The semiconductor device according to claim 16, further comprising: a third metal contact formed on top of the first metal contact and electrically coupled to the first metal contact; as well as A fourth metal contact is formed on top of the second metal contact and is electrically coupled to the second metal contact.

20. The semiconductor device according to claim 16, wherein A distance from a sidewall of the first metal contact to a sidewall of the second metal contact is in a range from eight nanometers to nineteen nanometers.

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