Semiconductor modules and methods for manufacturing semiconductor modules

Abstract

This invention provides a semiconductor module and a method for manufacturing a semiconductor module. The reliability of the device is improved by reducing deformation caused by thermal stress associated with bumps through a simple structure. The semiconductor module (1) includes: a laminated substrate (2) having a circuit pattern (22) disposed on the upper surface of an insulating plate (20) and a heat sink (21) disposed on the lower surface of the insulating plate; and a semiconductor element (3) having a collector electrode (30) disposed on its upper surface and an emitter electrode (32) and a gate electrode (31) disposed on its lower surface, the emitter electrode and the gate electrode being bonded to the upper surface of the circuit pattern via bumps (B). The bumps are formed from a sintered metal material with a shape in which the middle portion is recessed compared to the bonding portion.

Description

Technical Field

[0001] This invention relates to semiconductor modules and methods for manufacturing semiconductor modules. Background Technology

[0002] Semiconductor devices have substrates containing semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and FWDs (Free Wheeling Diodes), and are used in converter devices, etc.

[0003] For example, Patent Documents 1 to 3 disclosed below disclose a method for bonding a chip to a substrate in a semiconductor device. In Patent Documents 1 to 3, the chip is bonded to the substrate via bumps such as solder. Specifically, in Patent Document 1, solder bumps are disposed between the chip and the substrate, and during reflow soldering, the solder bumps, in a molten state, lift the chip upwards, thereby increasing the bonding height of the chip relative to the substrate. In Patent Document 1, it is assumed that the higher the bonding height, the longer the bonding life. The solder bumps after bonding have a shape that tapers in the center.

[0004] In Patent Document 2, solder bumps are disposed at corresponding locations on both the semiconductor chip and the circuit board to bond the solder pieces together. Additionally, on the outer side of the solder bumps, on the semiconductor element side, cylindrical bumps are disposed for adjusting the bump height. When the solder bumps melt, the tops of the cylindrical bumps abut against the circuit board side, thereby adjusting the bump height. At this time, the solder bumps form a waist-shaped structure that tapers in the center.

[0005] In Patent Document 3, spherical bumps containing metals such as gold and aluminum that can be relatively easily plastically deformed are used. After the spherical bumps are bonded to the chip at one end and to the insulating substrate at the other end, their height is adjusted by applying pressure in the thickness direction.

[0006] Patent Document 1: Japanese Patent Application Publication No. 61-156745

[0007] Patent Document 2: Japanese Patent Application Publication No. 5-67647

[0008] Patent Document 3: Japanese Patent Application Publication No. 2016-25237 Summary of the Invention

[0009] The problem the invention aims to solve

[0010] Typically, semiconductor modules generate heat during switching operations, thus applying thermal stress to their bonding portions, which can result in deformation. In the aforementioned documents (especially Patent Documents 1-2), a constricted shape is formed in the center by adjusting the bonding height of the bumps, thereby suppressing stress concentration and improving device reliability. However, the increased complexity of the structure and processes used to control the bonding height of the bumps becomes a major cause of cost increases.

[0011] The present invention was made in view of this purpose, and one object of which is to provide a semiconductor module and a method for manufacturing the semiconductor module that can improve the reliability of the device by reducing the deformation caused by the thermal stress associated with the bumps using a simple structure.

[0012] Solution for solving the problem

[0013] A semiconductor module according to one embodiment of the present invention is characterized in that the semiconductor module includes: a laminated substrate having a circuit pattern disposed on an upper surface of an insulating plate and a heat sink disposed on a lower surface of the insulating plate; and a semiconductor element having a collector disposed on an upper surface and an emitter electrode and a gate electrode disposed on a lower surface, the emitter electrode and the gate electrode being bonded to the upper surface of the circuit pattern via bumps, the bumps being formed of a metal sintering material with a shape in which the middle portion is recessed compared to the bonding portion.

[0014] A method for manufacturing a semiconductor module according to an embodiment of the present invention is a method for manufacturing a semiconductor module in which semiconductor elements are bonded to a multilayer substrate. The multilayer substrate is formed by distributing a circuit pattern on the upper surface of an insulating plate and distributing a heat sink on the lower surface of the insulating plate. The method is characterized by performing the following steps in the semiconductor module manufacturing method: a bump coating step, in which bumps made of a paste-like metal sintering material are coated on the bonding surface of the semiconductor element in such a way that the top of the bump is a tapered cone shape; and a bump bonding step, in which the top of the bump is pressed toward the circuit pattern and a recess is formed in the middle portion of the bump for bonding.

[0015] The effects of the invention

[0016] According to the present invention, the reliability of the device can be improved by reducing the deformation caused by thermal stress associated with the bumps using a simple structure. Attached Figure Description

[0017] Figure 1 This is a perspective view of the semiconductor module involved in this embodiment.

[0018] Figure 2 This is a top view of the semiconductor module involved in this embodiment.

[0019] Figure 3 This is a top view showing the circuit pattern of the semiconductor module involved in this embodiment.

[0020] Figure 4 (A) and Figure 4 (B) is a cross-sectional view of the semiconductor module involved in this embodiment.

[0021] Figure 5 (A) and Figure 5 (B) is a schematic diagram showing the flow of refrigerant in the semiconductor module according to this embodiment.

[0022] Figure 6 (A) and Figure 6 (B) is a perspective view showing a step example of a semiconductor module manufacturing method according to this embodiment.

[0023] Figure 7 (A) and Figure 7 (B) is a perspective view showing a step example of a semiconductor module manufacturing method according to this embodiment.

[0024] Figure 8 (A) and Figure 8 (B) is a perspective view and a cross-sectional view showing a step example of a semiconductor module manufacturing method according to this embodiment.

[0025] Figure 9 (A) and Figure 9 (B) is a perspective view showing a step example of a semiconductor module manufacturing method according to this embodiment.

[0026] Figure 10 (A) and Figure 10 (B) is a cross-sectional view showing a process example of a semiconductor module manufacturing method according to this embodiment.

[0027] Figure 11 (A) and Figure 11 (B) is a schematic diagram showing the change in the shape of the bump involved in this embodiment.

[0028] Explanation of reference numerals in the attached figures

[0029] 1. Semiconductor module; 2. Laminated substrate; 3. Semiconductor element; 4. Block electrode; 5. Sealing resin; 10. Cooler; 10a. Heat sink; 10b. Slot; 20. Insulating plate; 21. Heat sink; 22. Circuit pattern; 23. Collector circuit pattern; 24. Gate circuit pattern; 24a. L-section; 24b. H-section; 25. Emitter circuit pattern; 25a. Emitter section; 25b. Strip section; 25c. Strip section; 25d. Sensing emitter section; 30. Collector; 31. Gate electrode; 32. Emitter electrode; 40. 41. Collector block; 42. Gate electrode block; 43. Emitter electrode block; 44. Sensing emitter electrode block; 45. Flat plate portion; 46. Protrusion portion; 47. Through hole; B. Bump; B1. First joint portion; B2. Second joint portion; B3. Recess; D1. Outer diameter of the first joint portion; D2. Outer diameter of the second joint portion; D3. Outer diameter of the third joint portion; H. Coating height of the bump; S. Bonding material; T. Bonding height of the bump; θ1. Angle formed by the first joint portion relative to the bonding surface; θ2. Angle formed by the second joint portion relative to the bonding surface. Detailed Implementation

[0030] The following describes a semiconductor module to which the present invention can be applied. Figure 1 This is a perspective view of the semiconductor module involved in this embodiment. Figure 2 This is a top view of the semiconductor module involved in this embodiment. Figure 3 This is a top view showing the circuit pattern of the semiconductor module involved in this embodiment. Figure 4 (A) and Figure 4 (B) is a cross-sectional view of the semiconductor module involved in this embodiment. Figure 4 (A) is along Figure 2 A cross-sectional view cut off by line A-A. Figure 4 (B) is along Figure 2 A cross-sectional view cut off by the B-B line. Figure 5 (A) and Figure 5 (B) is a schematic diagram showing the flow of refrigerant in the semiconductor module according to this embodiment. Figure 5 (A) is a top view of the semiconductor module. Figure 5 (B) is a cross-sectional view of the semiconductor module. Furthermore, the semiconductor module shown below is merely an example and is not limited to it; appropriate modifications are possible.

[0031] In the following figures, the short side of the semiconductor module is defined as the X-direction, the long side as the Y-direction, and the height as the Z-direction. Additionally, depending on the context, the X-direction may sometimes be referred to as the left-right direction, the Y-direction as the front-back direction, and the Z-direction as the up-down direction. These directions (front-back, left-right, up-down) are terms used for ease of explanation, and the correspondence between the X, Y, and Z directions may change depending on the mounting orientation of the semiconductor module. For example, the heat dissipation surface (cooler side) of the semiconductor module may be designated as the lower surface side, and its opposite side as the upper surface side. Furthermore, in this specification, "top view" refers to the view of the upper surface of the semiconductor module from the Z-direction.

[0032] Semiconductor module 1 is used, for example, in power conversion devices such as power modules. Figures 1 to 4 (A) and Figure 4 As shown in (B), the semiconductor module 1 is constructed by arranging a plurality of semiconductor elements 3 and a plurality of block electrodes 4 on the upper surface of the laminated substrate 2.

[0033] The laminated substrate 2 is formed by stacking metal layers and insulating layers, and may be composed of, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal substrate. Specifically, the laminated substrate 2 has an insulating plate 20, a heat sink 21 disposed on the lower surface of the insulating plate 20, and a plurality of circuit patterns 22 disposed on the upper surface of the insulating plate 20. In addition, the laminated substrate 2 is formed into a rectangular shape in plan view, where the Y direction is longer than the X direction.

[0034] The insulating plate 20 has a thickness in the Z direction and is formed into a flat plate with an upper surface and a lower surface. The insulating plate 20 is formed from insulating materials such as ceramic materials like alumina (Al2O3), aluminum nitride (AlN), and silicon nitride (Si3N4), resin materials like epoxy, or epoxy resin materials using ceramic materials as fillers. Furthermore, the insulating plate 20 may also be referred to as an insulating layer or insulating film.

[0035] The heat sink 21 has a specified thickness and is formed as a whole covering the lower surface of the insulating plate 20. The heat sink 21 is formed, for example, from a metal plate with good thermal conductivity such as copper or aluminum. The lower surface of the heat sink 21 serves as a heat dissipation surface, and a cooler 10 is mounted on the heat dissipation surface.

[0036] The cooler 10 is, for example, a heat sink and has a rectangular shape when viewed from above. The cooler 10 is formed of metals such as copper and aluminum, or an alloy containing one or more of these metals, and its surface is, for example, plated. The cooler 10 is mounted to the semiconductor module 1 (heat sink 21) with a thermally conductive mixture or similar material spaced between it and the lower surface of the semiconductor module 1. The upper surface of the cooler 10 forms a smooth mating surface for contact with the lower surface of the semiconductor module 1. Multiple heat sink fins 10a protruding in the Z-direction are formed on the lower surface side of the cooler.

[0037] Multiple heat sinks 10a are arranged side-by-side with spacing along the Y direction. This forms a groove 10b between adjacent heat sinks 10a. Cooling of the semiconductor module 1 is achieved by the flow of refrigerant, such as air, through the groove 10b. The direction of refrigerant flow (flow direction) is referred to as the cooling direction F, which will be described in detail later. Furthermore, the cooler 10 is not limited to the structure described above and may also be a water-cooled cooler equipped with a water-cooling jacket.

[0038] like Figure 3 As shown, multiple (four in this embodiment) circuit patterns 22 are formed in an island shape (electrically insulated from each other) on the main surface of the insulating plate 20. The multiple circuit patterns 22 are composed of a pair of collector circuit patterns 23 connected to the collector electrode 30 of the semiconductor element 3 described later, a gate circuit pattern 24 connected to the gate electrode 31, and an emitter circuit pattern 25 connected to the emitter electrode 32.

[0039] The collector circuit pattern 23 has a top view elongated strip shape extending along the long side (Y direction) of the insulating plate 20 on the outer periphery of the insulating plate 20. A pair of collector circuit patterns 23 are arranged opposite each other in the short side (X direction) of the insulating plate 20.

[0040] The gate circuit pattern 24 has an L-shaped bend at one end of the insulating plate 20 along its long side and branches into four branches from the center of the insulating plate 20. Specifically, the gate circuit pattern 24 is formed by connecting an L-shaped portion 24a (viewed from above) and an H-shaped portion 24b (viewed from above). The L-shaped portion 24a extends from a corner of the insulating plate 20 toward the X direction and bends at a right angle at approximately the middle portion of the insulating plate 20 in the X direction, extending to the center of the insulating plate 20. The H-shaped portion 24b is formed by connecting the center of a pair of elongated portions extending in the Y direction with elongated portions extending in the X direction. The H-shaped portion 24b is disposed at the center of the insulating plate 20. The center of the H-shaped portion 24b is connected to the end of the L-shaped portion 24a at the center side. Furthermore, the H-shaped portion 24b constitutes a region in the center of the insulating plate 20 where the gate electrode 31 is joined via a bump B, as will be described in detail later.

[0041] The emitter circuit pattern 25 is formed in a roughly U-shape when viewed from above, surrounding the outer periphery of the H portion 24b. Specifically, the emitter circuit pattern 25 consists of an emitter portion 25a extending in the X direction along the short side on the other side of the long side of the insulating plate 20, a pair of elongated portions 25b and 25c extending from the emitter portion 25a in the Y direction, and a sensing emitter portion 25d connected to one of the elongated portions 25c.

[0042] One end of each of a pair of elongated portions 25b and 25c is connected to the emitter portion 25a, and the other end of each pair of elongated portions 25b and 25c extends along the Y direction. The pair of elongated portions 25b and 25c are arranged opposite each other such that the H portion 24b is sandwiched in the middle in the X direction. Each elongated portion 25b and 25c is arranged such that it is sandwiched between the collector circuit pattern 23 and the H portion 24b. The pair of collector circuit patterns 23, the pair of elongated portions 25b and 25c, and the pair of elongated portions of the H portion 24b extend parallel to each other in the Y direction. The sensing emitter portion 25d is arranged on the opposite side of the emitter portion 25a such that it sandwiches a collector circuit pattern 23 between itself and the emitter portion 25a. Furthermore, the sensing emitter portion 25d is arranged parallel to the L portion 24a of the gate circuit pattern 24 in the X direction and extends along the X direction. The sensing emitter portion 25d is connected to an elongated portion 25c. In addition, a pair of elongated portions 25b and 25c form an area on the outside of portion H 24b for the emitter electrode 32 to be engaged via bump B, as will be described in detail later.

[0043] In the circuit pattern 22 constructed in this way, as follows: Figure 3 As shown, the H-section 24b of the gate circuit pattern 24 is sandwiched between a pair of elongated sections 25b and 25c. Furthermore, the H-section 24b and the pair of elongated sections 25b and 25c are both sandwiched between a pair of collector circuit patterns 23. In addition, Figure 3 The double-dotted area represents the region where the block electrode 4 or semiconductor element 3, described later, is joined. Alternatively, the circuit pattern may be referred to as a circuit board.

[0044] Multiple semiconductor elements 3 are arranged at predetermined locations in the circuit pattern 22. The semiconductor elements 3 are formed into a square shape from a top view using a semiconductor substrate such as silicon (Si) or silicon carbide (SiC). In this embodiment, the semiconductor element 3 is composed of an RC (Reverse Conducting)-IGBT element that integrates the functions of an IGBT (Insulated Gate Bipolar Transistor) element and an FWD (Free Wheeling Diode) element.

[0045] Furthermore, semiconductor element 3 is not limited to this; it can also be constructed by combining switching elements such as IGBTs, power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and diodes such as FWDs (Free Wheeling Diodes). Additionally, RB (Reverse Blocking) IGBTs, which have sufficient withstand voltage relative to reverse bias, can also be used as semiconductor element 3. Furthermore, the shape, number, and placement of semiconductor elements 3 can be appropriately modified.

[0046] In this embodiment, four semiconductor elements 3 are disposed on the upper surface of the H portion 24b and the upper surface of a pair of elongated portions 25b and 25c via multiple bumps B. Specifically, the semiconductor elements 3 are disposed above the top of the branched H portion 24b and above the top or base of the elongated portions 25b and 25c. A collector electrode 30 is disposed on the upper surface of the semiconductor element 3, and a gate electrode 31 and an emitter electrode 32 are disposed on the lower surface of the semiconductor element 3. The gate electrode 31 is disposed at the center of one end side of the semiconductor element 3, and the emitter electrode 32 is disposed at the opposite end side.

[0047] Semiconductor element 3 has its gate electrode 31 positioned opposite the top surface of the H-section 24b, and its emitter electrode 32 positioned opposite the top surfaces of the elongated sections 25b and 25c. Semiconductor element 3 is bonded to circuit pattern 22 via bumps B. More specifically, for a semiconductor element 3, gate electrode 31 is electrically bonded to the top surface of the branched H-section 24b via one bump B. Furthermore, for a semiconductor element 3, emitter electrode 32 is electrically bonded to the top surfaces of the elongated sections 25b and 25c via three bumps B.

[0048] Thus, the gate electrode 31 and the emitter electrode 32 are arranged side by side in the X direction. In particular, in the X direction, the gate electrode 31 is positioned further inward than the emitter electrode 32. That is, the four gate electrodes 31 are arranged to be more biased toward the center of the module than the four emitter electrodes 32.

[0049] Bump B can be made of a metal sintering material. For example, a silver sintering material formed by sintering a silver nanoparticle paste containing metal nanoparticles such as silver can be used as bump B. Furthermore, it is not limited to silver; bump B can also be made of a metal sintering material formed by sintering a metal nanoparticle paste containing metal nanoparticles such as gold, silver, copper, aluminum, and nickel. The metal nanoparticle paste is formed, for example, by dispersing metal nanoparticles covered by an amine-based dispersion material in an organic solvent such as toluene. Bump B is formed, for example, into a cylindrical shape extending along the thickness direction (Z direction). Additionally, one end of bump B is bonded to the emitter electrode 32 or gate electrode 31 of the semiconductor element 3, and the other end is bonded to the circuit pattern 22, as will be described in detail later. Moreover, bump B has a drum shape with a recessed middle portion in the height direction (Z direction).

[0050] Additionally, block electrodes 4 are attached to each circuit pattern 22. Specifically, the block electrode 4 is composed of a collector block 40 attached to the collector circuit pattern 23, a gate electrode block 41 attached to the gate circuit pattern 24, an emitter electrode block 42 attached to the emitter circuit pattern 25, and a sensing emitter electrode block 43.

[0051] The collector block 40 is formed in a generally square shape when viewed from above, covering most of the upper part of the laminated substrate 2. Specifically, the collector block 40 has a flat plate portion 44 covering the upper part of the semiconductor element 3 and a pair of protrusions 45 protruding from both ends of the flat plate portion 44 in the X direction toward the collector circuit pattern 23. Thus, the collector block 40 appears generally U-shaped when viewed from the Y direction.

[0052] The plate portion 44 is formed in a generally square shape when viewed from above, covering a pair of collector circuit patterns 23, a pair of elongated portions 25b and 25c disposed between the pair of collector circuit patterns 23, an H portion 24b, and four semiconductor elements 3. The width of the plate portion 44 in the X direction corresponds to the relative spacing between the pair of collector circuit patterns 23. The width of the plate portion 44 in the Y direction corresponds to the length of the collector circuit patterns 23 in the Y direction. In addition, a circular through-hole 46 extending along the thickness direction is formed in the center of the plate portion 44.

[0053] The protrusion 45 has a generally cuboid shape, projecting downwards in the Z direction from its end in the X direction of the flat plate 44. The width of the protrusion 45 in the X direction is slightly smaller than the width of the collector circuit pattern 23. Furthermore, the width of the protrusion 45 in the Y direction corresponds to the width of the flat plate 44 and is slightly smaller than the width of the collector circuit pattern 23. Additionally, chamfers are formed at each corner on the upper surface side of the collector block 40. A pair of protrusions 45 are arranged along two opposite sides of the insulating plate 20.

[0054] The collector 30 of the semiconductor element 3 is electrically bonded to the lower surface of the flat plate portion 44 via a bonding material S. Additionally, the lower surfaces of each protrusion 45 are electrically bonded to the collector circuit pattern 23 via the bonding material S. The bonding material S can be a sheet-like sintered metal material. For example, a silver sintered material formed by sintering silver nanoparticle sheets containing metal nanoparticles such as silver can be used as the bonding material S. Furthermore, the bonding material S is not limited to silver and can be composed of a metal sintered material formed by sintering metal nanoparticle sheets containing other metal nanoparticles such as gold, silver, copper, aluminum, and nickel. The metal nanoparticle sheets are formed by bonding metal nanoparticles using an organic adhesive such as polyester. The bonding material S is formed, for example, into a rectangular shape of a predetermined thickness. Furthermore, the bonding material S is not limited to a metal sintered material and can also be made of solder. Additionally, the bonding material S is not limited to a sheet shape and can also be made of a paste. Furthermore, the height of the protrusion 45 in the Z direction preferably corresponds to the combined height of the thickness of the semiconductor element 3 and the height of the bump B.

[0055] The gate electrode block 41 has a long cuboid shape in the X direction. Specifically, the width of the gate electrode block 41 in the X direction corresponds to the width of the elongated portion in the X direction of the L portion 24a. The width of the gate electrode block 41 in the Y direction is slightly smaller than the width of the L portion 24a. In addition, chamfers are formed at each corner on the upper surface side of the collector electrode block 40. The lower surface of the gate electrode block 41 is electrically bonded to the upper surface of the elongated portion in the X direction of the L portion 24a via a bonding material S.

[0056] The emitter electrode block 42 has a cuboid shape extending in the X direction along the short side on the other side of the long side of the insulating plate 20. Specifically, the width of the emitter electrode block 42 in the X direction and the width in the Y direction are slightly smaller than the width of the emitter portion 25a. In addition, chamfers are formed at each corner of the upper surface side of the emitter electrode block 42. The lower surface of the emitter electrode block 42 is electrically bonded to the upper surface of the emitter portion 25a via a bonding material S. When viewed from above, the emitter electrode block 42 is disposed outside the collector block 40 (flat plate portion 44).

[0057] The sensing emitter electrode block 43 has a rectangular parallelepiped shape that is longer in the X direction. Specifically, the width of the sensing emitter electrode block 43 in both the X and Y directions is slightly smaller than the width of the sensing emitter portion 25d. Furthermore, chamfers are formed at each corner on the upper surface side of the collector block 40. The lower surface of the sensing emitter electrode block 43 is electrically bonded to the upper surface of the sensing emitter portion 25d via a bonding material S. When viewed from above, the sensing emitter electrode block 43 is disposed outside the collector block 40 (flat plate portion 44). The sensing emitter electrode block 43 and the gate electrode block 41 are arranged side-by-side in the X direction. Additionally, the length of the sensing emitter electrode block 43 in the X direction is less than the length of the gate electrode block 41.

[0058] The block electrode 4 thus constructed is configured such that its height is equal in the Z direction. Furthermore, the block electrode 4 is preferably formed from a metal material with good thermal conductivity, such as copper or aluminum. Additionally, the collector block 40 can be formed either integrally with the flat plate portion 44 and the pair of protrusions 45, or by joining the flat plate portion 44 and the pair of protrusions 45 together using welding or the like.

[0059] Additionally, a sealing resin 5 is filled into the space above the laminated substrate 2 (see reference). Figure 1 The sealing resin 5, for example, is filled with the through-hole 46 to seal the semiconductor element 3, the laminated substrate 2, and the block electrode 4. The sealing resin 5 can be epoxy resin or silicone gel.

[0060] However, in conventional semiconductor modules, semiconductor elements are disposed on the upper surface of a laminated substrate. An emitter electrode is disposed on the upper surface of the semiconductor element, and a collector electrode is disposed on the lower surface of the semiconductor element. The circuit patterns of the emitter electrode and the laminated substrate are electrically connected, for example, by bonding wires. Additionally, a cooler is disposed on the lower surface of the laminated substrate.

[0061] In conventional structures, the heat generated by the emitter electrode is dissipated through a cooler. In this case, since the emitter electrode is located on the surface side of the semiconductor device, the generated heat is transferred to the back side (collector side) of the semiconductor device and dissipated through the laminated substrate and the cooler.

[0062] Thus, since the semiconductor element generates heat on the emitter electrode side, the heat generated on the emitter electrode side needs to be transferred to the collector electrode side, which serves as the cooler side. Therefore, there is a problem of increased overall module thermal resistance corresponding to the thermal conductivity and thickness of the semiconductor element. Furthermore, as mentioned above, the emitter electrode is conventionally wired using bonding wires, resulting in longer wiring lengths and consequently, increased inductance.

[0063] Therefore, the inventors of this application conceived of this invention by focusing on the orientation of the emitter electrode, which serves as a heat source, in a semiconductor element. Specifically, the main objective of this invention is to reverse the bonding direction of the semiconductor element 3, positioning the emitter electrode 32 towards the laminated substrate 2. In this embodiment, the semiconductor element 3 is disposed on the upper surface of the laminated substrate 2. A collector electrode 30 is disposed on the upper surface of the semiconductor element 3, and an emitter electrode 32 is disposed on the lower surface of the semiconductor element 3. The emitter electrode 32 is bonded to the circuit pattern 22 on the laminated substrate 2 via a bump B.

[0064] Additionally, a block electrode 4 (collector block 40) is attached to the collector 30, which is located on the upper surface side of the semiconductor element 3. The collector block 40 has a flat plate portion 44 covering the upper part of the semiconductor element 3 and protrusions 45 extending from both ends of the flat plate portion 44 toward the circuit pattern 22. The protrusions 45 are attached to the circuit pattern 22.

[0065] According to this structure, the emitter electrode 32 faces the laminated substrate 2 and is bonded to the laminated substrate 2 via bumps B. Therefore, the heat generated by the emitter electrode 32 does not pass through the interior of the semiconductor device but can be directly transferred to the laminated substrate 2 (heat sink 21) through the bumps B. This reduces thermal resistance and improves cooling efficiency. Because the thermal resistance is reduced, the module size can be made close to the chip size, enabling overall module miniaturization. Furthermore, by implementing the wiring of the emitter electrode 32 via bumps B, the wiring length can be shortened compared to conventional bonding wires, and inductance can also be reduced.

[0066] Furthermore, the collector block 40 enables electrical connection of the collector 30, thereby eliminating unnecessary wiring and allowing heat from the semiconductor element 3 to be transferred to the laminated substrate 2 via the collector block 40. In other words, the collector block 40 can be used not only as an electrical bonding component but also as a heat transfer component. Therefore, the cooling effect can be further improved. Additionally, the use of numerous metal block electrodes 4 with high heat capacity enables the realization of modules with high thermal conductivity and short-circuit withstand capability.

[0067] Furthermore, in this embodiment, it is preferable that the relative directions of the pair of protrusions 45 in the collector block 40 are aligned with the direction of refrigerant flow (cooling direction F) within the range corresponding to the collector block 40 in the cooler 10 mounted on the lower surface of the semiconductor module 1. For example, Figure 1 As shown, the direction of refrigerant flow may be parallel to the grooves 10b in a cooler 10 having multiple heat sinks 10a with grooves 10b in one direction (X direction). Alternatively, for example, in a cooler 10 composed of a water-cooled jacket, the direction of liquid flow inside the water-cooled jacket may be aligned with the opposite direction of a pair of protrusions 45.

[0068] Specifically, such as Figure 5 As shown in (A), a pair of protrusions 45 have a cuboid shape that is longer in the Y direction and are opposite to each other in the X direction. In this case, it is preferable that the flow direction (cooling direction F) of the refrigerant flowing into the cooler 10 is towards the X direction. According to this structure, as Figure 5As shown in (B), the refrigerant flows from below one protrusion 45, through the underside of the flat plate 44, towards the underside of another protrusion 45. Thus, because the refrigerant flows in a direction perpendicular to the long side (long side) of the protrusion 45, a larger area of ​​refrigerant contributes to the cooling of the collector block 40.

[0069] like Figure 5 As shown in (B), on the midstream side of the refrigerant (the central side in the X direction of the semiconductor module 1), heat from the semiconductor element 3 can be released to the cooler 10 via the bump B. Additionally, on the upstream and downstream sides of the refrigerant (the outer sides in the X direction of the semiconductor module 1), heat from the semiconductor element 3 can be released to the cooler 10 via the plate portion 44 and the pair of protrusions 45. Thus, heat can be effectively released from both sides of the semiconductor element 3. As a result, the four semiconductor elements 3 disposed below the plate portion 44 and between the pair of protrusions 45 can be cooled uniformly. Therefore, temperature deviations of each semiconductor element 3 can be suppressed, and cooling performance can be improved.

[0070] Furthermore, in this embodiment, a through hole 46 extending along the thickness direction is formed in the center of the plate portion 44. With this structure, the through hole 46 can be utilized as an injection port for the sealing resin 5. Therefore, the sealing resin 5 can be filled completely between the plate portion 44 and the semiconductor element 3. Additionally, voids present during the injection of the sealing resin 5 can be easily removed.

[0071] Furthermore, in this embodiment, the gate electrode 31 is positioned closer to the center of the plate portion 44 than the emitter electrode 32. That is, as... Figure 3 as well as Figure 4 (A) and Figure 4 As shown in (B), the gate electrodes 31 of the four semiconductor elements 3 face the center of the plate portion 44, and the emitter electrodes 32 are located on the outer periphery of the gate electrodes 31. More specifically, when viewed from above, four semiconductor elements 3 are arranged in a 2×2 configuration below the plate portion 44, and the gate electrodes 31 of the semiconductor elements 3 are arranged opposite each other in the center of the plate portion 44. According to this structure, the emitter electrodes 32, which are heat-generating components, are not concentrated in the center of the module, but are spaced apart from each other. As a result, heat is not concentrated in the center of the module, but is dispersed to improve cooling efficiency. In addition, the gate electrodes 31 are disposed in the center of the laminated substrate 2, and the gate electrodes 31 are bonded to the branched top surface of the H portion 24b via bump B, thereby uniformly shortening the wiring length from the outside to the gate electrodes 31 and suppressing gate oscillation.

[0072] Furthermore, in this embodiment, a gate electrode block 41, an emitter electrode block 42, and a sensing emitter electrode block 43 are disposed on the outside of the collector block 40. That is, the collector block 40 is configured to be sandwiched between the gate electrode block 41, the emitter electrode block 42, and the sensing emitter electrode block 43 in the Y direction. According to this structure, since the emitter electrode block 42 and the sensing emitter electrode block 43 are disposed on the outside of the collector block 40, external connections can be easily obtained.

[0073] Furthermore, semiconductor modules typically generate heat during switching operations, which puts thermal stress on their bonding surfaces, potentially leading to deformation. Therefore, to ensure device reliability, a technique has been proposed that adjust the bonding height of the solder bumps connecting the chip and the substrate to create a drum-like shape by contracting the central portion of the solder bumps. While this structure can suppress stress concentration at the bonding surfaces, the increased complexity of the structure and processes used to control the bonding height of the solder bumps can be a major reason for the increased overall module cost.

[0074] Therefore, the inventors of this application conceived of the present invention by focusing on the material of the bump and the method of forming it. Specifically, in this embodiment, the bump B, made of a metal sintered material, has a column shape extending along the Z direction. The upper end of the bump B is engaged with the emitter electrode 32 or the gate electrode 31, and the lower end of the bump B is engaged with the circuit pattern 22 (the strip portion 25b or the H portion 24b). Moreover, the bump B has a shape in which the middle portion is recessed compared to the electrodes of the semiconductor element 3 or the engagement portion engaged with the circuit pattern 22.

[0075] According to this structure, because the middle portion of bump B is recessed, the area near the interface of the joint portion of bump B becomes wider than the width of the middle portion, allowing for a smooth outer surface shape during jointing. As a result, the concentration of thermal stress at this interface is suppressed, reducing deformation of bump B caused by thermal stress. For example, peeling and cracking at the interface (joint surface) of bump B can be suppressed. Furthermore, since bump B is made of a sintered metal material, the aforementioned recessed shape can be formed without complex height control, as will be described in detail later. Therefore, the reliability of the device can be improved with a simple structure.

[0076] Here, refer to Figure 11 (A) and Figure 11 (B) describes the shape of bump B in more detail. Figure 11 (A) and Figure 11 (B) is a schematic diagram illustrating the variation in the shape of the protrusion according to this embodiment. The cross-section of protrusion B after being cut by the XY plane has a generally circular shape. Furthermore, as described above, the middle portion of protrusion B in the height direction is concave compared to the joint portion. More specifically, as... Figure 11As shown in (A), the bump B has a first bonding portion B1 that is bonded to the semiconductor element 3 side, a second bonding portion B2 that is connected to the laminated substrate 2 side, and a recess B3 that is recessed between the first bonding portion B1 and the second bonding portion B2.

[0077] Let the width (outer diameter) of the first joint B1 be D1, the width (outer diameter) of the second joint B2 be D2, and the width (outer diameter) of the recess B3 be D3. Then, the relationship D1 = D2 > D3 holds true. That is, the outer diameter D1 of the first joint B1 is equal to the outer diameter D2 of the second joint B2, and the outer diameter D3 of the recess B3 is smaller than both outer diameters D1 and D2. Furthermore, let the height of the bump B (the relative spacing between the semiconductor element 3 and the laminated substrate 2) be T, the distance between the recess B3 and the semiconductor element 3 (electrode) be T1, and the distance between the recess B3 and the laminated substrate 2 (circuit pattern 22) be T2. Then, the relationships T = T1 + T2 and T1 = T2 hold true. That is, the recess B3 is located at the center in the height direction of the bump B (the central portion between the first joint B1 and the second joint B2).

[0078] The outer surface of the first junction B1 is a concave rounded corner shape with an acute angle θ1 formed relative to the junction surface at the semiconductor element 3 (electrode). Similarly, the outer surface of the second junction B2 is a concave rounded corner shape with an acute angle θ2 formed relative to the junction surface at the laminated substrate 2 (circuit pattern 22). Figure 11 In (A), the relationship θ1 = θ2 holds. That is, angle θ1 is equal to angle θ2.

[0079] Thus, by setting the outer surfaces of the first joint B1 and the second joint B2 to a concave rounded corner shape, the interface of the joint portion of the bump B can smoothly join with the electrode or circuit pattern 22. As a result, the thermal stress applied near the interface can be dispersed, making the bump B less prone to breakage.

[0080] In addition, Figure 11 In (A), the concave portion B3 is defined as being located in the central portion of the protrusion B along its height direction, but this is not limited to this structure and can be appropriately modified. For example, as... Figure 11 As shown in (B), the recess B3 can also be disposed biased towards the semiconductor element 3 side (T1 < T2). In this case, the angle θ1 formed by the concave rounded corner shape of the first junction B1 and the junction surface relative to the semiconductor element 3 is smaller than the angle θ2 formed by the concave rounded corner shape of the second junction B2 and the junction surface relative to the laminated substrate 2 (θ1 < θ2). According to this structure, since heat is generated by the emitter electrode 32 of the semiconductor element 3, the thermal stress dispersion effect can be further improved by reducing the angle θ1 on the semiconductor element 3 side.

[0081] In addition, Figure 11 In (B), the emitter electrode 32 is located on the outer side of the stacked substrate 2, closer to the gate electrode 31. According to this structure, the emitter electrodes 32, which are heat-generating components, are not concentrated in the center of the module, and the spacing between each emitter electrode 32 is achieved. As a result, heat is not concentrated in the center of the module, and heat can be dispersed, improving cooling efficiency.

[0082] Furthermore, multiple bumps B (three in this embodiment) are provided to engage with one emitter electrode 32. That is, the emitter electrode 32 is engaged with the circuit pattern 22 using multiple bumps B. According to this structure, as described above, since the heat of the semiconductor element 3 is mainly generated by the emitter electrode 32, by providing multiple bumps B on the emitter electrode 32, the heat dissipation (cooling performance) through these bumps B can be further improved. In addition, by arranging multiple bumps B side by side on the emitter electrode 32, the thermal stress dispersion effect can be further improved compared to the case where a single bump B is provided.

[0083] Furthermore, the emitter electrode 32 is located on the side of the gate electrode 31 closest to the pair of protrusions 45. Moreover, a plurality of bumps B are arranged side-by-side along the extending direction (Y direction) of the pair of protrusions 45. According to this structure, the plurality of bumps B can be arranged close to the protrusions 45. Since the protrusions 45 (collector block 40) are formed of a metal block with good thermal conductivity, the aforementioned heat dissipation can be further improved by arranging the bumps B close to the protrusions 45.

[0084] Next, refer to Figure 6 (A) and Figure 6 (B) to Figure 10 (A) and Figure 10 (B) describes the method for manufacturing the semiconductor module involved in this embodiment. Figure 6 (A) and Figure 6 (B) to Figure 10 (A) and Figure 10 (B) is a perspective view illustrating a step example of the manufacturing method of the semiconductor module according to this embodiment. Furthermore, the semiconductor module manufacturing method shown below is merely an example and is not limited to it, and can be appropriately modified. Additionally, for ease of explanation, the heat sink is omitted in the following figures. Figure 6 (A) and Figure 6 (B) Figure 7 (A) and Figure 7 (B) Figure 9 (A) and Figure 9 (B) Figure 10 (A) and Figure 10 (B) is a diagram showing the state before and after each process. Additionally, Figure 8(A) is a three-dimensional view of the bump coating process. Figure 8 (B) is Figure 8 A cross-sectional schematic diagram of (A).

[0085] The semiconductor module 1 manufacturing method according to this embodiment is configured by sequentially performing the following steps: a preparation step, in which a multilayer substrate 2 and a block electrode 4 are prepared; a chip placement step (see...). Figure 6 (A) and Figure 6 In the chip configuration process (B), semiconductor element 3 is configured on collector block 40; block electrode configuration process (refer to...) Figure 7 (A) and Figure 7 In the (B) electrode configuration process, a gate electrode block 41, an emitter electrode block 42, and a sensing emitter electrode block 43 are configured on the laminated substrate 2; the bump coating process (see...) Figure 8 (A) and Figure 8 (B) In the bump coating process, bumps are disposed on the semiconductor element 3; the bump bonding process (see reference) Figure 9 (A) and Figure 9 (B) Figure 10 (A) and Figure 10 In the bump bonding process (B), the bump-coated semiconductor element 3 is bonded to the laminated substrate 2; and the sealing process (see reference) Figure 1 In this sealing process, sealing resin 5 is filled. Furthermore, the order of these processes can be appropriately changed as long as no contradictions arise.

[0086] First, prepare the aforementioned stacked substrate 2 and block electrodes 4 (collector block 40, gate electrode block 41, emitter electrode block 42 and sensing emitter electrode block 43) in advance (preparation process).

[0087] Next, the chip configuration process is carried out. For example... Figure 6 (A) and Figure 6 As shown in (B), in the chip manufacturing process, four semiconductor elements 3 are arranged such that the collector 30 faces the lower surface of the plate portion 44. A bonding material S (see reference) is disposed on the upper surface (collector surface) of the semiconductor elements 3. Figure 4 (A) and Figure 4(B) and the semiconductor element 3 is disposed at a predetermined position on the plate portion 44. At this time, the gate electrode 31 of each semiconductor element 3 is disposed in such a way that it is located inside the emitter electrode 32 in the X direction. Then, the collector surface of the semiconductor element 3 is pressed toward the plate portion 44 with a predetermined pressure, and heated at a predetermined temperature for a predetermined time, thereby electrically bonding the semiconductor element 3 and the plate portion 44 via the bonding material S. In addition, the bonding material S can be a bonding material that is pre-formed into a sheet shape to match the shape of the semiconductor element 3, or a paste-like metal sintering material can be coated on the collector surface.

[0088] Next, the first electrode configuration process is performed. For example... Figure 7 (A) and Figure 7 As shown in (B), in the first electrode arrangement process, the gate electrode block 41, the emitter electrode block 42, and the sensing emitter electrode block 43 are arranged at predetermined locations on the circuit pattern 22. Specifically, the gate electrode block 41 is arranged on the upper surface of the L portion 24a via the bonding material S. The emitter electrode block 42 is arranged on the upper surface of the emitter portion 25a via the bonding material S. The sensing emitter electrode block 43 is arranged on the upper surface of the sensing emitter portion 25d via the bonding material S. Then, these block electrodes 4 are pressed toward the laminated substrate 2 with a predetermined pressure and heated at a predetermined temperature for a predetermined time, thereby electrically bonding the portions of the block electrodes 4, excluding the collector electrode block 40, to each circuit pattern 22 via the bonding material S.

[0089] Next, the bump coating process is performed. For example... Figure 8 As shown in (A), in the bump coating process, bumps B of predetermined height are disposed on the emitter electrode 32 and the gate electrode 31. Additionally, a bonding material S is disposed on the lower surface of a pair of protrusions 45. Furthermore, the bumps B preferably have a height that slightly protrudes from the lower surface of the bonding material S.

[0090] More specifically, bump B is applied in a manner that forms a tapered cone shape at its tip. As described above, bump B can be made using a paste-like metal sintering material with a predetermined viscosity. The metal sintering material preferably has a viscosity that allows bump B to maintain its conical shape after application, i.e., a viscosity that maintains the shape retention of bump B. In other words, a viscosity that causes bump B to flow after application is not preferred.

[0091] In addition, such as Figure 8As shown in (B), the bump B is coated such that its tip protrudes beyond the end faces (end faces of the bonding material S) of the pair of protrusions 45. That is, the coating height H (height of the cone) of the bump B is the height ΔH relative to the end face of the bonding material S. Furthermore, the coating height H of the bump B is 0.3 mm or more and 3.0 mm or less. Preferably, the coating height H of the bump B is 0.6 mm or more and 1.5 mm or less. The outer diameter of the bottom surface of the bump B (the maximum diameter of the cone) is 50% or more and 90% or less of the coating height H. Preferably, the outer diameter of the bottom surface of the bump B is 60% or more and 80% or less of the coating height H. By adjusting the coating height H of the bump B and the outer diameter of the bottom surface, the recessed shape of the bump B, described later, can be controlled.

[0092] As described above, a plurality of bumps B are arranged side-by-side on the emitter electrode 32. In this embodiment, the bumps B are formed of a paste-like metal sintered material, thereby minimizing the distance between the bumps B and allowing them to be arranged close together. Since the metal sintered material has sturdability and will not melt even when heated, adjacent bumps B will not contact each other, ensuring conductivity between the semiconductor element 3 and the laminated substrate 2, as will be described in detail later. As a result, the emitter electrode 32 can be reduced in size, enabling miniaturization of the entire module.

[0093] Next, the bump joining process is performed. For example... Figure 9 (A) and Figure 9 As shown in (B), in the bump bonding process, the emitter electrode 32 is bonded to the circuit pattern 22 via bump B, and a pair of protrusions 45 are bonded to the circuit pattern 22 via bonding material S. Specifically, the bump B disposed on the emitter electrode 32 is positioned on the upper surface of a pair of elongated portions 25b, 25c, and the bump B disposed on the gate electrode 31 is positioned on the upper surface of the H portion 24b. In addition, a pair of protrusions 45 are disposed on the upper surface of a pair of collector circuit patterns 23 via bonding material S.

[0094] More specifically, such as Figure 10 As shown in (A), the tips of each bump B are facing the laminated substrate 2, and the tips of each bump B are pressed towards the predetermined circuit pattern 22 to be bonded. The tips of each bump B are pressed until a pair of protrusions 45 contact (bond) the circuit pattern 22 via the bonding material S. As a result, the tips of the bumps B extend outward on the surface of the circuit pattern 22, becoming a shape with a larger width (see Figure 1). Figure 10 (B)). As a result, bump B is formed as Figure 11 (A) and Figure 11 (B) shows a drum shape with a concave middle section.

[0095] That is, in Figure 11 (A) and Figure 11 In the shape of the protrusion B shown in (B), the partial shapes of the first joint B1 and the recess B3 are... Figure 8 (A) and Figure 8 The bump is pre-formed in the bump coating process shown in (B). Then, in the bump joining process, the tip of the bump B is slightly flattened to form the shape of the remaining portion of the recess B3 and the second joining portion B2. Furthermore, the joining height T of the bump B is more than 20% and less than 55% of the coating height H of the bump B. Preferably, the joining height T of the bump B is more than 25% and less than 40% of the coating height H of the bump B. If the joining height T of the bump B is too large, the second joining portion B2 cannot expand, which may cause the bump B to break near the second joining portion B2. On the other hand, if the joining height T of the bump B is too small, the second joining portion B2 side will expand excessively, which may cause the bump B to break near the first joining portion B1.

[0096] In this case, the pair of protrusions 45 serve to define the engagement height T of the bump B and control the relative shape of the bump B. That is, the engagement height T of the bump B and the drum shape of the bump B can be adjusted according to the height of the pair of protrusions 45. Furthermore, the height of the pair of protrusions 45 is preferably set within the range formed by adding the engagement height T of the bump B to the thickness of the semiconductor element 3.

[0097] Thus, in this embodiment, by utilizing the viscosity of the metal, the tip of the cone-shaped bump B, corresponding to the height of the pair of protrusions 45, is pressed onto the circuit pattern 22, thereby forming a recess B3 in the middle portion of the bump B. This allows the bump B to be bonded to the circuit pattern 22 using a simple process.

[0098] Furthermore, in the bump bonding process, after pressing the top of bump B toward the circuit pattern 22 to form a recess B3 in the middle portion of bump B, bump B is heated to solidify it. Specifically, by pressing the collector block 40 toward the laminated substrate 2 with a predetermined pressure and heating it at a predetermined temperature for a predetermined time, the emitter electrode 32 is bonded to the circuit pattern 22 via bump B, and the collector block 40 is bonded to the collector circuit pattern 23 via bonding material S. Moreover, after heating, bump B maintains its overall shape and shrinks slightly, but does not melt, exhibiting a certain degree of shape retention. As a result, adjacent bumps B do not contact each other.

[0099] Next, the sealing process is carried out. For example... Figure 1As shown, in the sealing process, the space above the laminated substrate 2 is sealed with sealing resin 5. For example, a rectangular frame (not shown) is arranged around the laminated substrate 2, allowing the sealing resin 5 to be filled into the space within the frame without any omissions from the through-hole 46. By curing the sealing resin 5, the laminated substrate 2, the semiconductor element 3, and the block electrode 4 are sealed. Thus, the integrated semiconductor module 1 is completed.

[0100] As explained above, according to the present invention, by reversing the bonding direction of the semiconductor element 3 from the conventional orientation and arranging the emitter electrode 32 toward the laminated substrate 2 side, thermal resistance and inductance can be reduced. Furthermore, compared to the conventional approach, structures such as wires can be omitted, simplifying and miniaturizing the overall module structure. Additionally, by coating a paste-like metal sintering material into a conical shape to form a bump B, and pressing its tip against the bonding surface to form a drum shape, the deformation of the bump caused by thermal stress can be reduced using a simpler structure, thereby improving the reliability of the device.

[0101] Furthermore, in the above embodiments, the number and arrangement of semiconductor elements 3 are not limited to the above structure, but can be appropriately changed.

[0102] Furthermore, in the above embodiments, the number and layout of the circuit patterns 22 are not limited to the above structure, but can be appropriately changed.

[0103] Furthermore, in the above embodiments, the laminated substrate 2 and the semiconductor element 3 are formed into a rectangular or square shape when viewed from above, but are not limited to this structure. The laminated substrate 2 and the semiconductor element 3 may also be formed into polygonal shapes other than those described above.

[0104] Furthermore, in the above embodiment, the cross-section of bump B after being cut by the XY plane is described as having a generally circular shape, but this structure is not limited to this. The cross-sectional shape of bump B can be appropriately changed, such as a polygonal shape with four sides, a star shape, etc. In addition, the number of bumps B relative to each electrode of semiconductor element 3 is not limited to the above example, but can be appropriately changed.

[0105] Furthermore, in the above embodiment, the case where a conical bump B is formed on the side of the semiconductor element 3 during the bump coating process is described, but it is not limited to this. In the bump coating process, the conical bump B may also be formed on the side of the circuit pattern 22.

[0106] Furthermore, this embodiment and its variations have been described. As other embodiments, the above-described embodiments and variations may be combined in whole or in part.

[0107] Furthermore, this embodiment is not limited to the above-described embodiments and variations. Various changes, substitutions, and modifications can be made without departing from the spirit of the technical concept. Moreover, if the technical concept can be realized in other ways through technological advancements or derived technologies, this method can also be used to implement the present invention. Therefore, the claims cover all embodiments that may be included within the scope of the technical concept.

[0108] The following is a summary of the feature points in the above embodiments.

[0109] The semiconductor module described in the above embodiments is characterized in that the semiconductor module includes: a laminated substrate having a circuit pattern disposed on the upper surface of an insulating plate and a heat sink disposed on the lower surface of the insulating plate; and a semiconductor element having a collector electrode disposed on the upper surface and an emitter electrode and a gate electrode disposed on the lower surface, the emitter electrode and the gate electrode being bonded to the upper surface of the circuit pattern via bumps, the bumps being formed from a metal sintering material with a shape in which the middle portion is recessed compared to the bonding portion.

[0110] Furthermore, in the aforementioned semiconductor module, the bump is characterized by having: a first bonding portion that is bonded to the semiconductor element side; a second bonding portion that is connected to the laminated substrate side; and a recess that is recessed between the first bonding portion and the second bonding portion, wherein the first bonding portion and the second bonding portion have an inwardly rounded corner shape with an acute angle relative to the bonding surface.

[0111] Furthermore, in the aforementioned semiconductor module, the recess is characterized in that it is located in the central portion between the first junction and the second junction.

[0112] Furthermore, in the aforementioned semiconductor module, the recess is characterized in that it is disposed biased toward the semiconductor element side.

[0113] Furthermore, in the aforementioned semiconductor module, the concave rounded corner shape of the first junction and the angle formed with respect to the junction surface of the semiconductor element are smaller than the angle formed with respect to the concave rounded corner shape of the second junction and the junction surface of the laminated substrate.

[0114] Furthermore, in the aforementioned semiconductor module, the emitter electrode is located on the outer side of the stacked substrate, relative to the gate electrode.

[0115] Furthermore, in the aforementioned semiconductor module, the bumps that are engaged with the emitter electrode are provided in a plurality of form.

[0116] Furthermore, in the aforementioned semiconductor module, the semiconductor module is characterized in that it further includes a block electrode coupled to the collector electrode, the block electrode having: a flat plate portion covering the top of the semiconductor element; and a pair of protrusions protruding from both ends of the flat plate portion toward the circuit pattern and coupled to the circuit pattern.

[0117] Furthermore, in the aforementioned semiconductor module, the pair of protrusions are arranged along two opposite sides of the insulating plate, and the emitter electrode is located closer to the pair of protrusions than the gate electrode.

[0118] Furthermore, in the aforementioned semiconductor module, the emitter electrode is characterized in that it is engaged with the circuit pattern using a plurality of bumps, the plurality of bumps being arranged side by side along the extension direction of the pair of protrusions.

[0119] Furthermore, in the aforementioned semiconductor module, the semiconductor elements are characterized in that, when viewed from above, four semiconductor elements are arranged in a 2×2 configuration below the plate portion, and the gate electrodes of each semiconductor element are arranged opposite each other at the center of the plate portion.

[0120] Furthermore, the semiconductor module manufacturing method described in the above embodiments involves bonding semiconductor elements to a laminated substrate, wherein the laminated substrate is formed by distributing a circuit pattern on the upper surface of an insulating plate and distributing a heat sink on the lower surface of the insulating plate. The method is characterized by performing the following steps: a bump coating step, in which bumps made of a paste-like metal sintering material are coated on the bonding surface of the semiconductor element in a cone shape with a pointed tip; and a bump bonding step, in which the tip of the bump is pressed towards the circuit pattern, and a recess is formed in the middle portion of the bump for bonding.

[0121] Furthermore, in the semiconductor module manufacturing method described in the above embodiments, a chip placement process is performed before the bump coating process. In this chip placement process, the semiconductor element is placed on a block electrode, the block electrode having a flat plate portion covering the upper part of the semiconductor element and a pair of protrusions extending from both ends of the flat plate portion toward the circuit pattern. In the chip placement process, the semiconductor element is placed on the lower surface of the flat plate portion such that the collector electrode faces the lower surface of the flat plate portion. In the bump bonding process, the pair of protrusions are bonded to the circuit pattern.

[0122] Furthermore, in the semiconductor module manufacturing method described in the above embodiments, the bump is characterized in that, in the bump coating process, the bump is coated such that its top end protrudes beyond the end faces of the pair of protrusions.

[0123] Furthermore, in the semiconductor module manufacturing method described in the above embodiments, the bump bonding process is characterized in that, after pressing the top of the bump toward the circuit pattern to form a recess in the middle portion of the bump, the bump is heated to solidify it.

[0124] Industrial availability

[0125] As described above, the present invention has the effect of improving the reliability of the device by reducing the deformation of bumps caused by thermal stress using a simple structure. In particular, it is useful for semiconductor modules and methods of manufacturing semiconductor modules.

Claims

1. A semiconductor module characterized by comprising: a laminated substrate that is formed by disposing a circuit pattern on an upper surface of an insulating board and disposing a heat dissipation board on a lower surface of the insulating board; and a semiconductor element that is disposed with a collector electrode on an upper surface and is disposed with an emitter electrode and a gate electrode on a lower surface, the emitter electrode and the gate electrode being joined with an upper surface of the circuit pattern via a bump, the bump being formed in a shape in which an intermediate portion is recessed more than a joining portion by a metal sintered material, the emitter electrode being disposed at a position that is farther from the gate electrode toward an outer side of the laminated substrate, the semiconductor module further comprising a block electrode that is joined with the collector electrode, the block electrode having: a flat plate portion that covers an upper side of the semiconductor element; and a pair of protruding portions that protrude from both ends of the flat plate portion toward the circuit pattern to be joined with the circuit pattern, the pair of protruding portions being disposed along opposite two edges of the insulating board, the emitter electrode being disposed at a position that is farther from the gate electrode toward a side of the pair of protruding portions, the emitter electrode being joined with the circuit pattern by a plurality of the bumps, the plurality of the bumps being disposed side by side along an extension direction of the pair of protruding portions, a plurality of the semiconductor elements being disposed below the flat plate portion, the gate electrode of each semiconductor element being disposed in a manner that is opposite in the center of the flat plate portion.

2. The semiconductor module according to claim 1, characterized in that the bump has: a first joining portion that is joined with the semiconductor element side; a second joining portion that is joined with the laminated substrate side; and a recessed portion that is recessed between the first joining portion and the second joining portion, the first joining portion and the second joining portion have a concave round shape in which an angle with respect to a joining surface is an acute angle.

3. The semiconductor module according to claim 2, characterized in that the recessed portion is located at a central portion between the first joining portion and the second joining portion.

4. The semiconductor module according to claim 2, characterized in that the recessed portion is disposed toward the semiconductor element side.

5. The semiconductor module according to claim 4, characterized in that a concave round shape of the first joining portion and an angle with respect to a joining surface of the semiconductor element are smaller than a concave round shape of the second joining portion and an angle with respect to a joining surface of the laminated substrate.

6. The semiconductor module according to claim 1, characterized in that a plurality of the bumps that are joined with the emitter electrode are provided.

7. The semiconductor module according to claim 1, characterized in that the semiconductor element is disposed with four below the flat plate portion in a 2 x 2 manner when viewed from above.

8. A manufacturing method of a semiconductor module, which is a manufacturing method of the semiconductor module according to claim 1, characterized by comprising: a bump coating step in which the bump is coated in a manner that a tip end becomes a conical shape that is tapered in the manufacturing method of the semiconductor module; and a bump joining step in which the bump is joined with the semiconductor element in the manufacturing method of the semiconductor module. ​ a bump joining step in which the tip of the bump is pressed toward the circuit pattern, a recess is formed in the middle portion of the bump, and joining is performed.

9. The method of manufacturing a semiconductor module according to claim 8, wherein, before the bump coating step, a chip arrangement step is performed in which the semiconductor element is arranged at a block electrode having a flat plate portion covering the upper side of the semiconductor element and a pair of protruding portions protruding from both ends of the flat plate portion toward the circuit pattern, in the chip arrangement step, the semiconductor element is arranged at the lower surface of the flat plate portion in such a manner that the collector electrode faces the lower surface of the flat plate portion, in the bump joining step, the pair of protruding portions are joined to the circuit pattern.

10. The method of manufacturing a semiconductor module according to claim 9, wherein, in the bump coating step, the bump is coated in such a manner that the tip protrudes from the end surface of the pair of protruding portions.

11. The method of manufacturing a semiconductor module according to claim 9 or 10, wherein, in the bump joining step, after the tip of the bump is pressed toward the circuit pattern and a recess is formed in the middle portion of the bump, the bump is heated and cured.

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